| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.12 | 95.44 | 93.98 | 95.35 | 94.84 | 97.53 | 99.57 |
| T2763 | /workspace/coverage/cover_reg_top/40.xbar_smoke.963121569 | Jul 22 07:52:53 PM PDT 24 | Jul 22 07:53:04 PM PDT 24 | 179023724 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3858675610 | Jul 22 07:48:57 PM PDT 24 | Jul 22 07:49:04 PM PDT 24 | 33809513 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2454104028 | Jul 22 07:44:17 PM PDT 24 | Jul 22 07:53:33 PM PDT 24 | 5807889801 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2227263388 | Jul 22 07:54:04 PM PDT 24 | Jul 22 07:58:55 PM PDT 24 | 4231961932 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/19.xbar_same_source.264787066 | Jul 22 07:47:41 PM PDT 24 | Jul 22 07:48:17 PM PDT 24 | 1150801913 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2218707731 | Jul 22 08:00:36 PM PDT 24 | Jul 22 08:00:57 PM PDT 24 | 124464029 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3886557599 | Jul 22 07:58:46 PM PDT 24 | Jul 22 08:00:18 PM PDT 24 | 2255145123 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3462839269 | Jul 22 07:54:22 PM PDT 24 | Jul 22 07:58:12 PM PDT 24 | 1830054546 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2571591043 | Jul 22 07:49:48 PM PDT 24 | Jul 22 07:53:35 PM PDT 24 | 2610372390 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/67.xbar_random.4088430169 | Jul 22 07:57:41 PM PDT 24 | Jul 22 07:58:45 PM PDT 24 | 1663695601 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.4248593137 | Jul 22 07:42:01 PM PDT 24 | Jul 22 07:43:35 PM PDT 24 | 8275086534 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/44.xbar_random.2616855044 | Jul 22 07:53:42 PM PDT 24 | Jul 22 07:54:11 PM PDT 24 | 783769739 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1611173164 | Jul 22 07:51:13 PM PDT 24 | Jul 22 07:51:22 PM PDT 24 | 42842261 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2566435323 | Jul 22 07:49:56 PM PDT 24 | Jul 22 07:51:35 PM PDT 24 | 226505466 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/85.xbar_smoke.849365898 | Jul 22 08:00:50 PM PDT 24 | Jul 22 08:00:58 PM PDT 24 | 53259879 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1239545882 | Jul 22 07:42:14 PM PDT 24 | Jul 22 07:45:06 PM PDT 24 | 2064307641 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2086480757 | Jul 22 07:58:18 PM PDT 24 | Jul 22 08:06:35 PM PDT 24 | 14232719437 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.915932690 | Jul 22 07:43:05 PM PDT 24 | Jul 22 07:46:46 PM PDT 24 | 6014679950 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3206994158 | Jul 22 07:53:02 PM PDT 24 | Jul 22 07:54:17 PM PDT 24 | 269787329 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.80067899 | Jul 22 07:48:36 PM PDT 24 | Jul 22 07:53:40 PM PDT 24 | 3093265864 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2145155132 | Jul 22 07:57:07 PM PDT 24 | Jul 22 07:57:14 PM PDT 24 | 60773622 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2337201785 | Jul 22 07:55:56 PM PDT 24 | Jul 22 08:06:19 PM PDT 24 | 36132796910 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3655353659 | Jul 22 07:57:14 PM PDT 24 | Jul 22 08:48:08 PM PDT 24 | 179853035045 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1204618801 | Jul 22 07:56:24 PM PDT 24 | Jul 22 08:04:20 PM PDT 24 | 26208531994 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.4139451349 | Jul 22 07:54:36 PM PDT 24 | Jul 22 07:55:22 PM PDT 24 | 1061486971 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2562239481 | Jul 22 07:59:26 PM PDT 24 | Jul 22 08:52:14 PM PDT 24 | 162400307135 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/36.xbar_error_random.1646285330 | Jul 22 07:52:16 PM PDT 24 | Jul 22 07:52:56 PM PDT 24 | 387400556 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3433961193 | Jul 22 07:51:11 PM PDT 24 | Jul 22 07:51:19 PM PDT 24 | 41987979 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.185701196 | Jul 22 07:58:43 PM PDT 24 | Jul 22 08:00:18 PM PDT 24 | 9859013496 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/42.xbar_random.421576686 | Jul 22 07:54:35 PM PDT 24 | Jul 22 07:55:55 PM PDT 24 | 2178822426 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/1.chip_csr_rw.372052364 | Jul 22 07:41:33 PM PDT 24 | Jul 22 07:52:05 PM PDT 24 | 5892579300 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.2357297603 | Jul 22 07:56:24 PM PDT 24 | Jul 22 07:59:39 PM PDT 24 | 11439098944 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2376262007 | Jul 22 08:04:39 PM PDT 24 | Jul 22 08:17:55 PM PDT 24 | 13979761469 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.839734646 | Jul 22 08:03:06 PM PDT 24 | Jul 22 08:13:16 PM PDT 24 | 15500034171 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.4279319496 | Jul 22 07:59:13 PM PDT 24 | Jul 22 08:07:33 PM PDT 24 | 47747840422 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.586916715 | Jul 22 07:48:26 PM PDT 24 | Jul 22 07:50:57 PM PDT 24 | 1810840288 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/44.xbar_smoke.3850059473 | Jul 22 07:53:52 PM PDT 24 | Jul 22 07:54:03 PM PDT 24 | 165265886 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1695994914 | Jul 22 07:44:03 PM PDT 24 | Jul 22 07:44:37 PM PDT 24 | 336225260 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.16825012 | Jul 22 07:47:37 PM PDT 24 | Jul 22 07:48:51 PM PDT 24 | 1100047925 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1800770126 | Jul 22 07:53:32 PM PDT 24 | Jul 22 07:55:01 PM PDT 24 | 8114801485 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3023107460 | Jul 22 07:57:10 PM PDT 24 | Jul 22 07:57:18 PM PDT 24 | 41025464 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1336764993 | Jul 22 07:55:58 PM PDT 24 | Jul 22 07:56:35 PM PDT 24 | 399107551 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/42.xbar_error_random.3120572499 | Jul 22 07:53:35 PM PDT 24 | Jul 22 07:54:10 PM PDT 24 | 1072166352 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1868183847 | Jul 22 07:45:45 PM PDT 24 | Jul 22 07:47:15 PM PDT 24 | 1121392610 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.366142197 | Jul 22 07:55:21 PM PDT 24 | Jul 22 07:56:40 PM PDT 24 | 1070755040 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2098789938 | Jul 22 07:55:56 PM PDT 24 | Jul 22 07:56:04 PM PDT 24 | 48209987 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2712922732 | Jul 22 07:45:53 PM PDT 24 | Jul 22 07:57:04 PM PDT 24 | 6353792464 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.547962131 | Jul 22 07:49:58 PM PDT 24 | Jul 22 07:50:21 PM PDT 24 | 393096708 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.209703866 | Jul 22 07:41:26 PM PDT 24 | Jul 22 07:41:39 PM PDT 24 | 103066720 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1694060286 | Jul 22 07:49:18 PM PDT 24 | Jul 22 07:49:50 PM PDT 24 | 901387475 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3050523940 | Jul 22 08:02:25 PM PDT 24 | Jul 22 08:11:37 PM PDT 24 | 13495973509 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/5.xbar_same_source.1216337721 | Jul 22 07:42:57 PM PDT 24 | Jul 22 07:43:14 PM PDT 24 | 478233193 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2474380354 | Jul 22 08:00:35 PM PDT 24 | Jul 22 08:03:25 PM PDT 24 | 2227532273 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/49.xbar_stress_all.2005767905 | Jul 22 07:54:52 PM PDT 24 | Jul 22 07:59:23 PM PDT 24 | 3424112928 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3815504417 | Jul 22 07:50:45 PM PDT 24 | Jul 22 07:52:30 PM PDT 24 | 1674891048 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3358389452 | Jul 22 07:58:39 PM PDT 24 | Jul 22 08:07:22 PM PDT 24 | 13018062475 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.741743399 | Jul 22 07:59:51 PM PDT 24 | Jul 22 08:00:56 PM PDT 24 | 213983143 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.791119473 | Jul 22 07:55:55 PM PDT 24 | Jul 22 08:08:02 PM PDT 24 | 17538533337 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/18.xbar_error_random.2569110375 | Jul 22 07:48:13 PM PDT 24 | Jul 22 07:49:14 PM PDT 24 | 1705013568 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2590242634 | Jul 22 07:54:50 PM PDT 24 | Jul 22 07:55:57 PM PDT 24 | 3785210965 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3328145365 | Jul 22 07:53:52 PM PDT 24 | Jul 22 07:55:28 PM PDT 24 | 5567186040 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.185208382 | Jul 22 07:56:33 PM PDT 24 | Jul 22 07:58:15 PM PDT 24 | 1305797240 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/37.xbar_error_random.3439883600 | Jul 22 07:52:23 PM PDT 24 | Jul 22 07:52:45 PM PDT 24 | 619791710 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3678552464 | Jul 22 07:46:02 PM PDT 24 | Jul 22 07:46:44 PM PDT 24 | 974319234 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2896019026 | Jul 22 07:58:39 PM PDT 24 | Jul 22 07:59:09 PM PDT 24 | 297142393 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2401888900 | Jul 22 07:53:35 PM PDT 24 | Jul 22 08:02:30 PM PDT 24 | 15952764157 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.950636321 | Jul 22 07:50:45 PM PDT 24 | Jul 22 07:52:12 PM PDT 24 | 7893632642 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.4263229038 | Jul 22 07:41:07 PM PDT 24 | Jul 22 07:41:37 PM PDT 24 | 297414681 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/90.xbar_smoke.2354530328 | Jul 22 08:02:28 PM PDT 24 | Jul 22 08:02:54 PM PDT 24 | 217048426 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1873629724 | Jul 22 07:45:19 PM PDT 24 | Jul 22 07:45:29 PM PDT 24 | 58820631 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/18.xbar_smoke.3183242297 | Jul 22 07:47:20 PM PDT 24 | Jul 22 07:47:30 PM PDT 24 | 172868878 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1122853434 | Jul 22 07:43:37 PM PDT 24 | Jul 22 07:44:02 PM PDT 24 | 291025108 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2603660010 | Jul 22 08:02:28 PM PDT 24 | Jul 22 08:03:25 PM PDT 24 | 1227487322 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1539052073 | Jul 22 08:02:58 PM PDT 24 | Jul 22 08:03:35 PM PDT 24 | 308580710 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2396005513 | Jul 22 07:58:40 PM PDT 24 | Jul 22 07:58:58 PM PDT 24 | 337031114 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/98.xbar_error_random.1285770046 | Jul 22 08:03:06 PM PDT 24 | Jul 22 08:03:27 PM PDT 24 | 129708375 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.943267153 | Jul 22 07:55:56 PM PDT 24 | Jul 22 08:09:05 PM PDT 24 | 44173180129 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.451038320 | Jul 22 07:56:22 PM PDT 24 | Jul 22 07:57:05 PM PDT 24 | 322204490 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/26.xbar_same_source.2408773257 | Jul 22 07:49:47 PM PDT 24 | Jul 22 07:50:19 PM PDT 24 | 423803335 ps | ||
| T639 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.4283158045 | Jul 22 07:54:08 PM PDT 24 | Jul 22 07:55:35 PM PDT 24 | 2198650886 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/8.xbar_random.771968387 | Jul 22 07:43:55 PM PDT 24 | Jul 22 07:44:10 PM PDT 24 | 122041223 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2261541255 | Jul 22 07:50:39 PM PDT 24 | Jul 22 07:51:01 PM PDT 24 | 196739699 ps | ||
| T145 | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2984169601 | Jul 22 07:42:40 PM PDT 24 | Jul 22 07:46:21 PM PDT 24 | 5507070603 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3070277710 | Jul 22 07:53:22 PM PDT 24 | Jul 22 07:54:01 PM PDT 24 | 1034009695 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3162704873 | Jul 22 07:49:07 PM PDT 24 | Jul 22 07:50:35 PM PDT 24 | 8500443263 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1771552818 | Jul 22 07:48:58 PM PDT 24 | Jul 22 07:50:06 PM PDT 24 | 6760076692 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/17.xbar_random.2484357998 | Jul 22 07:47:08 PM PDT 24 | Jul 22 07:48:12 PM PDT 24 | 1601347601 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.611481759 | Jul 22 07:41:44 PM PDT 24 | Jul 22 07:49:47 PM PDT 24 | 9189526426 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1450576980 | Jul 22 08:02:59 PM PDT 24 | Jul 22 08:04:36 PM PDT 24 | 8722105307 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.647983532 | Jul 22 08:02:25 PM PDT 24 | Jul 22 08:03:58 PM PDT 24 | 5244703562 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1451906163 | Jul 22 07:44:38 PM PDT 24 | Jul 22 08:03:18 PM PDT 24 | 63237094129 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/19.xbar_stress_all.4195638284 | Jul 22 07:47:51 PM PDT 24 | Jul 22 07:52:16 PM PDT 24 | 2882370094 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/24.xbar_error_random.585231099 | Jul 22 07:49:16 PM PDT 24 | Jul 22 07:50:14 PM PDT 24 | 1490682350 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.461725734 | Jul 22 08:03:02 PM PDT 24 | Jul 22 08:03:18 PM PDT 24 | 159852064 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.802755980 | Jul 22 07:53:33 PM PDT 24 | Jul 22 08:02:48 PM PDT 24 | 4032010424 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1429171620 | Jul 22 07:52:13 PM PDT 24 | Jul 22 07:53:00 PM PDT 24 | 526805562 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/38.xbar_error_random.80844955 | Jul 22 07:52:47 PM PDT 24 | Jul 22 07:53:43 PM PDT 24 | 1490546667 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/4.xbar_error_random.1395647980 | Jul 22 07:42:39 PM PDT 24 | Jul 22 07:43:36 PM PDT 24 | 1689179853 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2984225998 | Jul 22 07:59:40 PM PDT 24 | Jul 22 08:00:42 PM PDT 24 | 3857812603 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3541901580 | Jul 22 07:44:48 PM PDT 24 | Jul 22 07:54:32 PM PDT 24 | 7864393492 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3603075286 | Jul 22 07:51:16 PM PDT 24 | Jul 22 07:56:46 PM PDT 24 | 2296605540 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1682066137 | Jul 22 07:57:40 PM PDT 24 | Jul 22 08:01:09 PM PDT 24 | 5710271893 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1776049168 | Jul 22 08:01:11 PM PDT 24 | Jul 22 08:01:50 PM PDT 24 | 323727967 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2594109272 | Jul 22 08:00:53 PM PDT 24 | Jul 22 08:01:33 PM PDT 24 | 70509690 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2869687242 | Jul 22 08:00:24 PM PDT 24 | Jul 22 08:01:46 PM PDT 24 | 8101546259 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/46.xbar_smoke.4117001943 | Jul 22 07:54:10 PM PDT 24 | Jul 22 07:54:18 PM PDT 24 | 44395671 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2551776330 | Jul 22 07:44:53 PM PDT 24 | Jul 22 07:50:01 PM PDT 24 | 4442261219 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4065214868 | Jul 22 07:46:05 PM PDT 24 | Jul 22 07:47:45 PM PDT 24 | 2686999029 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/45.xbar_stress_all.1960988310 | Jul 22 07:54:34 PM PDT 24 | Jul 22 07:58:03 PM PDT 24 | 2213045588 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.759829253 | Jul 22 07:59:00 PM PDT 24 | Jul 22 08:06:56 PM PDT 24 | 6180381752 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2263775024 | Jul 22 07:48:27 PM PDT 24 | Jul 22 07:48:36 PM PDT 24 | 49493268 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1692244705 | Jul 22 07:55:42 PM PDT 24 | Jul 22 07:56:02 PM PDT 24 | 57583655 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3374412555 | Jul 22 07:50:56 PM PDT 24 | Jul 22 07:51:07 PM PDT 24 | 135690066 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.508118395 | Jul 22 07:42:54 PM PDT 24 | Jul 22 08:00:30 PM PDT 24 | 61097939111 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1782483078 | Jul 22 07:57:53 PM PDT 24 | Jul 22 08:00:05 PM PDT 24 | 3178329266 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/38.xbar_smoke.1363341262 | Jul 22 07:52:33 PM PDT 24 | Jul 22 07:52:43 PM PDT 24 | 51593838 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1700989062 | Jul 22 07:56:56 PM PDT 24 | Jul 22 07:57:31 PM PDT 24 | 348328593 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.4118764624 | Jul 22 08:00:19 PM PDT 24 | Jul 22 08:19:51 PM PDT 24 | 65272916836 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/56.xbar_error_random.3526013296 | Jul 22 07:55:55 PM PDT 24 | Jul 22 07:56:17 PM PDT 24 | 510990704 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/42.xbar_smoke.1637518420 | Jul 22 07:53:23 PM PDT 24 | Jul 22 07:53:33 PM PDT 24 | 193462096 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.1513073386 | Jul 22 08:03:03 PM PDT 24 | Jul 22 08:04:45 PM PDT 24 | 1171519117 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/11.xbar_same_source.2061673914 | Jul 22 07:45:21 PM PDT 24 | Jul 22 07:45:59 PM PDT 24 | 506322721 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.273027457 | Jul 22 08:03:07 PM PDT 24 | Jul 22 08:18:57 PM PDT 24 | 91560985320 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/44.xbar_same_source.2982448329 | Jul 22 07:53:42 PM PDT 24 | Jul 22 07:54:17 PM PDT 24 | 467368877 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1304659143 | Jul 22 08:00:38 PM PDT 24 | Jul 22 08:16:47 PM PDT 24 | 84924550429 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/73.xbar_error_random.661198254 | Jul 22 07:58:46 PM PDT 24 | Jul 22 07:59:06 PM PDT 24 | 167751939 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/71.xbar_same_source.3744454217 | Jul 22 07:58:18 PM PDT 24 | Jul 22 07:59:26 PM PDT 24 | 2498494858 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.2035278863 | Jul 22 08:02:52 PM PDT 24 | Jul 22 08:03:28 PM PDT 24 | 531234565 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1304781740 | Jul 22 08:01:08 PM PDT 24 | Jul 22 08:02:37 PM PDT 24 | 5334481275 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1589671130 | Jul 22 07:53:59 PM PDT 24 | Jul 22 08:27:49 PM PDT 24 | 116499341508 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.4001514764 | Jul 22 08:02:56 PM PDT 24 | Jul 22 08:03:43 PM PDT 24 | 398382432 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/27.xbar_error_random.1627939007 | Jul 22 07:50:06 PM PDT 24 | Jul 22 07:50:39 PM PDT 24 | 864870601 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/61.xbar_stress_all.72217540 | Jul 22 07:59:07 PM PDT 24 | Jul 22 08:03:40 PM PDT 24 | 7838084398 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2987149255 | Jul 22 07:50:03 PM PDT 24 | Jul 22 07:50:10 PM PDT 24 | 46987697 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2177702237 | Jul 22 08:01:43 PM PDT 24 | Jul 22 08:03:10 PM PDT 24 | 1212344123 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2886216334 | Jul 22 08:03:33 PM PDT 24 | Jul 22 08:04:51 PM PDT 24 | 8397680334 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2800920656 | Jul 22 07:54:17 PM PDT 24 | Jul 22 08:11:32 PM PDT 24 | 64306252495 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3797747830 | Jul 22 07:53:53 PM PDT 24 | Jul 22 07:54:01 PM PDT 24 | 47224239 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/4.xbar_same_source.182756920 | Jul 22 07:42:43 PM PDT 24 | Jul 22 07:43:05 PM PDT 24 | 749317915 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3358655302 | Jul 22 07:55:12 PM PDT 24 | Jul 22 07:59:52 PM PDT 24 | 487712974 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3574047427 | Jul 22 07:58:17 PM PDT 24 | Jul 22 07:58:26 PM PDT 24 | 46208055 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3148205287 | Jul 22 08:05:17 PM PDT 24 | Jul 22 08:14:19 PM PDT 24 | 33063518075 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.517761947 | Jul 22 07:53:45 PM PDT 24 | Jul 22 08:01:11 PM PDT 24 | 7016005782 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1029251952 | Jul 22 07:49:38 PM PDT 24 | Jul 22 07:55:38 PM PDT 24 | 11121243807 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1458354410 | Jul 22 07:41:32 PM PDT 24 | Jul 22 07:50:23 PM PDT 24 | 7754360673 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/27.xbar_same_source.3329151829 | Jul 22 07:50:07 PM PDT 24 | Jul 22 07:50:25 PM PDT 24 | 530363208 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.385502223 | Jul 22 07:50:37 PM PDT 24 | Jul 22 07:52:52 PM PDT 24 | 2247986738 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2553319506 | Jul 22 07:56:11 PM PDT 24 | Jul 22 08:08:18 PM PDT 24 | 22204677521 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2081688292 | Jul 22 07:43:54 PM PDT 24 | Jul 22 07:52:16 PM PDT 24 | 8713537623 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2825292149 | Jul 22 07:54:13 PM PDT 24 | Jul 22 08:05:42 PM PDT 24 | 64616861060 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2814964607 | Jul 22 08:03:02 PM PDT 24 | Jul 22 08:03:44 PM PDT 24 | 941442414 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.163032547 | Jul 22 07:41:05 PM PDT 24 | Jul 22 07:43:35 PM PDT 24 | 4928262114 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/14.xbar_same_source.4046329007 | Jul 22 07:46:09 PM PDT 24 | Jul 22 07:47:24 PM PDT 24 | 2720733956 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3892963531 | Jul 22 07:59:51 PM PDT 24 | Jul 22 08:00:18 PM PDT 24 | 203819365 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1616087810 | Jul 22 07:58:59 PM PDT 24 | Jul 22 08:01:10 PM PDT 24 | 1590470301 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1439872607 | Jul 22 07:56:01 PM PDT 24 | Jul 22 07:56:41 PM PDT 24 | 801981208 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.59498660 | Jul 22 07:42:15 PM PDT 24 | Jul 22 07:52:24 PM PDT 24 | 7473524800 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/27.xbar_random.4304616 | Jul 22 07:50:03 PM PDT 24 | Jul 22 07:50:47 PM PDT 24 | 490885123 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/52.xbar_smoke.3169268602 | Jul 22 07:56:22 PM PDT 24 | Jul 22 07:56:33 PM PDT 24 | 199818820 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.938065183 | Jul 22 07:49:57 PM PDT 24 | Jul 22 07:51:42 PM PDT 24 | 5814733679 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2470003747 | Jul 22 07:53:23 PM PDT 24 | Jul 22 07:53:58 PM PDT 24 | 858565868 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/72.xbar_smoke.2937556310 | Jul 22 08:00:57 PM PDT 24 | Jul 22 08:01:08 PM PDT 24 | 168446260 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/86.xbar_random.1988760324 | Jul 22 08:02:47 PM PDT 24 | Jul 22 08:04:23 PM PDT 24 | 2305157755 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3621877985 | Jul 22 07:52:14 PM PDT 24 | Jul 22 07:52:37 PM PDT 24 | 190269102 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2342728359 | Jul 22 07:59:00 PM PDT 24 | Jul 22 08:06:11 PM PDT 24 | 24149838126 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1142951405 | Jul 22 07:54:37 PM PDT 24 | Jul 22 07:55:04 PM PDT 24 | 297155792 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.419071036 | Jul 22 07:59:51 PM PDT 24 | Jul 22 08:00:43 PM PDT 24 | 1425084354 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/90.xbar_error_random.2491558796 | Jul 22 08:05:17 PM PDT 24 | Jul 22 08:05:55 PM PDT 24 | 442029409 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2140236558 | Jul 22 08:02:57 PM PDT 24 | Jul 22 08:17:40 PM PDT 24 | 47563446828 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1630033263 | Jul 22 07:59:56 PM PDT 24 | Jul 22 08:35:15 PM PDT 24 | 117113542140 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1614502138 | Jul 22 07:56:42 PM PDT 24 | Jul 22 07:58:05 PM PDT 24 | 5053141802 ps | ||
| T30 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2504898819 | Jul 22 08:39:34 PM PDT 24 | Jul 22 08:44:36 PM PDT 24 | 5649548343 ps | ||
| T31 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1668305774 | Jul 22 08:39:38 PM PDT 24 | Jul 22 08:44:44 PM PDT 24 | 4216293048 ps | ||
| T32 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3973954894 | Jul 22 08:39:31 PM PDT 24 | Jul 22 08:44:44 PM PDT 24 | 5552195120 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1318469087 | Jul 22 08:40:21 PM PDT 24 | Jul 22 08:45:44 PM PDT 24 | 4227644838 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1937994191 | Jul 22 08:40:37 PM PDT 24 | Jul 22 08:45:16 PM PDT 24 | 4126376098 ps | ||
| T195 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.649717117 | Jul 22 08:39:35 PM PDT 24 | Jul 22 08:45:29 PM PDT 24 | 5087106328 ps | ||
| T196 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2220812521 | Jul 22 08:39:34 PM PDT 24 | Jul 22 08:44:42 PM PDT 24 | 4875014833 ps | ||
| T197 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1133993371 | Jul 22 08:39:31 PM PDT 24 | Jul 22 08:47:08 PM PDT 24 | 5776238886 ps | ||
| T198 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2868984450 | Jul 22 08:39:33 PM PDT 24 | Jul 22 08:43:56 PM PDT 24 | 4957612164 ps | ||
| T199 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1397018843 | Jul 22 08:39:55 PM PDT 24 | Jul 22 08:44:31 PM PDT 24 | 4331846792 ps |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3135079267 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5362898000 ps |
| CPU time | 557.89 seconds |
| Started | Jul 22 08:42:20 PM PDT 24 |
| Finished | Jul 22 08:51:38 PM PDT 24 |
| Peak memory | 650316 kb |
| Host | smart-1bcf63d6-4ac7-4496-b597-6a46ca7d9e59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3135079267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3135079267 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2865238910 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 12702944048 ps |
| CPU time | 1332.53 seconds |
| Started | Jul 22 08:25:09 PM PDT 24 |
| Finished | Jul 22 08:47:23 PM PDT 24 |
| Peak memory | 608308 kb |
| Host | smart-8d529d69-7896-4d67-9a42-0d0880284da9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865238910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2865238910 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1662567963 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 5326961071 ps |
| CPU time | 478.36 seconds |
| Started | Jul 22 07:46:50 PM PDT 24 |
| Finished | Jul 22 07:54:50 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-b868bf0a-928d-43e3-8c36-a69b26b60aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662567963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1662567963 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.3321351563 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5274118530 ps |
| CPU time | 933.22 seconds |
| Started | Jul 22 08:33:46 PM PDT 24 |
| Finished | Jul 22 08:49:20 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-070d15ef-5677-4d1d-8491-e97b60c3df3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321351563 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.3321351563 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2484826561 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 130833403521 ps |
| CPU time | 2088.58 seconds |
| Started | Jul 22 07:42:15 PM PDT 24 |
| Finished | Jul 22 08:17:05 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-f6d29983-b1b9-48c2-9717-cb32e43ed1bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484826561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2484826561 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2504898819 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5649548343 ps |
| CPU time | 300.8 seconds |
| Started | Jul 22 08:39:34 PM PDT 24 |
| Finished | Jul 22 08:44:36 PM PDT 24 |
| Peak memory | 657804 kb |
| Host | smart-42a23ade-8776-4b09-9a7e-5c4927f402ac |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504898819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2504898819 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.338374156 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 12352021110 ps |
| CPU time | 3401.77 seconds |
| Started | Jul 22 08:30:03 PM PDT 24 |
| Finished | Jul 22 09:26:46 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-ecef365b-6a7f-4caf-9b2e-eee65562755c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33837 4156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.338374156 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.648468158 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 94415842206 ps |
| CPU time | 1734.38 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 08:28:10 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-2f5d4a87-4116-46d7-8aa1-3dfdb25774cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648468158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_d evice_slow_rsp.648468158 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2232267130 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 6590665280 ps |
| CPU time | 625.43 seconds |
| Started | Jul 22 07:47:31 PM PDT 24 |
| Finished | Jul 22 07:58:01 PM PDT 24 |
| Peak memory | 599620 kb |
| Host | smart-ed9bb40c-381c-4bda-8659-cd6622d128c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232267130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2232267130 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.4008211669 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14838390864 ps |
| CPU time | 2956.53 seconds |
| Started | Jul 22 08:41:48 PM PDT 24 |
| Finished | Jul 22 09:31:06 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-3b001f70-c827-4f60-b8f5-b74b12e9b4e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4008211669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.4008211669 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.510564365 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 164544570657 ps |
| CPU time | 2805.33 seconds |
| Started | Jul 22 08:04:48 PM PDT 24 |
| Finished | Jul 22 08:51:36 PM PDT 24 |
| Peak memory | 576964 kb |
| Host | smart-ade076d9-dc2e-4fd7-94b0-024fd4580806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510564365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.510564365 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2804180213 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 25620523888 ps |
| CPU time | 2705.57 seconds |
| Started | Jul 22 08:12:46 PM PDT 24 |
| Finished | Jul 22 08:58:04 PM PDT 24 |
| Peak memory | 620152 kb |
| Host | smart-1da7e8e0-d396-4a38-89bf-176d928fc1a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2804180213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.2804180213 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2560979026 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 76800715636 ps |
| CPU time | 1406.96 seconds |
| Started | Jul 22 08:01:06 PM PDT 24 |
| Finished | Jul 22 08:24:38 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-8010e320-ab30-40e6-8fd0-43c6767ce95b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560979026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.2560979026 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.245994700 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6127207888 ps |
| CPU time | 1255.05 seconds |
| Started | Jul 22 08:30:58 PM PDT 24 |
| Finished | Jul 22 08:51:54 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-c356627b-8a1f-4475-87c6-b5eba0fe8d9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245994700 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_plic_all_irqs_0.245994700 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.9048572 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3371996555 ps |
| CPU time | 406.29 seconds |
| Started | Jul 22 08:26:25 PM PDT 24 |
| Finished | Jul 22 08:33:12 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-d8f46003-2139-4c36-ab7b-613c00c098ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9048 572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.9048572 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.411989971 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 141617329836 ps |
| CPU time | 2563.59 seconds |
| Started | Jul 22 07:52:12 PM PDT 24 |
| Finished | Jul 22 08:34:59 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-fd534563-206a-48a0-9853-240f3bd24939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411989971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_d evice_slow_rsp.411989971 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3917429534 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 11651915536 ps |
| CPU time | 1388.22 seconds |
| Started | Jul 22 08:14:33 PM PDT 24 |
| Finished | Jul 22 08:37:42 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-d1334139-d4f4-42fa-805c-539de607ae9d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917429534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3917429534 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2615870684 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 23524287864 ps |
| CPU time | 1519.64 seconds |
| Started | Jul 22 08:16:46 PM PDT 24 |
| Finished | Jul 22 08:42:06 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-171841c4-7f04-4daa-8340-562e2b502bc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2615870684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2615870684 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.45610422 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3410113220 ps |
| CPU time | 302.98 seconds |
| Started | Jul 22 08:15:13 PM PDT 24 |
| Finished | Jul 22 08:20:18 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-cb983750-d24c-4e8a-a608-e635cc102e3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=45610422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.45610422 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2310634556 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 109600553100 ps |
| CPU time | 1887.83 seconds |
| Started | Jul 22 07:55:17 PM PDT 24 |
| Finished | Jul 22 08:26:46 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-64863c79-55e7-4274-8f87-933e68dc5ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310634556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.2310634556 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.3841983930 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3499386503 ps |
| CPU time | 408.3 seconds |
| Started | Jul 22 08:28:42 PM PDT 24 |
| Finished | Jul 22 08:35:32 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-77527a54-222a-41c0-8359-e1b22558917a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841983930 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3841983930 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.569687094 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3797572108 ps |
| CPU time | 536.63 seconds |
| Started | Jul 22 08:22:48 PM PDT 24 |
| Finished | Jul 22 08:31:46 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-b4908f5c-4761-4c7b-84e0-dcea4f77ba1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569687094 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.569687094 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3437406859 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4320498489 ps |
| CPU time | 477.79 seconds |
| Started | Jul 22 07:43:27 PM PDT 24 |
| Finished | Jul 22 07:51:25 PM PDT 24 |
| Peak memory | 604384 kb |
| Host | smart-66a6a58c-70c4-4e91-a5c5-650858c27424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437406859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3437406859 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.910749980 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 5834925578 ps |
| CPU time | 680.01 seconds |
| Started | Jul 22 07:53:12 PM PDT 24 |
| Finished | Jul 22 08:04:34 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-e78fd236-c609-4ac6-8042-3a5ffdffdc5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910749980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_ with_rand_reset.910749980 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.836211628 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 21920265472 ps |
| CPU time | 4541.17 seconds |
| Started | Jul 22 08:38:27 PM PDT 24 |
| Finished | Jul 22 09:54:09 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-3aefe3fb-a9df-4630-8822-500e5b9e53fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836211628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.836211628 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.1642227403 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 14871154655 ps |
| CPU time | 579.74 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:12:49 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-1e5d209f-8877-4613-9111-8a6d61b7247d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642227403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1642227403 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2171499727 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4305737198 ps |
| CPU time | 275.64 seconds |
| Started | Jul 22 07:56:25 PM PDT 24 |
| Finished | Jul 22 08:01:02 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-bec1ff2c-d423-4b28-8a36-30a39a12a6ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171499727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.2171499727 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2838640373 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 23514435211 ps |
| CPU time | 5959.99 seconds |
| Started | Jul 22 08:24:56 PM PDT 24 |
| Finished | Jul 22 10:04:17 PM PDT 24 |
| Peak memory | 611432 kb |
| Host | smart-0a2e88b5-0a05-4f41-9b3c-9f5814367bd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2838640373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2838640373 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.301893962 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 57740739950 ps |
| CPU time | 10491.3 seconds |
| Started | Jul 22 08:18:10 PM PDT 24 |
| Finished | Jul 22 11:13:03 PM PDT 24 |
| Peak memory | 625248 kb |
| Host | smart-e2d0a8c7-3055-45cb-90fd-ed7d388cb4a0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=301893962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.301893962 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2886093974 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 44632089056 ps |
| CPU time | 4706.7 seconds |
| Started | Jul 22 08:15:11 PM PDT 24 |
| Finished | Jul 22 09:33:40 PM PDT 24 |
| Peak memory | 621176 kb |
| Host | smart-a7c4531e-4b4b-4ce9-a30e-9865e66b5f02 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2886093974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.2886093974 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.494263185 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 9951167200 ps |
| CPU time | 718.04 seconds |
| Started | Jul 22 07:47:33 PM PDT 24 |
| Finished | Jul 22 07:59:35 PM PDT 24 |
| Peak memory | 646472 kb |
| Host | smart-fd0e50f6-8e24-48b1-8ad0-435610b44baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494263185 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.494263185 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.107556322 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 25013235560 ps |
| CPU time | 1800.09 seconds |
| Started | Jul 22 08:19:31 PM PDT 24 |
| Finished | Jul 22 08:49:32 PM PDT 24 |
| Peak memory | 614816 kb |
| Host | smart-046f2882-4aff-47b5-b80a-8dc9f34c95e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10755632 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.107556322 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2790748968 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4899549064 ps |
| CPU time | 498.76 seconds |
| Started | Jul 22 08:23:32 PM PDT 24 |
| Finished | Jul 22 08:31:52 PM PDT 24 |
| Peak memory | 611220 kb |
| Host | smart-66299a2c-99af-4049-8735-eb275562fe87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790748968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2790748968 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2722274237 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5415670260 ps |
| CPU time | 361.9 seconds |
| Started | Jul 22 08:12:02 PM PDT 24 |
| Finished | Jul 22 08:18:05 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-54ca59da-7890-4aba-8617-b6e523d2ecdc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222742 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2722274237 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2804439411 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3440298765 ps |
| CPU time | 331.82 seconds |
| Started | Jul 22 08:11:14 PM PDT 24 |
| Finished | Jul 22 08:16:48 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-9b29d324-4981-4c6c-a195-b0db4522e251 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804 439411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2804439411 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.100233586 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 107822648041 ps |
| CPU time | 1076.11 seconds |
| Started | Jul 22 07:46:04 PM PDT 24 |
| Finished | Jul 22 08:04:01 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-1f08c85c-635e-4f2a-ab06-d6864e1f7564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100233586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.100233586 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1265554729 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 9805881976 ps |
| CPU time | 1747.06 seconds |
| Started | Jul 22 08:27:22 PM PDT 24 |
| Finished | Jul 22 08:56:30 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-af40381b-1800-427d-91f2-36a99a8b0e94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1265554729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1265554729 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.604751603 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 5479310854 ps |
| CPU time | 579.7 seconds |
| Started | Jul 22 08:30:15 PM PDT 24 |
| Finished | Jul 22 08:39:55 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-3c2f311e-70aa-4121-bb3f-8acbb8466650 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60 4751603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.604751603 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2432026553 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5269450992 ps |
| CPU time | 538.73 seconds |
| Started | Jul 22 08:41:08 PM PDT 24 |
| Finished | Jul 22 08:50:09 PM PDT 24 |
| Peak memory | 620088 kb |
| Host | smart-0927704b-d675-4769-bba7-d40dd98297dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2432026553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2432026553 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1234841300 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4522525354 ps |
| CPU time | 356.91 seconds |
| Started | Jul 22 07:47:02 PM PDT 24 |
| Finished | Jul 22 07:52:59 PM PDT 24 |
| Peak memory | 604268 kb |
| Host | smart-d75d9d1c-95a7-4231-989e-4825d3466a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234841300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1234841300 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3645536561 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3399522392 ps |
| CPU time | 122.97 seconds |
| Started | Jul 22 08:01:07 PM PDT 24 |
| Finished | Jul 22 08:03:14 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-e5e48daa-ef0b-43e9-9ba7-18443d0c39c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645536561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3645536561 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3509736506 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4589143613 ps |
| CPU time | 636.32 seconds |
| Started | Jul 22 08:19:47 PM PDT 24 |
| Finished | Jul 22 08:30:25 PM PDT 24 |
| Peak memory | 625348 kb |
| Host | smart-9c47558c-af0d-414a-917e-c43d9160def6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509736506 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3509736506 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.151534738 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5688406528 ps |
| CPU time | 762.47 seconds |
| Started | Jul 22 08:39:31 PM PDT 24 |
| Finished | Jul 22 08:52:15 PM PDT 24 |
| Peak memory | 650464 kb |
| Host | smart-820d7ce4-890f-41ed-8d3f-e21054494532 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 151534738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.151534738 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2798742279 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3488982360 ps |
| CPU time | 339.38 seconds |
| Started | Jul 22 08:45:49 PM PDT 24 |
| Finished | Jul 22 08:51:30 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-44654441-bb02-4b0d-84d1-644e7d0b687f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798742279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2798742279 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.724239610 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3145848547 ps |
| CPU time | 376.58 seconds |
| Started | Jul 22 08:17:05 PM PDT 24 |
| Finished | Jul 22 08:23:23 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-e14f977f-bdc5-4f13-9a83-ce77797f6771 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7242 39610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.724239610 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2768874988 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 5761707800 ps |
| CPU time | 911.21 seconds |
| Started | Jul 22 08:18:50 PM PDT 24 |
| Finished | Jul 22 08:34:03 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-ef8002e8-0235-45d3-aa3f-72943d1bc93f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2768874988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2768874988 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.3762657796 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3977788217 ps |
| CPU time | 291.85 seconds |
| Started | Jul 22 07:42:13 PM PDT 24 |
| Finished | Jul 22 07:47:06 PM PDT 24 |
| Peak memory | 597876 kb |
| Host | smart-14db7e81-0e3c-4e81-9618-aacf1b6f0e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762657796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3762657796 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3320782421 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5676613900 ps |
| CPU time | 631.77 seconds |
| Started | Jul 22 08:34:21 PM PDT 24 |
| Finished | Jul 22 08:44:54 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-f2f3addd-eb60-42cd-8526-3d8368941c47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320782421 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3320782421 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2775252844 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2949971696 ps |
| CPU time | 272.65 seconds |
| Started | Jul 22 08:11:04 PM PDT 24 |
| Finished | Jul 22 08:15:40 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-76e8082b-b38a-4c1d-97f7-008a91458dde |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775252844 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2775252844 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.343608977 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5399236696 ps |
| CPU time | 458.72 seconds |
| Started | Jul 22 08:39:29 PM PDT 24 |
| Finished | Jul 22 08:47:08 PM PDT 24 |
| Peak memory | 651756 kb |
| Host | smart-d325ed50-665e-43b4-b0f3-57033f1eae11 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 343608977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.343608977 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2859161396 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7604266081 ps |
| CPU time | 1087.5 seconds |
| Started | Jul 22 08:20:26 PM PDT 24 |
| Finished | Jul 22 08:38:34 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-695e2e29-69de-41cc-bd0d-dbb982cd6fc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859161396 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2859161396 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.4063287308 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 5634983780 ps |
| CPU time | 711.31 seconds |
| Started | Jul 22 08:42:44 PM PDT 24 |
| Finished | Jul 22 08:54:36 PM PDT 24 |
| Peak memory | 650400 kb |
| Host | smart-74742e85-df6c-40d6-b174-358626c23d29 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4063287308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4063287308 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3941159912 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 6020510464 ps |
| CPU time | 726.56 seconds |
| Started | Jul 22 08:45:46 PM PDT 24 |
| Finished | Jul 22 08:57:54 PM PDT 24 |
| Peak memory | 650060 kb |
| Host | smart-f0a9fb39-c21e-45b2-b06e-73cbbaab871f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3941159912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3941159912 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.4241036217 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3882084725 ps |
| CPU time | 279.43 seconds |
| Started | Jul 22 07:41:33 PM PDT 24 |
| Finished | Jul 22 07:46:14 PM PDT 24 |
| Peak memory | 598468 kb |
| Host | smart-35dae3de-5e3a-43cc-9a64-9fbce3525ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241036217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.4241036217 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.558895628 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 82917914077 ps |
| CPU time | 1548 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:25:55 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-2579b96c-f350-4249-890b-438a2f401969 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558895628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_d evice_slow_rsp.558895628 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.1367914967 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3270561180 ps |
| CPU time | 192.15 seconds |
| Started | Jul 22 08:22:08 PM PDT 24 |
| Finished | Jul 22 08:25:21 PM PDT 24 |
| Peak memory | 624216 kb |
| Host | smart-1c5a7ea0-de93-4fae-b852-b97d249e6a15 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367914967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1367914967 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.495685754 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7320259323 ps |
| CPU time | 364.21 seconds |
| Started | Jul 22 07:41:23 PM PDT 24 |
| Finished | Jul 22 07:47:29 PM PDT 24 |
| Peak memory | 664656 kb |
| Host | smart-624a6713-b0b3-4e3b-8f6d-67127e5cc8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495685754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.495685754 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.626436189 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4697902240 ps |
| CPU time | 733.5 seconds |
| Started | Jul 22 08:12:44 PM PDT 24 |
| Finished | Jul 22 08:25:11 PM PDT 24 |
| Peak memory | 611500 kb |
| Host | smart-abcf5c5a-f32d-4673-b04a-0705a00439de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=626436189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.626436189 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2504852580 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 5458439564 ps |
| CPU time | 1264.13 seconds |
| Started | Jul 22 08:19:06 PM PDT 24 |
| Finished | Jul 22 08:40:11 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-c2b9f56a-592f-4095-9aeb-f49aa0398fee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504852580 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2504852580 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2273648911 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3218944152 ps |
| CPU time | 279.49 seconds |
| Started | Jul 22 08:14:56 PM PDT 24 |
| Finished | Jul 22 08:19:36 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-c1d5ae64-5ad0-4f0b-8f30-17723f4b6de3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273648911 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2273648911 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1040548237 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6357385800 ps |
| CPU time | 939.3 seconds |
| Started | Jul 22 08:26:16 PM PDT 24 |
| Finished | Jul 22 08:41:56 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-88cf85e8-1b01-47c9-af6d-6acf31cbd6d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405482 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1040548237 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1844364812 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 48077939820 ps |
| CPU time | 5690.23 seconds |
| Started | Jul 22 08:19:45 PM PDT 24 |
| Finished | Jul 22 09:54:37 PM PDT 24 |
| Peak memory | 620680 kb |
| Host | smart-dc34cdf3-127c-443e-9fc1-882a3e858d10 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844364812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.1844364812 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.799302714 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8978525580 ps |
| CPU time | 2018.66 seconds |
| Started | Jul 22 08:18:25 PM PDT 24 |
| Finished | Jul 22 08:52:04 PM PDT 24 |
| Peak memory | 619260 kb |
| Host | smart-f30e05cf-22c1-4b94-86c0-91e9b027cc90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799302714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq.799302714 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1855675277 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2695509240 ps |
| CPU time | 336.05 seconds |
| Started | Jul 22 08:23:18 PM PDT 24 |
| Finished | Jul 22 08:28:55 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-5213f0eb-454a-4c54-a8fb-029d373dee75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855675277 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1855675277 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.165440013 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3232313868 ps |
| CPU time | 295.42 seconds |
| Started | Jul 22 08:19:37 PM PDT 24 |
| Finished | Jul 22 08:24:33 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-959a0960-b977-4a7e-884f-9ae6b2e042d0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165440013 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.165440013 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.673768351 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3814419353 ps |
| CPU time | 536.38 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 08:02:50 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-d41c985b-7a52-419e-83cd-4ffaa663d701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673768351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_ with_rand_reset.673768351 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2184138476 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7632942140 ps |
| CPU time | 1644.79 seconds |
| Started | Jul 22 08:27:23 PM PDT 24 |
| Finished | Jul 22 08:54:50 PM PDT 24 |
| Peak memory | 618916 kb |
| Host | smart-7582d609-bf23-4007-8490-3d7d60910e64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2184138476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.2184138476 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1683316343 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2650772640 ps |
| CPU time | 305.92 seconds |
| Started | Jul 22 08:16:58 PM PDT 24 |
| Finished | Jul 22 08:22:05 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-f9612361-d3b5-4070-acfa-29ed6557c226 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683316343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1683316343 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1734665164 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3576938563 ps |
| CPU time | 276.89 seconds |
| Started | Jul 22 08:12:59 PM PDT 24 |
| Finished | Jul 22 08:17:40 PM PDT 24 |
| Peak memory | 618372 kb |
| Host | smart-c5da192b-1a46-4343-8c71-c58de03759d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734665164 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.1734665164 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.849553812 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 6098037203 ps |
| CPU time | 520.8 seconds |
| Started | Jul 22 07:44:42 PM PDT 24 |
| Finished | Jul 22 07:53:25 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-9373bf0e-4fd3-4e18-9a43-dd66199c2a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849553812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.849553812 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.2293776444 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6315671460 ps |
| CPU time | 1512.88 seconds |
| Started | Jul 22 08:22:03 PM PDT 24 |
| Finished | Jul 22 08:47:16 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-961ffc18-90cf-417e-8413-69dfe0d30ef9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293776444 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.2293776444 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1494120646 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4080838086 ps |
| CPU time | 414.21 seconds |
| Started | Jul 22 08:10:38 PM PDT 24 |
| Finished | Jul 22 08:17:34 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-0885b49a-f57e-4e83-b39e-ce5fe14fee1f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149412 0646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1494120646 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2104230925 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 45191604781 ps |
| CPU time | 5089.11 seconds |
| Started | Jul 22 08:11:25 PM PDT 24 |
| Finished | Jul 22 09:36:16 PM PDT 24 |
| Peak memory | 623152 kb |
| Host | smart-53ce0b4a-0fc8-4bdb-a104-a5dfc6f600ab |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2104230925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.2104230925 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2794678176 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 15170380663 ps |
| CPU time | 1573.43 seconds |
| Started | Jul 22 07:41:16 PM PDT 24 |
| Finished | Jul 22 08:07:31 PM PDT 24 |
| Peak memory | 593700 kb |
| Host | smart-749a91ef-fc48-423c-9367-642e0aead376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794678176 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2794678176 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3814947306 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 5461729100 ps |
| CPU time | 610.64 seconds |
| Started | Jul 22 07:59:52 PM PDT 24 |
| Finished | Jul 22 08:10:05 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-7f33a97e-6aef-4458-a796-c2ce655e9180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814947306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3814947306 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1541716005 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 25037518480 ps |
| CPU time | 3437.44 seconds |
| Started | Jul 22 08:27:02 PM PDT 24 |
| Finished | Jul 22 09:24:21 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-44b1f526-52b7-4716-ba74-35cc3a8f4ca2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541716005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1541716005 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1653445770 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3442867457 ps |
| CPU time | 137.71 seconds |
| Started | Jul 22 08:17:09 PM PDT 24 |
| Finished | Jul 22 08:19:28 PM PDT 24 |
| Peak memory | 619904 kb |
| Host | smart-f27100be-3524-4a17-b401-bbc75c5f8c14 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534457 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1653445770 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.2544632981 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4899783644 ps |
| CPU time | 912.81 seconds |
| Started | Jul 22 08:14:18 PM PDT 24 |
| Finished | Jul 22 08:29:33 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-74b3ada9-1a2d-4012-b946-87cfcb1eb40e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544632981 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.2544632981 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2083550062 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5610767268 ps |
| CPU time | 551.17 seconds |
| Started | Jul 22 07:46:04 PM PDT 24 |
| Finished | Jul 22 07:55:17 PM PDT 24 |
| Peak memory | 604408 kb |
| Host | smart-455cad5c-3066-4912-afd4-65480ff47297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083550062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2083550062 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3479986070 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4054715083 ps |
| CPU time | 732.61 seconds |
| Started | Jul 22 08:28:46 PM PDT 24 |
| Finished | Jul 22 08:41:00 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-a6174ba1-c3d6-426b-8d8f-34123a298dca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3479986070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.3479986070 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1594315734 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 6574673010 ps |
| CPU time | 901.67 seconds |
| Started | Jul 22 08:03:09 PM PDT 24 |
| Finished | Jul 22 08:18:16 PM PDT 24 |
| Peak memory | 583308 kb |
| Host | smart-07e799fd-4e06-4422-b779-d3ed13f74abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594315734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1594315734 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.862173615 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 10716957376 ps |
| CPU time | 801.87 seconds |
| Started | Jul 22 07:42:41 PM PDT 24 |
| Finished | Jul 22 07:56:03 PM PDT 24 |
| Peak memory | 653584 kb |
| Host | smart-5a068738-fba5-47a9-b9a1-9d6bd474958c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862173615 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.862173615 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1997903662 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5731303674 ps |
| CPU time | 808 seconds |
| Started | Jul 22 08:35:27 PM PDT 24 |
| Finished | Jul 22 08:48:56 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-9b94a8c6-a465-4517-9488-b9f0e988dad7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19979036 62 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1997903662 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2088605821 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 25851679191 ps |
| CPU time | 1526.52 seconds |
| Started | Jul 22 08:37:10 PM PDT 24 |
| Finished | Jul 22 09:02:38 PM PDT 24 |
| Peak memory | 617608 kb |
| Host | smart-ed6c1436-4355-40bd-8798-c9c2a27fb3f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2088605821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2088605821 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.31635816 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 10794017755 ps |
| CPU time | 385.06 seconds |
| Started | Jul 22 07:53:40 PM PDT 24 |
| Finished | Jul 22 08:00:06 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-5741dd24-7423-48c1-8035-cfcd2832a8f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.31635816 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3632248519 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2247430275 ps |
| CPU time | 208.82 seconds |
| Started | Jul 22 07:57:39 PM PDT 24 |
| Finished | Jul 22 08:01:10 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-39fc7cc1-79f9-41c5-b581-5ddcf5937dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632248519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.3632248519 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1442393152 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2652237288 ps |
| CPU time | 129.55 seconds |
| Started | Jul 22 08:17:35 PM PDT 24 |
| Finished | Jul 22 08:19:45 PM PDT 24 |
| Peak memory | 621196 kb |
| Host | smart-fe7cab26-2d43-44cd-84d3-99c1d1daeb53 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442393152 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1442393152 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.660759963 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3695223983 ps |
| CPU time | 313.03 seconds |
| Started | Jul 22 07:50:19 PM PDT 24 |
| Finished | Jul 22 07:55:37 PM PDT 24 |
| Peak memory | 599928 kb |
| Host | smart-a935ea91-3de2-4ea1-b2f1-c953283dd30f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660759963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.660759963 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.134294558 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4007042000 ps |
| CPU time | 645.56 seconds |
| Started | Jul 22 08:17:16 PM PDT 24 |
| Finished | Jul 22 08:28:03 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-4d547045-042a-4765-83cb-30122ec0437d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134294558 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.134294558 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.1822124018 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3922661780 ps |
| CPU time | 601.3 seconds |
| Started | Jul 22 08:13:38 PM PDT 24 |
| Finished | Jul 22 08:23:40 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-3ed76953-5559-4c86-b7f3-263cc3602db6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822124018 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1822124018 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3654261043 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3744070130 ps |
| CPU time | 345.04 seconds |
| Started | Jul 22 08:44:44 PM PDT 24 |
| Finished | Jul 22 08:50:30 PM PDT 24 |
| Peak memory | 649176 kb |
| Host | smart-37cd8398-0f5d-4dde-b291-e5cc63771fe4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654261043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3654261043 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.487463268 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 21786924090 ps |
| CPU time | 1014.35 seconds |
| Started | Jul 22 07:57:12 PM PDT 24 |
| Finished | Jul 22 08:14:08 PM PDT 24 |
| Peak memory | 583188 kb |
| Host | smart-b37791ef-35ae-4076-aacb-7439315f2e2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487463268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_reset_error.487463268 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1874090786 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 13284084349 ps |
| CPU time | 1658.53 seconds |
| Started | Jul 22 08:26:05 PM PDT 24 |
| Finished | Jul 22 08:53:45 PM PDT 24 |
| Peak memory | 618872 kb |
| Host | smart-4abaf8e9-aa93-418d-ad8d-7f47fd65d299 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874090786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1874090786 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.3914524439 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3820278860 ps |
| CPU time | 294.8 seconds |
| Started | Jul 22 07:48:47 PM PDT 24 |
| Finished | Jul 22 07:53:44 PM PDT 24 |
| Peak memory | 599324 kb |
| Host | smart-c8c95b7a-14d6-4cfb-80f7-4867aaec7563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914524439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3914524439 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2603857093 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4455157228 ps |
| CPU time | 941.76 seconds |
| Started | Jul 22 08:26:14 PM PDT 24 |
| Finished | Jul 22 08:41:58 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-356a8d6c-677f-4117-929e-a2a02b236ee1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603857093 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2603857093 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.367376077 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 4786321976 ps |
| CPU time | 689.04 seconds |
| Started | Jul 22 08:15:55 PM PDT 24 |
| Finished | Jul 22 08:27:25 PM PDT 24 |
| Peak memory | 613472 kb |
| Host | smart-c6961ebe-1c04-4fe0-9e10-8cecd8096a8a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367376077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.367376077 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3785339743 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2123420246 ps |
| CPU time | 501.21 seconds |
| Started | Jul 22 07:46:29 PM PDT 24 |
| Finished | Jul 22 07:54:52 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-e111fd9c-f1c2-4018-83a9-b5af83cac085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785339743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3785339743 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.25278476 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 8328936344 ps |
| CPU time | 364.07 seconds |
| Started | Jul 22 07:42:11 PM PDT 24 |
| Finished | Jul 22 07:48:16 PM PDT 24 |
| Peak memory | 665824 kb |
| Host | smart-365adf15-8d06-41a7-b55a-246d335e17b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25278476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_res et.25278476 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1952516464 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 11758859100 ps |
| CPU time | 2507.09 seconds |
| Started | Jul 22 08:18:16 PM PDT 24 |
| Finished | Jul 22 09:00:05 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-806794aa-a9ed-4ca0-a832-1bd7cc8e5dbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525 16464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1952516464 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1829848966 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3970007002 ps |
| CPU time | 354.25 seconds |
| Started | Jul 22 08:14:44 PM PDT 24 |
| Finished | Jul 22 08:20:40 PM PDT 24 |
| Peak memory | 619600 kb |
| Host | smart-ce43b273-6b83-43b4-ab50-748dfe3fbbf7 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182984 8966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1829848966 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2313189851 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4332914201 ps |
| CPU time | 569.54 seconds |
| Started | Jul 22 07:57:05 PM PDT 24 |
| Finished | Jul 22 08:06:36 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-0b8da16b-ba1c-4a1d-b60f-f31a5d227bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313189851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.2313189851 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1998835867 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3936056783 ps |
| CPU time | 499.56 seconds |
| Started | Jul 22 07:49:16 PM PDT 24 |
| Finished | Jul 22 07:57:36 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-11bb684e-108a-4b8a-9e75-c2005b0f8ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998835867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1998835867 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.517881660 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 8372785742 ps |
| CPU time | 476.82 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:11:04 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-98a2d384-70f1-4fb7-906e-2c15acb60f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517881660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_reset_error.517881660 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.649985984 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 7930548041 ps |
| CPU time | 515.86 seconds |
| Started | Jul 22 08:39:09 PM PDT 24 |
| Finished | Jul 22 08:47:46 PM PDT 24 |
| Peak memory | 622912 kb |
| Host | smart-40524d02-cbff-4ff0-acb7-ac9b125c8831 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649985984 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.649985984 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3606172093 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 43808537012 ps |
| CPU time | 4570.74 seconds |
| Started | Jul 22 08:30:24 PM PDT 24 |
| Finished | Jul 22 09:46:36 PM PDT 24 |
| Peak memory | 621376 kb |
| Host | smart-f1c998fd-6d24-419e-90e4-446762e52e01 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3606172093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3606172093 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2868838938 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4000508104 ps |
| CPU time | 571.92 seconds |
| Started | Jul 22 08:31:06 PM PDT 24 |
| Finished | Jul 22 08:40:38 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-d8f13656-3f5d-452c-9205-db0944107d2a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868838938 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2868838938 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.521938260 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 483360415 ps |
| CPU time | 187.61 seconds |
| Started | Jul 22 07:44:54 PM PDT 24 |
| Finished | Jul 22 07:48:03 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-9e5e7c84-45b1-4f16-9d2d-63723deb9d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521938260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w ith_rand_reset.521938260 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2168897888 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 5972906949 ps |
| CPU time | 379.72 seconds |
| Started | Jul 22 07:58:19 PM PDT 24 |
| Finished | Jul 22 08:04:42 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-e6aebc04-e3ed-4fab-be01-9350f6080f10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168897888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2168897888 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.2674976340 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4825843580 ps |
| CPU time | 583.03 seconds |
| Started | Jul 22 08:40:28 PM PDT 24 |
| Finished | Jul 22 08:50:14 PM PDT 24 |
| Peak memory | 650400 kb |
| Host | smart-de54fdf1-54ca-4557-8768-e2d2c6e4cdd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2674976340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2674976340 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.852852947 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3928315208 ps |
| CPU time | 761.97 seconds |
| Started | Jul 22 08:26:42 PM PDT 24 |
| Finished | Jul 22 08:39:26 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-9a41e1b7-3321-470a-8218-50ae2a8ecc21 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852852947 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.852852947 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2661177495 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3284923697 ps |
| CPU time | 211.13 seconds |
| Started | Jul 22 07:49:19 PM PDT 24 |
| Finished | Jul 22 07:52:51 PM PDT 24 |
| Peak memory | 598144 kb |
| Host | smart-10c8e679-d381-49fe-b4b2-15245afdeb7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661177495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2661177495 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3560168728 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3124105506 ps |
| CPU time | 339.46 seconds |
| Started | Jul 22 08:14:39 PM PDT 24 |
| Finished | Jul 22 08:20:19 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-a66cd9d7-440f-4c17-8926-30390a57a0c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560168728 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3560168728 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.873865676 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2748376747 ps |
| CPU time | 110.39 seconds |
| Started | Jul 22 08:12:35 PM PDT 24 |
| Finished | Jul 22 08:14:30 PM PDT 24 |
| Peak memory | 621244 kb |
| Host | smart-d865a990-7576-487f-abd1-01f98df5348e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873865676 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.873865676 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2272679599 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3377037032 ps |
| CPU time | 358.92 seconds |
| Started | Jul 22 08:12:25 PM PDT 24 |
| Finished | Jul 22 08:18:25 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-850346e9-771d-4fa2-be28-a36aa0142eee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272679599 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2272679599 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2262935027 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 114503059136 ps |
| CPU time | 1910.97 seconds |
| Started | Jul 22 07:47:40 PM PDT 24 |
| Finished | Jul 22 08:19:32 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-c1610ca0-4d7b-4038-9f39-12d175456009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262935027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2262935027 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1136368841 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5947914296 ps |
| CPU time | 780.15 seconds |
| Started | Jul 22 08:41:27 PM PDT 24 |
| Finished | Jul 22 08:54:29 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-e7c93fb1-ed1c-4dd4-82a7-866fc17a5851 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1136368841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1136368841 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.3044361181 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 4747124468 ps |
| CPU time | 753.96 seconds |
| Started | Jul 22 08:44:23 PM PDT 24 |
| Finished | Jul 22 08:56:57 PM PDT 24 |
| Peak memory | 651096 kb |
| Host | smart-04348999-96db-4721-a8ae-adc2343f24ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3044361181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3044361181 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.2716408062 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7700568104 ps |
| CPU time | 1931.6 seconds |
| Started | Jul 22 08:12:12 PM PDT 24 |
| Finished | Jul 22 08:44:25 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-39520998-a667-4c62-8e9f-4c9a1705f9f1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27164 08062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2716408062 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.842130003 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4381077656 ps |
| CPU time | 770.96 seconds |
| Started | Jul 22 08:27:11 PM PDT 24 |
| Finished | Jul 22 08:40:03 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-c8a1aed3-9e67-490f-9a88-794f3c27beaf |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842130003 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.842130003 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1464986998 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 8803490228 ps |
| CPU time | 462.12 seconds |
| Started | Jul 22 07:41:25 PM PDT 24 |
| Finished | Jul 22 07:49:09 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-be07890b-0cfa-4393-8659-9a06448e5b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464986998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.1464986998 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2229202618 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 12262608256 ps |
| CPU time | 498.3 seconds |
| Started | Jul 22 07:44:43 PM PDT 24 |
| Finished | Jul 22 07:53:04 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-f36a547c-c470-4ddc-aab3-c710681d93cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229202618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.2229202618 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2222788651 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3736494152 ps |
| CPU time | 396.76 seconds |
| Started | Jul 22 08:13:13 PM PDT 24 |
| Finished | Jul 22 08:19:51 PM PDT 24 |
| Peak memory | 648984 kb |
| Host | smart-e5e5f6b2-f942-4d6a-a656-1e160a1694a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222788651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2222788651 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2365213859 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5318795830 ps |
| CPU time | 700.59 seconds |
| Started | Jul 22 08:10:05 PM PDT 24 |
| Finished | Jul 22 08:21:47 PM PDT 24 |
| Peak memory | 650728 kb |
| Host | smart-f8edf30e-f583-408e-8dba-b4bdf3a56917 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2365213859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2365213859 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3182610742 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3766808580 ps |
| CPU time | 323.79 seconds |
| Started | Jul 22 08:17:15 PM PDT 24 |
| Finished | Jul 22 08:22:39 PM PDT 24 |
| Peak memory | 649244 kb |
| Host | smart-403408ba-66ee-41de-bbdd-4cac3c68992f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182610742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3182610742 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1430209838 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4701693540 ps |
| CPU time | 546.54 seconds |
| Started | Jul 22 08:15:06 PM PDT 24 |
| Finished | Jul 22 08:24:14 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-e86f46b8-4b4f-4483-bbad-ad02e4032b84 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1430209838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1430209838 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1816054021 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4386383000 ps |
| CPU time | 455.11 seconds |
| Started | Jul 22 08:38:13 PM PDT 24 |
| Finished | Jul 22 08:45:49 PM PDT 24 |
| Peak memory | 649248 kb |
| Host | smart-9b407ca6-b2f0-4141-8f15-cde712b6c7cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816054021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1816054021 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.2333361061 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 6360693400 ps |
| CPU time | 769.59 seconds |
| Started | Jul 22 08:40:03 PM PDT 24 |
| Finished | Jul 22 08:52:55 PM PDT 24 |
| Peak memory | 650560 kb |
| Host | smart-3ec87952-912d-4268-9e70-e1f448cf5776 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2333361061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2333361061 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4267778292 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3640421760 ps |
| CPU time | 444.29 seconds |
| Started | Jul 22 08:38:45 PM PDT 24 |
| Finished | Jul 22 08:46:13 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-76976333-00c1-43df-bafa-84c60ee791e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267778292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4267778292 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.1385862554 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3967886386 ps |
| CPU time | 604.05 seconds |
| Started | Jul 22 08:38:08 PM PDT 24 |
| Finished | Jul 22 08:48:14 PM PDT 24 |
| Peak memory | 650328 kb |
| Host | smart-b009d68c-cf32-41dd-ad2f-805af2284576 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1385862554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.1385862554 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2687852536 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3588522880 ps |
| CPU time | 428.92 seconds |
| Started | Jul 22 08:40:55 PM PDT 24 |
| Finished | Jul 22 08:48:05 PM PDT 24 |
| Peak memory | 649192 kb |
| Host | smart-245eb6a2-9764-418b-8da6-7c6161ba3546 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687852536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2687852536 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.1538149424 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5170386888 ps |
| CPU time | 550.73 seconds |
| Started | Jul 22 08:37:59 PM PDT 24 |
| Finished | Jul 22 08:47:10 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-7064547b-9e03-4c82-b447-6f69bfde331d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1538149424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1538149424 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.263933683 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3912943212 ps |
| CPU time | 527.42 seconds |
| Started | Jul 22 08:39:46 PM PDT 24 |
| Finished | Jul 22 08:48:34 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-ec958042-3a07-4383-952b-93bc977862ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263933683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.263933683 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1394420740 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 5082485048 ps |
| CPU time | 551.23 seconds |
| Started | Jul 22 08:39:38 PM PDT 24 |
| Finished | Jul 22 08:48:50 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-7a1f14c6-9b2c-4f08-8010-5badb47dcdde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1394420740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1394420740 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2969633271 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3973094516 ps |
| CPU time | 461.13 seconds |
| Started | Jul 22 08:38:44 PM PDT 24 |
| Finished | Jul 22 08:46:29 PM PDT 24 |
| Peak memory | 649204 kb |
| Host | smart-82918689-fa07-42e0-8384-04ef067b142a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969633271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2969633271 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.1720088116 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 4280226656 ps |
| CPU time | 583.46 seconds |
| Started | Jul 22 08:39:31 PM PDT 24 |
| Finished | Jul 22 08:49:16 PM PDT 24 |
| Peak memory | 649856 kb |
| Host | smart-e1790d41-a599-42ae-9c48-012a6a62cafa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1720088116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1720088116 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1072194116 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3895750368 ps |
| CPU time | 356.3 seconds |
| Started | Jul 22 08:39:27 PM PDT 24 |
| Finished | Jul 22 08:45:24 PM PDT 24 |
| Peak memory | 649272 kb |
| Host | smart-a2f69948-09e1-4c05-bd6a-f83bff015aa9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072194116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1072194116 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452928213 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4173722444 ps |
| CPU time | 451.12 seconds |
| Started | Jul 22 08:39:38 PM PDT 24 |
| Finished | Jul 22 08:47:10 PM PDT 24 |
| Peak memory | 648968 kb |
| Host | smart-546a41d8-1f20-487c-9936-56ce2fc69f8e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452928213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2452928213 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.46267746 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5198535456 ps |
| CPU time | 760.22 seconds |
| Started | Jul 22 08:39:41 PM PDT 24 |
| Finished | Jul 22 08:52:23 PM PDT 24 |
| Peak memory | 650452 kb |
| Host | smart-f20688b2-e101-4a4c-83a4-fcd86c7a45d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 46267746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.46267746 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.225278617 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5842414756 ps |
| CPU time | 806.83 seconds |
| Started | Jul 22 08:39:58 PM PDT 24 |
| Finished | Jul 22 08:53:27 PM PDT 24 |
| Peak memory | 650564 kb |
| Host | smart-307fb85a-4778-4715-9683-14ce6808eaaf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 225278617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.225278617 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1704913605 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3274385104 ps |
| CPU time | 448.9 seconds |
| Started | Jul 22 08:29:55 PM PDT 24 |
| Finished | Jul 22 08:37:26 PM PDT 24 |
| Peak memory | 649112 kb |
| Host | smart-2fb914f8-601f-4e88-9564-0702bbe9d1dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704913605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.1704913605 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2960681012 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3836630824 ps |
| CPU time | 367.79 seconds |
| Started | Jul 22 08:41:05 PM PDT 24 |
| Finished | Jul 22 08:47:13 PM PDT 24 |
| Peak memory | 649044 kb |
| Host | smart-6195d082-f21e-45bb-bfe7-df109d806938 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960681012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2960681012 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1436124775 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3415583424 ps |
| CPU time | 341.28 seconds |
| Started | Jul 22 08:42:00 PM PDT 24 |
| Finished | Jul 22 08:47:43 PM PDT 24 |
| Peak memory | 648884 kb |
| Host | smart-37bcaf49-0f80-428e-9162-4fde12e2bd8c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436124775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1436124775 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.788593483 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5660556452 ps |
| CPU time | 540.01 seconds |
| Started | Jul 22 08:41:20 PM PDT 24 |
| Finished | Jul 22 08:50:22 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-afb18ee5-69b5-41cf-a617-335ccfc6eb1f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 788593483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.788593483 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.693445540 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3324365082 ps |
| CPU time | 417.45 seconds |
| Started | Jul 22 08:41:30 PM PDT 24 |
| Finished | Jul 22 08:48:29 PM PDT 24 |
| Peak memory | 649076 kb |
| Host | smart-81d4318b-ffc3-4636-99a5-c6dea6adb71f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693445540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.693445540 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.52869925 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3589538820 ps |
| CPU time | 394.3 seconds |
| Started | Jul 22 08:40:04 PM PDT 24 |
| Finished | Jul 22 08:46:40 PM PDT 24 |
| Peak memory | 649212 kb |
| Host | smart-2f7f4427-14ad-4dc6-aaf3-278f15e9d09f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52869925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw _alert_handler_lpg_sleep_mode_alerts.52869925 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.584983734 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4133258546 ps |
| CPU time | 379.08 seconds |
| Started | Jul 22 08:40:44 PM PDT 24 |
| Finished | Jul 22 08:47:05 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-623decf6-5925-4bbd-bfed-039944f4565f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584983734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.584983734 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.20921662 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3508454936 ps |
| CPU time | 383.18 seconds |
| Started | Jul 22 08:40:46 PM PDT 24 |
| Finished | Jul 22 08:47:11 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-1e8085c7-51f4-43e9-b82b-a445c6cc5f32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20921662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw _alert_handler_lpg_sleep_mode_alerts.20921662 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.425860222 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4560336534 ps |
| CPU time | 533.08 seconds |
| Started | Jul 22 08:41:30 PM PDT 24 |
| Finished | Jul 22 08:50:24 PM PDT 24 |
| Peak memory | 650100 kb |
| Host | smart-36c26197-489b-406a-9776-a5156182eab1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 425860222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.425860222 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724990215 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3682984942 ps |
| CPU time | 416.22 seconds |
| Started | Jul 22 08:41:59 PM PDT 24 |
| Finished | Jul 22 08:48:56 PM PDT 24 |
| Peak memory | 648888 kb |
| Host | smart-6b9f750f-01c4-4b14-81c5-1b06ba97db0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724990215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2724990215 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.215307297 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4336666000 ps |
| CPU time | 499.2 seconds |
| Started | Jul 22 08:42:06 PM PDT 24 |
| Finished | Jul 22 08:50:27 PM PDT 24 |
| Peak memory | 650228 kb |
| Host | smart-279322e9-10c1-4759-9cf4-70d6a7d07b64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 215307297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.215307297 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1097773694 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3356607486 ps |
| CPU time | 430.57 seconds |
| Started | Jul 22 08:37:40 PM PDT 24 |
| Finished | Jul 22 08:44:52 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-64ccd384-9980-4237-a402-db1aa84a066d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097773694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.1097773694 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3742482360 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5810124344 ps |
| CPU time | 688.18 seconds |
| Started | Jul 22 08:37:32 PM PDT 24 |
| Finished | Jul 22 08:49:02 PM PDT 24 |
| Peak memory | 650504 kb |
| Host | smart-b3a1bf86-631d-4344-9b5e-5ca7d9cfe34d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3742482360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3742482360 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4291680439 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 4084245792 ps |
| CPU time | 526.34 seconds |
| Started | Jul 22 08:40:43 PM PDT 24 |
| Finished | Jul 22 08:49:31 PM PDT 24 |
| Peak memory | 648916 kb |
| Host | smart-2ee53b3c-c7e3-476b-b917-3cfbf5b234c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291680439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4291680439 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.2691163991 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5120538344 ps |
| CPU time | 582.52 seconds |
| Started | Jul 22 08:41:18 PM PDT 24 |
| Finished | Jul 22 08:51:03 PM PDT 24 |
| Peak memory | 650368 kb |
| Host | smart-8d53085e-63fc-4de6-8e47-70725e794995 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2691163991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2691163991 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224351138 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4077507882 ps |
| CPU time | 365.21 seconds |
| Started | Jul 22 08:41:42 PM PDT 24 |
| Finished | Jul 22 08:47:48 PM PDT 24 |
| Peak memory | 649356 kb |
| Host | smart-2708eae7-2562-47c9-bf91-643cf49a6a65 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224351138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1224351138 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.872068628 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3830354660 ps |
| CPU time | 577.06 seconds |
| Started | Jul 22 08:41:32 PM PDT 24 |
| Finished | Jul 22 08:51:10 PM PDT 24 |
| Peak memory | 650496 kb |
| Host | smart-67105805-0172-455f-a4ad-89e07fd1ea0a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 872068628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.872068628 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1326460568 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 3388727800 ps |
| CPU time | 402.83 seconds |
| Started | Jul 22 08:36:54 PM PDT 24 |
| Finished | Jul 22 08:43:37 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-1ae5cccc-eed9-42f9-be39-6f09c207e1cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326460568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1326460568 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491411824 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 4143993916 ps |
| CPU time | 364.27 seconds |
| Started | Jul 22 08:42:27 PM PDT 24 |
| Finished | Jul 22 08:48:32 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-76c8e581-c9de-4e11-85fd-58acb6639404 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491411824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3491411824 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.1543298564 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4343615788 ps |
| CPU time | 703.65 seconds |
| Started | Jul 22 08:43:32 PM PDT 24 |
| Finished | Jul 22 08:55:17 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-77b00181-20dc-4d31-b39d-06bedfa7e3f5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1543298564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1543298564 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386367439 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3702967176 ps |
| CPU time | 386.2 seconds |
| Started | Jul 22 08:42:53 PM PDT 24 |
| Finished | Jul 22 08:49:20 PM PDT 24 |
| Peak memory | 649312 kb |
| Host | smart-38a4aee9-47fd-4a8b-8a6c-2708b13e199f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386367439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3386367439 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.92708475 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5094479016 ps |
| CPU time | 608.39 seconds |
| Started | Jul 22 08:41:15 PM PDT 24 |
| Finished | Jul 22 08:51:26 PM PDT 24 |
| Peak memory | 650444 kb |
| Host | smart-8853eea7-9036-422b-9c35-8fc9b14f83a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 92708475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.92708475 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.266832134 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3787353036 ps |
| CPU time | 435.6 seconds |
| Started | Jul 22 08:44:13 PM PDT 24 |
| Finished | Jul 22 08:51:30 PM PDT 24 |
| Peak memory | 649108 kb |
| Host | smart-312ba07c-d8c6-4452-ae5b-face40ca748d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266832134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_s w_alert_handler_lpg_sleep_mode_alerts.266832134 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.1314263056 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5235716464 ps |
| CPU time | 851.21 seconds |
| Started | Jul 22 08:42:15 PM PDT 24 |
| Finished | Jul 22 08:56:27 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-ba63ee86-5713-4b79-b4e8-a88a23640e64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1314263056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1314263056 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146842878 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4386603966 ps |
| CPU time | 445.7 seconds |
| Started | Jul 22 08:45:29 PM PDT 24 |
| Finished | Jul 22 08:52:56 PM PDT 24 |
| Peak memory | 649620 kb |
| Host | smart-7f98b38d-10ef-4a4e-8082-9bd2ef80246b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146842878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1146842878 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1979741461 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3224159062 ps |
| CPU time | 380.97 seconds |
| Started | Jul 22 08:41:53 PM PDT 24 |
| Finished | Jul 22 08:48:15 PM PDT 24 |
| Peak memory | 649016 kb |
| Host | smart-02e1c249-3b5f-4595-b352-066ba688d215 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979741461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1979741461 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2231186225 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3762222356 ps |
| CPU time | 350.91 seconds |
| Started | Jul 22 08:45:50 PM PDT 24 |
| Finished | Jul 22 08:51:42 PM PDT 24 |
| Peak memory | 649212 kb |
| Host | smart-a7259ba6-eaf8-4b4a-a0fa-0584a01ec1e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231186225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2231186225 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.643680360 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3881124652 ps |
| CPU time | 380.58 seconds |
| Started | Jul 22 08:42:15 PM PDT 24 |
| Finished | Jul 22 08:48:36 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-51c4f35f-a6c2-4b55-9b9b-ad509bc860eb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643680360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.643680360 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1221790081 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3631526262 ps |
| CPU time | 423.11 seconds |
| Started | Jul 22 08:45:49 PM PDT 24 |
| Finished | Jul 22 08:52:53 PM PDT 24 |
| Peak memory | 647984 kb |
| Host | smart-bfd4a104-54be-444a-a39e-25a0634f3c6b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221790081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1221790081 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.1185114754 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5190550680 ps |
| CPU time | 729.43 seconds |
| Started | Jul 22 08:42:29 PM PDT 24 |
| Finished | Jul 22 08:54:40 PM PDT 24 |
| Peak memory | 650484 kb |
| Host | smart-358270ea-599b-4ad9-a71d-2f33f6d119e6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1185114754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1185114754 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1910047049 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4057503270 ps |
| CPU time | 371.43 seconds |
| Started | Jul 22 08:45:01 PM PDT 24 |
| Finished | Jul 22 08:51:13 PM PDT 24 |
| Peak memory | 649612 kb |
| Host | smart-6942a105-713a-41ad-a95e-bd4f05a72335 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910047049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1910047049 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663707660 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3999241120 ps |
| CPU time | 413.87 seconds |
| Started | Jul 22 08:45:38 PM PDT 24 |
| Finished | Jul 22 08:52:33 PM PDT 24 |
| Peak memory | 649304 kb |
| Host | smart-42bddbc7-b0f5-4ef3-bc21-386e6645269a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663707660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1663707660 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441375946 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4077895452 ps |
| CPU time | 445.72 seconds |
| Started | Jul 22 08:47:18 PM PDT 24 |
| Finished | Jul 22 08:54:44 PM PDT 24 |
| Peak memory | 648944 kb |
| Host | smart-2381dd38-06aa-4e87-ac93-530b4b9f5619 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441375946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1441375946 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.421617487 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3996865016 ps |
| CPU time | 456.7 seconds |
| Started | Jul 22 08:44:13 PM PDT 24 |
| Finished | Jul 22 08:51:51 PM PDT 24 |
| Peak memory | 649052 kb |
| Host | smart-1833f741-51b1-465d-b73c-28ee00d1460a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421617487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.421617487 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.3184863681 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 4669823700 ps |
| CPU time | 776.84 seconds |
| Started | Jul 22 08:37:59 PM PDT 24 |
| Finished | Jul 22 08:50:57 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-fc6dd157-5a48-46e1-a1e3-4c0957f4426c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3184863681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3184863681 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.504719785 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4311725190 ps |
| CPU time | 403.21 seconds |
| Started | Jul 22 08:44:01 PM PDT 24 |
| Finished | Jul 22 08:50:45 PM PDT 24 |
| Peak memory | 649720 kb |
| Host | smart-905132d2-4282-4b3a-974f-37928873bea8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504719785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_s w_alert_handler_lpg_sleep_mode_alerts.504719785 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2397790362 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3180887464 ps |
| CPU time | 354.42 seconds |
| Started | Jul 22 08:44:02 PM PDT 24 |
| Finished | Jul 22 08:49:58 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-94c0847d-8a9f-4eef-95ad-b768f702be77 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397790362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2397790362 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1367448199 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3248002500 ps |
| CPU time | 349.19 seconds |
| Started | Jul 22 08:45:34 PM PDT 24 |
| Finished | Jul 22 08:51:24 PM PDT 24 |
| Peak memory | 649196 kb |
| Host | smart-4e6465a0-4fd8-42eb-81d0-06e49dd75a10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367448199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1367448199 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2272172054 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3810494456 ps |
| CPU time | 321.62 seconds |
| Started | Jul 22 08:45:30 PM PDT 24 |
| Finished | Jul 22 08:50:53 PM PDT 24 |
| Peak memory | 649224 kb |
| Host | smart-1f5ffa80-607c-4f80-8ca6-f377b498f97e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272172054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2272172054 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639365398 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3515968176 ps |
| CPU time | 345.22 seconds |
| Started | Jul 22 08:47:45 PM PDT 24 |
| Finished | Jul 22 08:53:30 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-943a0f91-ebdd-416d-82b4-ada841b178ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639365398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1639365398 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3397832030 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5022899140 ps |
| CPU time | 627.02 seconds |
| Started | Jul 22 08:44:58 PM PDT 24 |
| Finished | Jul 22 08:55:26 PM PDT 24 |
| Peak memory | 650668 kb |
| Host | smart-950aee83-677e-41cd-858c-9a4455a90f7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3397832030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3397832030 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.168156268 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4591789700 ps |
| CPU time | 550.69 seconds |
| Started | Jul 22 08:45:14 PM PDT 24 |
| Finished | Jul 22 08:54:26 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-c00b1793-70cb-42d3-81b0-912bed3b1782 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 168156268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.168156268 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2595640541 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4364580696 ps |
| CPU time | 573.99 seconds |
| Started | Jul 22 08:46:09 PM PDT 24 |
| Finished | Jul 22 08:55:44 PM PDT 24 |
| Peak memory | 651420 kb |
| Host | smart-4d23408b-f7cd-4634-933a-fc942545fe66 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2595640541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2595640541 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.3598350101 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 5616610720 ps |
| CPU time | 502.34 seconds |
| Started | Jul 22 08:46:17 PM PDT 24 |
| Finished | Jul 22 08:54:40 PM PDT 24 |
| Peak memory | 650380 kb |
| Host | smart-510d5318-e6a4-4808-a713-ce8a152a595c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3598350101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3598350101 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.382512031 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 32291280543 ps |
| CPU time | 4579.4 seconds |
| Started | Jul 22 07:40:47 PM PDT 24 |
| Finished | Jul 22 08:57:07 PM PDT 24 |
| Peak memory | 593544 kb |
| Host | smart-3c8b1a3d-0130-43c4-a2f8-8cb6ae819df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382512031 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.382512031 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.1047765676 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 5423922765 ps |
| CPU time | 221.34 seconds |
| Started | Jul 22 07:50:56 PM PDT 24 |
| Finished | Jul 22 07:54:39 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-faf1cf04-0f22-473e-8134-c6aabe851c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047765676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1047765676 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2686533133 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6989379960 ps |
| CPU time | 1694.67 seconds |
| Started | Jul 22 08:15:08 PM PDT 24 |
| Finished | Jul 22 08:43:25 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-04aae814-1051-4d8b-bc00-b55ce0dd6b62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2686533133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2686533133 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.4018397694 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4473099858 ps |
| CPU time | 526.15 seconds |
| Started | Jul 22 08:12:03 PM PDT 24 |
| Finished | Jul 22 08:20:50 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-d4aaa9c2-dc9c-44cf-b13d-eeeb5492cf6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018397694 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.4018397694 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3429836627 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 5985182800 ps |
| CPU time | 708.45 seconds |
| Started | Jul 22 08:13:40 PM PDT 24 |
| Finished | Jul 22 08:25:30 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-b5418010-7db3-48cb-bd1c-056dc964b9d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3429836627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3429836627 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.622097615 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3948575218 ps |
| CPU time | 713.25 seconds |
| Started | Jul 22 08:12:40 PM PDT 24 |
| Finished | Jul 22 08:24:46 PM PDT 24 |
| Peak memory | 625236 kb |
| Host | smart-14bdb0b6-ccc1-4dbd-8d1b-c3d59cab00b5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622097615 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.622097615 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1471000807 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4369137227 ps |
| CPU time | 491.72 seconds |
| Started | Jul 22 08:17:53 PM PDT 24 |
| Finished | Jul 22 08:26:06 PM PDT 24 |
| Peak memory | 624612 kb |
| Host | smart-bfce53c5-3e06-430b-ae4e-9a3629bd7c27 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471000807 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1471000807 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2503363528 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 23816637449 ps |
| CPU time | 2294.49 seconds |
| Started | Jul 22 08:13:26 PM PDT 24 |
| Finished | Jul 22 08:51:42 PM PDT 24 |
| Peak memory | 613888 kb |
| Host | smart-bc4264c1-6ef3-461b-b3cf-5139e4411ddb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2503363528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2503363528 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3784584245 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 7303535334 ps |
| CPU time | 350.95 seconds |
| Started | Jul 22 08:10:52 PM PDT 24 |
| Finished | Jul 22 08:16:44 PM PDT 24 |
| Peak memory | 611024 kb |
| Host | smart-6a82f208-af80-4ccd-94ce-8de604b8ce9a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784584245 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3784584245 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3435545050 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 8557664974 ps |
| CPU time | 851.06 seconds |
| Started | Jul 22 08:37:39 PM PDT 24 |
| Finished | Jul 22 08:51:51 PM PDT 24 |
| Peak memory | 621308 kb |
| Host | smart-3b8be385-9133-4ce6-a26a-b57a2a908818 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3435545050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3435545050 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1150116637 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 5868214339 ps |
| CPU time | 578.71 seconds |
| Started | Jul 22 07:41:23 PM PDT 24 |
| Finished | Jul 22 07:51:03 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-fe739ff6-23c7-4891-98f0-0d12f564943a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150116637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.1150116637 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.4157889023 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3426666395 ps |
| CPU time | 166.83 seconds |
| Started | Jul 22 07:45:54 PM PDT 24 |
| Finished | Jul 22 07:48:43 PM PDT 24 |
| Peak memory | 604380 kb |
| Host | smart-5682c541-b88c-4ac2-a087-2fc20a0bf221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157889023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.4157889023 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1164537398 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 5749383848 ps |
| CPU time | 703.55 seconds |
| Started | Jul 22 07:47:50 PM PDT 24 |
| Finished | Jul 22 07:59:35 PM PDT 24 |
| Peak memory | 577008 kb |
| Host | smart-a31450a7-b667-4a1d-929c-e2c260221e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164537398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1164537398 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2850487957 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 6200417219 ps |
| CPU time | 232.43 seconds |
| Started | Jul 22 08:00:07 PM PDT 24 |
| Finished | Jul 22 08:04:01 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-3a1d8434-ed79-47a6-8bad-798f02be3103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850487957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2850487957 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.735956827 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3804341592 ps |
| CPU time | 390.69 seconds |
| Started | Jul 22 08:14:56 PM PDT 24 |
| Finished | Jul 22 08:21:27 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-7b332d4a-7ac7-47d1-abff-98b53ff6a626 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735956827 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.735956827 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2942296738 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3959782200 ps |
| CPU time | 479.51 seconds |
| Started | Jul 22 08:23:33 PM PDT 24 |
| Finished | Jul 22 08:31:39 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-3101b3f1-db56-4432-b11d-aae8ffcf8838 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942296738 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2942296738 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2019259888 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4444174460 ps |
| CPU time | 570.95 seconds |
| Started | Jul 22 08:26:30 PM PDT 24 |
| Finished | Jul 22 08:36:02 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-0f8d398a-c862-452b-9c1c-5df981f21579 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019259888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2019259888 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.302972378 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 18905953400 ps |
| CPU time | 623.54 seconds |
| Started | Jul 22 08:12:04 PM PDT 24 |
| Finished | Jul 22 08:22:29 PM PDT 24 |
| Peak memory | 619540 kb |
| Host | smart-5c7a82c2-c72e-4e03-adce-1d53a002b2e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=302972378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.302972378 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2913933553 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 7531247706 ps |
| CPU time | 1297.41 seconds |
| Started | Jul 22 08:14:50 PM PDT 24 |
| Finished | Jul 22 08:36:28 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-e5b502fe-0c22-463a-b6cd-f809ba8b371e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913933553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2913933553 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1683624301 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2637879940 ps |
| CPU time | 285.04 seconds |
| Started | Jul 22 08:32:04 PM PDT 24 |
| Finished | Jul 22 08:36:50 PM PDT 24 |
| Peak memory | 621728 kb |
| Host | smart-ec3244f2-8911-466f-b9b0-cceb5830be8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683624301 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1683624301 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2675312294 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5256086520 ps |
| CPU time | 848.99 seconds |
| Started | Jul 22 08:12:49 PM PDT 24 |
| Finished | Jul 22 08:27:10 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-b2a4c668-9899-438d-a094-94b8c09918f8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675312294 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2675312294 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.3513479527 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2429449134 ps |
| CPU time | 192.02 seconds |
| Started | Jul 22 08:19:20 PM PDT 24 |
| Finished | Jul 22 08:22:34 PM PDT 24 |
| Peak memory | 611804 kb |
| Host | smart-20d10078-896d-4415-9875-cb1e34b5284f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513479527 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3513479527 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1853469975 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 7063540600 ps |
| CPU time | 1026.32 seconds |
| Started | Jul 22 08:15:05 PM PDT 24 |
| Finished | Jul 22 08:32:12 PM PDT 24 |
| Peak memory | 617504 kb |
| Host | smart-9c64aacb-5006-4776-87f8-2353b2cff207 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853469975 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1853469975 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2546520350 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 3307845216 ps |
| CPU time | 300.87 seconds |
| Started | Jul 22 08:14:26 PM PDT 24 |
| Finished | Jul 22 08:19:28 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-da8ded4d-57b1-4820-84b4-71e5ec6a9088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546520350 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2546520350 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3025395766 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7701636416 ps |
| CPU time | 2088.05 seconds |
| Started | Jul 22 08:14:07 PM PDT 24 |
| Finished | Jul 22 08:48:57 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-d1c95c9c-bfa1-42de-8d83-6f6473737f08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302539 5766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3025395766 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2519329807 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4725781684 ps |
| CPU time | 503.77 seconds |
| Started | Jul 22 08:14:17 PM PDT 24 |
| Finished | Jul 22 08:22:43 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-2cd42bbf-66a3-4d71-8803-d30875fdd73b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2519329807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2519329807 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1806692762 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 8060465944 ps |
| CPU time | 523.52 seconds |
| Started | Jul 22 08:13:33 PM PDT 24 |
| Finished | Jul 22 08:22:18 PM PDT 24 |
| Peak memory | 618100 kb |
| Host | smart-6e48e870-deb1-4336-a945-eefeead11dd3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1806692762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1806692762 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1923593382 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 9278285212 ps |
| CPU time | 802.02 seconds |
| Started | Jul 22 07:41:18 PM PDT 24 |
| Finished | Jul 22 07:54:41 PM PDT 24 |
| Peak memory | 653332 kb |
| Host | smart-fca10ea7-ca29-4763-8f03-b5175c83d4d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923593382 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1923593382 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.316220221 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 638629198 ps |
| CPU time | 27.29 seconds |
| Started | Jul 22 07:46:10 PM PDT 24 |
| Finished | Jul 22 07:46:38 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-e5b644a1-8ad0-4aff-8e8c-e1dd4f1dd055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316220221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .316220221 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2800063857 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3791359504 ps |
| CPU time | 313.9 seconds |
| Started | Jul 22 07:46:40 PM PDT 24 |
| Finished | Jul 22 07:51:56 PM PDT 24 |
| Peak memory | 604384 kb |
| Host | smart-52427492-c3b6-4587-b91b-5aaf9124943f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800063857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2800063857 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3081481999 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3477930787 ps |
| CPU time | 376.61 seconds |
| Started | Jul 22 07:48:30 PM PDT 24 |
| Finished | Jul 22 07:54:51 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-e86ad459-8aad-4812-9bcb-457e938a4018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081481999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.3081481999 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1470148252 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2634498939 ps |
| CPU time | 189.09 seconds |
| Started | Jul 22 07:51:14 PM PDT 24 |
| Finished | Jul 22 07:54:26 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-02cfe7dc-1fbf-4f15-bf06-0f13ea00bc95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470148252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1470148252 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.4283158045 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2198650886 ps |
| CPU time | 85.9 seconds |
| Started | Jul 22 07:54:08 PM PDT 24 |
| Finished | Jul 22 07:55:35 PM PDT 24 |
| Peak memory | 576840 kb |
| Host | smart-88638cc8-e7b9-4cec-9fb6-899176898c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283158045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.4283158045 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1246956205 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 5008908232 ps |
| CPU time | 885.61 seconds |
| Started | Jul 22 08:13:15 PM PDT 24 |
| Finished | Jul 22 08:28:02 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-deb914e8-0548-4320-b5f3-b6a253f926bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12469 56205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1246956205 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3379734462 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 11479000952 ps |
| CPU time | 2152.01 seconds |
| Started | Jul 22 08:20:27 PM PDT 24 |
| Finished | Jul 22 08:56:20 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-1aa29f7a-a072-4abf-a778-7a07a458f883 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3379734462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3379734462 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.2804274889 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 6303792858 ps |
| CPU time | 663.42 seconds |
| Started | Jul 22 08:36:25 PM PDT 24 |
| Finished | Jul 22 08:47:29 PM PDT 24 |
| Peak memory | 621480 kb |
| Host | smart-035a6193-076f-42e7-962e-490f3c0c2a5e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2804274889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2804274889 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1109255504 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 72986656196 ps |
| CPU time | 10235.8 seconds |
| Started | Jul 22 08:13:00 PM PDT 24 |
| Finished | Jul 22 11:03:39 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-7718532f-af7f-42de-8950-0fbb38aad9e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1109255504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1109255504 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1726240482 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3110576260 ps |
| CPU time | 487.29 seconds |
| Started | Jul 22 08:11:12 PM PDT 24 |
| Finished | Jul 22 08:19:20 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-d8f90502-dcdf-4800-83bc-1ac85ea558bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726240482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1726240482 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4049201106 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 24438811670 ps |
| CPU time | 7033.82 seconds |
| Started | Jul 22 08:22:39 PM PDT 24 |
| Finished | Jul 22 10:19:55 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-eded0969-abb9-46e4-88cd-f41500d36baa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4049201106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4049201106 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.689209437 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 8106293926 ps |
| CPU time | 798.23 seconds |
| Started | Jul 22 07:40:45 PM PDT 24 |
| Finished | Jul 22 07:54:04 PM PDT 24 |
| Peak memory | 592964 kb |
| Host | smart-d44e3e73-b351-46de-bbe1-b47f433dc925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689209437 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.689209437 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4032025594 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4525706968 ps |
| CPU time | 241.93 seconds |
| Started | Jul 22 07:41:15 PM PDT 24 |
| Finished | Jul 22 07:45:18 PM PDT 24 |
| Peak memory | 664012 kb |
| Host | smart-0090ad9f-f2f6-4a1c-ba6f-e535bb493bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032025594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.4032025594 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1009324787 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 5814525942 ps |
| CPU time | 631.24 seconds |
| Started | Jul 22 07:41:16 PM PDT 24 |
| Finished | Jul 22 07:51:48 PM PDT 24 |
| Peak memory | 597920 kb |
| Host | smart-53a380ff-08d6-44ec-9b79-96c394ec7bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009324787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1009324787 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2629042780 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 7100576052 ps |
| CPU time | 317.48 seconds |
| Started | Jul 22 07:40:46 PM PDT 24 |
| Finished | Jul 22 07:46:04 PM PDT 24 |
| Peak memory | 591068 kb |
| Host | smart-51727024-4cae-43b9-9d05-2faa4ed7ce65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629042780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2629042780 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1076972883 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 20450041515 ps |
| CPU time | 683.74 seconds |
| Started | Jul 22 07:43:46 PM PDT 24 |
| Finished | Jul 22 07:55:12 PM PDT 24 |
| Peak memory | 592796 kb |
| Host | smart-c8aeb939-d96f-45fd-a9d7-f22ae1ec2e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076972883 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1076972883 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1251428196 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 2453952796 ps |
| CPU time | 108.3 seconds |
| Started | Jul 22 07:40:47 PM PDT 24 |
| Finished | Jul 22 07:42:36 PM PDT 24 |
| Peak memory | 592056 kb |
| Host | smart-6934e2a3-6fb4-4a0e-aa8b-7ed672d355bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251428196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1251428196 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.4263229038 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 297414681 ps |
| CPU time | 28.68 seconds |
| Started | Jul 22 07:41:07 PM PDT 24 |
| Finished | Jul 22 07:41:37 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-9738b2f7-356c-4fcc-b0e6-d25bc8ba8805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263229038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 4263229038 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.673417956 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 44200864770 ps |
| CPU time | 751.81 seconds |
| Started | Jul 22 07:41:07 PM PDT 24 |
| Finished | Jul 22 07:53:40 PM PDT 24 |
| Peak memory | 576952 kb |
| Host | smart-19bc061a-b703-462a-b76a-b6eaa24caf21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673417956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de vice_slow_rsp.673417956 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.685582335 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 123539354 ps |
| CPU time | 8.45 seconds |
| Started | Jul 22 07:41:06 PM PDT 24 |
| Finished | Jul 22 07:41:15 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-0cd7dcf1-e3d2-4b15-92ad-3104edac0b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685582335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr. 685582335 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2249345932 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 419167294 ps |
| CPU time | 14.27 seconds |
| Started | Jul 22 07:41:07 PM PDT 24 |
| Finished | Jul 22 07:41:22 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-766cba30-01b1-47c5-b6f1-f567430163d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249345932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2249345932 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.1026700162 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 125122590 ps |
| CPU time | 8.43 seconds |
| Started | Jul 22 07:41:23 PM PDT 24 |
| Finished | Jul 22 07:41:34 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-8a250458-fb9e-4ada-a12c-683c771e9bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026700162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1026700162 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.421961909 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 78693266925 ps |
| CPU time | 887.14 seconds |
| Started | Jul 22 07:40:59 PM PDT 24 |
| Finished | Jul 22 07:55:47 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-aeb0fc2d-9877-440e-b06a-fdfe8d3542b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421961909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.421961909 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3041339684 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 24167460407 ps |
| CPU time | 427.76 seconds |
| Started | Jul 22 07:40:56 PM PDT 24 |
| Finished | Jul 22 07:48:05 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-e2d21fb0-2882-4206-bec1-19f736fd62ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041339684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3041339684 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4139429667 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 267558729 ps |
| CPU time | 24.17 seconds |
| Started | Jul 22 07:40:56 PM PDT 24 |
| Finished | Jul 22 07:41:21 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-1c128af8-55d2-4718-a28c-3703b8fc34d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139429667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.4139429667 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1005426397 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 87671476 ps |
| CPU time | 9.38 seconds |
| Started | Jul 22 07:41:10 PM PDT 24 |
| Finished | Jul 22 07:41:20 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-6dddddea-398b-4da7-9ff0-0670f125bf81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005426397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1005426397 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.2483631691 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 229103999 ps |
| CPU time | 9.54 seconds |
| Started | Jul 22 07:40:57 PM PDT 24 |
| Finished | Jul 22 07:41:07 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-f36652e4-7dcc-4a00-9090-48ce7b462be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483631691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2483631691 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.350449606 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 7471246401 ps |
| CPU time | 74.97 seconds |
| Started | Jul 22 07:41:09 PM PDT 24 |
| Finished | Jul 22 07:42:24 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-7ddc9572-6361-47c1-85ab-f6ebdcd88ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350449606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.350449606 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1775832175 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 5305179294 ps |
| CPU time | 92.76 seconds |
| Started | Jul 22 07:40:56 PM PDT 24 |
| Finished | Jul 22 07:42:30 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-c17919a1-3a2b-42d3-82a6-e0b70c192ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775832175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1775832175 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.809481729 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 49876205 ps |
| CPU time | 6.61 seconds |
| Started | Jul 22 07:40:58 PM PDT 24 |
| Finished | Jul 22 07:41:05 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-f2514034-9aaa-451c-889a-b0ebfce903a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809481729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays. 809481729 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1294153628 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 826424451 ps |
| CPU time | 26.68 seconds |
| Started | Jul 22 07:41:07 PM PDT 24 |
| Finished | Jul 22 07:41:36 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-c3097f06-8fcb-43b2-80f0-aeb9b64b2aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294153628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1294153628 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.163032547 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 4928262114 ps |
| CPU time | 148.59 seconds |
| Started | Jul 22 07:41:05 PM PDT 24 |
| Finished | Jul 22 07:43:35 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-e40a9366-a07c-49b9-8fd5-530a80ec2b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163032547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.163032547 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3997250461 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 5941624848 ps |
| CPU time | 770.1 seconds |
| Started | Jul 22 07:41:06 PM PDT 24 |
| Finished | Jul 22 07:53:57 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-5fbe040d-fcbe-4360-9eec-591b7b9d87b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997250461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3997250461 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1037206969 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 156527961 ps |
| CPU time | 58.86 seconds |
| Started | Jul 22 07:41:11 PM PDT 24 |
| Finished | Jul 22 07:42:10 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-07026a8d-e970-42bd-9303-5185a4f4e494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037206969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.1037206969 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1950622928 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 398693445 ps |
| CPU time | 17.69 seconds |
| Started | Jul 22 07:41:06 PM PDT 24 |
| Finished | Jul 22 07:41:24 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-6034a5fb-8547-4fe6-a8e3-22ad635dad57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950622928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1950622928 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4244319082 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 63161354983 ps |
| CPU time | 9871.94 seconds |
| Started | Jul 22 07:41:18 PM PDT 24 |
| Finished | Jul 22 10:25:53 PM PDT 24 |
| Peak memory | 640516 kb |
| Host | smart-af1f696b-a666-40f2-8fbd-8bd516c2503b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244319082 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.4244319082 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1509651197 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 9658773618 ps |
| CPU time | 1144.52 seconds |
| Started | Jul 22 07:41:14 PM PDT 24 |
| Finished | Jul 22 08:00:20 PM PDT 24 |
| Peak memory | 592044 kb |
| Host | smart-bd9d2a15-1a26-4adf-9286-f1270cf3c6e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509651197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1509651197 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1458354410 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 7754360673 ps |
| CPU time | 529.08 seconds |
| Started | Jul 22 07:41:32 PM PDT 24 |
| Finished | Jul 22 07:50:23 PM PDT 24 |
| Peak memory | 638184 kb |
| Host | smart-0a85fff6-0cb4-4fb2-9f51-08867572ffbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458354410 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.1458354410 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.372052364 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 5892579300 ps |
| CPU time | 630.54 seconds |
| Started | Jul 22 07:41:33 PM PDT 24 |
| Finished | Jul 22 07:52:05 PM PDT 24 |
| Peak memory | 599704 kb |
| Host | smart-57efce9c-48ee-433c-9b7c-436345cf0f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372052364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.372052364 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2651082340 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 3178755720 ps |
| CPU time | 138.64 seconds |
| Started | Jul 22 07:41:23 PM PDT 24 |
| Finished | Jul 22 07:43:43 PM PDT 24 |
| Peak memory | 589824 kb |
| Host | smart-d7484b5c-e494-403e-b434-e5beeb7b46f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651082340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2651082340 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.611481759 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 9189526426 ps |
| CPU time | 482.73 seconds |
| Started | Jul 22 07:41:44 PM PDT 24 |
| Finished | Jul 22 07:49:47 PM PDT 24 |
| Peak memory | 591892 kb |
| Host | smart-d6a29de2-c49b-4c4a-bd5c-f4312dde7e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611481759 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.chip_rv_dm_lc_disabled.611481759 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3658141254 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2955315176 ps |
| CPU time | 223.98 seconds |
| Started | Jul 22 07:41:20 PM PDT 24 |
| Finished | Jul 22 07:45:06 PM PDT 24 |
| Peak memory | 604420 kb |
| Host | smart-798b30ef-ba3e-428c-9ff5-16259e16934a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658141254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3658141254 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.512715932 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 211516809 ps |
| CPU time | 17.84 seconds |
| Started | Jul 22 07:41:22 PM PDT 24 |
| Finished | Jul 22 07:41:41 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-0875330d-d039-4619-963e-6b8aeb14f36a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512715932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.512715932 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1805908601 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 41328791504 ps |
| CPU time | 691.37 seconds |
| Started | Jul 22 07:41:25 PM PDT 24 |
| Finished | Jul 22 07:52:58 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-baf4ba7c-31ec-4f55-b5ca-45a9760c7f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805908601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1805908601 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1725169219 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 275926505 ps |
| CPU time | 13.84 seconds |
| Started | Jul 22 07:41:27 PM PDT 24 |
| Finished | Jul 22 07:41:41 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-26931484-6146-4105-a6ba-31b1e8323acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725169219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1725169219 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1872524017 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 991017538 ps |
| CPU time | 32.78 seconds |
| Started | Jul 22 07:41:27 PM PDT 24 |
| Finished | Jul 22 07:42:00 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-7efd588a-3f5f-451c-a1a8-066b6cbf4c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872524017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1872524017 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.2463344605 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 2168517663 ps |
| CPU time | 72 seconds |
| Started | Jul 22 07:41:22 PM PDT 24 |
| Finished | Jul 22 07:42:35 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-ea577420-6a67-4975-93b4-34c3cf14fd5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463344605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.2463344605 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2089542841 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 12939154392 ps |
| CPU time | 138.39 seconds |
| Started | Jul 22 07:41:22 PM PDT 24 |
| Finished | Jul 22 07:43:42 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-5b1ddfa9-971f-416a-ac2a-6a01694644c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089542841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2089542841 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.660688397 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 10786598966 ps |
| CPU time | 186.37 seconds |
| Started | Jul 22 07:41:22 PM PDT 24 |
| Finished | Jul 22 07:44:30 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-de8c1e9f-d64b-41fb-90eb-0ca628b9c495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660688397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.660688397 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.209703866 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 103066720 ps |
| CPU time | 12.53 seconds |
| Started | Jul 22 07:41:26 PM PDT 24 |
| Finished | Jul 22 07:41:39 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-28449eaf-b189-4aa7-92af-6abbc71909ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209703866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay s.209703866 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.489141269 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 1200776925 ps |
| CPU time | 32.17 seconds |
| Started | Jul 22 07:41:25 PM PDT 24 |
| Finished | Jul 22 07:41:58 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-3fd3e383-c27a-420d-bfa6-f0887bc3b774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489141269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.489141269 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1076794853 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 200130729 ps |
| CPU time | 9.6 seconds |
| Started | Jul 22 07:41:15 PM PDT 24 |
| Finished | Jul 22 07:41:26 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-3883b2d7-e70c-4da5-b79f-e054ebfba733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076794853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1076794853 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1080097225 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 8885321470 ps |
| CPU time | 87.02 seconds |
| Started | Jul 22 07:41:15 PM PDT 24 |
| Finished | Jul 22 07:42:43 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-2630ab1a-a006-405e-b5ed-1eb48e236900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080097225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1080097225 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2118856389 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 5268215323 ps |
| CPU time | 83.3 seconds |
| Started | Jul 22 07:41:14 PM PDT 24 |
| Finished | Jul 22 07:42:39 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-bb1eef25-e49f-4adb-b1fc-ddc71ee66033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118856389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2118856389 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2958485864 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 58725590 ps |
| CPU time | 6.88 seconds |
| Started | Jul 22 07:41:15 PM PDT 24 |
| Finished | Jul 22 07:41:23 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-b7d9f4de-e372-4568-9f75-8a106da58f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958485864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .2958485864 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.1312388869 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 780882390 ps |
| CPU time | 82.77 seconds |
| Started | Jul 22 07:41:28 PM PDT 24 |
| Finished | Jul 22 07:42:52 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-f00cf1cf-4619-42ca-b88c-427a3bd4e9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312388869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1312388869 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2539678475 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 11213447877 ps |
| CPU time | 385.76 seconds |
| Started | Jul 22 07:41:24 PM PDT 24 |
| Finished | Jul 22 07:47:51 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-dc03e97e-72f5-4ac2-b791-99c7104ea8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539678475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2539678475 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2309915264 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 248176533 ps |
| CPU time | 14.09 seconds |
| Started | Jul 22 07:43:16 PM PDT 24 |
| Finished | Jul 22 07:43:31 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-6af4839d-6d7f-43f1-82db-37870bcf8078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309915264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2309915264 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3541901580 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 7864393492 ps |
| CPU time | 582.96 seconds |
| Started | Jul 22 07:44:48 PM PDT 24 |
| Finished | Jul 22 07:54:32 PM PDT 24 |
| Peak memory | 640368 kb |
| Host | smart-29c97d73-645e-4ab8-90d3-c5bebcad3db9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541901580 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.3541901580 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2551776330 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 4442261219 ps |
| CPU time | 307.48 seconds |
| Started | Jul 22 07:44:53 PM PDT 24 |
| Finished | Jul 22 07:50:01 PM PDT 24 |
| Peak memory | 597796 kb |
| Host | smart-60eb9112-4685-4d38-bba2-d8c822563b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551776330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2551776330 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2277195739 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 15564202128 ps |
| CPU time | 1710.04 seconds |
| Started | Jul 22 07:44:34 PM PDT 24 |
| Finished | Jul 22 08:13:06 PM PDT 24 |
| Peak memory | 593500 kb |
| Host | smart-5ad904d1-6f20-4795-8e8b-5a94d8f04e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277195739 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2277195739 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.1317753999 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5484228270 ps |
| CPU time | 402.91 seconds |
| Started | Jul 22 07:44:28 PM PDT 24 |
| Finished | Jul 22 07:51:12 PM PDT 24 |
| Peak memory | 604432 kb |
| Host | smart-0378ca27-b4b1-47dd-874a-f13666482d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317753999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1317753999 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1390597650 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 2081825151 ps |
| CPU time | 84.77 seconds |
| Started | Jul 22 07:44:39 PM PDT 24 |
| Finished | Jul 22 07:46:05 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-7953861e-2f59-429c-8464-607e2d90d2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390597650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1390597650 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1451906163 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 63237094129 ps |
| CPU time | 1119.42 seconds |
| Started | Jul 22 07:44:38 PM PDT 24 |
| Finished | Jul 22 08:03:18 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-75a58f5d-1038-4b3c-afb7-d142cacec508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451906163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1451906163 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.745824724 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 1325136706 ps |
| CPU time | 48.93 seconds |
| Started | Jul 22 07:44:40 PM PDT 24 |
| Finished | Jul 22 07:45:29 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-0d5296de-ea69-48c8-9954-3515486eb275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745824724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .745824724 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.650638857 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 419562652 ps |
| CPU time | 31.32 seconds |
| Started | Jul 22 07:44:39 PM PDT 24 |
| Finished | Jul 22 07:45:11 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-7953b857-b09b-44ca-b117-afb7cd7a6752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650638857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.650638857 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.965618811 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 1868703484 ps |
| CPU time | 62.13 seconds |
| Started | Jul 22 07:44:59 PM PDT 24 |
| Finished | Jul 22 07:46:02 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-373ca6a3-1ce0-4dac-bffb-22fcf38c23f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965618811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.965618811 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2591982295 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 13451170011 ps |
| CPU time | 144.94 seconds |
| Started | Jul 22 07:44:39 PM PDT 24 |
| Finished | Jul 22 07:47:05 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-05ba991f-6368-41f1-9ed9-afb02f4101aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591982295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2591982295 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3454752713 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 3597311040 ps |
| CPU time | 60.7 seconds |
| Started | Jul 22 07:44:42 PM PDT 24 |
| Finished | Jul 22 07:45:45 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-2886c344-5aae-45e8-9667-e238fc49d386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454752713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3454752713 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.31903837 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 515899681 ps |
| CPU time | 46.68 seconds |
| Started | Jul 22 07:44:37 PM PDT 24 |
| Finished | Jul 22 07:45:25 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-d0ca1e76-5501-4881-bbe6-6518b1377038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31903837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delay s.31903837 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2660122914 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 495953553 ps |
| CPU time | 36.73 seconds |
| Started | Jul 22 07:44:44 PM PDT 24 |
| Finished | Jul 22 07:45:23 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-e014b481-427c-4070-9473-b8b498ed21ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660122914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2660122914 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.310569328 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 206660549 ps |
| CPU time | 9.31 seconds |
| Started | Jul 22 07:45:08 PM PDT 24 |
| Finished | Jul 22 07:45:19 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-46178b8b-11c6-48a5-b237-2e1822e72ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310569328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.310569328 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2760641488 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 7670619186 ps |
| CPU time | 77.95 seconds |
| Started | Jul 22 07:44:27 PM PDT 24 |
| Finished | Jul 22 07:45:47 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-8bae3453-2183-4caf-829c-6b898809f934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760641488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2760641488 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3696300783 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 3045033556 ps |
| CPU time | 51.37 seconds |
| Started | Jul 22 07:44:30 PM PDT 24 |
| Finished | Jul 22 07:45:22 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-eba729ef-48e1-4741-8923-97b5f3806a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696300783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3696300783 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.479338589 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 41491772 ps |
| CPU time | 6.11 seconds |
| Started | Jul 22 07:44:29 PM PDT 24 |
| Finished | Jul 22 07:44:36 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-f3bcbe69-02be-4ece-8bf8-86b68a84d5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479338589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays .479338589 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.91084768 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 2463569065 ps |
| CPU time | 96.97 seconds |
| Started | Jul 22 07:44:43 PM PDT 24 |
| Finished | Jul 22 07:46:23 PM PDT 24 |
| Peak memory | 577068 kb |
| Host | smart-cfdaa965-abb0-45c5-8f87-363aed9d7ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91084768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.91084768 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1055105102 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 2769762025 ps |
| CPU time | 250.46 seconds |
| Started | Jul 22 07:44:40 PM PDT 24 |
| Finished | Jul 22 07:48:52 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-0918fc14-0856-4779-aadf-1fd0a6443a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055105102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1055105102 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1359389958 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 343249725 ps |
| CPU time | 37.21 seconds |
| Started | Jul 22 07:44:40 PM PDT 24 |
| Finished | Jul 22 07:45:18 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-c434211a-bf3b-46a0-9578-cc23cf69d2ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359389958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1359389958 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.800790479 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 10945136859 ps |
| CPU time | 822.78 seconds |
| Started | Jul 22 07:45:09 PM PDT 24 |
| Finished | Jul 22 07:58:53 PM PDT 24 |
| Peak memory | 653560 kb |
| Host | smart-a2f6a453-7343-489a-bc6d-19eab1c2511f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800790479 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.800790479 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3287978729 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 5879893568 ps |
| CPU time | 632.76 seconds |
| Started | Jul 22 07:45:09 PM PDT 24 |
| Finished | Jul 22 07:55:43 PM PDT 24 |
| Peak memory | 599204 kb |
| Host | smart-b528d8c4-e83e-4ed2-8b3e-e4a255db718d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287978729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3287978729 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1267591454 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 16769657555 ps |
| CPU time | 1954.19 seconds |
| Started | Jul 22 07:44:49 PM PDT 24 |
| Finished | Jul 22 08:17:25 PM PDT 24 |
| Peak memory | 593808 kb |
| Host | smart-9c6336e7-3af9-416c-ba54-5d99374133e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267591454 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.1267591454 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.3257747344 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 2653681722 ps |
| CPU time | 103.77 seconds |
| Started | Jul 22 07:45:25 PM PDT 24 |
| Finished | Jul 22 07:47:09 PM PDT 24 |
| Peak memory | 604420 kb |
| Host | smart-0d47962a-f58b-401f-b365-1cb3fe6b2c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257747344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.3257747344 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.819813419 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 613049614 ps |
| CPU time | 25.84 seconds |
| Started | Jul 22 07:44:58 PM PDT 24 |
| Finished | Jul 22 07:45:25 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-4b90c760-9c16-491e-9302-87221196a307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819813419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 819813419 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1457205466 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 136933693573 ps |
| CPU time | 2556.98 seconds |
| Started | Jul 22 07:45:02 PM PDT 24 |
| Finished | Jul 22 08:27:40 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-4b551940-7931-431b-bb03-918197cd501d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457205466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1457205466 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2645072354 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 318818164 ps |
| CPU time | 37.38 seconds |
| Started | Jul 22 07:45:09 PM PDT 24 |
| Finished | Jul 22 07:45:47 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-0df405e3-a89b-4915-b871-b052acf1fdef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645072354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2645072354 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.3433006106 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 435775350 ps |
| CPU time | 30.36 seconds |
| Started | Jul 22 07:44:59 PM PDT 24 |
| Finished | Jul 22 07:45:31 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-d4a3f0a9-f78e-4a2a-a26d-733a5414b943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433006106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3433006106 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.2770029833 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 452222522 ps |
| CPU time | 36.28 seconds |
| Started | Jul 22 07:45:47 PM PDT 24 |
| Finished | Jul 22 07:46:25 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5acf2a5a-5f66-439a-b5d5-12fe625f3154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770029833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.2770029833 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.855135584 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 21744533132 ps |
| CPU time | 217.17 seconds |
| Started | Jul 22 07:44:59 PM PDT 24 |
| Finished | Jul 22 07:48:37 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-1b809b38-fa51-4d19-928d-4b4e852c8f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855135584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.855135584 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4255549673 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 11734373453 ps |
| CPU time | 203.29 seconds |
| Started | Jul 22 07:44:58 PM PDT 24 |
| Finished | Jul 22 07:48:23 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-4c996996-cd7c-4c11-b7eb-2dc815a1f5ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255549673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.4255549673 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4186019272 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 33754624 ps |
| CPU time | 6.13 seconds |
| Started | Jul 22 07:45:08 PM PDT 24 |
| Finished | Jul 22 07:45:15 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-0538af28-d29d-45c3-9d75-06cf9a430b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186019272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.4186019272 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.2061673914 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 506322721 ps |
| CPU time | 36.19 seconds |
| Started | Jul 22 07:45:21 PM PDT 24 |
| Finished | Jul 22 07:45:59 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-9c4bea82-34cf-4088-ac3f-e35ea52c0da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061673914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2061673914 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.415842481 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 236708482 ps |
| CPU time | 9.92 seconds |
| Started | Jul 22 07:44:49 PM PDT 24 |
| Finished | Jul 22 07:45:00 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-7530a302-25aa-46bb-8cd8-3b0b39527bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415842481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.415842481 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.190790476 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 9805411936 ps |
| CPU time | 98.42 seconds |
| Started | Jul 22 07:44:48 PM PDT 24 |
| Finished | Jul 22 07:46:27 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-642d44b4-7ee7-4a82-8676-43fe3bd37315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190790476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.190790476 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1588773697 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 5973829597 ps |
| CPU time | 98.46 seconds |
| Started | Jul 22 07:45:10 PM PDT 24 |
| Finished | Jul 22 07:46:50 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-8684f164-b27b-4a8a-9367-97184d5be614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588773697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1588773697 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1323012568 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 40473408 ps |
| CPU time | 5.63 seconds |
| Started | Jul 22 07:44:53 PM PDT 24 |
| Finished | Jul 22 07:44:59 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-91aa37ef-bee6-4741-be3b-1555162e5424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323012568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.1323012568 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.1681103535 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 1873793025 ps |
| CPU time | 69.11 seconds |
| Started | Jul 22 07:45:14 PM PDT 24 |
| Finished | Jul 22 07:46:25 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-d743c766-00b0-4c78-a1a3-41ce2912f358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681103535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1681103535 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3583534252 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 4128585511 ps |
| CPU time | 326.59 seconds |
| Started | Jul 22 07:45:14 PM PDT 24 |
| Finished | Jul 22 07:50:42 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-173bfa9e-ec3c-4101-b0a8-8e446096babf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583534252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3583534252 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1228647822 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 66497714 ps |
| CPU time | 65 seconds |
| Started | Jul 22 07:45:10 PM PDT 24 |
| Finished | Jul 22 07:46:16 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-ed85468e-529d-4863-8fbc-c02cd2c1a094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228647822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.1228647822 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1723162144 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 2656609514 ps |
| CPU time | 341.75 seconds |
| Started | Jul 22 07:45:14 PM PDT 24 |
| Finished | Jul 22 07:50:57 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-1abd7511-d43e-4985-822e-09d4a56a49b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723162144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1723162144 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2203173099 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 262099571 ps |
| CPU time | 13.24 seconds |
| Started | Jul 22 07:44:59 PM PDT 24 |
| Finished | Jul 22 07:45:14 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-ea0696be-4042-4303-a4ee-5bec4c57674c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203173099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2203173099 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2598660354 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 8822115448 ps |
| CPU time | 964.31 seconds |
| Started | Jul 22 07:45:32 PM PDT 24 |
| Finished | Jul 22 08:01:38 PM PDT 24 |
| Peak memory | 648660 kb |
| Host | smart-c0e07918-3b09-44c3-9177-8a8181cc6671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598660354 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.2598660354 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1208623310 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5124235264 ps |
| CPU time | 587.2 seconds |
| Started | Jul 22 07:45:33 PM PDT 24 |
| Finished | Jul 22 07:55:21 PM PDT 24 |
| Peak memory | 599360 kb |
| Host | smart-447864c4-ae04-4413-b555-3daf01c16b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208623310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1208623310 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2787575940 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 14788822430 ps |
| CPU time | 1838.56 seconds |
| Started | Jul 22 07:45:19 PM PDT 24 |
| Finished | Jul 22 08:15:59 PM PDT 24 |
| Peak memory | 593708 kb |
| Host | smart-4952a758-ae5a-4474-8513-c850b118262f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787575940 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2787575940 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2895208509 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4699980152 ps |
| CPU time | 370.34 seconds |
| Started | Jul 22 07:45:18 PM PDT 24 |
| Finished | Jul 22 07:51:30 PM PDT 24 |
| Peak memory | 604380 kb |
| Host | smart-666ead88-09fc-4257-a2a6-417612e3e579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895208509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2895208509 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.1582513716 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 469565693 ps |
| CPU time | 39.24 seconds |
| Started | Jul 22 07:45:20 PM PDT 24 |
| Finished | Jul 22 07:46:00 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-0e09259e-5f55-445f-8d44-89984734e576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582513716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .1582513716 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3542081714 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 82582517026 ps |
| CPU time | 1547.55 seconds |
| Started | Jul 22 07:45:19 PM PDT 24 |
| Finished | Jul 22 08:11:07 PM PDT 24 |
| Peak memory | 577172 kb |
| Host | smart-f2d19721-a067-478c-b20a-6294658767e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542081714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3542081714 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4017691508 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 623105515 ps |
| CPU time | 24.56 seconds |
| Started | Jul 22 07:45:31 PM PDT 24 |
| Finished | Jul 22 07:45:57 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-d0691d47-7012-4b03-91d8-aa08541515e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017691508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.4017691508 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.457970787 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 420555557 ps |
| CPU time | 32.4 seconds |
| Started | Jul 22 07:45:20 PM PDT 24 |
| Finished | Jul 22 07:45:53 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-9809f0bb-0423-484d-8fff-cd778adc5108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457970787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.457970787 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.3537230499 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 2256690079 ps |
| CPU time | 73.36 seconds |
| Started | Jul 22 07:45:20 PM PDT 24 |
| Finished | Jul 22 07:46:35 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-aebbc8c0-7b70-4cc5-a3fc-49cd5c0c27d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537230499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.3537230499 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1706119165 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 44629524219 ps |
| CPU time | 486.18 seconds |
| Started | Jul 22 07:45:41 PM PDT 24 |
| Finished | Jul 22 07:53:49 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-62532049-974b-47f8-a86a-5ca795b52264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706119165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1706119165 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2847722226 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 68341567578 ps |
| CPU time | 1227.57 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 08:06:28 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-78d5135a-ee48-4060-9cd9-91f1ab2c8523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847722226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2847722226 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1873629724 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 58820631 ps |
| CPU time | 8.84 seconds |
| Started | Jul 22 07:45:19 PM PDT 24 |
| Finished | Jul 22 07:45:29 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-573e452f-3f36-44f6-b394-a539af1877d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873629724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.1873629724 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.2627055147 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 896632896 ps |
| CPU time | 26.56 seconds |
| Started | Jul 22 07:45:20 PM PDT 24 |
| Finished | Jul 22 07:45:48 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-6a927d04-74ac-4dc2-ac6a-7d7646e788d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627055147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2627055147 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.2790672454 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 165048497 ps |
| CPU time | 8.73 seconds |
| Started | Jul 22 07:45:56 PM PDT 24 |
| Finished | Jul 22 07:46:07 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-4a17fa16-4f5b-4937-963b-53846f61cf61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790672454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2790672454 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3068692087 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 6203220338 ps |
| CPU time | 61.47 seconds |
| Started | Jul 22 07:45:20 PM PDT 24 |
| Finished | Jul 22 07:46:23 PM PDT 24 |
| Peak memory | 574824 kb |
| Host | smart-923d75ae-a31f-4a63-bc71-d7294315c3f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068692087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3068692087 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1328646637 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 5359050631 ps |
| CPU time | 93.21 seconds |
| Started | Jul 22 07:45:20 PM PDT 24 |
| Finished | Jul 22 07:46:54 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-b07cba54-acf1-40e5-9e2d-d6b3547d3fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328646637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1328646637 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.420516351 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 54242619 ps |
| CPU time | 6.76 seconds |
| Started | Jul 22 07:45:24 PM PDT 24 |
| Finished | Jul 22 07:45:31 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-6b6990c3-a1e4-4bfe-a2dd-b7cde001ad28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420516351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays .420516351 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.932728035 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1748757596 ps |
| CPU time | 160.86 seconds |
| Started | Jul 22 07:45:31 PM PDT 24 |
| Finished | Jul 22 07:48:14 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-35267c63-66d1-422c-9df6-441fa4a0b6a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932728035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.932728035 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4065214868 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 2686999029 ps |
| CPU time | 99.63 seconds |
| Started | Jul 22 07:46:05 PM PDT 24 |
| Finished | Jul 22 07:47:45 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-2ae164f7-c204-44a9-bd1e-4ee2cb1d9363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065214868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4065214868 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.853974484 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 337011198 ps |
| CPU time | 211.39 seconds |
| Started | Jul 22 07:45:33 PM PDT 24 |
| Finished | Jul 22 07:49:05 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-7cc17024-b8ec-4f49-998c-1b0a57672aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853974484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_ with_rand_reset.853974484 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2684693210 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 405253266 ps |
| CPU time | 178.71 seconds |
| Started | Jul 22 07:45:32 PM PDT 24 |
| Finished | Jul 22 07:48:32 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-1283a9b2-fe84-4c75-80d2-864babaee370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684693210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.2684693210 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.392180331 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 1007683896 ps |
| CPU time | 39.44 seconds |
| Started | Jul 22 07:45:31 PM PDT 24 |
| Finished | Jul 22 07:46:12 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-613e1450-db9f-4340-ae18-127c2d77a7fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392180331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.392180331 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1380659086 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 11833798774 ps |
| CPU time | 1032.24 seconds |
| Started | Jul 22 07:45:54 PM PDT 24 |
| Finished | Jul 22 08:03:07 PM PDT 24 |
| Peak memory | 648436 kb |
| Host | smart-ecd9c21d-14f6-49f0-aaed-e53812d2bc22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380659086 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.1380659086 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2712922732 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 6353792464 ps |
| CPU time | 669.76 seconds |
| Started | Jul 22 07:45:53 PM PDT 24 |
| Finished | Jul 22 07:57:04 PM PDT 24 |
| Peak memory | 598908 kb |
| Host | smart-bf5550dd-dde7-450f-8099-0e11d9f62a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712922732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2712922732 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3073322208 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 16742870744 ps |
| CPU time | 2243.25 seconds |
| Started | Jul 22 07:45:32 PM PDT 24 |
| Finished | Jul 22 08:22:57 PM PDT 24 |
| Peak memory | 593708 kb |
| Host | smart-d00921e1-b023-47fd-a72d-4beca0312553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073322208 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3073322208 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.1937281712 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2882327413 ps |
| CPU time | 108.78 seconds |
| Started | Jul 22 07:45:44 PM PDT 24 |
| Finished | Jul 22 07:47:33 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-13f293ff-8422-480d-81e2-3773beb4bb95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937281712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .1937281712 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.393501838 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 15015090857 ps |
| CPU time | 248.14 seconds |
| Started | Jul 22 07:45:47 PM PDT 24 |
| Finished | Jul 22 07:49:57 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-b34df5d9-efae-4608-abfe-41e9b19469bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393501838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.393501838 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2300342062 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 74745172 ps |
| CPU time | 9.62 seconds |
| Started | Jul 22 07:45:56 PM PDT 24 |
| Finished | Jul 22 07:46:08 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-f34083f2-d030-4cc3-9fb7-1108eaa69d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300342062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2300342062 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.3494763935 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 34820379 ps |
| CPU time | 5.43 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:46:02 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-0575cf4f-4068-49a8-a73b-3462516a49cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494763935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3494763935 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.3190623016 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 1166243945 ps |
| CPU time | 41.46 seconds |
| Started | Jul 22 07:45:46 PM PDT 24 |
| Finished | Jul 22 07:46:29 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-a794b898-cbbb-4278-b2e3-11810181144e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190623016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3190623016 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.648779584 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 37697489310 ps |
| CPU time | 365.56 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:51:53 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-fbb7941e-bb4a-4eed-b60b-851e03b24db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648779584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.648779584 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3222300775 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 50884938462 ps |
| CPU time | 844.39 seconds |
| Started | Jul 22 07:45:47 PM PDT 24 |
| Finished | Jul 22 07:59:53 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-7a9ce251-cac9-4076-8a61-ad22dc022680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222300775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3222300775 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4077125923 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 244862913 ps |
| CPU time | 24.81 seconds |
| Started | Jul 22 07:45:42 PM PDT 24 |
| Finished | Jul 22 07:46:07 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-2c6fd44a-8c48-4015-af3a-d14680ad65da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077125923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.4077125923 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2658690522 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 228044634 ps |
| CPU time | 9.34 seconds |
| Started | Jul 22 07:46:16 PM PDT 24 |
| Finished | Jul 22 07:46:26 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-8ecebc90-ca87-469c-b83c-c2baddd0aecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658690522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2658690522 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.3120411858 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 215519347 ps |
| CPU time | 10.07 seconds |
| Started | Jul 22 07:45:30 PM PDT 24 |
| Finished | Jul 22 07:45:42 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-6db756d0-6c89-4076-a77e-eb664ae8ded3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120411858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3120411858 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1221550074 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 10587452559 ps |
| CPU time | 104.05 seconds |
| Started | Jul 22 07:45:42 PM PDT 24 |
| Finished | Jul 22 07:47:27 PM PDT 24 |
| Peak memory | 574856 kb |
| Host | smart-0e38b00e-5f16-42da-9b02-a71ebb6f405f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221550074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1221550074 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2001543669 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 5856272245 ps |
| CPU time | 97.27 seconds |
| Started | Jul 22 07:45:41 PM PDT 24 |
| Finished | Jul 22 07:47:20 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-ddbbd9c1-6b7d-4741-81c9-384132e0ddd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001543669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2001543669 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3717116575 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 45907493 ps |
| CPU time | 6 seconds |
| Started | Jul 22 07:45:40 PM PDT 24 |
| Finished | Jul 22 07:45:47 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-4dfb809a-dc30-455f-8634-01c3c7a210a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717116575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3717116575 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3525518023 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 2149937634 ps |
| CPU time | 208.99 seconds |
| Started | Jul 22 07:45:54 PM PDT 24 |
| Finished | Jul 22 07:49:25 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-8af00d7b-2c58-4db6-8dc9-514c6b209bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525518023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3525518023 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3454584701 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 241069055 ps |
| CPU time | 18.5 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:46:15 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-f82e7c41-a8c3-4094-943a-e9ec9f1d6a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454584701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3454584701 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2987534628 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 810091229 ps |
| CPU time | 289.57 seconds |
| Started | Jul 22 07:45:54 PM PDT 24 |
| Finished | Jul 22 07:50:45 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-e9fc92d5-48e6-4f80-b58d-fe167909da72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987534628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.2987534628 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2332649978 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 23022201502 ps |
| CPU time | 946.9 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 08:01:43 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-52c64654-0b5a-4bf3-a4e9-90d4ae5d1a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332649978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.2332649978 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2285811218 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 19642200 ps |
| CPU time | 5.5 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:46:01 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-266fa762-8024-4dea-a5f5-102c64a2445f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285811218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2285811218 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.74155834 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 8018722878 ps |
| CPU time | 816.05 seconds |
| Started | Jul 22 07:46:15 PM PDT 24 |
| Finished | Jul 22 07:59:52 PM PDT 24 |
| Peak memory | 653580 kb |
| Host | smart-99e4c0e7-8680-4863-8f60-2bb91908cb46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74155834 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.74155834 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.1388696310 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 4281228228 ps |
| CPU time | 320.43 seconds |
| Started | Jul 22 07:46:15 PM PDT 24 |
| Finished | Jul 22 07:51:36 PM PDT 24 |
| Peak memory | 599108 kb |
| Host | smart-129f3181-4feb-405e-aad9-3dd0330cb302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388696310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1388696310 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3840500956 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 31523834657 ps |
| CPU time | 4096.45 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 08:54:13 PM PDT 24 |
| Peak memory | 593872 kb |
| Host | smart-0b00ba98-880b-465d-8cf8-3470c4d20558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840500956 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3840500956 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3678552464 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 974319234 ps |
| CPU time | 40.45 seconds |
| Started | Jul 22 07:46:02 PM PDT 24 |
| Finished | Jul 22 07:46:44 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-2849a9df-7d21-4ad1-92c5-5a2835b28655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678552464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3678552464 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3043419125 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 119305634569 ps |
| CPU time | 1903.33 seconds |
| Started | Jul 22 07:46:03 PM PDT 24 |
| Finished | Jul 22 08:17:48 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-782ce690-3eb2-4191-a469-d80177f1cf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043419125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3043419125 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.487063693 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 497757503 ps |
| CPU time | 20.7 seconds |
| Started | Jul 22 07:46:04 PM PDT 24 |
| Finished | Jul 22 07:46:25 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-b2b7a2c6-ea95-4380-b015-a19e7a98954b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487063693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.487063693 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.3715952084 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 2473653049 ps |
| CPU time | 89.38 seconds |
| Started | Jul 22 07:46:05 PM PDT 24 |
| Finished | Jul 22 07:47:35 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-961f323b-624a-4d60-8991-72959dd5b383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715952084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3715952084 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1519632237 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 6458188876 ps |
| CPU time | 100.28 seconds |
| Started | Jul 22 07:46:10 PM PDT 24 |
| Finished | Jul 22 07:47:50 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-78dd3e71-77bb-41f5-91a5-9ef449233354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519632237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1519632237 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1646189886 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 372671541 ps |
| CPU time | 33.32 seconds |
| Started | Jul 22 07:46:04 PM PDT 24 |
| Finished | Jul 22 07:46:38 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-eaae7a84-7c34-442b-a620-47d990645706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646189886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.1646189886 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.4046329007 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 2720733956 ps |
| CPU time | 74.42 seconds |
| Started | Jul 22 07:46:09 PM PDT 24 |
| Finished | Jul 22 07:47:24 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-a5cb78a8-079b-448e-931a-732d2d37dd3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046329007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4046329007 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2488779909 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 256331806 ps |
| CPU time | 10.56 seconds |
| Started | Jul 22 07:45:57 PM PDT 24 |
| Finished | Jul 22 07:46:10 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-6bc8818e-8511-4478-9213-63b2b49ba5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488779909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2488779909 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.923920130 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 6759706756 ps |
| CPU time | 72.73 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:47:10 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-9c6b46e5-7eb3-4a7e-accc-a40d51fc37e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923920130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.923920130 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2236106280 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 6445703796 ps |
| CPU time | 109.93 seconds |
| Started | Jul 22 07:46:06 PM PDT 24 |
| Finished | Jul 22 07:47:56 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-39fb1692-ee5b-436b-af15-7e70d667ad34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236106280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2236106280 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2654793770 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 47114698 ps |
| CPU time | 6.5 seconds |
| Started | Jul 22 07:45:54 PM PDT 24 |
| Finished | Jul 22 07:46:02 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-15a71771-932c-4fe0-8d41-6fbb0b02b414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654793770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2654793770 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1679304969 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 13081769612 ps |
| CPU time | 522.02 seconds |
| Started | Jul 22 07:46:05 PM PDT 24 |
| Finished | Jul 22 07:54:48 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-c4d4a12e-39cb-4bd7-8d74-8c07aa5995cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679304969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1679304969 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.59364168 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 13752674444 ps |
| CPU time | 531.41 seconds |
| Started | Jul 22 07:46:05 PM PDT 24 |
| Finished | Jul 22 07:54:57 PM PDT 24 |
| Peak memory | 577044 kb |
| Host | smart-00905ecf-06a7-4d45-907a-c121749ecb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59364168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.59364168 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1160817477 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 6546541226 ps |
| CPU time | 702.67 seconds |
| Started | Jul 22 07:46:32 PM PDT 24 |
| Finished | Jul 22 07:58:16 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-672d0454-956c-40de-a8a8-18a1e8ae3828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160817477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.1160817477 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3090431630 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 439331354 ps |
| CPU time | 18.98 seconds |
| Started | Jul 22 07:46:25 PM PDT 24 |
| Finished | Jul 22 07:46:45 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-b3f47dd8-1627-48d5-8ed9-8531d34ff8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090431630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3090431630 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2814490742 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 6292623772 ps |
| CPU time | 532.52 seconds |
| Started | Jul 22 07:46:38 PM PDT 24 |
| Finished | Jul 22 07:55:32 PM PDT 24 |
| Peak memory | 641156 kb |
| Host | smart-02cd1771-4185-409a-a5bc-d75e5c7c4c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814490742 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.2814490742 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.3456376951 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 3481769320 ps |
| CPU time | 312.85 seconds |
| Started | Jul 22 07:46:38 PM PDT 24 |
| Finished | Jul 22 07:51:53 PM PDT 24 |
| Peak memory | 599200 kb |
| Host | smart-17b10d63-e16e-4389-ae1c-87647220329f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456376951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.3456376951 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.780187778 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 31949069619 ps |
| CPU time | 4097.24 seconds |
| Started | Jul 22 07:46:15 PM PDT 24 |
| Finished | Jul 22 08:54:33 PM PDT 24 |
| Peak memory | 593380 kb |
| Host | smart-c985aef2-d2f7-4f32-9d7d-94d9f55eae12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780187778 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.chip_same_csr_outstanding.780187778 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1941946546 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 3520059736 ps |
| CPU time | 227.85 seconds |
| Started | Jul 22 07:46:15 PM PDT 24 |
| Finished | Jul 22 07:50:04 PM PDT 24 |
| Peak memory | 599328 kb |
| Host | smart-814a1f2b-9825-4d54-acb6-d60e8d5bf42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941946546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1941946546 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.650421265 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 3432472018 ps |
| CPU time | 143.51 seconds |
| Started | Jul 22 07:46:44 PM PDT 24 |
| Finished | Jul 22 07:49:09 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-f06a193a-0bf5-4811-9e55-66b8349b0a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650421265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 650421265 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3249023112 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 107856001361 ps |
| CPU time | 1843.15 seconds |
| Started | Jul 22 07:46:27 PM PDT 24 |
| Finished | Jul 22 08:17:12 PM PDT 24 |
| Peak memory | 576968 kb |
| Host | smart-b5979e56-5470-4fa2-9ed2-f718a27b8734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249023112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3249023112 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3137414209 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 973105241 ps |
| CPU time | 38.77 seconds |
| Started | Jul 22 07:46:29 PM PDT 24 |
| Finished | Jul 22 07:47:08 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-84cde408-bf73-4fef-920c-8850d7ac61c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137414209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3137414209 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2154967584 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 1245092238 ps |
| CPU time | 44.66 seconds |
| Started | Jul 22 07:46:47 PM PDT 24 |
| Finished | Jul 22 07:47:33 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-2300f305-6528-4d81-a749-59c382ed8ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154967584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2154967584 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3825626037 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 403819386 ps |
| CPU time | 14.6 seconds |
| Started | Jul 22 07:46:27 PM PDT 24 |
| Finished | Jul 22 07:46:42 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-a69ba8ad-5d42-4777-a3ed-40fe8b20b48f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825626037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3825626037 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3795817087 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 51647653627 ps |
| CPU time | 497.48 seconds |
| Started | Jul 22 07:46:26 PM PDT 24 |
| Finished | Jul 22 07:54:44 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-4665a54c-019e-4161-8d71-0a161cdfbb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795817087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3795817087 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1015479790 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 55695326453 ps |
| CPU time | 908.87 seconds |
| Started | Jul 22 07:46:27 PM PDT 24 |
| Finished | Jul 22 08:01:37 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-7edaf808-8e81-477c-829a-6266db2b2cad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015479790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1015479790 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1485096269 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 370317916 ps |
| CPU time | 29.25 seconds |
| Started | Jul 22 07:46:25 PM PDT 24 |
| Finished | Jul 22 07:46:56 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-bbfe403a-00f9-4c4e-b099-e1f1dba9db37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485096269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1485096269 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.3433883956 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 360653972 ps |
| CPU time | 27.95 seconds |
| Started | Jul 22 07:47:30 PM PDT 24 |
| Finished | Jul 22 07:48:02 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-348d5329-8666-4d5f-93c6-9337b43cb8c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433883956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3433883956 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3928575570 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 169460129 ps |
| CPU time | 8.06 seconds |
| Started | Jul 22 07:46:29 PM PDT 24 |
| Finished | Jul 22 07:46:38 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-d49827e4-8443-4140-94b6-5a07753cf3b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928575570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3928575570 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1929937286 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 11556146574 ps |
| CPU time | 106.14 seconds |
| Started | Jul 22 07:46:26 PM PDT 24 |
| Finished | Jul 22 07:48:13 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-56553be5-fbce-40f1-bf19-ad4c1ea7897c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929937286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1929937286 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3358377717 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 3959311324 ps |
| CPU time | 65.7 seconds |
| Started | Jul 22 07:46:27 PM PDT 24 |
| Finished | Jul 22 07:47:33 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-4d17bfe5-f7d8-4e84-8b5f-3d0836515d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358377717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3358377717 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.83629389 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 33683301 ps |
| CPU time | 5.59 seconds |
| Started | Jul 22 07:46:26 PM PDT 24 |
| Finished | Jul 22 07:46:33 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-78e8e05a-89c8-4c0d-bad4-36b9155b983d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83629389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.83629389 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.43798621 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 14587407594 ps |
| CPU time | 545.53 seconds |
| Started | Jul 22 07:46:25 PM PDT 24 |
| Finished | Jul 22 07:55:32 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-5f48b312-ba14-44b7-9cd6-155382ad5129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43798621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.43798621 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.185910919 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 3663163043 ps |
| CPU time | 293.44 seconds |
| Started | Jul 22 07:46:40 PM PDT 24 |
| Finished | Jul 22 07:51:35 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-d6fd6667-5fed-4161-bbb8-4a1e957d300e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185910919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.185910919 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1254397313 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 291251946 ps |
| CPU time | 100.95 seconds |
| Started | Jul 22 07:46:27 PM PDT 24 |
| Finished | Jul 22 07:48:09 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-43021c4a-e99c-4fb3-a76c-2eeca8a5ad23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254397313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.1254397313 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.828511557 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1413959733 ps |
| CPU time | 292.49 seconds |
| Started | Jul 22 07:46:39 PM PDT 24 |
| Finished | Jul 22 07:51:33 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-9687cd71-9dd9-4279-812b-cef94f81d6fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828511557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_reset_error.828511557 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2452823738 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 287918242 ps |
| CPU time | 34.02 seconds |
| Started | Jul 22 07:47:31 PM PDT 24 |
| Finished | Jul 22 07:48:09 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-811c0898-4c5b-48b9-9254-4102d98eb79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452823738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2452823738 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1797264196 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 7053451576 ps |
| CPU time | 463.31 seconds |
| Started | Jul 22 07:47:08 PM PDT 24 |
| Finished | Jul 22 07:54:53 PM PDT 24 |
| Peak memory | 640256 kb |
| Host | smart-fe5ba06f-f64d-4062-827d-342396ef7291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797264196 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.1797264196 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.2477215816 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 5731177144 ps |
| CPU time | 564.18 seconds |
| Started | Jul 22 07:47:00 PM PDT 24 |
| Finished | Jul 22 07:56:25 PM PDT 24 |
| Peak memory | 599352 kb |
| Host | smart-e37c0ad9-4a84-4af4-b5f3-353de7c2f295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477215816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2477215816 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2690123317 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 24869397060 ps |
| CPU time | 3017.19 seconds |
| Started | Jul 22 07:46:38 PM PDT 24 |
| Finished | Jul 22 08:36:58 PM PDT 24 |
| Peak memory | 594148 kb |
| Host | smart-8bcf24fc-adab-4ff1-a99b-bdc333c4d906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690123317 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2690123317 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.3746942874 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 658504108 ps |
| CPU time | 55.3 seconds |
| Started | Jul 22 07:46:52 PM PDT 24 |
| Finished | Jul 22 07:47:48 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-44780e13-7db7-47c2-9ac9-44d4bfd18409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746942874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .3746942874 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1660153603 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 147912272082 ps |
| CPU time | 2612.73 seconds |
| Started | Jul 22 07:46:49 PM PDT 24 |
| Finished | Jul 22 08:30:23 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-74e39b9e-eae9-4e17-bbbc-ee0a729fbb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660153603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1660153603 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2834050922 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 248117696 ps |
| CPU time | 23.98 seconds |
| Started | Jul 22 07:46:52 PM PDT 24 |
| Finished | Jul 22 07:47:17 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-ff6b2aa0-5ec0-4f68-b229-5b4a3938c702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834050922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.2834050922 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3065361351 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 289515900 ps |
| CPU time | 25.08 seconds |
| Started | Jul 22 07:46:49 PM PDT 24 |
| Finished | Jul 22 07:47:16 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-2a4dba22-5d08-4a12-ac8c-933b71550d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065361351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3065361351 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.296512932 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 788584192 ps |
| CPU time | 28.5 seconds |
| Started | Jul 22 07:46:38 PM PDT 24 |
| Finished | Jul 22 07:47:09 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-15aefabc-51b4-4f21-becd-16b7df34362e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296512932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.296512932 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3557229046 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 40402764010 ps |
| CPU time | 429.1 seconds |
| Started | Jul 22 07:46:49 PM PDT 24 |
| Finished | Jul 22 07:54:00 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-c2c2e82e-79c5-444c-a863-fd3fe107eeac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557229046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3557229046 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3999823815 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 45434779466 ps |
| CPU time | 669.54 seconds |
| Started | Jul 22 07:46:52 PM PDT 24 |
| Finished | Jul 22 07:58:03 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-7d98c671-8840-4d99-9020-55d00c565c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999823815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3999823815 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.233238729 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 576778861 ps |
| CPU time | 47.42 seconds |
| Started | Jul 22 07:46:50 PM PDT 24 |
| Finished | Jul 22 07:47:39 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-c740c7a0-4a9b-48f8-b7ff-c2827f15008b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233238729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_dela ys.233238729 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2625593463 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 94981068 ps |
| CPU time | 10.96 seconds |
| Started | Jul 22 07:46:49 PM PDT 24 |
| Finished | Jul 22 07:47:02 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-b2127879-8dbb-4ee4-9681-cfc815f1ed19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625593463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2625593463 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.68930195 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 215553458 ps |
| CPU time | 9.09 seconds |
| Started | Jul 22 07:46:41 PM PDT 24 |
| Finished | Jul 22 07:46:52 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-d2fe11a4-c59a-4ae6-8863-e90eea9d0cc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68930195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.68930195 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1506335381 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 9609962505 ps |
| CPU time | 92.91 seconds |
| Started | Jul 22 07:46:39 PM PDT 24 |
| Finished | Jul 22 07:48:13 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-d2afbfa3-f9eb-407d-a860-17d448e2786b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506335381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1506335381 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1743672438 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 2932742027 ps |
| CPU time | 51.43 seconds |
| Started | Jul 22 07:46:41 PM PDT 24 |
| Finished | Jul 22 07:47:35 PM PDT 24 |
| Peak memory | 574852 kb |
| Host | smart-24bc579e-d566-4de3-b8e6-7a8e170f6cf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743672438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1743672438 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2770763671 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 50578828 ps |
| CPU time | 7.27 seconds |
| Started | Jul 22 07:46:38 PM PDT 24 |
| Finished | Jul 22 07:46:47 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-bc7beb2d-88fe-440f-9bae-7aa57a7f24aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770763671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2770763671 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.2339728292 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 585813561 ps |
| CPU time | 51.87 seconds |
| Started | Jul 22 07:46:49 PM PDT 24 |
| Finished | Jul 22 07:47:42 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-0e9cef3c-7504-4d1f-96d2-a494cacfad9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339728292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2339728292 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.349118994 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 13295343104 ps |
| CPU time | 418.64 seconds |
| Started | Jul 22 07:46:52 PM PDT 24 |
| Finished | Jul 22 07:53:52 PM PDT 24 |
| Peak memory | 577068 kb |
| Host | smart-fea72cb0-7f2f-402d-bdb9-dd19dd6b74dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349118994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.349118994 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3745922705 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 168920127 ps |
| CPU time | 115.92 seconds |
| Started | Jul 22 07:46:58 PM PDT 24 |
| Finished | Jul 22 07:48:55 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-28236445-2a5b-4d74-a114-16a8e80e56b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745922705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.3745922705 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3823895906 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 506611737 ps |
| CPU time | 24.16 seconds |
| Started | Jul 22 07:46:52 PM PDT 24 |
| Finished | Jul 22 07:47:17 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-10dfabd1-a599-49ee-b51e-4e4dd59f700d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823895906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3823895906 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.4130055470 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 6691999064 ps |
| CPU time | 393.06 seconds |
| Started | Jul 22 07:47:11 PM PDT 24 |
| Finished | Jul 22 07:53:46 PM PDT 24 |
| Peak memory | 642648 kb |
| Host | smart-03c61a01-60fe-47c5-b844-2bdcb760f195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130055470 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.4130055470 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3558275812 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5715248978 ps |
| CPU time | 535.76 seconds |
| Started | Jul 22 07:47:20 PM PDT 24 |
| Finished | Jul 22 07:56:17 PM PDT 24 |
| Peak memory | 599124 kb |
| Host | smart-cfa96af0-0e75-4db7-b5aa-bc1667f17ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558275812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3558275812 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.931040570 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 31732396724 ps |
| CPU time | 3786.83 seconds |
| Started | Jul 22 07:47:00 PM PDT 24 |
| Finished | Jul 22 08:50:08 PM PDT 24 |
| Peak memory | 594084 kb |
| Host | smart-4c87765e-0abf-4185-90f1-f54e517e4bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931040570 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.chip_same_csr_outstanding.931040570 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.16825012 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1100047925 ps |
| CPU time | 70.82 seconds |
| Started | Jul 22 07:47:37 PM PDT 24 |
| Finished | Jul 22 07:48:51 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-f5d3811a-f63e-45ea-9c3f-5346d14e7032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16825012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.16825012 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1344750894 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 47979830225 ps |
| CPU time | 742.29 seconds |
| Started | Jul 22 07:47:08 PM PDT 24 |
| Finished | Jul 22 07:59:31 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-64988c27-238a-4211-9409-6bd0099d92da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344750894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1344750894 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1847659518 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 176329570 ps |
| CPU time | 9.69 seconds |
| Started | Jul 22 07:47:10 PM PDT 24 |
| Finished | Jul 22 07:47:22 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-e4c6f560-a282-4ebf-80c7-13286319767a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847659518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1847659518 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3261265382 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 2208815877 ps |
| CPU time | 69.3 seconds |
| Started | Jul 22 07:47:20 PM PDT 24 |
| Finished | Jul 22 07:48:30 PM PDT 24 |
| Peak memory | 576876 kb |
| Host | smart-e5e0804f-a16e-4c2a-9e93-fef3e2a55417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261265382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3261265382 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.2484357998 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 1601347601 ps |
| CPU time | 62.18 seconds |
| Started | Jul 22 07:47:08 PM PDT 24 |
| Finished | Jul 22 07:48:12 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-fcdd52b5-5dd9-434c-bad5-e26f7269bc51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484357998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2484357998 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.4174953118 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 77374386909 ps |
| CPU time | 829.5 seconds |
| Started | Jul 22 07:47:09 PM PDT 24 |
| Finished | Jul 22 08:01:00 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-f5c18e71-0d20-4d72-bffa-f45506e6a679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174953118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4174953118 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.3292856380 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 29252907221 ps |
| CPU time | 477.29 seconds |
| Started | Jul 22 07:47:11 PM PDT 24 |
| Finished | Jul 22 07:55:11 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-1dc3004b-5c9e-4a29-85ec-3b1c3b5cd33a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292856380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3292856380 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.4190145586 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 135689727 ps |
| CPU time | 17.81 seconds |
| Started | Jul 22 07:46:59 PM PDT 24 |
| Finished | Jul 22 07:47:18 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-ac493ad0-9117-4b05-9d26-536af1e70b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190145586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.4190145586 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.2472062955 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 1138140756 ps |
| CPU time | 33.21 seconds |
| Started | Jul 22 07:47:12 PM PDT 24 |
| Finished | Jul 22 07:47:47 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-87a136ba-0b95-4d47-b4ef-4e2ee25589d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472062955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2472062955 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2634599930 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 213870814 ps |
| CPU time | 8.92 seconds |
| Started | Jul 22 07:46:59 PM PDT 24 |
| Finished | Jul 22 07:47:09 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-67fc0d48-8a28-405c-9e7a-d51c976763e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634599930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2634599930 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.3103129389 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 9630591545 ps |
| CPU time | 94.41 seconds |
| Started | Jul 22 07:47:00 PM PDT 24 |
| Finished | Jul 22 07:48:35 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-fe3a488e-d0bb-4558-aec0-88d5205ffd49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103129389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3103129389 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.3389029552 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 6098039945 ps |
| CPU time | 104.46 seconds |
| Started | Jul 22 07:47:08 PM PDT 24 |
| Finished | Jul 22 07:48:55 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-aff0ba1c-ee63-41e1-8e81-0d00d8c18f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389029552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3389029552 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.412704252 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 51739592 ps |
| CPU time | 6.3 seconds |
| Started | Jul 22 07:47:00 PM PDT 24 |
| Finished | Jul 22 07:47:07 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-b8d91a54-c4ef-404d-90b2-b68a395876ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412704252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays .412704252 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.3772029313 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3203028125 ps |
| CPU time | 316.5 seconds |
| Started | Jul 22 07:47:11 PM PDT 24 |
| Finished | Jul 22 07:52:30 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-5a7be6fb-2e61-43b6-aaa3-5888f306d439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772029313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3772029313 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.10021519 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 2332391402 ps |
| CPU time | 166.1 seconds |
| Started | Jul 22 07:47:43 PM PDT 24 |
| Finished | Jul 22 07:50:30 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-8d2761b0-4e68-4347-89b7-cf4701432815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.10021519 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2903477682 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 487804643 ps |
| CPU time | 213.11 seconds |
| Started | Jul 22 07:47:10 PM PDT 24 |
| Finished | Jul 22 07:50:45 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-9797f084-32d5-410b-b7b2-0347b8c722c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903477682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.2903477682 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3384214335 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5325236443 ps |
| CPU time | 337.52 seconds |
| Started | Jul 22 07:47:42 PM PDT 24 |
| Finished | Jul 22 07:53:20 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-01a5dc6a-e2e9-4d00-8e30-5ac349b03db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384214335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.3384214335 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1918271059 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 1081839808 ps |
| CPU time | 43.37 seconds |
| Started | Jul 22 07:47:21 PM PDT 24 |
| Finished | Jul 22 07:48:06 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-a1ea023c-c473-4896-a01c-b7bf10c6fc31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918271059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1918271059 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.476363689 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 16431445144 ps |
| CPU time | 2265.3 seconds |
| Started | Jul 22 07:47:09 PM PDT 24 |
| Finished | Jul 22 08:24:57 PM PDT 24 |
| Peak memory | 593656 kb |
| Host | smart-b5a69fa6-875b-4ebe-ba7b-24fc78f9e814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476363689 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.476363689 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.2690054161 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4425056134 ps |
| CPU time | 236.98 seconds |
| Started | Jul 22 07:47:20 PM PDT 24 |
| Finished | Jul 22 07:51:18 PM PDT 24 |
| Peak memory | 599204 kb |
| Host | smart-d74c1cd7-c2fb-4f9d-b566-68e4d8d3ba17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690054161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2690054161 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1429333804 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 371792556 ps |
| CPU time | 34.53 seconds |
| Started | Jul 22 07:47:19 PM PDT 24 |
| Finished | Jul 22 07:47:55 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-16293b04-7ff4-4f24-882b-59a2fab572a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429333804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1429333804 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1618176192 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 58232769933 ps |
| CPU time | 909.77 seconds |
| Started | Jul 22 07:47:29 PM PDT 24 |
| Finished | Jul 22 08:02:41 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-579994aa-0172-4273-8cd1-9da72500c274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618176192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.1618176192 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1289314523 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 80416900 ps |
| CPU time | 6.86 seconds |
| Started | Jul 22 07:47:30 PM PDT 24 |
| Finished | Jul 22 07:47:39 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-7bc998ec-b74a-4d17-82e9-11c6c6571374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289314523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.1289314523 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2569110375 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 1705013568 ps |
| CPU time | 60.31 seconds |
| Started | Jul 22 07:48:13 PM PDT 24 |
| Finished | Jul 22 07:49:14 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-89160ec7-1455-41c6-85fa-497b70c4fbf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569110375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2569110375 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.3954912563 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 1065097701 ps |
| CPU time | 36.25 seconds |
| Started | Jul 22 07:47:30 PM PDT 24 |
| Finished | Jul 22 07:48:08 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-df5887de-a7a7-4c2a-bc04-2c16f39a583b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954912563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3954912563 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.426663141 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 33923137840 ps |
| CPU time | 351.63 seconds |
| Started | Jul 22 07:47:21 PM PDT 24 |
| Finished | Jul 22 07:53:14 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-ee8d6f81-dd00-49fb-95a9-b0916353813e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426663141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.426663141 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1633324753 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 35934344767 ps |
| CPU time | 623.09 seconds |
| Started | Jul 22 07:47:20 PM PDT 24 |
| Finished | Jul 22 07:57:45 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-f40f1ede-98e6-4dcc-96cf-b3cda58f1e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633324753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1633324753 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.493247352 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 480910028 ps |
| CPU time | 47.43 seconds |
| Started | Jul 22 07:47:30 PM PDT 24 |
| Finished | Jul 22 07:48:19 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-f979d469-ce5f-4a31-9069-ee86a4c14f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493247352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_dela ys.493247352 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.469328800 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 407674666 ps |
| CPU time | 33.23 seconds |
| Started | Jul 22 07:47:21 PM PDT 24 |
| Finished | Jul 22 07:47:55 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-fc3150d6-074f-4d74-a7b6-9fbd1a88a979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469328800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.469328800 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3183242297 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 172868878 ps |
| CPU time | 8.37 seconds |
| Started | Jul 22 07:47:20 PM PDT 24 |
| Finished | Jul 22 07:47:30 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-28c1f9bf-4d0a-4c00-8cce-3b561920a989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183242297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3183242297 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.973203636 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 10166810944 ps |
| CPU time | 100.67 seconds |
| Started | Jul 22 07:47:22 PM PDT 24 |
| Finished | Jul 22 07:49:03 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-967805a4-8708-4c26-a8db-8e5b0593b56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973203636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.973203636 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.4119384048 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 3890609144 ps |
| CPU time | 61.7 seconds |
| Started | Jul 22 07:47:29 PM PDT 24 |
| Finished | Jul 22 07:48:32 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-98d6562c-cef6-458f-97ed-9337270d2b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119384048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4119384048 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.299593939 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 50822777 ps |
| CPU time | 6.5 seconds |
| Started | Jul 22 07:47:23 PM PDT 24 |
| Finished | Jul 22 07:47:30 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-b4899196-b8ea-4aad-858a-e3469422c3fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299593939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays .299593939 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.465449196 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 6270652288 ps |
| CPU time | 247.04 seconds |
| Started | Jul 22 07:47:34 PM PDT 24 |
| Finished | Jul 22 07:51:46 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-7273ae6d-2246-4653-9f4a-9381b9180bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465449196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.465449196 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3729382229 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 7953183297 ps |
| CPU time | 302.98 seconds |
| Started | Jul 22 07:47:42 PM PDT 24 |
| Finished | Jul 22 07:52:46 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-6570fb21-68d2-4828-ae95-6f575aae0f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729382229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3729382229 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.4100040960 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 637756870 ps |
| CPU time | 145.94 seconds |
| Started | Jul 22 07:47:30 PM PDT 24 |
| Finished | Jul 22 07:50:00 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-52ca2c28-cf20-4d85-ab83-e7eb6be4bdd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100040960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.4100040960 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3726767951 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 77653377 ps |
| CPU time | 6.8 seconds |
| Started | Jul 22 07:47:43 PM PDT 24 |
| Finished | Jul 22 07:47:51 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-62a4e6e7-3a7b-4b60-a4d6-40d28270a680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726767951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3726767951 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3039231575 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 9830339104 ps |
| CPU time | 730.04 seconds |
| Started | Jul 22 07:47:55 PM PDT 24 |
| Finished | Jul 22 08:00:06 PM PDT 24 |
| Peak memory | 653612 kb |
| Host | smart-8231741d-edb9-44f6-b8c8-755287877c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039231575 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.3039231575 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2018328683 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 4149733390 ps |
| CPU time | 318.15 seconds |
| Started | Jul 22 07:47:56 PM PDT 24 |
| Finished | Jul 22 07:53:16 PM PDT 24 |
| Peak memory | 597976 kb |
| Host | smart-12e7da9a-97b0-4524-8ba0-65539b8be434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018328683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2018328683 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3464043838 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 29624222966 ps |
| CPU time | 4193.89 seconds |
| Started | Jul 22 07:47:43 PM PDT 24 |
| Finished | Jul 22 08:57:38 PM PDT 24 |
| Peak memory | 593716 kb |
| Host | smart-28f3f597-6083-4d3d-a23f-753eed652cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464043838 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3464043838 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.3291693352 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3937995038 ps |
| CPU time | 221.17 seconds |
| Started | Jul 22 07:47:31 PM PDT 24 |
| Finished | Jul 22 07:51:15 PM PDT 24 |
| Peak memory | 604484 kb |
| Host | smart-248d92db-3f8b-432e-85df-0c0b9aa10167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291693352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3291693352 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2110610585 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 402266731 ps |
| CPU time | 27.33 seconds |
| Started | Jul 22 07:47:40 PM PDT 24 |
| Finished | Jul 22 07:48:09 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-df047a5c-ff66-4c7d-9829-e9e8b43e3368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110610585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2110610585 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.860116391 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 1385028156 ps |
| CPU time | 55.1 seconds |
| Started | Jul 22 07:47:42 PM PDT 24 |
| Finished | Jul 22 07:48:38 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-e0b8aa8e-cd4d-4f0f-b811-43b60e0691e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860116391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .860116391 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.2225389865 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 2199307219 ps |
| CPU time | 82.06 seconds |
| Started | Jul 22 07:47:41 PM PDT 24 |
| Finished | Jul 22 07:49:04 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-559d6028-4aa0-4a34-95ad-957e67fb8f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225389865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2225389865 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.575653938 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 1966479919 ps |
| CPU time | 69.52 seconds |
| Started | Jul 22 07:47:43 PM PDT 24 |
| Finished | Jul 22 07:48:54 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-66ed23a7-1bf1-4bb3-be40-018740715095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575653938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.575653938 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.4102440208 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 45720054564 ps |
| CPU time | 530.24 seconds |
| Started | Jul 22 07:47:31 PM PDT 24 |
| Finished | Jul 22 07:56:26 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-6c72cc63-eed2-4627-8572-35fc0981b445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102440208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.4102440208 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3921431124 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 53514092133 ps |
| CPU time | 817.37 seconds |
| Started | Jul 22 07:47:42 PM PDT 24 |
| Finished | Jul 22 08:01:20 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-07a89f38-4696-46ee-9b9e-41584131b78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921431124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3921431124 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.359759899 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 112035616 ps |
| CPU time | 11.5 seconds |
| Started | Jul 22 07:47:33 PM PDT 24 |
| Finished | Jul 22 07:47:49 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-44ac4772-9b4f-4d66-80b2-50f37a511cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359759899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_dela ys.359759899 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.264787066 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 1150801913 ps |
| CPU time | 35.55 seconds |
| Started | Jul 22 07:47:41 PM PDT 24 |
| Finished | Jul 22 07:48:17 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-78b5cf41-b262-4bb2-89e0-1e9e8108c7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264787066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.264787066 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2404867860 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 220737437 ps |
| CPU time | 8.91 seconds |
| Started | Jul 22 07:47:29 PM PDT 24 |
| Finished | Jul 22 07:47:40 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-830883ae-7d60-484e-8f12-68398fcb1d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404867860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2404867860 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3572679691 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 6015084955 ps |
| CPU time | 61.17 seconds |
| Started | Jul 22 07:47:34 PM PDT 24 |
| Finished | Jul 22 07:48:39 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-08d93c01-f8a8-46c6-b899-43de2f513c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572679691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3572679691 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3350272880 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 4437214748 ps |
| CPU time | 73.2 seconds |
| Started | Jul 22 07:47:43 PM PDT 24 |
| Finished | Jul 22 07:48:57 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-bb0be37f-86ae-4690-b672-8601087b157e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350272880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3350272880 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3093376867 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 49672847 ps |
| CPU time | 6.7 seconds |
| Started | Jul 22 07:47:33 PM PDT 24 |
| Finished | Jul 22 07:47:43 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-7f1caab1-86ec-4030-83aa-60a8f9601c79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093376867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3093376867 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.4195638284 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 2882370094 ps |
| CPU time | 263.12 seconds |
| Started | Jul 22 07:47:51 PM PDT 24 |
| Finished | Jul 22 07:52:16 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-2b97246e-615e-4612-ad2a-c58c9835125f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195638284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.4195638284 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.2418532023 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 8427468836 ps |
| CPU time | 276.93 seconds |
| Started | Jul 22 07:47:54 PM PDT 24 |
| Finished | Jul 22 07:52:33 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-fa89b8a8-6e50-4f8e-95d9-b05994d44383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418532023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2418532023 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3820932530 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 218833387 ps |
| CPU time | 52.84 seconds |
| Started | Jul 22 07:48:13 PM PDT 24 |
| Finished | Jul 22 07:49:08 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-43079175-7605-4735-a3d7-3ae0258c6333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820932530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.3820932530 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3548007450 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 838113401 ps |
| CPU time | 50.77 seconds |
| Started | Jul 22 07:48:13 PM PDT 24 |
| Finished | Jul 22 07:49:06 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-04683bd7-728a-4a84-8837-35553fa57bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548007450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3548007450 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.407615164 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 295594758 ps |
| CPU time | 14.88 seconds |
| Started | Jul 22 07:47:40 PM PDT 24 |
| Finished | Jul 22 07:47:56 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-1d615ebb-6bc3-4ce0-ab37-ed01c3043741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407615164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.407615164 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1378741918 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 29386522600 ps |
| CPU time | 4438.53 seconds |
| Started | Jul 22 07:41:34 PM PDT 24 |
| Finished | Jul 22 08:55:35 PM PDT 24 |
| Peak memory | 594524 kb |
| Host | smart-3905470d-02f1-44a2-91a2-bc0b37b663b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378741918 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.1378741918 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.3212063839 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 11481929700 ps |
| CPU time | 1040.19 seconds |
| Started | Jul 22 07:41:35 PM PDT 24 |
| Finished | Jul 22 07:58:57 PM PDT 24 |
| Peak memory | 592208 kb |
| Host | smart-38ed2e7a-04fd-4ce4-aa49-501a8e7a05ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212063839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.3212063839 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3517969042 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4304270847 ps |
| CPU time | 245.18 seconds |
| Started | Jul 22 07:41:49 PM PDT 24 |
| Finished | Jul 22 07:45:55 PM PDT 24 |
| Peak memory | 662832 kb |
| Host | smart-631ddbd2-b9d1-4ecd-9db8-02d9f6c8f18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517969042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3517969042 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.925153278 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 5912778655 ps |
| CPU time | 346.75 seconds |
| Started | Jul 22 07:42:01 PM PDT 24 |
| Finished | Jul 22 07:47:50 PM PDT 24 |
| Peak memory | 645684 kb |
| Host | smart-79216377-d95d-4408-aca4-319e16fbf3bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925153278 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.925153278 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3423257488 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 4673418560 ps |
| CPU time | 336.67 seconds |
| Started | Jul 22 07:43:51 PM PDT 24 |
| Finished | Jul 22 07:49:29 PM PDT 24 |
| Peak memory | 598180 kb |
| Host | smart-5c667ced-5853-4233-bc1a-db91325aebdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423257488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3423257488 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.352321914 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 8310883600 ps |
| CPU time | 373.23 seconds |
| Started | Jul 22 07:41:35 PM PDT 24 |
| Finished | Jul 22 07:47:50 PM PDT 24 |
| Peak memory | 591004 kb |
| Host | smart-bbcb6ba2-4786-438a-8f57-ff77ee09d2d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352321914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .chip_prim_tl_access.352321914 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2222272166 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 17957184398 ps |
| CPU time | 580.33 seconds |
| Started | Jul 22 07:42:41 PM PDT 24 |
| Finished | Jul 22 07:52:22 PM PDT 24 |
| Peak memory | 591892 kb |
| Host | smart-4b83e242-4675-4944-86e0-767c4b4c403b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222272166 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.2222272166 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.803270495 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 28144994164 ps |
| CPU time | 4135.21 seconds |
| Started | Jul 22 07:41:33 PM PDT 24 |
| Finished | Jul 22 08:50:30 PM PDT 24 |
| Peak memory | 594248 kb |
| Host | smart-7f796323-24e8-411a-9c33-e8775a0be7d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803270495 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.803270495 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2087530455 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 1003363850 ps |
| CPU time | 88.57 seconds |
| Started | Jul 22 07:41:40 PM PDT 24 |
| Finished | Jul 22 07:43:09 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-7ed7f217-370a-4c8c-940b-f6d0252afb4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087530455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2087530455 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1821180596 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 106870753235 ps |
| CPU time | 1863.11 seconds |
| Started | Jul 22 07:42:16 PM PDT 24 |
| Finished | Jul 22 08:13:22 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-cadcaf2e-25a3-47b5-972a-9791664f9f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821180596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.1821180596 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1088708557 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 906466292 ps |
| CPU time | 34.97 seconds |
| Started | Jul 22 07:41:42 PM PDT 24 |
| Finished | Jul 22 07:42:17 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-4f331108-2c2b-4c71-b12e-818faba17b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088708557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1088708557 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2907765025 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 2462354618 ps |
| CPU time | 73.39 seconds |
| Started | Jul 22 07:41:58 PM PDT 24 |
| Finished | Jul 22 07:43:14 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-5ce3f7d4-cf84-4192-b2d8-f1abb20dfc39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907765025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2907765025 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.402999515 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 2233612953 ps |
| CPU time | 82.07 seconds |
| Started | Jul 22 07:41:34 PM PDT 24 |
| Finished | Jul 22 07:42:58 PM PDT 24 |
| Peak memory | 576840 kb |
| Host | smart-fda27bb7-2820-46fb-9821-c09e4bab0251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402999515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.402999515 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.3069550814 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 51855800396 ps |
| CPU time | 592 seconds |
| Started | Jul 22 07:42:01 PM PDT 24 |
| Finished | Jul 22 07:51:56 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-48c48c27-bb1c-4a75-8c37-3fb2fdf07901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069550814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3069550814 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.488701062 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 60639873664 ps |
| CPU time | 1044.02 seconds |
| Started | Jul 22 07:43:51 PM PDT 24 |
| Finished | Jul 22 08:01:17 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-af3963be-58a3-4fd5-9912-83e35f91a47f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488701062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.488701062 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2130916802 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 630813931 ps |
| CPU time | 54.98 seconds |
| Started | Jul 22 07:41:41 PM PDT 24 |
| Finished | Jul 22 07:42:37 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-b5049139-290c-40e5-8938-4eaf9619fb10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130916802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.2130916802 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.2630870290 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 2352194819 ps |
| CPU time | 69.95 seconds |
| Started | Jul 22 07:41:40 PM PDT 24 |
| Finished | Jul 22 07:42:51 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-a973b758-9986-4473-80a0-70716658de22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630870290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2630870290 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.186270867 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 51369112 ps |
| CPU time | 6.25 seconds |
| Started | Jul 22 07:41:34 PM PDT 24 |
| Finished | Jul 22 07:41:42 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-22ee0c61-f4a6-4a3a-98cb-b1920b27ab6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186270867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.186270867 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.105782130 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 6279534995 ps |
| CPU time | 61.17 seconds |
| Started | Jul 22 07:44:41 PM PDT 24 |
| Finished | Jul 22 07:45:43 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-f780a57f-b343-495a-a7c2-458ef8fb715d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105782130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.105782130 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.774324037 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 5970951723 ps |
| CPU time | 99.86 seconds |
| Started | Jul 22 07:41:34 PM PDT 24 |
| Finished | Jul 22 07:43:16 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-162c711b-3dfb-4a23-bb39-e739dafc29c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774324037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.774324037 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3064220079 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 48312591 ps |
| CPU time | 6.13 seconds |
| Started | Jul 22 07:41:37 PM PDT 24 |
| Finished | Jul 22 07:41:43 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c97a7f9f-6096-406b-bb49-35f08016dd3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064220079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3064220079 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2167086100 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 6548599 ps |
| CPU time | 3.81 seconds |
| Started | Jul 22 07:41:42 PM PDT 24 |
| Finished | Jul 22 07:41:47 PM PDT 24 |
| Peak memory | 566356 kb |
| Host | smart-f027a127-b469-4bf0-9f06-3dd585553f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167086100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2167086100 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.4226278473 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 1886469301 ps |
| CPU time | 149.14 seconds |
| Started | Jul 22 07:41:42 PM PDT 24 |
| Finished | Jul 22 07:44:12 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-53307457-e645-4b47-869e-d8bdbe58e6cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226278473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4226278473 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1819794694 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 6684988984 ps |
| CPU time | 379.45 seconds |
| Started | Jul 22 07:41:43 PM PDT 24 |
| Finished | Jul 22 07:48:03 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-2b83e731-a8c0-4cd3-ab90-46d038c0ef0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819794694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.1819794694 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1332302596 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 3674193277 ps |
| CPU time | 382.56 seconds |
| Started | Jul 22 07:41:49 PM PDT 24 |
| Finished | Jul 22 07:48:12 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-12b3cabd-28f1-4443-99a7-5771fd8426eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332302596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.1332302596 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1642997165 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 278261296 ps |
| CPU time | 35.42 seconds |
| Started | Jul 22 07:41:41 PM PDT 24 |
| Finished | Jul 22 07:42:17 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-5edb9685-8efc-4e45-980c-e65d3aa02aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642997165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1642997165 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3435833535 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3142992540 ps |
| CPU time | 163.07 seconds |
| Started | Jul 22 07:47:55 PM PDT 24 |
| Finished | Jul 22 07:50:40 PM PDT 24 |
| Peak memory | 604492 kb |
| Host | smart-f923152d-f158-4862-88a5-8b4637de5b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435833535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3435833535 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.782781604 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 499112269 ps |
| CPU time | 23.88 seconds |
| Started | Jul 22 07:48:11 PM PDT 24 |
| Finished | Jul 22 07:48:36 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-914d0ecc-73e5-4433-bcf5-9a26f02d7bac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782781604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device. 782781604 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3997244528 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 4455713993 ps |
| CPU time | 79.56 seconds |
| Started | Jul 22 07:48:11 PM PDT 24 |
| Finished | Jul 22 07:49:32 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-e6fb1ec6-5a3e-4c50-ad88-4ab93a886953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997244528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.3997244528 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.890996850 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 180870524 ps |
| CPU time | 20.73 seconds |
| Started | Jul 22 07:48:10 PM PDT 24 |
| Finished | Jul 22 07:48:31 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-3f65d897-a6dc-4312-aaf6-5a8a6993800a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890996850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr .890996850 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2644386322 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 2088633649 ps |
| CPU time | 77.65 seconds |
| Started | Jul 22 07:48:11 PM PDT 24 |
| Finished | Jul 22 07:49:29 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4501cc00-6f6e-4305-b32d-c9d2a0354e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644386322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2644386322 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.4166573047 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 277033942 ps |
| CPU time | 12.71 seconds |
| Started | Jul 22 07:48:00 PM PDT 24 |
| Finished | Jul 22 07:48:13 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-d7605b78-a473-479f-8615-e5b0d63f2ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166573047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.4166573047 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3594340999 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 4611752859 ps |
| CPU time | 49.4 seconds |
| Started | Jul 22 07:48:25 PM PDT 24 |
| Finished | Jul 22 07:49:17 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-f0c4769c-e3e0-46d2-a32a-3a63a4b9b0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594340999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3594340999 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.2075052313 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 48824418988 ps |
| CPU time | 813.16 seconds |
| Started | Jul 22 07:48:00 PM PDT 24 |
| Finished | Jul 22 08:01:35 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-ce96ecb4-9bed-4d04-91ff-7b980ac2efc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075052313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2075052313 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1661149795 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 397065972 ps |
| CPU time | 38.13 seconds |
| Started | Jul 22 07:48:02 PM PDT 24 |
| Finished | Jul 22 07:48:41 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-06524c3d-4080-4eed-af2e-3fb8c86a1ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661149795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1661149795 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.724151095 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2048754797 ps |
| CPU time | 63.45 seconds |
| Started | Jul 22 07:48:11 PM PDT 24 |
| Finished | Jul 22 07:49:16 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-69ec7e2d-cf1d-4100-b10e-e905d5691e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724151095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.724151095 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.4230700965 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 206846497 ps |
| CPU time | 8.94 seconds |
| Started | Jul 22 07:47:52 PM PDT 24 |
| Finished | Jul 22 07:48:02 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-16cd47b6-74fc-4f69-8f5c-08891301bcd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230700965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.4230700965 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.3733397238 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 9324779337 ps |
| CPU time | 95.48 seconds |
| Started | Jul 22 07:48:01 PM PDT 24 |
| Finished | Jul 22 07:49:38 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-4df4d950-5e0f-4b52-9305-a423172a1620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733397238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3733397238 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.434510587 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 4869607441 ps |
| CPU time | 82.91 seconds |
| Started | Jul 22 07:48:22 PM PDT 24 |
| Finished | Jul 22 07:49:47 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-179945a7-b7d9-4d51-b709-f2088956232d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434510587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.434510587 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.854723655 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 44153661 ps |
| CPU time | 6.07 seconds |
| Started | Jul 22 07:47:57 PM PDT 24 |
| Finished | Jul 22 07:48:05 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-838c0ca3-eff9-4a17-a49a-1bfc373efb8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854723655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays .854723655 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.243141683 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 671005085 ps |
| CPU time | 66.32 seconds |
| Started | Jul 22 07:48:11 PM PDT 24 |
| Finished | Jul 22 07:49:19 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-2d1f85f0-6c8d-4071-b8de-77cd1f538b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243141683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.243141683 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.586916715 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 1810840288 ps |
| CPU time | 148.06 seconds |
| Started | Jul 22 07:48:26 PM PDT 24 |
| Finished | Jul 22 07:50:57 PM PDT 24 |
| Peak memory | 576948 kb |
| Host | smart-f461c675-0b6e-4d4e-8475-f22556e0e001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586916715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.586916715 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2993597432 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 18614324329 ps |
| CPU time | 799.06 seconds |
| Started | Jul 22 07:48:10 PM PDT 24 |
| Finished | Jul 22 08:01:30 PM PDT 24 |
| Peak memory | 577072 kb |
| Host | smart-e16083da-37aa-4737-93ee-c27c9209e957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993597432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.2993597432 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.3876272946 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 117040740 ps |
| CPU time | 14.18 seconds |
| Started | Jul 22 07:48:12 PM PDT 24 |
| Finished | Jul 22 07:48:27 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-9ae67aa8-bd7a-49d1-b567-84f3ba179d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876272946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3876272946 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1276568259 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3674632121 ps |
| CPU time | 207.13 seconds |
| Started | Jul 22 07:48:31 PM PDT 24 |
| Finished | Jul 22 07:52:02 PM PDT 24 |
| Peak memory | 600368 kb |
| Host | smart-e1aa6998-25fb-4ab3-8240-8a249139bb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276568259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1276568259 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2671971943 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 484271389 ps |
| CPU time | 37.65 seconds |
| Started | Jul 22 07:48:25 PM PDT 24 |
| Finished | Jul 22 07:49:07 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-f93b8233-8b2b-4ce4-8590-3c754ce8c54d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671971943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2671971943 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1795261858 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 148411518805 ps |
| CPU time | 2457.13 seconds |
| Started | Jul 22 07:48:29 PM PDT 24 |
| Finished | Jul 22 08:29:30 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-0e6fa049-6df9-4402-9582-4c865d0e0d8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795261858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1795261858 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2945844572 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 376332859 ps |
| CPU time | 16.37 seconds |
| Started | Jul 22 07:50:40 PM PDT 24 |
| Finished | Jul 22 07:50:59 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-c2721e1f-6cf6-45bb-9c60-c23bfbdcb209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945844572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2945844572 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.1998658390 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 1058202029 ps |
| CPU time | 35.99 seconds |
| Started | Jul 22 07:48:39 PM PDT 24 |
| Finished | Jul 22 07:49:15 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-caeb5d4f-91f1-4b62-925a-1b6db4e8cb2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998658390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1998658390 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3869094288 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 1620857872 ps |
| CPU time | 64.26 seconds |
| Started | Jul 22 07:48:26 PM PDT 24 |
| Finished | Jul 22 07:49:34 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-4615c556-4c57-4c48-a989-fd9cceed5c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869094288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3869094288 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2291014616 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 43566252673 ps |
| CPU time | 425.56 seconds |
| Started | Jul 22 07:48:27 PM PDT 24 |
| Finished | Jul 22 07:55:36 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-64cb5f1c-15c8-4dcd-8aca-27177a2df714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291014616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2291014616 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.4053142476 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 23992729659 ps |
| CPU time | 408.42 seconds |
| Started | Jul 22 07:48:28 PM PDT 24 |
| Finished | Jul 22 07:55:19 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-433d3ade-2d71-479c-9e06-c378190b5de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053142476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4053142476 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.2962975613 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 199218457 ps |
| CPU time | 18.74 seconds |
| Started | Jul 22 07:48:29 PM PDT 24 |
| Finished | Jul 22 07:48:51 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-a4422c2d-28bc-4615-9890-c2f6df7fc2df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962975613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.2962975613 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.2909611287 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 2774330884 ps |
| CPU time | 83.77 seconds |
| Started | Jul 22 07:48:26 PM PDT 24 |
| Finished | Jul 22 07:49:54 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-ea9ef4bd-fe7c-4049-9ac7-6d779efcd8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909611287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2909611287 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.1179605121 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 46663385 ps |
| CPU time | 6.77 seconds |
| Started | Jul 22 07:48:27 PM PDT 24 |
| Finished | Jul 22 07:48:37 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-156788bb-38c0-40c1-89b1-244537d1a427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179605121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1179605121 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2119937236 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 9965213435 ps |
| CPU time | 104.46 seconds |
| Started | Jul 22 07:48:25 PM PDT 24 |
| Finished | Jul 22 07:50:13 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-8413d72c-0ca6-4a48-b8c1-3dff11c26046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119937236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2119937236 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.864359717 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 3760798336 ps |
| CPU time | 62.2 seconds |
| Started | Jul 22 07:48:26 PM PDT 24 |
| Finished | Jul 22 07:49:32 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-1ed549b4-d8b3-4a69-9f37-9d929f2198bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864359717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.864359717 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2263775024 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 49493268 ps |
| CPU time | 5.82 seconds |
| Started | Jul 22 07:48:27 PM PDT 24 |
| Finished | Jul 22 07:48:36 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-a40d6ee5-581b-4d15-ad27-e8852fe2050b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263775024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2263775024 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.1935528502 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 1933909573 ps |
| CPU time | 73.42 seconds |
| Started | Jul 22 07:48:36 PM PDT 24 |
| Finished | Jul 22 07:49:51 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-0c281206-e0db-4314-b13e-9fee7c986321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935528502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1935528502 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2261541255 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 196739699 ps |
| CPU time | 19.69 seconds |
| Started | Jul 22 07:50:39 PM PDT 24 |
| Finished | Jul 22 07:51:01 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-b3bf141d-2fa6-4301-89a4-c59afa2d88cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261541255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2261541255 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.80067899 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 3093265864 ps |
| CPU time | 302.23 seconds |
| Started | Jul 22 07:48:36 PM PDT 24 |
| Finished | Jul 22 07:53:40 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-c567246e-7a68-4ad7-b935-296c238ae3ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80067899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_w ith_rand_reset.80067899 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1588188165 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 3988028866 ps |
| CPU time | 286.28 seconds |
| Started | Jul 22 07:48:37 PM PDT 24 |
| Finished | Jul 22 07:53:24 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-cd6f0406-2220-486d-a7d8-b27f83c98a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588188165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.1588188165 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.4153369028 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 851992154 ps |
| CPU time | 33.86 seconds |
| Started | Jul 22 07:48:37 PM PDT 24 |
| Finished | Jul 22 07:49:11 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-8a45fc0f-77f4-4098-bf7a-b7406ca0bb13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153369028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.4153369028 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.2935134709 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4314396070 ps |
| CPU time | 282.88 seconds |
| Started | Jul 22 07:48:38 PM PDT 24 |
| Finished | Jul 22 07:53:21 PM PDT 24 |
| Peak memory | 604588 kb |
| Host | smart-11cbd268-9c07-44b2-8178-e3f7301c9d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935134709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2935134709 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.695420978 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 2835001599 ps |
| CPU time | 97.8 seconds |
| Started | Jul 22 07:50:45 PM PDT 24 |
| Finished | Jul 22 07:52:26 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-e2c1fc17-fadc-4614-8636-e761d4f0a7cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695420978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 695420978 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1034315264 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 77280512019 ps |
| CPU time | 1246.41 seconds |
| Started | Jul 22 07:49:45 PM PDT 24 |
| Finished | Jul 22 08:10:33 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-ff90a82f-76f5-4cdf-a8d1-2064192e887c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034315264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1034315264 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.968291999 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 190575523 ps |
| CPU time | 20.22 seconds |
| Started | Jul 22 07:49:45 PM PDT 24 |
| Finished | Jul 22 07:50:06 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-101e9df7-db77-41a3-b029-26f312f7f4bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968291999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .968291999 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2583391718 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 1591445565 ps |
| CPU time | 46.47 seconds |
| Started | Jul 22 07:50:46 PM PDT 24 |
| Finished | Jul 22 07:51:35 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-99f0eb84-947a-42a8-8558-80cdce6aafb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583391718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2583391718 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.2935929369 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 360373463 ps |
| CPU time | 38.28 seconds |
| Started | Jul 22 07:48:44 PM PDT 24 |
| Finished | Jul 22 07:49:23 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-4c355e21-3424-495e-a3a2-c6046ceccf8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935929369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2935929369 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2195643711 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 85724813647 ps |
| CPU time | 931.52 seconds |
| Started | Jul 22 07:50:41 PM PDT 24 |
| Finished | Jul 22 08:06:16 PM PDT 24 |
| Peak memory | 576920 kb |
| Host | smart-25f67ab1-d41a-46ef-a3da-4ff2ac05dd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195643711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2195643711 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2295735740 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 60756377167 ps |
| CPU time | 1076.14 seconds |
| Started | Jul 22 07:48:45 PM PDT 24 |
| Finished | Jul 22 08:06:42 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-66fae5fb-bcd4-4289-9d1e-832f83a8d4c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295735740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2295735740 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.296052935 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 288013839 ps |
| CPU time | 24.39 seconds |
| Started | Jul 22 07:48:43 PM PDT 24 |
| Finished | Jul 22 07:49:08 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-c6e02e17-6750-4a8e-9841-59b19b388827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296052935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela ys.296052935 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.2414004242 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 55367370 ps |
| CPU time | 7.07 seconds |
| Started | Jul 22 07:48:46 PM PDT 24 |
| Finished | Jul 22 07:48:54 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-8f5ec910-8675-4c77-82a1-3c13dddee6b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414004242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2414004242 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.691662993 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 237858137 ps |
| CPU time | 10.29 seconds |
| Started | Jul 22 07:48:47 PM PDT 24 |
| Finished | Jul 22 07:48:59 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-4bdcb4cd-905c-4902-bf44-0d777f28df15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691662993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.691662993 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2422555023 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 8208434741 ps |
| CPU time | 89.48 seconds |
| Started | Jul 22 07:48:44 PM PDT 24 |
| Finished | Jul 22 07:50:14 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-bd4fd221-8af1-42b7-b5d0-00a22e88b560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422555023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2422555023 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3303829983 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 5829889524 ps |
| CPU time | 97.75 seconds |
| Started | Jul 22 07:48:44 PM PDT 24 |
| Finished | Jul 22 07:50:22 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-83620c2c-4a66-4c65-8329-a0b4fe933d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303829983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3303829983 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.640051263 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 52025461 ps |
| CPU time | 6.8 seconds |
| Started | Jul 22 07:48:41 PM PDT 24 |
| Finished | Jul 22 07:48:49 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-24a88ce4-803e-4749-9f6d-32f6d5247729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640051263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays .640051263 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.3508913265 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 2135569947 ps |
| CPU time | 176.99 seconds |
| Started | Jul 22 07:48:49 PM PDT 24 |
| Finished | Jul 22 07:51:47 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-b160009e-80e6-41ef-bbf8-f2aea8e0df93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508913265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3508913265 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3815504417 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 1674891048 ps |
| CPU time | 101.17 seconds |
| Started | Jul 22 07:50:45 PM PDT 24 |
| Finished | Jul 22 07:52:30 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-6e9fb270-36cc-4be1-91ce-a1c15a6a85e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815504417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3815504417 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2271176282 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 4890439404 ps |
| CPU time | 369.68 seconds |
| Started | Jul 22 07:49:39 PM PDT 24 |
| Finished | Jul 22 07:55:50 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-a9b38b7d-0493-4ff0-8422-fc927996bf08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271176282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2271176282 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2387299243 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 115522866 ps |
| CPU time | 54.71 seconds |
| Started | Jul 22 07:48:49 PM PDT 24 |
| Finished | Jul 22 07:49:45 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-09020b0d-83c5-414e-a133-38450097dc23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387299243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2387299243 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.1538188896 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 547514720 ps |
| CPU time | 22.95 seconds |
| Started | Jul 22 07:50:45 PM PDT 24 |
| Finished | Jul 22 07:51:11 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-f27f846b-8fe3-4c5f-a775-bce8b7c45b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538188896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1538188896 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.4271185847 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 2626424630 ps |
| CPU time | 122.61 seconds |
| Started | Jul 22 07:49:03 PM PDT 24 |
| Finished | Jul 22 07:51:06 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-d3cdb522-ef3e-4590-991d-85d6e3ca0bc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271185847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .4271185847 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.751095772 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 93678308799 ps |
| CPU time | 1604.49 seconds |
| Started | Jul 22 07:48:56 PM PDT 24 |
| Finished | Jul 22 08:15:42 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-0e74d1f0-f208-44a1-8e5e-da0ff4b92924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751095772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.751095772 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1125463928 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 229477230 ps |
| CPU time | 25.16 seconds |
| Started | Jul 22 07:50:02 PM PDT 24 |
| Finished | Jul 22 07:50:29 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-dbeab15c-c686-4e6d-810b-1c716f1d8040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125463928 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1125463928 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1157863280 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 1729352666 ps |
| CPU time | 66.39 seconds |
| Started | Jul 22 07:48:56 PM PDT 24 |
| Finished | Jul 22 07:50:04 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-504b36f4-52c5-4ca5-84d4-fa389e36b2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157863280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1157863280 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2100749811 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 535715484 ps |
| CPU time | 22.65 seconds |
| Started | Jul 22 07:48:57 PM PDT 24 |
| Finished | Jul 22 07:49:21 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-47290360-016c-429c-afa8-b5081caba4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100749811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2100749811 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.757963973 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 69081907500 ps |
| CPU time | 677.56 seconds |
| Started | Jul 22 07:48:57 PM PDT 24 |
| Finished | Jul 22 08:00:16 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-bf57d4fa-b2e1-4eb9-bc76-83386e032393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757963973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.757963973 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3978213634 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 52807862241 ps |
| CPU time | 875.8 seconds |
| Started | Jul 22 07:48:59 PM PDT 24 |
| Finished | Jul 22 08:03:36 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-7539c61c-4459-414c-b8aa-05e9c4ab4d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978213634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3978213634 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2255127622 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 428454296 ps |
| CPU time | 35.88 seconds |
| Started | Jul 22 07:48:57 PM PDT 24 |
| Finished | Jul 22 07:49:34 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-e4884041-439f-46fb-9abe-fdec7a8e7f7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255127622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.2255127622 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.1258198906 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 1203582504 ps |
| CPU time | 39.24 seconds |
| Started | Jul 22 07:49:01 PM PDT 24 |
| Finished | Jul 22 07:49:41 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-092bdaa1-f00e-419a-a95c-99cf4c469ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258198906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1258198906 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.834482881 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 152950666 ps |
| CPU time | 8.24 seconds |
| Started | Jul 22 07:49:03 PM PDT 24 |
| Finished | Jul 22 07:49:11 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-5c6d54b2-0853-4f38-a447-d144951890c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834482881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.834482881 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1771552818 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 6760076692 ps |
| CPU time | 67.64 seconds |
| Started | Jul 22 07:48:58 PM PDT 24 |
| Finished | Jul 22 07:50:06 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-868d126f-13b6-431d-b4fc-dacdd8f3e19d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771552818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1771552818 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.1985455193 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 4420263264 ps |
| CPU time | 75.75 seconds |
| Started | Jul 22 07:48:56 PM PDT 24 |
| Finished | Jul 22 07:50:13 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-5db725c5-828a-4bd1-9f87-8fbda48d14f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985455193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1985455193 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3858675610 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 33809513 ps |
| CPU time | 6.01 seconds |
| Started | Jul 22 07:48:57 PM PDT 24 |
| Finished | Jul 22 07:49:04 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-209ee686-b1c1-4eee-89f5-3ad4c5b083d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858675610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.3858675610 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.4113139298 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 8014395839 ps |
| CPU time | 343.83 seconds |
| Started | Jul 22 07:49:07 PM PDT 24 |
| Finished | Jul 22 07:54:52 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-acc9e8ab-5721-47dd-a2ff-0379a60e8803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113139298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4113139298 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3664769853 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 1765711092 ps |
| CPU time | 140.14 seconds |
| Started | Jul 22 07:49:08 PM PDT 24 |
| Finished | Jul 22 07:51:30 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-ff8dc841-0d7a-4def-92a4-0a9a725abec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664769853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3664769853 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.353853872 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 185001013 ps |
| CPU time | 44.76 seconds |
| Started | Jul 22 07:50:02 PM PDT 24 |
| Finished | Jul 22 07:50:49 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-3dc459c1-2188-4c2a-89b8-5b96e1982687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353853872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.353853872 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1136393307 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 472151983 ps |
| CPU time | 145.85 seconds |
| Started | Jul 22 07:49:07 PM PDT 24 |
| Finished | Jul 22 07:51:34 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-d4d519a3-3bc9-4266-afc1-37e003fe363f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136393307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1136393307 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1273721097 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 190629316 ps |
| CPU time | 19.59 seconds |
| Started | Jul 22 07:48:58 PM PDT 24 |
| Finished | Jul 22 07:49:18 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-8b56cee7-2704-401f-a1c8-58dd8b394bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273721097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1273721097 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.322328253 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 4003055795 ps |
| CPU time | 265.3 seconds |
| Started | Jul 22 07:49:07 PM PDT 24 |
| Finished | Jul 22 07:53:34 PM PDT 24 |
| Peak memory | 599408 kb |
| Host | smart-a6ec0732-a307-4b8c-b2d3-cf7da35238d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322328253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.322328253 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.1884375205 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 660882416 ps |
| CPU time | 27.36 seconds |
| Started | Jul 22 07:49:18 PM PDT 24 |
| Finished | Jul 22 07:49:46 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-c78f6c4b-defa-4551-82ff-7a36e0aadce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884375205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .1884375205 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3199648700 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 98470018211 ps |
| CPU time | 1616.43 seconds |
| Started | Jul 22 07:49:18 PM PDT 24 |
| Finished | Jul 22 08:16:16 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-4a41ffee-49ac-406e-bb39-7cd5ee787d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199648700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.3199648700 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1694060286 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 901387475 ps |
| CPU time | 31.18 seconds |
| Started | Jul 22 07:49:18 PM PDT 24 |
| Finished | Jul 22 07:49:50 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-36519b33-eca8-4831-96ab-0b9db78d091a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694060286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1694060286 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.585231099 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 1490682350 ps |
| CPU time | 57.32 seconds |
| Started | Jul 22 07:49:16 PM PDT 24 |
| Finished | Jul 22 07:50:14 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-0add6068-b0aa-40a4-960b-cb96eeac7044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585231099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.585231099 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.1859353355 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 30586866 ps |
| CPU time | 5.99 seconds |
| Started | Jul 22 07:49:08 PM PDT 24 |
| Finished | Jul 22 07:49:15 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d056c871-ebf3-43a8-b67a-9eb2401556ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859353355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.1859353355 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2776433814 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 44785756274 ps |
| CPU time | 427.53 seconds |
| Started | Jul 22 07:50:02 PM PDT 24 |
| Finished | Jul 22 07:57:11 PM PDT 24 |
| Peak memory | 576876 kb |
| Host | smart-34910286-3d1d-4335-baea-20e4ad8ae7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776433814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2776433814 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.3564668940 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 9783985160 ps |
| CPU time | 166.89 seconds |
| Started | Jul 22 07:49:17 PM PDT 24 |
| Finished | Jul 22 07:52:05 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-36f0bc65-778f-4f95-83de-806efa9d4803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564668940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3564668940 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2480759793 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 346833510 ps |
| CPU time | 33.46 seconds |
| Started | Jul 22 07:49:07 PM PDT 24 |
| Finished | Jul 22 07:49:41 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-da9dd131-a834-442c-86d5-c8bc4ad2dcaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480759793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2480759793 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.1541405132 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 185063030 ps |
| CPU time | 17.04 seconds |
| Started | Jul 22 07:49:15 PM PDT 24 |
| Finished | Jul 22 07:49:33 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-41e7b605-6d55-4d81-8f85-c7b5add006e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541405132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1541405132 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3162990020 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 162598133 ps |
| CPU time | 8.05 seconds |
| Started | Jul 22 07:50:02 PM PDT 24 |
| Finished | Jul 22 07:50:12 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-3e0bef4b-3e76-49e1-a206-15a65d1a0f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162990020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3162990020 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3162704873 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 8500443263 ps |
| CPU time | 86.28 seconds |
| Started | Jul 22 07:49:07 PM PDT 24 |
| Finished | Jul 22 07:50:35 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-8df98a16-ed93-48be-9766-7152d399c39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162704873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3162704873 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2247327289 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 3042483819 ps |
| CPU time | 52.62 seconds |
| Started | Jul 22 07:49:07 PM PDT 24 |
| Finished | Jul 22 07:50:00 PM PDT 24 |
| Peak memory | 574936 kb |
| Host | smart-65ca1302-ec91-4e2a-bc29-045cb0f9c854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247327289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2247327289 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1879309059 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 42976971 ps |
| CPU time | 6.32 seconds |
| Started | Jul 22 07:49:06 PM PDT 24 |
| Finished | Jul 22 07:49:14 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-b5fa3cbb-9586-417c-9f1f-1d5ac223ed44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879309059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.1879309059 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1162407724 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 10284317008 ps |
| CPU time | 338.71 seconds |
| Started | Jul 22 07:49:18 PM PDT 24 |
| Finished | Jul 22 07:54:58 PM PDT 24 |
| Peak memory | 577044 kb |
| Host | smart-7a61a30a-3aed-43d4-a38a-a550c1f628dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162407724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1162407724 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1812579279 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 3355855778 ps |
| CPU time | 130.36 seconds |
| Started | Jul 22 07:49:16 PM PDT 24 |
| Finished | Jul 22 07:51:27 PM PDT 24 |
| Peak memory | 577084 kb |
| Host | smart-0aa47366-2c15-4633-abb5-e95b4dec9b49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812579279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1812579279 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.47434839 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 3309813593 ps |
| CPU time | 125.61 seconds |
| Started | Jul 22 07:49:20 PM PDT 24 |
| Finished | Jul 22 07:51:26 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-27e10e9d-ebaf-4484-b185-a7a1226755a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47434839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_reset_error.47434839 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3882630503 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 195886664 ps |
| CPU time | 25.51 seconds |
| Started | Jul 22 07:49:19 PM PDT 24 |
| Finished | Jul 22 07:49:46 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-5dded1d5-ef7e-417b-b7d4-f7b855a828b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882630503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3882630503 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.1634568697 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 394778358 ps |
| CPU time | 37.91 seconds |
| Started | Jul 22 07:49:36 PM PDT 24 |
| Finished | Jul 22 07:50:15 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-7b178f3f-1d18-41ca-a48c-6ee69aa80837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634568697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .1634568697 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2285751638 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 52076773707 ps |
| CPU time | 928.2 seconds |
| Started | Jul 22 07:49:36 PM PDT 24 |
| Finished | Jul 22 08:05:06 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-e8875a4c-aa1e-4aab-bcee-d7853f7cb88a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285751638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.2285751638 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2434666969 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 469958523 ps |
| CPU time | 20.56 seconds |
| Started | Jul 22 07:49:36 PM PDT 24 |
| Finished | Jul 22 07:49:57 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-3663fb0f-b672-4737-a493-1e164f0123cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434666969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2434666969 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.3234253800 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 641431000 ps |
| CPU time | 25.38 seconds |
| Started | Jul 22 07:49:28 PM PDT 24 |
| Finished | Jul 22 07:49:54 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-ad0c96c3-ae79-4483-945a-e200de7bdf99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234253800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3234253800 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.390021270 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 2414098114 ps |
| CPU time | 82.38 seconds |
| Started | Jul 22 07:50:11 PM PDT 24 |
| Finished | Jul 22 07:51:36 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-d019e8ac-e09e-45fc-93cf-e5d52cf1b153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390021270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.390021270 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1466366433 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 63823003527 ps |
| CPU time | 663.07 seconds |
| Started | Jul 22 07:49:29 PM PDT 24 |
| Finished | Jul 22 08:00:33 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-cd5a901d-1316-44e4-94d0-445afa2d8782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466366433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1466366433 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.2017646067 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 45273337302 ps |
| CPU time | 779.58 seconds |
| Started | Jul 22 07:49:36 PM PDT 24 |
| Finished | Jul 22 08:02:37 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-f7d33bec-b72f-4961-a003-efb8baed5f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017646067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2017646067 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1779144229 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 391852435 ps |
| CPU time | 35.37 seconds |
| Started | Jul 22 07:50:11 PM PDT 24 |
| Finished | Jul 22 07:50:47 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-58edd9c5-0f6d-4842-8a4e-7153f750e1f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779144229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.1779144229 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.696344255 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 525699114 ps |
| CPU time | 36.76 seconds |
| Started | Jul 22 07:49:26 PM PDT 24 |
| Finished | Jul 22 07:50:03 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-830159b4-dab4-4c4c-b1f9-f5530979439c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696344255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.696344255 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.2684026884 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 260546061 ps |
| CPU time | 9.46 seconds |
| Started | Jul 22 07:49:21 PM PDT 24 |
| Finished | Jul 22 07:49:31 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-89095757-8f01-4c2c-ac1a-bb2ca86bf370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684026884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2684026884 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.357403297 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 11028908068 ps |
| CPU time | 100.74 seconds |
| Started | Jul 22 07:49:19 PM PDT 24 |
| Finished | Jul 22 07:51:01 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-0d83b1e0-d26b-4095-9058-9e69e60cf78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357403297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.357403297 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.283799479 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 5758728307 ps |
| CPU time | 98.28 seconds |
| Started | Jul 22 07:49:17 PM PDT 24 |
| Finished | Jul 22 07:50:56 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-af7c4e34-3ec4-40c7-81ff-2c58626b07e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283799479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.283799479 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.1750700492 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 44015038 ps |
| CPU time | 6.33 seconds |
| Started | Jul 22 07:49:26 PM PDT 24 |
| Finished | Jul 22 07:49:33 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-efacad2c-1ae2-43ab-8bc1-d9878540fad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750700492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.1750700492 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1535171298 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 129646992 ps |
| CPU time | 8.64 seconds |
| Started | Jul 22 07:49:40 PM PDT 24 |
| Finished | Jul 22 07:49:50 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-f443bcc7-95af-4847-868d-1fd846a5109c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535171298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1535171298 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.1029251952 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 11121243807 ps |
| CPU time | 358.31 seconds |
| Started | Jul 22 07:49:38 PM PDT 24 |
| Finished | Jul 22 07:55:38 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-df936276-ec27-4d9e-b59f-b16805ca80aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029251952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1029251952 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2615657487 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 7842695210 ps |
| CPU time | 489.92 seconds |
| Started | Jul 22 07:49:39 PM PDT 24 |
| Finished | Jul 22 07:57:51 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-4e69ecde-3047-4e1f-85b4-09ec9d941454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615657487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2615657487 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2637620619 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 4911596280 ps |
| CPU time | 320.92 seconds |
| Started | Jul 22 07:49:38 PM PDT 24 |
| Finished | Jul 22 07:55:00 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-727ec225-1fb5-4d8a-a826-8839b54eaa85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637620619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2637620619 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.129234057 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 268222916 ps |
| CPU time | 12.29 seconds |
| Started | Jul 22 07:49:32 PM PDT 24 |
| Finished | Jul 22 07:49:46 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-0b73f28b-df82-49c7-8301-3955fe083298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129234057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.129234057 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.1692461133 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3331650618 ps |
| CPU time | 203.34 seconds |
| Started | Jul 22 07:49:38 PM PDT 24 |
| Finished | Jul 22 07:53:03 PM PDT 24 |
| Peak memory | 593540 kb |
| Host | smart-fb304e29-a40a-488a-8000-133294f9485c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692461133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1692461133 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.547962131 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 393096708 ps |
| CPU time | 20.22 seconds |
| Started | Jul 22 07:49:58 PM PDT 24 |
| Finished | Jul 22 07:50:21 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-aca64fac-47b0-4ef3-ba4b-756fb474f77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547962131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device. 547962131 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.356182056 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 21170579386 ps |
| CPU time | 377.24 seconds |
| Started | Jul 22 07:49:47 PM PDT 24 |
| Finished | Jul 22 07:56:05 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-09016ea3-783a-4e65-9c77-6030e550f4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356182056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d evice_slow_rsp.356182056 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1293613760 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 421250031 ps |
| CPU time | 19.19 seconds |
| Started | Jul 22 07:49:48 PM PDT 24 |
| Finished | Jul 22 07:50:08 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-7a5ba883-fb41-4c25-a596-75b70c10081f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293613760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1293613760 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.1548856865 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 2553502717 ps |
| CPU time | 77.14 seconds |
| Started | Jul 22 07:49:48 PM PDT 24 |
| Finished | Jul 22 07:51:06 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-32d23449-f03b-4aba-a09e-ac89566c4753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548856865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1548856865 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1500816320 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 2064594425 ps |
| CPU time | 66.32 seconds |
| Started | Jul 22 07:49:48 PM PDT 24 |
| Finished | Jul 22 07:50:55 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-1d5f1bfe-b325-4aee-abf0-24c0cd3387fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500816320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1500816320 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2084761081 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 14363045600 ps |
| CPU time | 154.58 seconds |
| Started | Jul 22 07:49:50 PM PDT 24 |
| Finished | Jul 22 07:52:25 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-56728b0b-578a-4e49-aeeb-11cc8027dec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084761081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2084761081 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3161853278 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 65215691234 ps |
| CPU time | 1052.76 seconds |
| Started | Jul 22 07:49:47 PM PDT 24 |
| Finished | Jul 22 08:07:21 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-d8c8fe9d-9cc1-4470-960a-8638aba8d40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161853278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3161853278 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.2907610813 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 406476540 ps |
| CPU time | 37.35 seconds |
| Started | Jul 22 07:49:51 PM PDT 24 |
| Finished | Jul 22 07:50:29 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-a940a5de-67be-427b-9d87-74f574c004d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907610813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.2907610813 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.2408773257 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 423803335 ps |
| CPU time | 31.15 seconds |
| Started | Jul 22 07:49:47 PM PDT 24 |
| Finished | Jul 22 07:50:19 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-cfc29695-7cde-4f5c-af86-fb1fded538f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408773257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2408773257 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.4229141670 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 227137273 ps |
| CPU time | 9.67 seconds |
| Started | Jul 22 07:49:38 PM PDT 24 |
| Finished | Jul 22 07:49:49 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-3cb21aed-8a69-436b-81ba-25aa807ff392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229141670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4229141670 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3215936972 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 9016438081 ps |
| CPU time | 90.81 seconds |
| Started | Jul 22 07:49:50 PM PDT 24 |
| Finished | Jul 22 07:51:21 PM PDT 24 |
| Peak memory | 574928 kb |
| Host | smart-a36aeb89-cf88-4054-bf76-0ad519cb8a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215936972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3215936972 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.4252989299 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 5480095400 ps |
| CPU time | 97.32 seconds |
| Started | Jul 22 07:49:50 PM PDT 24 |
| Finished | Jul 22 07:51:29 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-a4901961-d765-49b6-b43b-bec487d6f1a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252989299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4252989299 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.776953499 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 43738933 ps |
| CPU time | 6.3 seconds |
| Started | Jul 22 07:49:39 PM PDT 24 |
| Finished | Jul 22 07:49:48 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-0ea9b4b4-078d-4b19-b2ba-b79862b7d913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776953499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays .776953499 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2571591043 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 2610372390 ps |
| CPU time | 226.14 seconds |
| Started | Jul 22 07:49:48 PM PDT 24 |
| Finished | Jul 22 07:53:35 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-ec261360-3003-418a-b7ab-148bfd41c95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571591043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2571591043 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3585786546 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 1321167622 ps |
| CPU time | 105.36 seconds |
| Started | Jul 22 07:49:56 PM PDT 24 |
| Finished | Jul 22 07:51:44 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-14688576-5330-4a05-ada9-32c90ba0dba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585786546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3585786546 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2566435323 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 226505466 ps |
| CPU time | 98.35 seconds |
| Started | Jul 22 07:49:56 PM PDT 24 |
| Finished | Jul 22 07:51:35 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-c35593af-d9fa-4467-992c-0ae625b40cfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566435323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2566435323 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1471462524 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 331047246 ps |
| CPU time | 103.25 seconds |
| Started | Jul 22 07:50:04 PM PDT 24 |
| Finished | Jul 22 07:51:48 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-3b0c38be-b0a0-4680-a4ca-4d76be74afb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471462524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.1471462524 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.349835110 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 1223198238 ps |
| CPU time | 52.67 seconds |
| Started | Jul 22 07:49:59 PM PDT 24 |
| Finished | Jul 22 07:50:54 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-a3ef8887-fbbf-4331-92a8-032d710eaad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349835110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.349835110 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2818521505 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4186828034 ps |
| CPU time | 230.68 seconds |
| Started | Jul 22 07:49:55 PM PDT 24 |
| Finished | Jul 22 07:53:47 PM PDT 24 |
| Peak memory | 604420 kb |
| Host | smart-09cb2fe1-c474-4eda-bc6d-f1d8c45e8e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818521505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2818521505 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2773301478 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 505632796 ps |
| CPU time | 50.56 seconds |
| Started | Jul 22 07:50:11 PM PDT 24 |
| Finished | Jul 22 07:51:02 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-268a1157-4fdf-4d74-8d9f-b45d9fb58ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773301478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2773301478 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.4139319467 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 54920950582 ps |
| CPU time | 963.8 seconds |
| Started | Jul 22 07:50:07 PM PDT 24 |
| Finished | Jul 22 08:06:12 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-e93bd3d2-87f6-4426-acaa-1cf6fa2c8c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139319467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.4139319467 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1684646878 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 603656112 ps |
| CPU time | 24.78 seconds |
| Started | Jul 22 07:50:13 PM PDT 24 |
| Finished | Jul 22 07:50:38 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-778d3328-8056-4f5c-b019-eca2460cea6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684646878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1684646878 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.1627939007 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 864870601 ps |
| CPU time | 31.7 seconds |
| Started | Jul 22 07:50:06 PM PDT 24 |
| Finished | Jul 22 07:50:39 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-0c99877d-7f85-4e98-bbe7-4ccc0f718172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627939007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1627939007 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.4304616 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 490885123 ps |
| CPU time | 42.86 seconds |
| Started | Jul 22 07:50:03 PM PDT 24 |
| Finished | Jul 22 07:50:47 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a702a09e-8c3a-440a-b5a8-287b589e4eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4304616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.4304616 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.1384422089 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 9932518996 ps |
| CPU time | 100.95 seconds |
| Started | Jul 22 07:50:06 PM PDT 24 |
| Finished | Jul 22 07:51:48 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-4c18ba48-4e07-455a-ac29-41abcf3390ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384422089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1384422089 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.828909283 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 50191873888 ps |
| CPU time | 888.28 seconds |
| Started | Jul 22 07:50:05 PM PDT 24 |
| Finished | Jul 22 08:04:54 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-e0c50943-79ba-4c63-a3cd-d99c4850794a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828909283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.828909283 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1408052437 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 583103922 ps |
| CPU time | 47.27 seconds |
| Started | Jul 22 07:50:00 PM PDT 24 |
| Finished | Jul 22 07:50:50 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-87e3380f-9d76-4dc3-80b4-0f288a15954a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408052437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1408052437 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.3329151829 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 530363208 ps |
| CPU time | 17.41 seconds |
| Started | Jul 22 07:50:07 PM PDT 24 |
| Finished | Jul 22 07:50:25 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-43949d88-c271-45e0-b7d3-c944348e18c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329151829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3329151829 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.1013276854 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 173950755 ps |
| CPU time | 8.78 seconds |
| Started | Jul 22 07:49:57 PM PDT 24 |
| Finished | Jul 22 07:50:07 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-17149cf9-919b-4a8d-a312-526c5321d40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013276854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1013276854 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2725618294 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 9924818719 ps |
| CPU time | 91.09 seconds |
| Started | Jul 22 07:50:03 PM PDT 24 |
| Finished | Jul 22 07:51:35 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-c212219b-5796-4199-8a13-74f9695560fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725618294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2725618294 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.938065183 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 5814733679 ps |
| CPU time | 103.36 seconds |
| Started | Jul 22 07:49:57 PM PDT 24 |
| Finished | Jul 22 07:51:42 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-f3cf1916-6399-4638-bff8-03ed2583f38d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938065183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.938065183 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2987149255 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 46987697 ps |
| CPU time | 5.77 seconds |
| Started | Jul 22 07:50:03 PM PDT 24 |
| Finished | Jul 22 07:50:10 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-95a037ce-3a6b-4ef6-8b47-4c0df97b253a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987149255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2987149255 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.4205026700 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1001366420 ps |
| CPU time | 96.43 seconds |
| Started | Jul 22 07:50:07 PM PDT 24 |
| Finished | Jul 22 07:51:44 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-fbdf50de-3c6f-483d-bef8-019683ae6286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205026700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4205026700 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.878739139 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 6646300038 ps |
| CPU time | 223.6 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 07:54:00 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-d59cc6a7-a65f-4544-8a46-13f1e1dc467f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878739139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.878739139 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3822375538 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 3984800238 ps |
| CPU time | 345.66 seconds |
| Started | Jul 22 07:50:47 PM PDT 24 |
| Finished | Jul 22 07:56:36 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-47865ce7-b8ce-4325-81d7-817250ea769d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822375538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.3822375538 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3826154053 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 21703184218 ps |
| CPU time | 1029.84 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 08:07:27 PM PDT 24 |
| Peak memory | 583120 kb |
| Host | smart-186aa4f4-ec46-486d-85dc-1f4935fc4442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826154053 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3826154053 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1303981540 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 929847309 ps |
| CPU time | 42 seconds |
| Started | Jul 22 07:50:22 PM PDT 24 |
| Finished | Jul 22 07:51:08 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-c3f3a70a-7f8d-4377-a322-b1bdf725546e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303981540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1303981540 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.4100343533 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 314263195 ps |
| CPU time | 23.13 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:50:54 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-69a978b6-53a0-40b7-aa80-29dd387bcff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100343533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .4100343533 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2330443604 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 105888890695 ps |
| CPU time | 1765.26 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 08:19:42 PM PDT 24 |
| Peak memory | 577008 kb |
| Host | smart-caa4f15b-53cd-483c-962a-41c0739fef7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330443604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.2330443604 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2451986318 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 314361541 ps |
| CPU time | 34.94 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:51:05 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-a620ec1f-8848-4e09-9543-238fcf54064a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451986318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2451986318 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2070081626 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 460834782 ps |
| CPU time | 18.49 seconds |
| Started | Jul 22 07:50:17 PM PDT 24 |
| Finished | Jul 22 07:50:37 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-bd427f31-6d79-48ab-9e58-f1a9a61eac8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070081626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2070081626 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.326321109 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 1106613151 ps |
| CPU time | 39.39 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 07:50:56 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-34b590b9-1538-4ad0-9bb0-1c39fbaa4440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326321109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.326321109 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.111974352 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 32267833911 ps |
| CPU time | 334.58 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 07:55:52 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-1440604e-5b89-4940-9707-8cd88e1b4c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111974352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.111974352 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.2501343369 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 23073825660 ps |
| CPU time | 412.48 seconds |
| Started | Jul 22 07:50:16 PM PDT 24 |
| Finished | Jul 22 07:57:10 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-e6767f61-07c6-4fbe-8f92-90614c041d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501343369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2501343369 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.1351950758 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 175419312 ps |
| CPU time | 18.03 seconds |
| Started | Jul 22 07:50:19 PM PDT 24 |
| Finished | Jul 22 07:50:42 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-5f5b579d-b80a-4200-a6e0-d85d358a8173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351950758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.1351950758 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3398841639 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 51952578 ps |
| CPU time | 7.32 seconds |
| Started | Jul 22 07:50:47 PM PDT 24 |
| Finished | Jul 22 07:50:58 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-64d5795f-88a6-4809-8b11-973a39dd6dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398841639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3398841639 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.1871096442 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 113350471 ps |
| CPU time | 6.36 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 07:50:23 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-d66b2c42-6706-485e-9e94-fd619ab62028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871096442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1871096442 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.1362393453 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 8525638976 ps |
| CPU time | 90.76 seconds |
| Started | Jul 22 07:50:47 PM PDT 24 |
| Finished | Jul 22 07:52:21 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-aef45917-6a47-4db8-9632-297a1073741a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362393453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1362393453 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1835489435 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 6234181469 ps |
| CPU time | 105.95 seconds |
| Started | Jul 22 07:50:15 PM PDT 24 |
| Finished | Jul 22 07:52:02 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-0f3890fa-0df6-43c8-be37-5f79b738e722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835489435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1835489435 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3564205708 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 36560722 ps |
| CPU time | 5.6 seconds |
| Started | Jul 22 07:50:16 PM PDT 24 |
| Finished | Jul 22 07:50:23 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-fdaa382e-90a1-4d4f-bbc7-8e5c9803a12e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564205708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3564205708 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2201861215 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1393794780 ps |
| CPU time | 50.84 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:51:58 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-4780e9d0-83d1-4d3c-8b0c-c21b20a00562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201861215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2201861215 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1443672966 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 1126037859 ps |
| CPU time | 75.07 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:51:45 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-25b59cb4-fac3-4bc8-8bc0-37473bb7cc41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443672966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1443672966 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3884805503 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 914759338 ps |
| CPU time | 258.92 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:54:49 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-b2b821f5-6f67-4a4d-bb68-c250054985d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884805503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.3884805503 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.306367605 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 71989218 ps |
| CPU time | 16.5 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:50:47 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-e258cbb7-3219-4ef3-b334-ebea04665666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306367605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_reset_error.306367605 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.4169060816 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 266365764 ps |
| CPU time | 32.55 seconds |
| Started | Jul 22 07:50:26 PM PDT 24 |
| Finished | Jul 22 07:51:02 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-7b9b7f1d-72eb-4644-9f2c-36e6b474fdb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169060816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.4169060816 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.681212352 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 3577238910 ps |
| CPU time | 195.92 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:53:46 PM PDT 24 |
| Peak memory | 604452 kb |
| Host | smart-e59f27f0-296b-4ebb-be99-bcc18bf7fece |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681212352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.681212352 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3516001960 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 86401277 ps |
| CPU time | 7.35 seconds |
| Started | Jul 22 07:50:42 PM PDT 24 |
| Finished | Jul 22 07:50:53 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-ef6e800a-5548-4a4f-a86b-b28a91b4f4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516001960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3516001960 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.324537059 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 103044691590 ps |
| CPU time | 1852.95 seconds |
| Started | Jul 22 07:50:38 PM PDT 24 |
| Finished | Jul 22 08:21:34 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-c71d3845-8a6a-4c70-9603-fbd0a77bc0d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324537059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.324537059 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1754698723 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 128580552 ps |
| CPU time | 16.19 seconds |
| Started | Jul 22 07:50:39 PM PDT 24 |
| Finished | Jul 22 07:50:58 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-6f631841-ff17-4cf5-8b17-12e73c9b93f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754698723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1754698723 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.3678128644 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 2146245006 ps |
| CPU time | 66.05 seconds |
| Started | Jul 22 07:50:42 PM PDT 24 |
| Finished | Jul 22 07:51:51 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-a2bbb69b-0f36-4537-87f3-4a61829de272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678128644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3678128644 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.3231788165 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 2471504589 ps |
| CPU time | 101 seconds |
| Started | Jul 22 07:50:26 PM PDT 24 |
| Finished | Jul 22 07:52:11 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-f2995f4e-f23b-4662-b5f0-2776c11d8792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231788165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.3231788165 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.4088664767 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 24455339409 ps |
| CPU time | 257.27 seconds |
| Started | Jul 22 07:50:28 PM PDT 24 |
| Finished | Jul 22 07:54:48 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-9ee8fc9f-b7e4-4b80-9c47-21612de704ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088664767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.4088664767 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.604122906 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 14194958585 ps |
| CPU time | 208.12 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:53:58 PM PDT 24 |
| Peak memory | 576952 kb |
| Host | smart-6abaa824-3d81-48ce-b458-0a7505a963d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604122906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.604122906 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1429131787 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 91660046 ps |
| CPU time | 10.01 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:50:40 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-5d272905-e9a0-4f0c-bbd3-da74d3df8f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429131787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1429131787 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1232275586 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 2725255611 ps |
| CPU time | 75.36 seconds |
| Started | Jul 22 07:51:03 PM PDT 24 |
| Finished | Jul 22 07:52:21 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-f5983c70-4c88-4fb9-a9c4-4fed6ceb0749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232275586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1232275586 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.4057065059 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 207713785 ps |
| CPU time | 9.83 seconds |
| Started | Jul 22 07:50:26 PM PDT 24 |
| Finished | Jul 22 07:50:40 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-6d3dc7b7-b70d-4932-8929-bc6efae62e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057065059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4057065059 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.2823434041 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 8438556905 ps |
| CPU time | 78.27 seconds |
| Started | Jul 22 07:50:33 PM PDT 24 |
| Finished | Jul 22 07:51:52 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-2ed2bff6-96a0-4e7b-8961-245fadd7a6ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823434041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2823434041 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3953495509 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 6230843949 ps |
| CPU time | 106.27 seconds |
| Started | Jul 22 07:50:27 PM PDT 24 |
| Finished | Jul 22 07:52:17 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-4eafc75f-ab6a-49ea-b128-ea6179ef69ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953495509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3953495509 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.410272257 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 43138016 ps |
| CPU time | 6.35 seconds |
| Started | Jul 22 07:50:44 PM PDT 24 |
| Finished | Jul 22 07:50:54 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-afd7345b-fa04-4445-b7a7-44c649d95f3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410272257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays .410272257 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3770403505 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 1791539446 ps |
| CPU time | 68.12 seconds |
| Started | Jul 22 07:50:43 PM PDT 24 |
| Finished | Jul 22 07:51:54 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-567b78c4-2747-4396-8316-967afbfbdd0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770403505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3770403505 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.689200619 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 7272727878 ps |
| CPU time | 314.69 seconds |
| Started | Jul 22 07:50:38 PM PDT 24 |
| Finished | Jul 22 07:55:55 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-c959529b-5158-4115-9a12-7395bdcc37d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689200619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.689200619 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1137102484 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 945830520 ps |
| CPU time | 98.55 seconds |
| Started | Jul 22 07:50:39 PM PDT 24 |
| Finished | Jul 22 07:52:20 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-e2d9b409-a4ed-4956-9e22-1f8e5d9cf5ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137102484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1137102484 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.385502223 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 2247986738 ps |
| CPU time | 134.13 seconds |
| Started | Jul 22 07:50:37 PM PDT 24 |
| Finished | Jul 22 07:52:52 PM PDT 24 |
| Peak memory | 577012 kb |
| Host | smart-18fba7c3-bddd-4141-9970-a6fc38df80ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385502223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_reset_error.385502223 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2497290484 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 938922892 ps |
| CPU time | 37.23 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:51:46 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-aea47400-4083-444b-a467-5be3df5073e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497290484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2497290484 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1738207447 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 37987738072 ps |
| CPU time | 7181.94 seconds |
| Started | Jul 22 07:41:49 PM PDT 24 |
| Finished | Jul 22 09:41:33 PM PDT 24 |
| Peak memory | 594232 kb |
| Host | smart-39b4016c-90f8-467d-be11-ce69b21fef20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738207447 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1738207447 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.4288479383 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 16816607322 ps |
| CPU time | 1959.47 seconds |
| Started | Jul 22 07:41:51 PM PDT 24 |
| Finished | Jul 22 08:14:31 PM PDT 24 |
| Peak memory | 593096 kb |
| Host | smart-b701f6f6-cf0f-4325-95ef-7b5340ffb5dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288479383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.4288479383 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.59498660 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 7473524800 ps |
| CPU time | 607.85 seconds |
| Started | Jul 22 07:42:15 PM PDT 24 |
| Finished | Jul 22 07:52:24 PM PDT 24 |
| Peak memory | 645516 kb |
| Host | smart-27144544-7e6b-418e-9c83-20a20bde6008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59498660 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.59498660 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.2704886962 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 14717292029 ps |
| CPU time | 1504.26 seconds |
| Started | Jul 22 07:42:02 PM PDT 24 |
| Finished | Jul 22 08:07:09 PM PDT 24 |
| Peak memory | 592804 kb |
| Host | smart-7514236c-1b17-4372-9819-6f8964f2b028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704886962 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.2704886962 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2986799044 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2722503616 ps |
| CPU time | 158.78 seconds |
| Started | Jul 22 07:42:01 PM PDT 24 |
| Finished | Jul 22 07:44:42 PM PDT 24 |
| Peak memory | 604324 kb |
| Host | smart-00d725a3-5440-45aa-bcb8-abc6227648b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986799044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2986799044 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1999880393 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 179628529 ps |
| CPU time | 18.48 seconds |
| Started | Jul 22 07:42:14 PM PDT 24 |
| Finished | Jul 22 07:42:33 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-e4f415e5-db8a-40c0-92e8-7221486ba40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999880393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1999880393 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2165358438 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 313023357 ps |
| CPU time | 30.92 seconds |
| Started | Jul 22 07:44:44 PM PDT 24 |
| Finished | Jul 22 07:45:17 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-9366be6d-0702-465e-a22d-ad0b1d5f5c92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165358438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2165358438 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.4256898824 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 510739110 ps |
| CPU time | 44.87 seconds |
| Started | Jul 22 07:42:12 PM PDT 24 |
| Finished | Jul 22 07:42:58 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-01ae878a-acc4-4536-ba79-a6893fc52c88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256898824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.4256898824 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.2064240867 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 1816729265 ps |
| CPU time | 67.03 seconds |
| Started | Jul 22 07:42:02 PM PDT 24 |
| Finished | Jul 22 07:43:11 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-63f94712-2615-4b9c-ab35-1945ed835025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064240867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2064240867 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.437745667 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 106724151413 ps |
| CPU time | 1160.74 seconds |
| Started | Jul 22 07:42:12 PM PDT 24 |
| Finished | Jul 22 08:01:34 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-e16415e5-e972-40fe-b202-62509c7ad117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437745667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.437745667 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.4041358546 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 60862502402 ps |
| CPU time | 1002.55 seconds |
| Started | Jul 22 07:42:12 PM PDT 24 |
| Finished | Jul 22 07:58:56 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-b021cde1-c7ee-4561-93c3-0761d1bac071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041358546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4041358546 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.125645268 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 138826835 ps |
| CPU time | 15.76 seconds |
| Started | Jul 22 07:42:04 PM PDT 24 |
| Finished | Jul 22 07:42:22 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-d277c691-74ec-4f83-b2fc-bd18086ba8ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125645268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay s.125645268 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1029617064 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 383562360 ps |
| CPU time | 30.98 seconds |
| Started | Jul 22 07:42:12 PM PDT 24 |
| Finished | Jul 22 07:42:44 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-7dc45681-fa85-4752-8c16-ee4b0fad3dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029617064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1029617064 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3900335231 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 243336932 ps |
| CPU time | 8.93 seconds |
| Started | Jul 22 07:43:31 PM PDT 24 |
| Finished | Jul 22 07:43:41 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-24accc72-8a1a-493a-a528-33668ac84fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900335231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3900335231 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.4248593137 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 8275086534 ps |
| CPU time | 91.48 seconds |
| Started | Jul 22 07:42:01 PM PDT 24 |
| Finished | Jul 22 07:43:35 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-44a47184-0d8a-447d-92ee-2524951d3e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248593137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4248593137 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2587476947 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 3019041494 ps |
| CPU time | 48.71 seconds |
| Started | Jul 22 07:42:03 PM PDT 24 |
| Finished | Jul 22 07:42:54 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-e8e0bb04-d8c4-4169-a8d4-f1435b8a8ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587476947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2587476947 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2915138855 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 44374187 ps |
| CPU time | 6.67 seconds |
| Started | Jul 22 07:42:08 PM PDT 24 |
| Finished | Jul 22 07:42:15 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-aa6d63a3-bf1d-4193-9e39-6e0c4335621e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915138855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2915138855 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1239545882 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 2064307641 ps |
| CPU time | 171.98 seconds |
| Started | Jul 22 07:42:14 PM PDT 24 |
| Finished | Jul 22 07:45:06 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-3f0dd7ab-d557-4872-9a38-d168b0f35d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239545882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1239545882 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.1017129401 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 11999777711 ps |
| CPU time | 466.01 seconds |
| Started | Jul 22 07:43:53 PM PDT 24 |
| Finished | Jul 22 07:51:40 PM PDT 24 |
| Peak memory | 577020 kb |
| Host | smart-c3a7412c-c41c-4434-a2c0-49e869a8ad4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017129401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.1017129401 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1003497487 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2624840020 ps |
| CPU time | 197.53 seconds |
| Started | Jul 22 07:42:26 PM PDT 24 |
| Finished | Jul 22 07:45:44 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-73d56ccf-5004-4ce2-bbaf-ed2ea23c6cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003497487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.1003497487 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.628850521 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 183144554 ps |
| CPU time | 78.91 seconds |
| Started | Jul 22 07:42:17 PM PDT 24 |
| Finished | Jul 22 07:43:37 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-80c53d51-c719-4392-b51b-372d793f7cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628850521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_reset_error.628850521 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2913174186 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 240473631 ps |
| CPU time | 26.57 seconds |
| Started | Jul 22 07:42:11 PM PDT 24 |
| Finished | Jul 22 07:42:39 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-cc86bcae-ea5a-4ac4-8dc9-4bbe9da8745e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913174186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2913174186 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.1639100028 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 2043790730 ps |
| CPU time | 92.74 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:52:41 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-0cfed11b-22a1-4a76-9055-19b8cb1168d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639100028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1639100028 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3618902679 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 81472242645 ps |
| CPU time | 1545.26 seconds |
| Started | Jul 22 07:50:48 PM PDT 24 |
| Finished | Jul 22 08:16:36 PM PDT 24 |
| Peak memory | 577016 kb |
| Host | smart-e5fed75e-fa15-4088-8e6d-b38a8de7772a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618902679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.3618902679 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3374412555 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 135690066 ps |
| CPU time | 9.36 seconds |
| Started | Jul 22 07:50:56 PM PDT 24 |
| Finished | Jul 22 07:51:07 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-37bb0862-5145-4c7f-a8a4-a1b4834c29ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374412555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.3374412555 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1356917303 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 321815677 ps |
| CPU time | 28.92 seconds |
| Started | Jul 22 07:50:48 PM PDT 24 |
| Finished | Jul 22 07:51:19 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-0a3e1c46-64fb-48f3-82df-0434e066c334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356917303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1356917303 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.1418401512 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 1518677635 ps |
| CPU time | 54.85 seconds |
| Started | Jul 22 07:50:47 PM PDT 24 |
| Finished | Jul 22 07:51:45 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-ccd1f04a-10fd-49a2-a440-d9bd204beb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418401512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.1418401512 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2339919082 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 59855790720 ps |
| CPU time | 598.57 seconds |
| Started | Jul 22 07:50:47 PM PDT 24 |
| Finished | Jul 22 08:00:49 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-9fbdf2fa-4fbb-4ea1-b463-43d8da676365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339919082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2339919082 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3688871743 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 33712212907 ps |
| CPU time | 531.91 seconds |
| Started | Jul 22 07:50:48 PM PDT 24 |
| Finished | Jul 22 07:59:42 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-b2683153-1059-4000-ad1c-401c38340cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688871743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3688871743 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3080329049 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 186614847 ps |
| CPU time | 19.79 seconds |
| Started | Jul 22 07:50:47 PM PDT 24 |
| Finished | Jul 22 07:51:10 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-f0463644-c0d9-4f65-8f86-de5792d13a6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080329049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3080329049 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.882585715 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 505023961 ps |
| CPU time | 31.95 seconds |
| Started | Jul 22 07:50:53 PM PDT 24 |
| Finished | Jul 22 07:51:26 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-a4681e9f-3305-4a88-b13e-199767f80388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882585715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.882585715 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.2251824500 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 43793682 ps |
| CPU time | 6.49 seconds |
| Started | Jul 22 07:50:39 PM PDT 24 |
| Finished | Jul 22 07:50:48 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-983fc7d0-a4ab-47f5-8611-6bfbee43a5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251824500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2251824500 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.950636321 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 7893632642 ps |
| CPU time | 84.28 seconds |
| Started | Jul 22 07:50:45 PM PDT 24 |
| Finished | Jul 22 07:52:12 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-fa17ff3c-18a7-41b9-af0e-c10407ac63f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950636321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.950636321 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2145176372 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 5310801373 ps |
| CPU time | 85.76 seconds |
| Started | Jul 22 07:50:59 PM PDT 24 |
| Finished | Jul 22 07:52:26 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-6b56c54a-b141-420c-8471-cdae01407751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145176372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2145176372 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1086354727 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 53046856 ps |
| CPU time | 6.34 seconds |
| Started | Jul 22 07:51:02 PM PDT 24 |
| Finished | Jul 22 07:51:10 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-285ac6c5-4089-4e32-ba5c-7a20bd70f54b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086354727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1086354727 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3747308759 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 4502055244 ps |
| CPU time | 127.68 seconds |
| Started | Jul 22 07:51:11 PM PDT 24 |
| Finished | Jul 22 07:53:21 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-8b27d8f4-e2eb-41fd-a873-f225d765813e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747308759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3747308759 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.138741113 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 984455719 ps |
| CPU time | 219.46 seconds |
| Started | Jul 22 07:50:58 PM PDT 24 |
| Finished | Jul 22 07:54:39 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-40ffd61d-0c75-4009-8d33-b7a696937556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138741113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_ with_rand_reset.138741113 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.647268074 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 19129505 ps |
| CPU time | 24.36 seconds |
| Started | Jul 22 07:50:57 PM PDT 24 |
| Finished | Jul 22 07:51:22 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-ea244126-8221-4a6b-8e34-5f76dd9f0d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647268074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_reset_error.647268074 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4137137970 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1030735055 ps |
| CPU time | 39.84 seconds |
| Started | Jul 22 07:51:12 PM PDT 24 |
| Finished | Jul 22 07:51:56 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-175ec2d5-7ac3-43ec-895f-cce3909fdaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137137970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4137137970 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.4278007821 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2504042855 ps |
| CPU time | 88.32 seconds |
| Started | Jul 22 07:51:11 PM PDT 24 |
| Finished | Jul 22 07:52:42 PM PDT 24 |
| Peak memory | 577068 kb |
| Host | smart-79aa6083-350f-4745-954c-99c13fdf1b14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278007821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .4278007821 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3384545588 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 28650091375 ps |
| CPU time | 515.16 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:59:42 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-555fb3b0-278f-46b8-b1ed-bec58b81b8f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384545588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.3384545588 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1430710777 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 123075622 ps |
| CPU time | 14.63 seconds |
| Started | Jul 22 07:51:04 PM PDT 24 |
| Finished | Jul 22 07:51:20 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-99edf8b1-d7a8-4107-80c5-d12569045f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430710777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1430710777 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.1787978793 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 380332774 ps |
| CPU time | 14.67 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:51:21 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-2d80f510-083d-47cd-aca0-1510e24754cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787978793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1787978793 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.811750916 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 194513956 ps |
| CPU time | 19.41 seconds |
| Started | Jul 22 07:50:57 PM PDT 24 |
| Finished | Jul 22 07:51:17 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-881f1119-f925-4067-b91f-b3b2bef54b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811750916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.811750916 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3439648924 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 64199301383 ps |
| CPU time | 637.89 seconds |
| Started | Jul 22 07:51:11 PM PDT 24 |
| Finished | Jul 22 08:01:51 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-8ceab3fe-750a-429a-b715-90183281e19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439648924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3439648924 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2161277913 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 56144992092 ps |
| CPU time | 965.71 seconds |
| Started | Jul 22 07:50:58 PM PDT 24 |
| Finished | Jul 22 08:07:05 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-cec0214e-bc86-469b-9939-8ecd3d70f022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161277913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2161277913 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1257514922 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 278139848 ps |
| CPU time | 23.49 seconds |
| Started | Jul 22 07:51:11 PM PDT 24 |
| Finished | Jul 22 07:51:37 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-74ae8e7e-8ff0-4572-b057-9a4f907dbe52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257514922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.1257514922 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1815138653 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 337809611 ps |
| CPU time | 28.81 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:51:35 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-ab017443-af33-4833-b1b9-25324d35cf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815138653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1815138653 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.2552273563 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 229749580 ps |
| CPU time | 9.45 seconds |
| Started | Jul 22 07:50:58 PM PDT 24 |
| Finished | Jul 22 07:51:08 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-3815bd8e-04b1-4de1-8833-62a4cc9375dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552273563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2552273563 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3300226174 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 5176373053 ps |
| CPU time | 54.18 seconds |
| Started | Jul 22 07:50:57 PM PDT 24 |
| Finished | Jul 22 07:51:52 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-71d5b691-a536-4a63-a234-64dec5faf1ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300226174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3300226174 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.4066864427 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 4495583232 ps |
| CPU time | 76.31 seconds |
| Started | Jul 22 07:51:16 PM PDT 24 |
| Finished | Jul 22 07:52:39 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-345cc693-7791-4402-824f-1207c1b19693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066864427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4066864427 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3433961193 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 41987979 ps |
| CPU time | 5.75 seconds |
| Started | Jul 22 07:51:11 PM PDT 24 |
| Finished | Jul 22 07:51:19 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-96b3fadc-0978-4fb1-b672-8017c826a846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433961193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.3433961193 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.3921883626 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 5543411582 ps |
| CPU time | 213.26 seconds |
| Started | Jul 22 07:51:05 PM PDT 24 |
| Finished | Jul 22 07:54:41 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-c349306c-9e58-4400-a32a-21119359b20d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921883626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3921883626 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3647901733 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 2374320426 ps |
| CPU time | 339.86 seconds |
| Started | Jul 22 07:51:16 PM PDT 24 |
| Finished | Jul 22 07:57:00 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-01cd4a23-9d5c-4fb1-bcbb-a0ea43d812a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647901733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.3647901733 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3603075286 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 2296605540 ps |
| CPU time | 325.18 seconds |
| Started | Jul 22 07:51:16 PM PDT 24 |
| Finished | Jul 22 07:56:46 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-54aa44f0-df61-49dd-94c4-2b8e5c6f8766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603075286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3603075286 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1194646142 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 320908476 ps |
| CPU time | 17.29 seconds |
| Started | Jul 22 07:51:04 PM PDT 24 |
| Finished | Jul 22 07:51:23 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-b42b4a6d-6f73-46f8-a701-6cc8ff998c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194646142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1194646142 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.1161144185 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1375183745 ps |
| CPU time | 95.61 seconds |
| Started | Jul 22 07:51:16 PM PDT 24 |
| Finished | Jul 22 07:52:56 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-9f2f0590-d81d-49d2-9ea7-2f518d875acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161144185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .1161144185 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.343779358 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 29806396310 ps |
| CPU time | 500.06 seconds |
| Started | Jul 22 07:51:19 PM PDT 24 |
| Finished | Jul 22 07:59:44 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-6e54573a-eebb-4957-97e5-62d423795aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343779358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.343779358 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2756515540 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 202916405 ps |
| CPU time | 11.82 seconds |
| Started | Jul 22 07:51:24 PM PDT 24 |
| Finished | Jul 22 07:51:39 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-acbaecaf-4ca0-4047-b11f-b5d22745ce08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756515540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.2756515540 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.3002299198 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 881872854 ps |
| CPU time | 25.63 seconds |
| Started | Jul 22 07:51:14 PM PDT 24 |
| Finished | Jul 22 07:51:43 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-d19b7c0b-0a31-4b42-885b-99c68e7bb68c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002299198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3002299198 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.849360646 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 263353903 ps |
| CPU time | 22.75 seconds |
| Started | Jul 22 07:51:17 PM PDT 24 |
| Finished | Jul 22 07:51:44 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-3636c1f2-69a8-4f4c-ae00-d05c5d62d001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849360646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.849360646 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.308424126 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 35160166093 ps |
| CPU time | 326.27 seconds |
| Started | Jul 22 07:51:23 PM PDT 24 |
| Finished | Jul 22 07:56:53 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-3d3983b8-0e4d-42a8-a7a1-fd2237b1af52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308424126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.308424126 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2667262472 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 30310890602 ps |
| CPU time | 539.23 seconds |
| Started | Jul 22 07:51:15 PM PDT 24 |
| Finished | Jul 22 08:00:19 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-630f9e03-22c0-4a1e-b50e-0f81ea95dc13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667262472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2667262472 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2400457184 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 186731507 ps |
| CPU time | 16.58 seconds |
| Started | Jul 22 07:53:04 PM PDT 24 |
| Finished | Jul 22 07:53:22 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-2febc164-d5f0-4ffb-9d78-15e714712bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400457184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2400457184 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.961236610 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 454612435 ps |
| CPU time | 29.39 seconds |
| Started | Jul 22 07:53:04 PM PDT 24 |
| Finished | Jul 22 07:53:35 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-14682a43-2353-4e58-93d3-165bab79bccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961236610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.961236610 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.1891089000 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 53348029 ps |
| CPU time | 6.94 seconds |
| Started | Jul 22 07:51:15 PM PDT 24 |
| Finished | Jul 22 07:51:26 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-ddeb7a89-6a53-4bd9-b02a-31724ffb6fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891089000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1891089000 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1650854592 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 8126361721 ps |
| CPU time | 82.59 seconds |
| Started | Jul 22 07:51:19 PM PDT 24 |
| Finished | Jul 22 07:52:47 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-c005e2f5-164d-4c36-8885-234d7e8e295c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650854592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1650854592 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2456077155 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 4539031055 ps |
| CPU time | 74.86 seconds |
| Started | Jul 22 07:51:23 PM PDT 24 |
| Finished | Jul 22 07:52:41 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-0cdff688-7250-467a-be5a-524543ccdbbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456077155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2456077155 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1611173164 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 42842261 ps |
| CPU time | 6.51 seconds |
| Started | Jul 22 07:51:13 PM PDT 24 |
| Finished | Jul 22 07:51:22 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-345b9e9a-e287-46e2-ad5c-f15610521914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611173164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.1611173164 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1403544848 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2586983912 ps |
| CPU time | 77.73 seconds |
| Started | Jul 22 07:51:25 PM PDT 24 |
| Finished | Jul 22 07:52:45 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-766e2b89-9770-498a-bf13-0d71aa96f298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403544848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1403544848 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3844057070 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 2210539849 ps |
| CPU time | 194.9 seconds |
| Started | Jul 22 07:51:23 PM PDT 24 |
| Finished | Jul 22 07:54:41 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-8cad6b5d-b3d7-4c4b-9dc9-a75556f65c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844057070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3844057070 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.4284905653 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 18276207 ps |
| CPU time | 14.44 seconds |
| Started | Jul 22 07:51:23 PM PDT 24 |
| Finished | Jul 22 07:51:41 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-be193896-b707-433c-a7d3-8fb6ef1e5450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284905653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.4284905653 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2999295739 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 6549636617 ps |
| CPU time | 270.81 seconds |
| Started | Jul 22 07:51:23 PM PDT 24 |
| Finished | Jul 22 07:55:57 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-a41f8c41-ce52-4b2a-9cfd-eb96044ff6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999295739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.2999295739 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2243698990 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 32668362 ps |
| CPU time | 7.02 seconds |
| Started | Jul 22 07:51:20 PM PDT 24 |
| Finished | Jul 22 07:51:32 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-e0519746-5a0a-4b21-a7a9-495645db6d93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243698990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2243698990 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.4202425994 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 1630265572 ps |
| CPU time | 71.49 seconds |
| Started | Jul 22 07:51:33 PM PDT 24 |
| Finished | Jul 22 07:52:47 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-02d3bec7-ddab-431f-b221-d50820082aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202425994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .4202425994 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3190520487 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 86029166313 ps |
| CPU time | 1535.98 seconds |
| Started | Jul 22 07:51:34 PM PDT 24 |
| Finished | Jul 22 08:17:12 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-ed502654-e9e2-4527-9488-37b7ec20d291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190520487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.3190520487 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.436203777 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 22736648 ps |
| CPU time | 5.53 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:51:51 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-bec53e17-3420-4040-ae1d-b26dbd2e2506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436203777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr .436203777 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.2347600795 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 103901008 ps |
| CPU time | 12.61 seconds |
| Started | Jul 22 07:51:40 PM PDT 24 |
| Finished | Jul 22 07:51:57 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-9827ad19-8872-4b9f-9a9a-08c3347f00f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347600795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.2347600795 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.625955295 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 680825686 ps |
| CPU time | 24.77 seconds |
| Started | Jul 22 07:51:32 PM PDT 24 |
| Finished | Jul 22 07:51:59 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-181521e0-abea-4073-97b9-ac85bb3e520d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625955295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.625955295 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3538032423 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 15602316217 ps |
| CPU time | 144.69 seconds |
| Started | Jul 22 07:51:32 PM PDT 24 |
| Finished | Jul 22 07:53:59 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-d71f102d-cc79-47d7-8302-fb392874a228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538032423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3538032423 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1679748755 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 32394810282 ps |
| CPU time | 487.21 seconds |
| Started | Jul 22 07:51:39 PM PDT 24 |
| Finished | Jul 22 07:59:50 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-41caa496-40b9-4e0e-b43c-dabc11799096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679748755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1679748755 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.327606957 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 306801088 ps |
| CPU time | 25.21 seconds |
| Started | Jul 22 07:51:39 PM PDT 24 |
| Finished | Jul 22 07:52:07 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-5e515867-5065-445f-86da-ce0ddb5c5b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327606957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_dela ys.327606957 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.151247675 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 1749308186 ps |
| CPU time | 55.8 seconds |
| Started | Jul 22 07:51:42 PM PDT 24 |
| Finished | Jul 22 07:52:41 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-64c90d13-5481-4d33-89cc-c3e8ecb65db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151247675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.151247675 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.3324331753 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 45462055 ps |
| CPU time | 6.06 seconds |
| Started | Jul 22 07:51:33 PM PDT 24 |
| Finished | Jul 22 07:51:41 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-9cc58940-5081-42a9-ae45-03ff7041bf6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324331753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3324331753 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2862692543 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 8169768050 ps |
| CPU time | 84.19 seconds |
| Started | Jul 22 07:51:39 PM PDT 24 |
| Finished | Jul 22 07:53:06 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-9b1c9ffc-c705-4cee-938e-9e5da7a4d659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862692543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2862692543 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1653493712 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 6573083491 ps |
| CPU time | 109.3 seconds |
| Started | Jul 22 07:51:32 PM PDT 24 |
| Finished | Jul 22 07:53:23 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-0b1fe368-5cc8-419e-9fb7-8aed67db3320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653493712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1653493712 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2405336806 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 38609967 ps |
| CPU time | 5.73 seconds |
| Started | Jul 22 07:51:32 PM PDT 24 |
| Finished | Jul 22 07:51:40 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-7ecafbae-63be-418a-8684-5dd64a7db21b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405336806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2405336806 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.128997919 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3452200945 ps |
| CPU time | 262.07 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:56:07 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-dfc45eab-664f-43c2-8091-d7ff02170f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128997919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.128997919 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.1673620788 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 752640158 ps |
| CPU time | 65.93 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:52:51 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-876867b1-f2ed-4f6a-87d6-9ce44893fb4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673620788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1673620788 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3686673664 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 368675545 ps |
| CPU time | 113.51 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:53:39 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-198e7a3b-87b2-4777-8634-f3db3e07295f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686673664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3686673664 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1457322115 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 138277024 ps |
| CPU time | 53.81 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:52:38 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-7e60e817-5c4a-42a8-aff9-1aeb7693e7ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457322115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1457322115 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.3084553804 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 660468636 ps |
| CPU time | 25.73 seconds |
| Started | Jul 22 07:51:40 PM PDT 24 |
| Finished | Jul 22 07:52:10 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-87a1a485-a86f-489a-824f-c1606a2229d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084553804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3084553804 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.844317977 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 357876788 ps |
| CPU time | 37.53 seconds |
| Started | Jul 22 07:51:53 PM PDT 24 |
| Finished | Jul 22 07:52:32 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-03785277-8db1-429f-8ab6-12954bb28f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844317977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device. 844317977 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1589671130 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 116499341508 ps |
| CPU time | 2029.12 seconds |
| Started | Jul 22 07:53:59 PM PDT 24 |
| Finished | Jul 22 08:27:49 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-20277118-d84f-40e9-bf91-62a519bf5c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589671130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.1589671130 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2205055445 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 767648088 ps |
| CPU time | 33 seconds |
| Started | Jul 22 07:51:57 PM PDT 24 |
| Finished | Jul 22 07:52:32 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-eb4775d3-f580-4ce1-b5e3-9f80419dc346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205055445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.2205055445 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.1308366071 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 56290714 ps |
| CPU time | 7.53 seconds |
| Started | Jul 22 07:51:54 PM PDT 24 |
| Finished | Jul 22 07:52:02 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-d72b918a-f932-4d81-9870-c8539c52411c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308366071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1308366071 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.440706252 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 1552439558 ps |
| CPU time | 49.65 seconds |
| Started | Jul 22 07:53:18 PM PDT 24 |
| Finished | Jul 22 07:54:11 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-f8d1ff45-964f-4dec-a271-7e207fdde429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440706252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.440706252 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2345849826 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 96773932243 ps |
| CPU time | 955.64 seconds |
| Started | Jul 22 07:51:53 PM PDT 24 |
| Finished | Jul 22 08:07:50 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-2cc51ee2-62de-4bb5-a0df-acd194f500e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345849826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2345849826 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3015997001 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 18253603352 ps |
| CPU time | 307.38 seconds |
| Started | Jul 22 07:51:53 PM PDT 24 |
| Finished | Jul 22 07:57:02 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-424a130e-fcf0-4e2a-8ec6-a7dd1789c9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015997001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3015997001 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2246275425 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 441244034 ps |
| CPU time | 38.21 seconds |
| Started | Jul 22 07:54:08 PM PDT 24 |
| Finished | Jul 22 07:54:48 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-a340a2d7-9f6a-4979-abc2-b83d97627ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246275425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2246275425 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.908274324 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 1028340918 ps |
| CPU time | 32.86 seconds |
| Started | Jul 22 07:51:54 PM PDT 24 |
| Finished | Jul 22 07:52:28 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-bd4c43c4-a8a8-46fa-8ad9-dc6f369446d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908274324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.908274324 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.4032684451 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 207091297 ps |
| CPU time | 9.24 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:51:54 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-62282d23-04ce-4d25-9534-fcbb07b775b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032684451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4032684451 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2169591848 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 8998848985 ps |
| CPU time | 88.99 seconds |
| Started | Jul 22 07:51:42 PM PDT 24 |
| Finished | Jul 22 07:53:14 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-b574bbce-063c-4cff-b2cf-fc991e86be82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169591848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2169591848 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2745131730 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 5503255626 ps |
| CPU time | 91.46 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:53:16 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-2f1451d5-6abd-4ef4-b51a-6a71852c3a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745131730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2745131730 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2890108911 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 54472075 ps |
| CPU time | 7.01 seconds |
| Started | Jul 22 07:51:41 PM PDT 24 |
| Finished | Jul 22 07:51:52 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-7b0fad81-94e8-432b-9c8e-d049dd1be386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890108911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.2890108911 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1171657963 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1926881793 ps |
| CPU time | 158.47 seconds |
| Started | Jul 22 07:51:54 PM PDT 24 |
| Finished | Jul 22 07:54:33 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-fe337d23-afbe-4a2b-894c-52d9246f4fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171657963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1171657963 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2344544585 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 2956968246 ps |
| CPU time | 117.56 seconds |
| Started | Jul 22 07:51:54 PM PDT 24 |
| Finished | Jul 22 07:53:52 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-ad3e7603-225d-4f50-b767-d1080607265b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344544585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2344544585 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.527523434 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 1731741273 ps |
| CPU time | 202.97 seconds |
| Started | Jul 22 07:52:26 PM PDT 24 |
| Finished | Jul 22 07:55:50 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-65baf1e3-f42a-4ffd-8ead-f2729ab18aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527523434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_ with_rand_reset.527523434 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2584516984 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 7374261472 ps |
| CPU time | 707.91 seconds |
| Started | Jul 22 07:51:58 PM PDT 24 |
| Finished | Jul 22 08:03:47 PM PDT 24 |
| Peak memory | 578028 kb |
| Host | smart-2071b641-354d-425e-8779-b6356c622673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584516984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2584516984 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1357618067 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 802005127 ps |
| CPU time | 32.58 seconds |
| Started | Jul 22 07:53:46 PM PDT 24 |
| Finished | Jul 22 07:54:21 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-b612cb07-8a10-47b5-8ce3-401dba65c8e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357618067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1357618067 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2214671364 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 788939339 ps |
| CPU time | 54.55 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 07:53:00 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-813d158b-81cb-4b86-b5ea-298669b8f92c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214671364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2214671364 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1922746472 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 103715308202 ps |
| CPU time | 2065.9 seconds |
| Started | Jul 22 07:52:04 PM PDT 24 |
| Finished | Jul 22 08:26:33 PM PDT 24 |
| Peak memory | 576988 kb |
| Host | smart-d255b6aa-9213-44e8-944e-210afbeb3073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922746472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.1922746472 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3465861651 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 207434815 ps |
| CPU time | 22.59 seconds |
| Started | Jul 22 07:52:08 PM PDT 24 |
| Finished | Jul 22 07:52:33 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-2845aaf4-cc01-4849-a690-8b21d9ed5a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465861651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3465861651 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.737097778 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 508434106 ps |
| CPU time | 42 seconds |
| Started | Jul 22 07:54:09 PM PDT 24 |
| Finished | Jul 22 07:54:53 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-783acbf6-e26e-4cef-a1f7-ac1293c24c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737097778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.737097778 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.2642742018 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 1256167032 ps |
| CPU time | 52.64 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 07:52:59 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-69bd2b39-1aca-4995-9b51-d258930ed536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642742018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2642742018 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3641611091 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 85273798554 ps |
| CPU time | 846.17 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 08:06:11 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-582d0e52-026f-41c6-9323-3abdef17a465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641611091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3641611091 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1563170826 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 35195360038 ps |
| CPU time | 586.33 seconds |
| Started | Jul 22 07:52:06 PM PDT 24 |
| Finished | Jul 22 08:01:55 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-559f399c-82b3-4969-a41b-d2bce44b73e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563170826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1563170826 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.1696236309 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 344765219 ps |
| CPU time | 31.99 seconds |
| Started | Jul 22 07:52:04 PM PDT 24 |
| Finished | Jul 22 07:52:39 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-1e52fc20-9138-4d42-b246-b6eb7d745e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696236309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.1696236309 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.3383936336 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 261000146 ps |
| CPU time | 18.87 seconds |
| Started | Jul 22 07:53:45 PM PDT 24 |
| Finished | Jul 22 07:54:07 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-1668df04-f678-4983-95f5-6c45ff890e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383936336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3383936336 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3012650401 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 249555284 ps |
| CPU time | 9.29 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 07:52:15 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-8bd6611a-6ae0-4586-af8c-d2239cbde538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012650401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3012650401 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.418936795 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 6902190715 ps |
| CPU time | 68.75 seconds |
| Started | Jul 22 07:53:57 PM PDT 24 |
| Finished | Jul 22 07:55:07 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-5842dc4c-f249-4269-a6b8-f313f7ad7a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418936795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.418936795 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.4073518855 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 5757859687 ps |
| CPU time | 95.47 seconds |
| Started | Jul 22 07:54:08 PM PDT 24 |
| Finished | Jul 22 07:55:45 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-9642dc93-bb3e-4ba6-8629-7d3ef43da891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073518855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.4073518855 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2963502255 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 48448688 ps |
| CPU time | 6.65 seconds |
| Started | Jul 22 07:52:05 PM PDT 24 |
| Finished | Jul 22 07:52:14 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-88653375-9b5a-4ebd-8b71-4955df8e44cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963502255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2963502255 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2881188637 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2586667927 ps |
| CPU time | 94 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 07:53:39 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-194bfe3a-599a-4754-a8b4-4d5a5476ac0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881188637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2881188637 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3051874714 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 5000823658 ps |
| CPU time | 285.89 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 07:56:51 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-e0deddc1-8ac3-4fce-a347-25fa147906b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051874714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3051874714 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.2976660299 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 6445450290 ps |
| CPU time | 604.07 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 08:02:09 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-8454fa3a-a3eb-4808-8142-f693935f9681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976660299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.2976660299 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.210122244 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 1148868993 ps |
| CPU time | 50.73 seconds |
| Started | Jul 22 07:52:03 PM PDT 24 |
| Finished | Jul 22 07:52:56 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-cbea3132-3f0c-4f80-923b-02d40884f5b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210122244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.210122244 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3097494051 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 3020252275 ps |
| CPU time | 108.25 seconds |
| Started | Jul 22 07:52:13 PM PDT 24 |
| Finished | Jul 22 07:54:04 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-34843c58-1662-4858-8b44-be4008481e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097494051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3097494051 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3950915803 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 788255499 ps |
| CPU time | 32.76 seconds |
| Started | Jul 22 07:52:15 PM PDT 24 |
| Finished | Jul 22 07:52:52 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-04a77fb0-37b0-4a5a-92a9-a5ac46cfcd35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950915803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3950915803 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.1646285330 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 387400556 ps |
| CPU time | 36.63 seconds |
| Started | Jul 22 07:52:16 PM PDT 24 |
| Finished | Jul 22 07:52:56 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-a7d7cacf-a522-478a-8235-dd12addf335b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646285330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1646285330 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1592147244 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 100050942 ps |
| CPU time | 10.93 seconds |
| Started | Jul 22 07:52:16 PM PDT 24 |
| Finished | Jul 22 07:52:31 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-94d60fc7-a6be-41fd-b922-eb2339dd070c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592147244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1592147244 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1434011811 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 39024457968 ps |
| CPU time | 375.63 seconds |
| Started | Jul 22 07:53:22 PM PDT 24 |
| Finished | Jul 22 07:59:40 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-b77d4de2-1464-4e6e-9870-48cc13abebc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434011811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1434011811 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2506355375 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 32692381842 ps |
| CPU time | 539.22 seconds |
| Started | Jul 22 07:52:13 PM PDT 24 |
| Finished | Jul 22 08:01:15 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-b672f111-70f4-41ac-985d-c9e262738f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506355375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2506355375 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3621877985 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 190269102 ps |
| CPU time | 19.19 seconds |
| Started | Jul 22 07:52:14 PM PDT 24 |
| Finished | Jul 22 07:52:37 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-176c024f-633f-4cce-a92a-47b3e4857c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621877985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.3621877985 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.4257939398 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2437708981 ps |
| CPU time | 80.44 seconds |
| Started | Jul 22 07:52:13 PM PDT 24 |
| Finished | Jul 22 07:53:37 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-fe4c8c2d-18d7-4c6c-9e7b-41cea302c9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257939398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4257939398 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.4185495670 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 236386751 ps |
| CPU time | 9.56 seconds |
| Started | Jul 22 07:52:07 PM PDT 24 |
| Finished | Jul 22 07:52:20 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-d6688d87-6b40-4eee-965e-bf07e1d609ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185495670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.4185495670 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.476980959 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 5507930141 ps |
| CPU time | 55.08 seconds |
| Started | Jul 22 07:52:04 PM PDT 24 |
| Finished | Jul 22 07:53:02 PM PDT 24 |
| Peak memory | 574788 kb |
| Host | smart-450d920d-5b0a-4900-9f21-e517b3bfeec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476980959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.476980959 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1503285645 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 5657136869 ps |
| CPU time | 90.85 seconds |
| Started | Jul 22 07:52:19 PM PDT 24 |
| Finished | Jul 22 07:53:53 PM PDT 24 |
| Peak memory | 574788 kb |
| Host | smart-aebb8e87-dfbc-4bdd-9fcb-c8fa6e82b7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503285645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1503285645 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1161777226 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 38066646 ps |
| CPU time | 5.43 seconds |
| Started | Jul 22 07:53:57 PM PDT 24 |
| Finished | Jul 22 07:54:04 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-ec94c255-d8eb-4ab2-877f-1ea7d4304491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161777226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1161777226 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1429171620 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 526805562 ps |
| CPU time | 43.83 seconds |
| Started | Jul 22 07:52:13 PM PDT 24 |
| Finished | Jul 22 07:53:00 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-9f2b6f11-2a28-4e3b-ac0a-656b3331f940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429171620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1429171620 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.145070926 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 2721998924 ps |
| CPU time | 195.64 seconds |
| Started | Jul 22 07:52:15 PM PDT 24 |
| Finished | Jul 22 07:55:35 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-c4374e97-4647-4970-b128-08664f6e609c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145070926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.145070926 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3576922837 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 130124288 ps |
| CPU time | 40.42 seconds |
| Started | Jul 22 07:52:13 PM PDT 24 |
| Finished | Jul 22 07:52:57 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-890b48eb-3c55-4f5a-b750-ea75b5db5b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576922837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.3576922837 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2097574528 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 187921848 ps |
| CPU time | 72.21 seconds |
| Started | Jul 22 07:52:13 PM PDT 24 |
| Finished | Jul 22 07:53:28 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-6ff77794-74de-4ca2-a8e2-afeef114b924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097574528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.2097574528 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1977389931 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 20821318 ps |
| CPU time | 5.62 seconds |
| Started | Jul 22 07:52:14 PM PDT 24 |
| Finished | Jul 22 07:52:23 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-a31c88c7-1d8c-4032-9de6-ea6e5919117c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977389931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1977389931 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.1136788801 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 2991473601 ps |
| CPU time | 145.64 seconds |
| Started | Jul 22 07:52:24 PM PDT 24 |
| Finished | Jul 22 07:54:51 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-c926ad29-5757-4e5d-8d10-3922e5ec4984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136788801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .1136788801 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3405206236 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 24687294782 ps |
| CPU time | 405.43 seconds |
| Started | Jul 22 07:52:21 PM PDT 24 |
| Finished | Jul 22 07:59:09 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-bce3be52-401a-4dd8-b147-50cff747a9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405206236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3405206236 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3929686176 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 140901451 ps |
| CPU time | 18.77 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 07:52:56 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-42b13f03-fc09-4ebd-ab11-4bdfd477d295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929686176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3929686176 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.3439883600 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 619791710 ps |
| CPU time | 21.25 seconds |
| Started | Jul 22 07:52:23 PM PDT 24 |
| Finished | Jul 22 07:52:45 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-95e81aae-d075-4993-a37a-d4f08e59a5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439883600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3439883600 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.861245359 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 283463285 ps |
| CPU time | 26.97 seconds |
| Started | Jul 22 07:52:23 PM PDT 24 |
| Finished | Jul 22 07:52:52 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-1e385c7b-0267-4a7c-9883-c4e907e52d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861245359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.861245359 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.938974278 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 90213865349 ps |
| CPU time | 894.6 seconds |
| Started | Jul 22 07:54:06 PM PDT 24 |
| Finished | Jul 22 08:09:03 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-c241691b-07dc-449d-898d-f8dd2b39d67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938974278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.938974278 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3480052294 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 47011393214 ps |
| CPU time | 785.3 seconds |
| Started | Jul 22 07:52:23 PM PDT 24 |
| Finished | Jul 22 08:05:30 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-4205ba0e-698a-40ce-a42c-0f46def9c288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480052294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3480052294 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3239458074 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 241475064 ps |
| CPU time | 20.23 seconds |
| Started | Jul 22 07:52:28 PM PDT 24 |
| Finished | Jul 22 07:52:49 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-9d2f059f-5e22-4cb4-9027-01944070f2c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239458074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.3239458074 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.432047604 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 937982527 ps |
| CPU time | 28.87 seconds |
| Started | Jul 22 07:52:24 PM PDT 24 |
| Finished | Jul 22 07:52:54 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-06cb46d3-7d74-48fa-8630-3ac1fe7ab730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432047604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.432047604 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2206781328 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 128722160 ps |
| CPU time | 7.41 seconds |
| Started | Jul 22 07:52:19 PM PDT 24 |
| Finished | Jul 22 07:52:30 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-f044102d-6209-499e-b15e-6c1a50eacd63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206781328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2206781328 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.397280200 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 10391305533 ps |
| CPU time | 105.31 seconds |
| Started | Jul 22 07:52:22 PM PDT 24 |
| Finished | Jul 22 07:54:09 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-8bc86754-0195-4f8d-bacf-94e48a771d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397280200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.397280200 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.943093339 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3285236929 ps |
| CPU time | 56.07 seconds |
| Started | Jul 22 07:52:29 PM PDT 24 |
| Finished | Jul 22 07:53:26 PM PDT 24 |
| Peak memory | 574876 kb |
| Host | smart-7c0e10a1-7df8-4900-b43c-28e9720f0e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943093339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.943093339 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2404852753 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 50718060 ps |
| CPU time | 6.5 seconds |
| Started | Jul 22 07:52:24 PM PDT 24 |
| Finished | Jul 22 07:52:32 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-77f93cb0-9df7-414b-bc91-5443f37c8658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404852753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2404852753 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.3070077864 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 948024580 ps |
| CPU time | 90.42 seconds |
| Started | Jul 22 07:52:33 PM PDT 24 |
| Finished | Jul 22 07:54:05 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-6b1d427d-e648-43d7-8ed7-76925866d972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070077864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3070077864 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2361766554 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 10683478157 ps |
| CPU time | 341.25 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 07:58:18 PM PDT 24 |
| Peak memory | 577120 kb |
| Host | smart-bc0b1843-56f0-40a3-9407-a0ff575ab591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361766554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2361766554 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2213518126 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 5705020983 ps |
| CPU time | 441.45 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 07:59:58 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-74ef81a6-ece3-4785-ae88-aa6d6bc89799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213518126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.2213518126 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.4195565899 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 8395832099 ps |
| CPU time | 409.99 seconds |
| Started | Jul 22 07:52:32 PM PDT 24 |
| Finished | Jul 22 07:59:24 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-4b063c09-f59a-402b-a6ab-7160ed4f8d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195565899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.4195565899 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3009555807 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 141608769 ps |
| CPU time | 9.24 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 07:52:47 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-c81bfadd-6868-48ae-8bda-6011269c1f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009555807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3009555807 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.171425381 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 917891688 ps |
| CPU time | 67.41 seconds |
| Started | Jul 22 07:52:33 PM PDT 24 |
| Finished | Jul 22 07:53:43 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-79cdf865-f0ae-4f82-ad9d-2afb60b41e4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171425381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device. 171425381 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.959797133 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 44760927928 ps |
| CPU time | 666.61 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 08:05:43 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-af607ffa-3da5-4f38-9bba-87602b753337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959797133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.959797133 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4016930278 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 212798164 ps |
| CPU time | 24.09 seconds |
| Started | Jul 22 07:54:28 PM PDT 24 |
| Finished | Jul 22 07:54:53 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-adc59cf7-174d-45eb-8225-3bad42360b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016930278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.4016930278 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.80844955 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 1490546667 ps |
| CPU time | 55.31 seconds |
| Started | Jul 22 07:52:47 PM PDT 24 |
| Finished | Jul 22 07:53:43 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-be80704d-8561-48f9-9cd9-07ba300c8b14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80844955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.80844955 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3461255175 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 428437250 ps |
| CPU time | 35.17 seconds |
| Started | Jul 22 07:52:33 PM PDT 24 |
| Finished | Jul 22 07:53:11 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-01b8a6dc-988b-4671-9901-d4b1cff7529d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461255175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3461255175 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1504523774 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 100564165020 ps |
| CPU time | 1049.07 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 08:10:05 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-dfeeab58-dd94-4c4b-9bb3-d8eb1b3bcb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504523774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1504523774 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.183252518 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 50302652651 ps |
| CPU time | 859.21 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 08:06:56 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-30f6923b-386a-435a-9596-cb614db0e08e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183252518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.183252518 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.76644969 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 447269895 ps |
| CPU time | 40.79 seconds |
| Started | Jul 22 07:52:32 PM PDT 24 |
| Finished | Jul 22 07:53:15 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-1d694a09-078b-4ad5-9316-05dff4918c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76644969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delay s.76644969 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.923220061 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 1065477997 ps |
| CPU time | 34.2 seconds |
| Started | Jul 22 07:52:44 PM PDT 24 |
| Finished | Jul 22 07:53:19 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-7fe613b0-3d8f-4793-9e22-e7d805f0dff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923220061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.923220061 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1363341262 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 51593838 ps |
| CPU time | 6.88 seconds |
| Started | Jul 22 07:52:33 PM PDT 24 |
| Finished | Jul 22 07:52:43 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-dc89bf4b-85c1-4dc7-a76d-9819d67f2e5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363341262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1363341262 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.144379065 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 9737517249 ps |
| CPU time | 99.48 seconds |
| Started | Jul 22 07:52:33 PM PDT 24 |
| Finished | Jul 22 07:54:15 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-457e1ff2-3855-4e50-ac18-9401f5f9cc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144379065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.144379065 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.882830349 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 4821233647 ps |
| CPU time | 84.3 seconds |
| Started | Jul 22 07:52:36 PM PDT 24 |
| Finished | Jul 22 07:54:04 PM PDT 24 |
| Peak memory | 574824 kb |
| Host | smart-01c08239-407b-4703-85d4-70dcba818d06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882830349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.882830349 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.765054549 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 48461811 ps |
| CPU time | 6.3 seconds |
| Started | Jul 22 07:52:34 PM PDT 24 |
| Finished | Jul 22 07:52:42 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-0f5f63a2-38a5-409e-8d3e-8d8ef4b2c134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765054549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays .765054549 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3442631298 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 3076172599 ps |
| CPU time | 105.22 seconds |
| Started | Jul 22 07:52:45 PM PDT 24 |
| Finished | Jul 22 07:54:31 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-778a8852-3c8c-4cd8-bf2b-b4276ef51ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442631298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3442631298 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2124560105 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 9841230673 ps |
| CPU time | 362.21 seconds |
| Started | Jul 22 07:52:44 PM PDT 24 |
| Finished | Jul 22 07:58:47 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-d043e538-20dc-467f-a694-df243b9764da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124560105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2124560105 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2247136294 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 255860784 ps |
| CPU time | 67.03 seconds |
| Started | Jul 22 07:52:45 PM PDT 24 |
| Finished | Jul 22 07:53:53 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-0d56fd42-73ef-4f6a-8c33-e7768c904b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247136294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.2247136294 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1510117848 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 631959243 ps |
| CPU time | 164.76 seconds |
| Started | Jul 22 07:52:46 PM PDT 24 |
| Finished | Jul 22 07:55:32 PM PDT 24 |
| Peak memory | 577020 kb |
| Host | smart-5f368afd-fa2e-435c-ac47-c245adb15a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510117848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1510117848 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3601630108 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 168830951 ps |
| CPU time | 21.77 seconds |
| Started | Jul 22 07:52:44 PM PDT 24 |
| Finished | Jul 22 07:53:07 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-f307167b-da07-4dc1-8780-53869545588e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601630108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3601630108 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1893350635 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 533443225 ps |
| CPU time | 60.32 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 07:53:55 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-2aa55bbe-5c0d-48c4-96ce-329982871b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893350635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .1893350635 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2368535711 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 87473256233 ps |
| CPU time | 1560.16 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 08:18:55 PM PDT 24 |
| Peak memory | 576948 kb |
| Host | smart-ff41f777-8aa8-4987-a677-cd57e22b7ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368535711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.2368535711 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2470003747 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 858565868 ps |
| CPU time | 32.89 seconds |
| Started | Jul 22 07:53:23 PM PDT 24 |
| Finished | Jul 22 07:53:58 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-c1edf79f-3599-4f84-a364-277cf9f7ef62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470003747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.2470003747 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.2999986166 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 364974844 ps |
| CPU time | 33.17 seconds |
| Started | Jul 22 07:52:55 PM PDT 24 |
| Finished | Jul 22 07:53:30 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-65a906f0-7999-465a-93d1-c01ef9ffbc9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999986166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2999986166 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1943810443 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 495089079 ps |
| CPU time | 22.06 seconds |
| Started | Jul 22 07:52:45 PM PDT 24 |
| Finished | Jul 22 07:53:08 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-cddf1e80-469f-42f8-9331-ca5b0964b14c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943810443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1943810443 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.411653950 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 43828407329 ps |
| CPU time | 417.43 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 07:59:52 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-1546e240-dc32-49b4-97bf-6c653f827b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411653950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.411653950 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1015239617 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 44920017759 ps |
| CPU time | 760.27 seconds |
| Started | Jul 22 07:52:55 PM PDT 24 |
| Finished | Jul 22 08:05:37 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-987cc2ef-8ea6-4320-9b0f-d22015f976f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015239617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1015239617 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.2150451424 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 256880783 ps |
| CPU time | 24.91 seconds |
| Started | Jul 22 07:52:46 PM PDT 24 |
| Finished | Jul 22 07:53:12 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-d6ea494e-1e9d-4385-a5df-2e7864361770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150451424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.2150451424 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1669207229 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 1565246905 ps |
| CPU time | 44.72 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 07:53:39 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-e4edd325-d9dc-41c7-95c8-d5757355bd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669207229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1669207229 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.89137268 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 51932766 ps |
| CPU time | 7 seconds |
| Started | Jul 22 07:52:46 PM PDT 24 |
| Finished | Jul 22 07:52:53 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-2c076ee0-8b90-4d7f-a52a-91b8d6d9db82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89137268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.89137268 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.3138511843 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 7469460636 ps |
| CPU time | 76.41 seconds |
| Started | Jul 22 07:52:44 PM PDT 24 |
| Finished | Jul 22 07:54:02 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-c7ea56cf-4ad6-46b6-b87d-25656c2bb0cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138511843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3138511843 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2244283602 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 4211611191 ps |
| CPU time | 67.2 seconds |
| Started | Jul 22 07:52:47 PM PDT 24 |
| Finished | Jul 22 07:53:55 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-65888cd9-578f-4a35-9166-720d6bff481b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244283602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2244283602 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2623020339 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 39674842 ps |
| CPU time | 6.05 seconds |
| Started | Jul 22 07:52:44 PM PDT 24 |
| Finished | Jul 22 07:52:51 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-4a82944f-cb99-4413-8fa4-88c230cc1f84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623020339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2623020339 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.432718619 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 12741247048 ps |
| CPU time | 355.05 seconds |
| Started | Jul 22 07:55:01 PM PDT 24 |
| Finished | Jul 22 08:00:58 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-0783ee82-5204-4e2e-817d-cf77268c5330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432718619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.432718619 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3177500037 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 7330026708 ps |
| CPU time | 228.97 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 07:56:44 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-95ec5067-99d4-4c81-a81b-48be50dc76bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177500037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3177500037 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2924551172 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 141417807 ps |
| CPU time | 38.94 seconds |
| Started | Jul 22 07:52:54 PM PDT 24 |
| Finished | Jul 22 07:53:35 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-424b45a3-4c50-48c4-809e-f63a70ad518b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924551172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2924551172 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.4024933327 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 219138023 ps |
| CPU time | 85.94 seconds |
| Started | Jul 22 07:52:55 PM PDT 24 |
| Finished | Jul 22 07:54:22 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-9073c210-2493-4815-9d6f-db1d3501da64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024933327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.4024933327 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3709806613 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 235467390 ps |
| CPU time | 31.82 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 07:53:27 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-4aa401e2-19aa-4824-aa76-6d22f7780c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709806613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3709806613 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1880285582 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 31008016600 ps |
| CPU time | 5342.57 seconds |
| Started | Jul 22 07:42:27 PM PDT 24 |
| Finished | Jul 22 09:11:30 PM PDT 24 |
| Peak memory | 594676 kb |
| Host | smart-574f15d8-2935-44d8-841f-0adde708de6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880285582 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.1880285582 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3625613568 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 3809928740 ps |
| CPU time | 337.63 seconds |
| Started | Jul 22 07:42:20 PM PDT 24 |
| Finished | Jul 22 07:47:58 PM PDT 24 |
| Peak memory | 593668 kb |
| Host | smart-0c2c921e-10a9-4bf3-a15f-677f71a07e5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625613568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3625613568 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2984169601 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 5507070603 ps |
| CPU time | 219.99 seconds |
| Started | Jul 22 07:42:40 PM PDT 24 |
| Finished | Jul 22 07:46:21 PM PDT 24 |
| Peak memory | 664148 kb |
| Host | smart-2b779dc1-a218-4ff6-bc27-7bc2f4d1af2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984169601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.2984169601 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.2167340785 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5847219825 ps |
| CPU time | 563.71 seconds |
| Started | Jul 22 07:42:40 PM PDT 24 |
| Finished | Jul 22 07:52:04 PM PDT 24 |
| Peak memory | 599456 kb |
| Host | smart-7a8a7cc1-29b1-4921-a71f-376e8f70cb3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167340785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2167340785 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2825610067 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 30571889884 ps |
| CPU time | 4673.92 seconds |
| Started | Jul 22 07:42:36 PM PDT 24 |
| Finished | Jul 22 09:00:31 PM PDT 24 |
| Peak memory | 593892 kb |
| Host | smart-5884723f-cbfe-42e8-8466-175ab9ff6b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825610067 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2825610067 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.3965157180 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3781542327 ps |
| CPU time | 218.79 seconds |
| Started | Jul 22 07:42:21 PM PDT 24 |
| Finished | Jul 22 07:46:01 PM PDT 24 |
| Peak memory | 600312 kb |
| Host | smart-d4609976-a09c-44dd-8487-1959c81d5ba0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965157180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.3965157180 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.357967021 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 343094745 ps |
| CPU time | 35.05 seconds |
| Started | Jul 22 07:42:32 PM PDT 24 |
| Finished | Jul 22 07:43:08 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-b939e4a4-37b9-4261-8da8-dde89177aab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357967021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.357967021 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2441926127 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 104646739620 ps |
| CPU time | 1672.02 seconds |
| Started | Jul 22 07:42:45 PM PDT 24 |
| Finished | Jul 22 08:10:38 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-e5639bf4-a51d-4917-8790-e6b7928458b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441926127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.2441926127 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1222806953 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 70599133 ps |
| CPU time | 9.99 seconds |
| Started | Jul 22 07:42:33 PM PDT 24 |
| Finished | Jul 22 07:42:43 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-ee0cc99c-4960-441d-bf48-3842f9553544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222806953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1222806953 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.1395647980 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 1689179853 ps |
| CPU time | 56.14 seconds |
| Started | Jul 22 07:42:39 PM PDT 24 |
| Finished | Jul 22 07:43:36 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-f770ab94-9b57-4f94-856b-7c728cea417e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395647980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1395647980 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.1120016173 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 392688625 ps |
| CPU time | 34.5 seconds |
| Started | Jul 22 07:42:29 PM PDT 24 |
| Finished | Jul 22 07:43:04 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-b929ac55-9d4a-4fe5-a64b-9b31defdf483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120016173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1120016173 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.970989240 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 49049009504 ps |
| CPU time | 479.41 seconds |
| Started | Jul 22 07:42:32 PM PDT 24 |
| Finished | Jul 22 07:50:32 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-166b1edc-f053-4b6f-a4d1-7152782d9dd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970989240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.970989240 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1161968278 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 13169499072 ps |
| CPU time | 220.61 seconds |
| Started | Jul 22 07:42:39 PM PDT 24 |
| Finished | Jul 22 07:46:21 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-432d7e55-64b3-4cc8-a8c6-ed937e03d1bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161968278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1161968278 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2897887043 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 233327279 ps |
| CPU time | 23.2 seconds |
| Started | Jul 22 07:43:01 PM PDT 24 |
| Finished | Jul 22 07:43:25 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-73ca264e-52e6-4011-90f4-77fc0c210eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897887043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.2897887043 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.182756920 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 749317915 ps |
| CPU time | 21.89 seconds |
| Started | Jul 22 07:42:43 PM PDT 24 |
| Finished | Jul 22 07:43:05 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-879c91fd-ae87-4578-9abe-90c3aa092eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182756920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.182756920 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.3569242854 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 228138440 ps |
| CPU time | 10.5 seconds |
| Started | Jul 22 07:42:21 PM PDT 24 |
| Finished | Jul 22 07:42:32 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-4c215f9e-0145-4dbf-85e4-3c5bfc994beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569242854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3569242854 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1812138423 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 7244654418 ps |
| CPU time | 77.96 seconds |
| Started | Jul 22 07:42:50 PM PDT 24 |
| Finished | Jul 22 07:44:09 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-a98b7b92-0bc2-47d3-a65d-d2bae8196a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812138423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1812138423 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.1500245741 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 4699090254 ps |
| CPU time | 83.32 seconds |
| Started | Jul 22 07:42:50 PM PDT 24 |
| Finished | Jul 22 07:44:14 PM PDT 24 |
| Peak memory | 574824 kb |
| Host | smart-f4e79791-398c-4f20-9295-1bedb00affd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500245741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1500245741 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2635971858 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 49774135 ps |
| CPU time | 6.26 seconds |
| Started | Jul 22 07:43:00 PM PDT 24 |
| Finished | Jul 22 07:43:06 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-71a182a1-6223-44c9-b0ce-c19df430c28b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635971858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2635971858 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.4104940030 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 15955082021 ps |
| CPU time | 619.23 seconds |
| Started | Jul 22 07:42:33 PM PDT 24 |
| Finished | Jul 22 07:52:53 PM PDT 24 |
| Peak memory | 577008 kb |
| Host | smart-611b5e8b-befa-4e81-a124-6ee3b8d0c668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104940030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4104940030 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3130223437 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 1207343658 ps |
| CPU time | 108.63 seconds |
| Started | Jul 22 07:42:44 PM PDT 24 |
| Finished | Jul 22 07:44:34 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-83defab1-aebe-428b-9c9b-94e8d6e3f56f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130223437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3130223437 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1898701043 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 7946262011 ps |
| CPU time | 571.29 seconds |
| Started | Jul 22 07:43:47 PM PDT 24 |
| Finished | Jul 22 07:53:21 PM PDT 24 |
| Peak memory | 577008 kb |
| Host | smart-f18f3a05-fc50-43ee-9884-8f48adb67637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898701043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1898701043 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3732207616 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 40908553 ps |
| CPU time | 8.14 seconds |
| Started | Jul 22 07:42:40 PM PDT 24 |
| Finished | Jul 22 07:42:48 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-41882d51-7dd6-4d7f-92a7-44bef9d1af7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732207616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.3732207616 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.205166226 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 254287197 ps |
| CPU time | 26.36 seconds |
| Started | Jul 22 07:42:42 PM PDT 24 |
| Finished | Jul 22 07:43:09 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-b80c5a3b-9d03-40b9-bc1e-889c364e4cd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205166226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.205166226 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3250901184 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 587824515 ps |
| CPU time | 20.79 seconds |
| Started | Jul 22 07:55:01 PM PDT 24 |
| Finished | Jul 22 07:55:23 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-c6b3444c-adf5-4f60-b681-73545d7b205f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250901184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3250901184 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2800920656 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 64306252495 ps |
| CPU time | 1032.97 seconds |
| Started | Jul 22 07:54:17 PM PDT 24 |
| Finished | Jul 22 08:11:32 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-c7f1103e-a74d-4b4f-8f36-bbebc8a5fae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800920656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.2800920656 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.4041272277 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 171710419 ps |
| CPU time | 18.75 seconds |
| Started | Jul 22 07:53:00 PM PDT 24 |
| Finished | Jul 22 07:53:20 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-ce37ddd8-7adf-4398-8d7f-5dea2e7f2624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041272277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.4041272277 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.866275154 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 56104008 ps |
| CPU time | 7.68 seconds |
| Started | Jul 22 07:53:02 PM PDT 24 |
| Finished | Jul 22 07:53:11 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-76feb22c-e0be-44aa-8c83-620372a122ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866275154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.866275154 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1175068346 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1144396883 ps |
| CPU time | 40.11 seconds |
| Started | Jul 22 07:52:57 PM PDT 24 |
| Finished | Jul 22 07:53:39 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-63894c68-cd54-4b82-8272-fe12a6dc98d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175068346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1175068346 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3574601667 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 55116412311 ps |
| CPU time | 530.97 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 08:01:46 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-c52f31d3-6183-4cfc-b717-dc016cbdcdb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574601667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3574601667 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.3577553669 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 59786102010 ps |
| CPU time | 1021.1 seconds |
| Started | Jul 22 07:52:52 PM PDT 24 |
| Finished | Jul 22 08:09:55 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-2bb4b8eb-a3f0-48d7-9e58-6518f9f330e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577553669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3577553669 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1463468409 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 337711282 ps |
| CPU time | 27.97 seconds |
| Started | Jul 22 07:55:00 PM PDT 24 |
| Finished | Jul 22 07:55:30 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-d8e77b3e-fd72-4d7c-a7f8-886945765e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463468409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1463468409 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.1912110504 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 186040668 ps |
| CPU time | 16.63 seconds |
| Started | Jul 22 07:53:04 PM PDT 24 |
| Finished | Jul 22 07:53:21 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ab5768cb-5c9f-4344-8e22-e28c10bf8944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912110504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1912110504 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.963121569 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 179023724 ps |
| CPU time | 9.07 seconds |
| Started | Jul 22 07:52:53 PM PDT 24 |
| Finished | Jul 22 07:53:04 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-c88f988e-efc1-4c25-8101-79603604b46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963121569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.963121569 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2768900236 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 8326000410 ps |
| CPU time | 85.66 seconds |
| Started | Jul 22 07:52:54 PM PDT 24 |
| Finished | Jul 22 07:54:21 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-66cc5813-a9c6-4800-acf3-35a582486b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768900236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2768900236 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.607062887 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 3738860034 ps |
| CPU time | 62.75 seconds |
| Started | Jul 22 07:52:56 PM PDT 24 |
| Finished | Jul 22 07:54:01 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-f99f9d36-134c-4971-93bf-717099cffec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607062887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.607062887 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.156825776 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 44831101 ps |
| CPU time | 6.29 seconds |
| Started | Jul 22 07:53:22 PM PDT 24 |
| Finished | Jul 22 07:53:31 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-d5a118e6-a190-4931-a64a-30f42bf75c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156825776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays .156825776 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3468231690 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 8426846360 ps |
| CPU time | 310.28 seconds |
| Started | Jul 22 07:53:01 PM PDT 24 |
| Finished | Jul 22 07:58:12 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-f245d673-285d-4e53-bdfb-d2380e3a914a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468231690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3468231690 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.3846482761 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 1019802660 ps |
| CPU time | 90.24 seconds |
| Started | Jul 22 07:53:02 PM PDT 24 |
| Finished | Jul 22 07:54:34 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-06842547-3168-47a8-9f1f-26552712d40c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846482761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3846482761 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3206994158 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 269787329 ps |
| CPU time | 74.44 seconds |
| Started | Jul 22 07:53:02 PM PDT 24 |
| Finished | Jul 22 07:54:17 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-b56c6703-9a29-4f2e-8af8-fe61996a18ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206994158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.3206994158 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3086942446 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 851049439 ps |
| CPU time | 251.84 seconds |
| Started | Jul 22 07:53:03 PM PDT 24 |
| Finished | Jul 22 07:57:16 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-3fecf591-f858-4605-a498-274fde1540e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086942446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3086942446 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.1784130736 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 138568359 ps |
| CPU time | 19.04 seconds |
| Started | Jul 22 07:53:01 PM PDT 24 |
| Finished | Jul 22 07:53:21 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-f5b69414-1019-44e9-98d8-0d8b5d2909c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784130736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1784130736 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.575137852 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 1731545815 ps |
| CPU time | 86.91 seconds |
| Started | Jul 22 07:53:12 PM PDT 24 |
| Finished | Jul 22 07:54:41 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-dccae09c-31c1-4a17-99f8-068dc2566bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575137852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 575137852 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.3560738271 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 31243778918 ps |
| CPU time | 533.62 seconds |
| Started | Jul 22 07:53:11 PM PDT 24 |
| Finished | Jul 22 08:02:06 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-b1ea959d-8640-4b14-9a95-bc81134420ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560738271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.3560738271 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.772273391 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 269000345 ps |
| CPU time | 13.52 seconds |
| Started | Jul 22 07:53:15 PM PDT 24 |
| Finished | Jul 22 07:53:30 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-7bc31a77-8507-4d00-a32e-e50c34372ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772273391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr .772273391 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.2236855018 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 505350350 ps |
| CPU time | 38.35 seconds |
| Started | Jul 22 07:53:12 PM PDT 24 |
| Finished | Jul 22 07:53:51 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-396483bd-36cf-4e21-896d-88aa643dd906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236855018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2236855018 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.3177614836 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 1945178465 ps |
| CPU time | 64.88 seconds |
| Started | Jul 22 07:53:03 PM PDT 24 |
| Finished | Jul 22 07:54:09 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-81d443c1-3a62-495f-af54-b81b716759d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177614836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3177614836 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2265065216 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 80559281446 ps |
| CPU time | 860.84 seconds |
| Started | Jul 22 07:53:03 PM PDT 24 |
| Finished | Jul 22 08:07:25 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-779753cb-5cf1-4393-add7-da113a621d07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265065216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2265065216 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2006148011 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 49721763101 ps |
| CPU time | 894.79 seconds |
| Started | Jul 22 07:53:01 PM PDT 24 |
| Finished | Jul 22 08:07:58 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-4854c6bb-d6d5-43f7-9b2c-44fccdebc401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006148011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2006148011 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.670199347 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 435308296 ps |
| CPU time | 40.77 seconds |
| Started | Jul 22 07:53:02 PM PDT 24 |
| Finished | Jul 22 07:53:44 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-5c9a6a9d-96b0-4d94-a6da-711878a2f2ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670199347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela ys.670199347 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.3685640646 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 992136607 ps |
| CPU time | 30.87 seconds |
| Started | Jul 22 07:53:11 PM PDT 24 |
| Finished | Jul 22 07:53:44 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-36ce9b85-774e-40d0-b9dc-bc04378776d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685640646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3685640646 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.2529747781 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 42208320 ps |
| CPU time | 5.93 seconds |
| Started | Jul 22 07:53:06 PM PDT 24 |
| Finished | Jul 22 07:53:12 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-2aa19930-fab4-4aaf-b6aa-e40e9421b072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529747781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2529747781 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3116018550 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 6775054174 ps |
| CPU time | 73.09 seconds |
| Started | Jul 22 07:53:01 PM PDT 24 |
| Finished | Jul 22 07:54:16 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-2301b47c-c856-4c05-933a-6754beef9bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116018550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3116018550 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2590723447 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5052138466 ps |
| CPU time | 88.93 seconds |
| Started | Jul 22 07:53:04 PM PDT 24 |
| Finished | Jul 22 07:54:34 PM PDT 24 |
| Peak memory | 574856 kb |
| Host | smart-cd1995f7-a6ec-4ccc-aabe-76325741c5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590723447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2590723447 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4294156394 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 36768687 ps |
| CPU time | 6.23 seconds |
| Started | Jul 22 07:53:01 PM PDT 24 |
| Finished | Jul 22 07:53:08 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-9879e95b-51cb-4f97-9444-20ffabd15eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294156394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.4294156394 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.842986640 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1154378156 ps |
| CPU time | 41.74 seconds |
| Started | Jul 22 07:53:12 PM PDT 24 |
| Finished | Jul 22 07:53:55 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-eea3c465-06df-4d2b-9647-a2b9d68f232b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842986640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.842986640 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2595932921 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 7662932261 ps |
| CPU time | 247.85 seconds |
| Started | Jul 22 07:54:06 PM PDT 24 |
| Finished | Jul 22 07:58:16 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-27528431-b7cf-482f-a3e7-d99bace2b898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595932921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2595932921 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1958710487 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 2619340592 ps |
| CPU time | 233.93 seconds |
| Started | Jul 22 07:53:12 PM PDT 24 |
| Finished | Jul 22 07:57:08 PM PDT 24 |
| Peak memory | 577032 kb |
| Host | smart-525ccaec-6dd5-4f44-a0d3-a840b2a2b170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958710487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1958710487 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.828045597 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 185017878 ps |
| CPU time | 10.12 seconds |
| Started | Jul 22 07:53:15 PM PDT 24 |
| Finished | Jul 22 07:53:27 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-677b0286-1741-4938-8b8f-60f990766b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828045597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.828045597 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3070277710 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1034009695 ps |
| CPU time | 36.93 seconds |
| Started | Jul 22 07:53:22 PM PDT 24 |
| Finished | Jul 22 07:54:01 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-3829e317-e31c-435a-a0b4-5ea591c8080d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070277710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .3070277710 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.911416623 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 109178141213 ps |
| CPU time | 1913.98 seconds |
| Started | Jul 22 07:53:22 PM PDT 24 |
| Finished | Jul 22 08:25:18 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-25b9f2aa-4d39-4ed9-9370-8e7dfe089acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911416623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.911416623 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3735805299 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 780862762 ps |
| CPU time | 36.36 seconds |
| Started | Jul 22 07:53:34 PM PDT 24 |
| Finished | Jul 22 07:54:12 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-7e9d6dec-00b9-4542-873e-59adca54e14d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735805299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3735805299 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.3120572499 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 1072166352 ps |
| CPU time | 33.5 seconds |
| Started | Jul 22 07:53:35 PM PDT 24 |
| Finished | Jul 22 07:54:10 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-b1a2dd6c-3d39-4f82-b58d-1961ffd33046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120572499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3120572499 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.421576686 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 2178822426 ps |
| CPU time | 76.88 seconds |
| Started | Jul 22 07:54:35 PM PDT 24 |
| Finished | Jul 22 07:55:55 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-4f41fe88-9cc6-45e9-b344-c1d9f5773c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421576686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.421576686 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3338848528 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 44196517692 ps |
| CPU time | 443.77 seconds |
| Started | Jul 22 07:53:24 PM PDT 24 |
| Finished | Jul 22 08:00:49 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-9646b666-7777-444e-a5cd-8538c6e403b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338848528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3338848528 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.542239858 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 32432055056 ps |
| CPU time | 531.55 seconds |
| Started | Jul 22 07:53:24 PM PDT 24 |
| Finished | Jul 22 08:02:17 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-4939950d-d8a6-4a8d-b2c3-4bebf05a538c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542239858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.542239858 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.4068205709 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 583140078 ps |
| CPU time | 48 seconds |
| Started | Jul 22 07:53:25 PM PDT 24 |
| Finished | Jul 22 07:54:14 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-9855a3f7-932a-47ba-acc2-2d83889e4c49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068205709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.4068205709 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2732261974 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 140715574 ps |
| CPU time | 11.21 seconds |
| Started | Jul 22 07:53:27 PM PDT 24 |
| Finished | Jul 22 07:53:39 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-8d68aade-2790-4f8c-a243-725b7276c03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732261974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2732261974 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1637518420 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 193462096 ps |
| CPU time | 8.6 seconds |
| Started | Jul 22 07:53:23 PM PDT 24 |
| Finished | Jul 22 07:53:33 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-fd29dbb2-bf77-49c2-af12-8e84c85a19ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637518420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1637518420 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1026450708 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 7729446148 ps |
| CPU time | 83 seconds |
| Started | Jul 22 07:53:22 PM PDT 24 |
| Finished | Jul 22 07:54:47 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-b6732c70-4bdf-4216-8ca7-fcfdebd15527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026450708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1026450708 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.743698795 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 5712218769 ps |
| CPU time | 90.69 seconds |
| Started | Jul 22 07:54:28 PM PDT 24 |
| Finished | Jul 22 07:56:01 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-4b7ecfcd-58e6-4373-b214-fd81da54402e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743698795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.743698795 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3662258998 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 40765795 ps |
| CPU time | 6.39 seconds |
| Started | Jul 22 07:53:23 PM PDT 24 |
| Finished | Jul 22 07:53:31 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-b1f16f28-0195-4e2c-b7dd-8b6fd7e999a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662258998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.3662258998 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2401888900 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 15952764157 ps |
| CPU time | 533.13 seconds |
| Started | Jul 22 07:53:35 PM PDT 24 |
| Finished | Jul 22 08:02:30 PM PDT 24 |
| Peak memory | 577032 kb |
| Host | smart-30bbe7c7-3a57-4323-bfe0-d325a781de8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401888900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2401888900 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.802755980 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 4032010424 ps |
| CPU time | 553.74 seconds |
| Started | Jul 22 07:53:33 PM PDT 24 |
| Finished | Jul 22 08:02:48 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-1dd870fd-b730-4f9a-8fea-bad250f70434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802755980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_ with_rand_reset.802755980 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2359062464 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 8648644044 ps |
| CPU time | 403.1 seconds |
| Started | Jul 22 07:53:33 PM PDT 24 |
| Finished | Jul 22 08:00:17 PM PDT 24 |
| Peak memory | 577104 kb |
| Host | smart-8d6ac33a-ae99-4b6c-82c9-a33baf262b92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359062464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2359062464 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3807813640 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 543018120 ps |
| CPU time | 21.1 seconds |
| Started | Jul 22 07:53:32 PM PDT 24 |
| Finished | Jul 22 07:53:54 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-f32d103f-d3e3-404f-b835-74bf2b21efd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807813640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3807813640 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.2029782028 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1105672819 ps |
| CPU time | 51.93 seconds |
| Started | Jul 22 07:53:34 PM PDT 24 |
| Finished | Jul 22 07:54:27 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-b4cc1b05-39bc-4bf1-aa26-79df78bec822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029782028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2029782028 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3401872761 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 120386202135 ps |
| CPU time | 2231.33 seconds |
| Started | Jul 22 07:53:37 PM PDT 24 |
| Finished | Jul 22 08:30:51 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-749a8083-733a-4b76-ada6-c21e5d99c8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401872761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.3401872761 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1713676459 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 262152149 ps |
| CPU time | 30.98 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 07:55:09 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-82389b84-9633-4e12-90d2-9e552464f0e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713676459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1713676459 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.4196274887 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 2116841669 ps |
| CPU time | 64.84 seconds |
| Started | Jul 22 07:54:40 PM PDT 24 |
| Finished | Jul 22 07:55:48 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f43c2758-7b92-4faf-8eef-024d6157b58e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196274887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.4196274887 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.3706595436 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 183724222 ps |
| CPU time | 10.41 seconds |
| Started | Jul 22 07:53:35 PM PDT 24 |
| Finished | Jul 22 07:53:47 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-51dd62f3-f524-482c-8e26-506d349f3932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706595436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3706595436 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2047895172 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 50252353381 ps |
| CPU time | 546.36 seconds |
| Started | Jul 22 07:53:34 PM PDT 24 |
| Finished | Jul 22 08:02:42 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-17a098ab-3128-4890-b62d-37504ba9479b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047895172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2047895172 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2362743683 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 13572313515 ps |
| CPU time | 215.81 seconds |
| Started | Jul 22 07:53:34 PM PDT 24 |
| Finished | Jul 22 07:57:12 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-4c81b898-4a74-42cb-bc82-a7b23906ed43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362743683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2362743683 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.600937623 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 198678128 ps |
| CPU time | 20.12 seconds |
| Started | Jul 22 07:53:34 PM PDT 24 |
| Finished | Jul 22 07:53:56 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-0a4bed22-de92-44b1-9e80-56282196b109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600937623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_dela ys.600937623 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.78576883 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 1896814815 ps |
| CPU time | 58.07 seconds |
| Started | Jul 22 07:53:36 PM PDT 24 |
| Finished | Jul 22 07:54:38 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-9a39af26-5cba-4f1d-9fb8-fa818995c94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78576883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.78576883 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.2630446002 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 190558562 ps |
| CPU time | 8.94 seconds |
| Started | Jul 22 07:53:33 PM PDT 24 |
| Finished | Jul 22 07:53:43 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-34aacaae-50fe-4d9d-8e2c-065d0815dffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630446002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2630446002 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1800770126 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 8114801485 ps |
| CPU time | 87.25 seconds |
| Started | Jul 22 07:53:32 PM PDT 24 |
| Finished | Jul 22 07:55:01 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-cfe9ade6-7ad4-4467-9158-164e7e28681b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800770126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1800770126 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1738886695 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 4644071926 ps |
| CPU time | 82.57 seconds |
| Started | Jul 22 07:53:35 PM PDT 24 |
| Finished | Jul 22 07:54:59 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-fea0aefd-a543-4173-8c24-9caa6c43ad36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738886695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.1738886695 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2699114351 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 45393633 ps |
| CPU time | 5.51 seconds |
| Started | Jul 22 07:54:39 PM PDT 24 |
| Finished | Jul 22 07:54:47 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-1ee7846b-7a34-4176-8529-0fba3e0db463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699114351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2699114351 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.969146312 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 10681524848 ps |
| CPU time | 326.65 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 07:59:19 PM PDT 24 |
| Peak memory | 576956 kb |
| Host | smart-3d291071-f186-4b43-a207-f369ff8623c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969146312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.969146312 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.301447432 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 2627586791 ps |
| CPU time | 196.7 seconds |
| Started | Jul 22 07:53:44 PM PDT 24 |
| Finished | Jul 22 07:57:04 PM PDT 24 |
| Peak memory | 576988 kb |
| Host | smart-be9f3d74-e6da-4bce-b58e-6f78ca12a374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301447432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.301447432 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.517761947 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 7016005782 ps |
| CPU time | 441.81 seconds |
| Started | Jul 22 07:53:45 PM PDT 24 |
| Finished | Jul 22 08:01:11 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-e17b5e23-0a0d-4185-8d24-e63d3274ac29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517761947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.517761947 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.4261542312 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 1346957533 ps |
| CPU time | 54.44 seconds |
| Started | Jul 22 07:53:35 PM PDT 24 |
| Finished | Jul 22 07:54:32 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-908c3d4b-163c-4e5e-8d3e-468635f3ff6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261542312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.4261542312 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2632160496 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 1190360578 ps |
| CPU time | 40.23 seconds |
| Started | Jul 22 07:53:53 PM PDT 24 |
| Finished | Jul 22 07:54:34 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-5c1d4586-09ba-4629-80f3-8b3a6460f3a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632160496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .2632160496 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2351663982 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 18239266197 ps |
| CPU time | 330.68 seconds |
| Started | Jul 22 07:53:46 PM PDT 24 |
| Finished | Jul 22 07:59:20 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-aac0af03-a47c-4500-a91b-e40c454c87f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351663982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2351663982 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2999017650 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1400864673 ps |
| CPU time | 54.33 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 07:54:59 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-0cb27ccf-ba68-4ef3-8843-974249680ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999017650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.2999017650 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.472859778 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1611931862 ps |
| CPU time | 54.57 seconds |
| Started | Jul 22 07:53:53 PM PDT 24 |
| Finished | Jul 22 07:54:49 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-7f56c515-6442-48aa-950f-c8c51d9c42c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472859778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.472859778 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.2616855044 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 783769739 ps |
| CPU time | 28.8 seconds |
| Started | Jul 22 07:53:42 PM PDT 24 |
| Finished | Jul 22 07:54:11 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-4a0649a4-f4bf-4ba8-8ce0-745bec69aa03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616855044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2616855044 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3752409093 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 49123621303 ps |
| CPU time | 482.5 seconds |
| Started | Jul 22 07:54:25 PM PDT 24 |
| Finished | Jul 22 08:02:29 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-2ad235b5-06cd-4e48-8e0b-edc8bfb30f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752409093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3752409093 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2282358315 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 23661062135 ps |
| CPU time | 387.4 seconds |
| Started | Jul 22 07:54:05 PM PDT 24 |
| Finished | Jul 22 08:00:34 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-28bc1be2-ec05-4df7-970c-4763ed113b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282358315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2282358315 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3052009432 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 104664958 ps |
| CPU time | 12.8 seconds |
| Started | Jul 22 07:53:43 PM PDT 24 |
| Finished | Jul 22 07:53:58 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-a435ac06-59fd-4187-b83f-20508b6e0210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052009432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3052009432 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.2982448329 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 467368877 ps |
| CPU time | 33.42 seconds |
| Started | Jul 22 07:53:42 PM PDT 24 |
| Finished | Jul 22 07:54:17 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-dc8ed648-68d9-46c8-b8f0-1e352557f145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982448329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2982448329 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3850059473 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 165265886 ps |
| CPU time | 8.6 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 07:54:03 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-f7379ce8-b886-4dc7-a6aa-42f4d17695df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850059473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3850059473 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.4065957046 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 8188827509 ps |
| CPU time | 86.74 seconds |
| Started | Jul 22 07:53:45 PM PDT 24 |
| Finished | Jul 22 07:55:15 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-c2aa256a-e2f8-4985-81ab-fa824b780ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065957046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.4065957046 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1467997964 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 4991158730 ps |
| CPU time | 87.43 seconds |
| Started | Jul 22 07:53:46 PM PDT 24 |
| Finished | Jul 22 07:55:16 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-37bc799f-9cd8-421e-a44a-a005aeb85180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467997964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1467997964 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1271814513 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 40642492 ps |
| CPU time | 6.3 seconds |
| Started | Jul 22 07:53:43 PM PDT 24 |
| Finished | Jul 22 07:53:50 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-fcf97a92-1227-45f4-836e-a5a47bb5f4d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271814513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1271814513 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2057088671 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 6771875253 ps |
| CPU time | 254.53 seconds |
| Started | Jul 22 07:54:02 PM PDT 24 |
| Finished | Jul 22 07:58:18 PM PDT 24 |
| Peak memory | 577124 kb |
| Host | smart-daa93119-42ce-44ab-abfa-6a5ec671190f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057088671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2057088671 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2325091711 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 5442159728 ps |
| CPU time | 211.03 seconds |
| Started | Jul 22 07:53:55 PM PDT 24 |
| Finished | Jul 22 07:57:27 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-4a88e600-003e-41f6-aa9c-0d6c828bd742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325091711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2325091711 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.56978829 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 3660069650 ps |
| CPU time | 503.5 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 08:02:17 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-f80b32b2-469b-4a9f-a418-7651370db283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56978829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_w ith_rand_reset.56978829 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.4032988406 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1146222038 ps |
| CPU time | 241.4 seconds |
| Started | Jul 22 07:53:51 PM PDT 24 |
| Finished | Jul 22 07:57:54 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-95e55674-4568-4a8c-a506-19e52f007693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032988406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.4032988406 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3556758878 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 916298391 ps |
| CPU time | 35.41 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 07:54:29 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-c9914887-64f6-46f1-bd0b-8c488ca28b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556758878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3556758878 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1098917367 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 828721348 ps |
| CPU time | 63.81 seconds |
| Started | Jul 22 07:54:03 PM PDT 24 |
| Finished | Jul 22 07:55:07 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-00fe6b09-ccfa-48f0-8945-c83c71fb8f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098917367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .1098917367 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2848164956 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 25782252079 ps |
| CPU time | 436.06 seconds |
| Started | Jul 22 07:53:53 PM PDT 24 |
| Finished | Jul 22 08:01:11 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-e6214345-4737-4a1b-b0e5-29843a3732fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848164956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.2848164956 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.379767849 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 147456280 ps |
| CPU time | 19.04 seconds |
| Started | Jul 22 07:54:02 PM PDT 24 |
| Finished | Jul 22 07:54:22 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-cc034fcf-82fd-40db-b290-79b64a4a9ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379767849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr .379767849 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3534522025 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 88824832 ps |
| CPU time | 9.67 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 07:54:16 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-be0027e3-a7a7-40c2-b54d-7b2a02926f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534522025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3534522025 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.533703831 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 579499318 ps |
| CPU time | 47.34 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 07:54:41 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-54be45c9-ce29-437f-8209-7683faea5005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533703831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.533703831 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.538701054 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 56862452442 ps |
| CPU time | 581.3 seconds |
| Started | Jul 22 07:53:53 PM PDT 24 |
| Finished | Jul 22 08:03:36 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-3215bed8-c4f7-403e-858a-97ec45f7c3e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538701054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.538701054 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.538296386 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 32774936739 ps |
| CPU time | 547.27 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 08:03:00 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-899a96c6-81f9-419f-bd38-cb356a5a96f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538296386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.538296386 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.168585806 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 436327590 ps |
| CPU time | 35.4 seconds |
| Started | Jul 22 07:53:53 PM PDT 24 |
| Finished | Jul 22 07:54:30 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-89fa60d2-e1fc-424d-a1e5-3d954c2f5a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168585806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.168585806 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3066167939 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 992577631 ps |
| CPU time | 30.96 seconds |
| Started | Jul 22 07:54:03 PM PDT 24 |
| Finished | Jul 22 07:54:35 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-466abb4c-43c6-400b-86c3-1d0e9046be91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066167939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3066167939 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.800264097 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 48537627 ps |
| CPU time | 6.36 seconds |
| Started | Jul 22 07:53:57 PM PDT 24 |
| Finished | Jul 22 07:54:04 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-7f85946b-2afd-441d-a055-cb4acd9130e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800264097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.800264097 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1818566208 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 7911486026 ps |
| CPU time | 81.68 seconds |
| Started | Jul 22 07:53:51 PM PDT 24 |
| Finished | Jul 22 07:55:14 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-cf3f83f2-7086-453a-8dca-c15490dfd79d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818566208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1818566208 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3328145365 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 5567186040 ps |
| CPU time | 93.99 seconds |
| Started | Jul 22 07:53:52 PM PDT 24 |
| Finished | Jul 22 07:55:28 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-3c19c7a2-4ff1-4549-8abb-908fc717cd2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328145365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3328145365 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3797747830 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 47224239 ps |
| CPU time | 6.85 seconds |
| Started | Jul 22 07:53:53 PM PDT 24 |
| Finished | Jul 22 07:54:01 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-3f48fd7a-c8f9-4b25-9e31-582048d7ae09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797747830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.3797747830 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.1960988310 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 2213045588 ps |
| CPU time | 204.5 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 07:58:03 PM PDT 24 |
| Peak memory | 576204 kb |
| Host | smart-1a82a740-783d-4b8a-832a-c948aa295f8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960988310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1960988310 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3039619418 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 2921640784 ps |
| CPU time | 220.46 seconds |
| Started | Jul 22 07:54:48 PM PDT 24 |
| Finished | Jul 22 07:58:33 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-7ebc64f0-9b0d-4e2a-abc0-7a781a5044f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039619418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3039619418 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2227263388 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 4231961932 ps |
| CPU time | 289.35 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 07:58:55 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-37382120-8992-4ddc-8827-1f241e8bf855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227263388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.2227263388 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2039386823 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 179130484 ps |
| CPU time | 41.81 seconds |
| Started | Jul 22 07:54:05 PM PDT 24 |
| Finished | Jul 22 07:54:48 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-2ddf2253-bb30-4de7-a5bc-20b63054e1ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039386823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2039386823 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.9414277 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 112463089 ps |
| CPU time | 8.73 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 07:54:14 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-2e1ebcc3-2ade-470e-b18e-809f055a3b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9414277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.9414277 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2492398844 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 2638491336 ps |
| CPU time | 120.42 seconds |
| Started | Jul 22 07:54:05 PM PDT 24 |
| Finished | Jul 22 07:56:07 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-c93d857f-7592-416c-bee2-b862f7c37c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492398844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .2492398844 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3927117207 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 56040080861 ps |
| CPU time | 931.84 seconds |
| Started | Jul 22 07:54:11 PM PDT 24 |
| Finished | Jul 22 08:09:44 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-8dc8352b-e947-4c40-9ab8-0b0f8c3bc556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927117207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3927117207 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4271536467 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 1120140923 ps |
| CPU time | 41.13 seconds |
| Started | Jul 22 07:54:01 PM PDT 24 |
| Finished | Jul 22 07:54:43 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-7f836dde-b20d-4296-9ae1-586354e0644e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271536467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.4271536467 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2403456853 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 2389860846 ps |
| CPU time | 77.56 seconds |
| Started | Jul 22 07:54:03 PM PDT 24 |
| Finished | Jul 22 07:55:22 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-4731a25e-3718-47f8-8292-1698d590d986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403456853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2403456853 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.743750421 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 2455129859 ps |
| CPU time | 79.44 seconds |
| Started | Jul 22 07:55:11 PM PDT 24 |
| Finished | Jul 22 07:56:32 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-c9c0f5ef-f6ab-4176-b069-9ea333d0a18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743750421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.743750421 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3836418973 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 75797940167 ps |
| CPU time | 825.51 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 08:07:51 PM PDT 24 |
| Peak memory | 576108 kb |
| Host | smart-f0d78dd2-8080-4c1b-a256-2e8c12d5ab16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836418973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3836418973 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1408441490 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 29287798644 ps |
| CPU time | 448.01 seconds |
| Started | Jul 22 07:55:11 PM PDT 24 |
| Finished | Jul 22 08:02:40 PM PDT 24 |
| Peak memory | 576900 kb |
| Host | smart-c743d466-f9f6-457e-81f2-00d6aed57764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408441490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1408441490 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3413676850 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 550644893 ps |
| CPU time | 47.2 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 07:54:53 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-c8b1c1ec-f142-437a-8cf5-52282776912a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413676850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3413676850 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1190029912 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1272894314 ps |
| CPU time | 37.94 seconds |
| Started | Jul 22 07:54:04 PM PDT 24 |
| Finished | Jul 22 07:54:44 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-24f1c4cd-ec78-47c9-9166-ba6f96e13422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190029912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1190029912 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4117001943 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 44395671 ps |
| CPU time | 6.4 seconds |
| Started | Jul 22 07:54:10 PM PDT 24 |
| Finished | Jul 22 07:54:18 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-54f0b694-ab34-4f3c-9a70-a83b1090e217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117001943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4117001943 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1938985304 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 8581493677 ps |
| CPU time | 84.23 seconds |
| Started | Jul 22 07:54:07 PM PDT 24 |
| Finished | Jul 22 07:55:32 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-1b936629-ca30-4933-a5e4-be8235b7eb08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938985304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1938985304 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1316231023 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 5952803316 ps |
| CPU time | 93.25 seconds |
| Started | Jul 22 07:54:06 PM PDT 24 |
| Finished | Jul 22 07:55:41 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-276b2b3c-d664-4bc2-92bf-642383fcb8f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316231023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1316231023 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2672309815 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 51236582 ps |
| CPU time | 6.81 seconds |
| Started | Jul 22 07:54:03 PM PDT 24 |
| Finished | Jul 22 07:54:11 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-26f9d48a-4cd7-43c4-a24f-a4b4f6580842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672309815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.2672309815 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2383297281 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 13774199478 ps |
| CPU time | 468.47 seconds |
| Started | Jul 22 07:54:06 PM PDT 24 |
| Finished | Jul 22 08:01:56 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-83ebe49f-0dce-4a9d-9e0a-e97be2a02e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383297281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2383297281 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.135757776 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 1136023205 ps |
| CPU time | 84.16 seconds |
| Started | Jul 22 07:54:16 PM PDT 24 |
| Finished | Jul 22 07:55:42 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-b455a273-a266-4900-bf24-eb5f544ca28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135757776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.135757776 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1323636062 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 9185627201 ps |
| CPU time | 539.24 seconds |
| Started | Jul 22 07:54:16 PM PDT 24 |
| Finished | Jul 22 08:03:17 PM PDT 24 |
| Peak memory | 577064 kb |
| Host | smart-09260951-2ede-4867-9d91-509da3e3771a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323636062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1323636062 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2136572807 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 7451851288 ps |
| CPU time | 335.75 seconds |
| Started | Jul 22 07:54:47 PM PDT 24 |
| Finished | Jul 22 08:00:27 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-f5ef0dd8-df4f-49a2-b43d-1aea13693e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136572807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.2136572807 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.654763782 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 312909592 ps |
| CPU time | 37.54 seconds |
| Started | Jul 22 07:54:10 PM PDT 24 |
| Finished | Jul 22 07:54:49 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-596158a2-cb67-4753-a650-bb554f6a3582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654763782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.654763782 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.289698335 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 673472201 ps |
| CPU time | 27.17 seconds |
| Started | Jul 22 07:55:23 PM PDT 24 |
| Finished | Jul 22 07:55:52 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-94057814-fd46-4d35-aab9-61df874486ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289698335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 289698335 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3886182948 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 81030794250 ps |
| CPU time | 1477.87 seconds |
| Started | Jul 22 07:54:16 PM PDT 24 |
| Finished | Jul 22 08:18:55 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-30b7afa8-7ce0-44d0-90ba-e84e7ea724a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886182948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3886182948 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1255829376 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 264250413 ps |
| CPU time | 26.99 seconds |
| Started | Jul 22 07:54:32 PM PDT 24 |
| Finished | Jul 22 07:55:02 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-206d3fa8-c61c-4ceb-898f-cbc3de146eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255829376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.1255829376 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1286049615 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 418467125 ps |
| CPU time | 32.44 seconds |
| Started | Jul 22 07:54:25 PM PDT 24 |
| Finished | Jul 22 07:54:58 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-79dac50a-eb87-491a-ae78-bb1281da05fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286049615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1286049615 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.1096196004 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 366685939 ps |
| CPU time | 16.09 seconds |
| Started | Jul 22 07:54:13 PM PDT 24 |
| Finished | Jul 22 07:54:30 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-202fa6a4-d490-49a3-b8f7-6774dbc11f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096196004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1096196004 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2825292149 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 64616861060 ps |
| CPU time | 687.79 seconds |
| Started | Jul 22 07:54:13 PM PDT 24 |
| Finished | Jul 22 08:05:42 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-5a4329ff-97be-41d5-85eb-2c61cf3e0020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825292149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2825292149 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2373524601 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 21579315679 ps |
| CPU time | 352.07 seconds |
| Started | Jul 22 07:54:15 PM PDT 24 |
| Finished | Jul 22 08:00:09 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-5ad5decd-ec7e-41d6-b149-16a79e6a42b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373524601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2373524601 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.2543293545 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 39985741 ps |
| CPU time | 6.85 seconds |
| Started | Jul 22 07:54:17 PM PDT 24 |
| Finished | Jul 22 07:54:25 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-cae499bb-29fb-4114-b839-da6b3bdde171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543293545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.2543293545 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2632531016 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 465761180 ps |
| CPU time | 31.52 seconds |
| Started | Jul 22 07:54:22 PM PDT 24 |
| Finished | Jul 22 07:54:54 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-31a13866-acae-40b8-a49e-b53173b46e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632531016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2632531016 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.3498268923 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 157284306 ps |
| CPU time | 7.92 seconds |
| Started | Jul 22 07:54:13 PM PDT 24 |
| Finished | Jul 22 07:54:22 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-5a49f283-f240-442d-a36b-99ec490c2fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498268923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3498268923 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3478271334 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 8185322516 ps |
| CPU time | 83.26 seconds |
| Started | Jul 22 07:54:15 PM PDT 24 |
| Finished | Jul 22 07:55:40 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-06d3a70f-21d6-4f92-87f3-ab644ff0c6a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478271334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3478271334 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.37438696 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 5998049406 ps |
| CPU time | 92.55 seconds |
| Started | Jul 22 07:55:00 PM PDT 24 |
| Finished | Jul 22 07:56:34 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-654489c8-5d6e-4321-9d56-5178c1974460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.37438696 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1448665909 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 43132321 ps |
| CPU time | 6.44 seconds |
| Started | Jul 22 07:54:16 PM PDT 24 |
| Finished | Jul 22 07:54:24 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-638a3f5d-61da-421d-97a2-0dbeb11a796d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448665909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.1448665909 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.4267117930 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 4041528898 ps |
| CPU time | 154.82 seconds |
| Started | Jul 22 07:54:25 PM PDT 24 |
| Finished | Jul 22 07:57:01 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-f19c6f1d-c673-44bf-a202-de0fe814c0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267117930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4267117930 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3275363326 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 10146355157 ps |
| CPU time | 330.61 seconds |
| Started | Jul 22 07:54:24 PM PDT 24 |
| Finished | Jul 22 07:59:56 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-50f90ba2-4b96-4fde-96b3-966d8380aa3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275363326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3275363326 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3462839269 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1830054546 ps |
| CPU time | 229.36 seconds |
| Started | Jul 22 07:54:22 PM PDT 24 |
| Finished | Jul 22 07:58:12 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-b76e8b9f-56d9-4c45-a860-521a60809e7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462839269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3462839269 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2612125852 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 2509834436 ps |
| CPU time | 316.5 seconds |
| Started | Jul 22 07:54:26 PM PDT 24 |
| Finished | Jul 22 07:59:43 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-3f7592f7-a810-4cd5-b196-81de16ab84df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612125852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.2612125852 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2554380175 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 960418086 ps |
| CPU time | 35.68 seconds |
| Started | Jul 22 07:55:59 PM PDT 24 |
| Finished | Jul 22 07:56:37 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-2d631d12-f4d3-4b9c-aa64-dc98201bc1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554380175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2554380175 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1116517987 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 2245636796 ps |
| CPU time | 92.74 seconds |
| Started | Jul 22 07:54:29 PM PDT 24 |
| Finished | Jul 22 07:56:03 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-d55d410e-92b5-44e1-8d5b-6e0b18a936a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116517987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1116517987 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.4189960285 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 53492801706 ps |
| CPU time | 869.58 seconds |
| Started | Jul 22 07:54:36 PM PDT 24 |
| Finished | Jul 22 08:09:09 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-25615171-90eb-433b-a249-496e240c67c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189960285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.4189960285 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.822050269 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 765420375 ps |
| CPU time | 25.49 seconds |
| Started | Jul 22 07:54:39 PM PDT 24 |
| Finished | Jul 22 07:55:07 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-affbcdab-1c49-4e3e-b1e2-603974549ffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822050269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr .822050269 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.669138816 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 1634744616 ps |
| CPU time | 53.45 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 07:55:32 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-19596f1a-66ef-41b6-89b6-8a5253f294b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669138816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.669138816 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.4207551082 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 696230781 ps |
| CPU time | 22.65 seconds |
| Started | Jul 22 07:54:24 PM PDT 24 |
| Finished | Jul 22 07:54:48 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-76cde110-d281-4ce3-9ea6-d67906831989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207551082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.4207551082 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2509800719 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 54349348900 ps |
| CPU time | 588.64 seconds |
| Started | Jul 22 07:54:23 PM PDT 24 |
| Finished | Jul 22 08:04:13 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-22753754-787f-4565-b217-a091749d305c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509800719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2509800719 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3943577683 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 71929304026 ps |
| CPU time | 1160.89 seconds |
| Started | Jul 22 07:54:24 PM PDT 24 |
| Finished | Jul 22 08:13:47 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-ac747874-c07a-4ace-80e9-555c87e1f96f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943577683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3943577683 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3908022349 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 326364223 ps |
| CPU time | 25.22 seconds |
| Started | Jul 22 07:54:26 PM PDT 24 |
| Finished | Jul 22 07:54:52 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-68481819-cdd1-40af-8c32-1415f7588c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908022349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3908022349 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.368098980 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 436871903 ps |
| CPU time | 34.68 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 07:55:12 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-be83c22e-099f-47e7-a195-ab63d3e32d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368098980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.368098980 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2349819496 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 194277878 ps |
| CPU time | 9.07 seconds |
| Started | Jul 22 07:54:23 PM PDT 24 |
| Finished | Jul 22 07:54:33 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-313c79ec-b5d0-45c1-a133-5be7edf3ce90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349819496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2349819496 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.800299324 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 6845389621 ps |
| CPU time | 70.25 seconds |
| Started | Jul 22 07:54:24 PM PDT 24 |
| Finished | Jul 22 07:55:35 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-410fbc69-144d-4a46-8802-98fb41505612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800299324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.800299324 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.70242478 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 5863694765 ps |
| CPU time | 101.86 seconds |
| Started | Jul 22 07:54:24 PM PDT 24 |
| Finished | Jul 22 07:56:07 PM PDT 24 |
| Peak memory | 574848 kb |
| Host | smart-e58fab30-9a4c-46c3-9732-c5d3d798a3e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70242478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.70242478 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.785624429 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 50432297 ps |
| CPU time | 5.97 seconds |
| Started | Jul 22 07:54:23 PM PDT 24 |
| Finished | Jul 22 07:54:30 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-1dcfd74b-1cc1-41f6-90b1-7344d47ddccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785624429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .785624429 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.1685823376 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 1422569377 ps |
| CPU time | 125.68 seconds |
| Started | Jul 22 07:54:38 PM PDT 24 |
| Finished | Jul 22 07:56:47 PM PDT 24 |
| Peak memory | 576900 kb |
| Host | smart-61f25209-65c6-4052-9bbe-141737d82238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685823376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1685823376 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3889206018 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 862923340 ps |
| CPU time | 29.01 seconds |
| Started | Jul 22 07:54:37 PM PDT 24 |
| Finished | Jul 22 07:55:09 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-52462002-631d-4d99-9625-4feb704727e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889206018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3889206018 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3075195551 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 5014904796 ps |
| CPU time | 487.9 seconds |
| Started | Jul 22 07:54:33 PM PDT 24 |
| Finished | Jul 22 08:02:43 PM PDT 24 |
| Peak memory | 577008 kb |
| Host | smart-60f4b62e-a98e-42b9-8dad-29fbffdc2db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075195551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3075195551 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.2869774623 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 465645533 ps |
| CPU time | 158.85 seconds |
| Started | Jul 22 07:54:37 PM PDT 24 |
| Finished | Jul 22 07:57:19 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-47965488-92aa-4a49-b303-07f3dcf20ed3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869774623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.2869774623 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.4139451349 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 1061486971 ps |
| CPU time | 42.86 seconds |
| Started | Jul 22 07:54:36 PM PDT 24 |
| Finished | Jul 22 07:55:22 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-ff025417-a20d-48a3-b74a-253af02bd496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139451349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4139451349 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2955600842 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 192641975 ps |
| CPU time | 13.08 seconds |
| Started | Jul 22 07:54:37 PM PDT 24 |
| Finished | Jul 22 07:54:53 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c40f8e19-b189-4edb-a161-d5b2c56fc7e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955600842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2955600842 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.184082317 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 48522856377 ps |
| CPU time | 868.66 seconds |
| Started | Jul 22 07:54:36 PM PDT 24 |
| Finished | Jul 22 08:09:08 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-68f7c426-3726-49a6-883a-2cb1c1140d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184082317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d evice_slow_rsp.184082317 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.426794174 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 894314304 ps |
| CPU time | 30.09 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 07:55:07 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-54ed21e2-40b6-4bc8-89ca-e13f6049f08c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426794174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr .426794174 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3350511757 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 2474495680 ps |
| CPU time | 90.92 seconds |
| Started | Jul 22 07:54:38 PM PDT 24 |
| Finished | Jul 22 07:56:12 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-13dd6283-c5c9-4a95-8bf9-c592c5118062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350511757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3350511757 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.4102863138 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 788652565 ps |
| CPU time | 31.75 seconds |
| Started | Jul 22 07:54:36 PM PDT 24 |
| Finished | Jul 22 07:55:11 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-c1559a7d-5eee-4a7c-922d-d492c8bc67b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102863138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.4102863138 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3219357942 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 70012011295 ps |
| CPU time | 719.31 seconds |
| Started | Jul 22 07:54:54 PM PDT 24 |
| Finished | Jul 22 08:06:59 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-501863b0-303a-4d5a-8782-ca3602b2977f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219357942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3219357942 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.4000971950 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 61677835460 ps |
| CPU time | 993.04 seconds |
| Started | Jul 22 07:55:08 PM PDT 24 |
| Finished | Jul 22 08:11:44 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-947614ff-b22e-441a-8af3-3111eff27aa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000971950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4000971950 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1142951405 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 297155792 ps |
| CPU time | 24.72 seconds |
| Started | Jul 22 07:54:37 PM PDT 24 |
| Finished | Jul 22 07:55:04 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-943f9c92-023b-4812-85e0-e5e30261ec0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142951405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.1142951405 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2660380041 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 39908144 ps |
| CPU time | 6.37 seconds |
| Started | Jul 22 07:54:35 PM PDT 24 |
| Finished | Jul 22 07:54:45 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-cfb50788-6335-4b2c-a940-3b6d588a83df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660380041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2660380041 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1579151551 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 44721322 ps |
| CPU time | 6.11 seconds |
| Started | Jul 22 07:54:37 PM PDT 24 |
| Finished | Jul 22 07:54:46 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-b7629d56-e175-4cd1-904f-a6eb43628db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579151551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1579151551 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.156877636 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 9540543152 ps |
| CPU time | 99.45 seconds |
| Started | Jul 22 07:54:34 PM PDT 24 |
| Finished | Jul 22 07:56:17 PM PDT 24 |
| Peak memory | 574864 kb |
| Host | smart-151c9d02-b180-4b11-ae4c-7049dc6ae89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156877636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.156877636 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2711795815 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 3645973268 ps |
| CPU time | 57.34 seconds |
| Started | Jul 22 07:54:37 PM PDT 24 |
| Finished | Jul 22 07:55:37 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-1ff77a0f-43a8-41f3-b618-726b5259ccdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711795815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2711795815 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1627640487 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 44357088 ps |
| CPU time | 5.99 seconds |
| Started | Jul 22 07:54:35 PM PDT 24 |
| Finished | Jul 22 07:54:44 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-6b558712-88e7-4a92-84dc-ea09dc14887a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627640487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1627640487 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.2005767905 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 3424112928 ps |
| CPU time | 266.3 seconds |
| Started | Jul 22 07:54:52 PM PDT 24 |
| Finished | Jul 22 07:59:23 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-ca47959b-9375-4db1-9e9b-847f6e7a4204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005767905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2005767905 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2773012392 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 20495438702 ps |
| CPU time | 768.12 seconds |
| Started | Jul 22 07:54:50 PM PDT 24 |
| Finished | Jul 22 08:07:44 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-4358bbcd-9065-42b6-b9b3-0745c3b76742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773012392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2773012392 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.645547722 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 4356042828 ps |
| CPU time | 340.3 seconds |
| Started | Jul 22 07:54:51 PM PDT 24 |
| Finished | Jul 22 08:00:36 PM PDT 24 |
| Peak memory | 577228 kb |
| Host | smart-529b868b-eac4-4bb7-812d-52502a7e8a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645547722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_ with_rand_reset.645547722 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3846791736 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 1985235711 ps |
| CPU time | 210.83 seconds |
| Started | Jul 22 07:54:48 PM PDT 24 |
| Finished | Jul 22 07:58:23 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-b0a60125-7ed2-47b3-b620-77b1cf037352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846791736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3846791736 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1949928911 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 1356183394 ps |
| CPU time | 57.7 seconds |
| Started | Jul 22 07:54:36 PM PDT 24 |
| Finished | Jul 22 07:55:37 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-bad39a85-98e0-4865-a118-bc61e058707e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949928911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1949928911 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.4274453502 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 6565822922 ps |
| CPU time | 466.96 seconds |
| Started | Jul 22 07:43:07 PM PDT 24 |
| Finished | Jul 22 07:50:54 PM PDT 24 |
| Peak memory | 637916 kb |
| Host | smart-2de10e0d-caca-45d1-a7be-b1f78fe6429d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274453502 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.4274453502 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.3627449191 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 4527397008 ps |
| CPU time | 557.63 seconds |
| Started | Jul 22 07:43:05 PM PDT 24 |
| Finished | Jul 22 07:52:24 PM PDT 24 |
| Peak memory | 599704 kb |
| Host | smart-cc761bf9-e5fb-40fe-8911-bfa2569db1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627449191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3627449191 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3972889670 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 16268916610 ps |
| CPU time | 2177.47 seconds |
| Started | Jul 22 07:42:44 PM PDT 24 |
| Finished | Jul 22 08:19:02 PM PDT 24 |
| Peak memory | 593804 kb |
| Host | smart-019de050-8904-401d-a758-9676859be55d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972889670 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3972889670 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.298735147 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3718048780 ps |
| CPU time | 319.42 seconds |
| Started | Jul 22 07:43:37 PM PDT 24 |
| Finished | Jul 22 07:48:58 PM PDT 24 |
| Peak memory | 604364 kb |
| Host | smart-a893cac7-d445-42c9-b151-742b2b863ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298735147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.298735147 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3811698761 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 280113206 ps |
| CPU time | 15.77 seconds |
| Started | Jul 22 07:43:05 PM PDT 24 |
| Finished | Jul 22 07:43:22 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-aa5f5234-6d46-4aa5-864b-23d43f09f787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811698761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3811698761 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.912770533 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 49593342184 ps |
| CPU time | 840.42 seconds |
| Started | Jul 22 07:43:02 PM PDT 24 |
| Finished | Jul 22 07:57:04 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-5b5fd3ec-22a0-4628-b570-037e87728b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912770533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.912770533 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2883545764 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 383426158 ps |
| CPU time | 18.81 seconds |
| Started | Jul 22 07:43:45 PM PDT 24 |
| Finished | Jul 22 07:44:05 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-3889bbc5-fedd-4ed9-bb8e-272096c7629d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883545764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2883545764 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.3865443726 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 84064018 ps |
| CPU time | 6.36 seconds |
| Started | Jul 22 07:43:13 PM PDT 24 |
| Finished | Jul 22 07:43:21 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-8081944b-89cf-4af3-872f-258966133cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865443726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3865443726 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2175383395 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 532206649 ps |
| CPU time | 43.7 seconds |
| Started | Jul 22 07:43:01 PM PDT 24 |
| Finished | Jul 22 07:43:46 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-7501b8c7-0df8-47ba-b729-230c28ecfac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175383395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2175383395 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3892132246 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 81991250806 ps |
| CPU time | 776.63 seconds |
| Started | Jul 22 07:42:57 PM PDT 24 |
| Finished | Jul 22 07:55:54 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-fb1b051e-3d54-4b7e-aae1-37f7e532197a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892132246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3892132246 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.508118395 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 61097939111 ps |
| CPU time | 1055.69 seconds |
| Started | Jul 22 07:42:54 PM PDT 24 |
| Finished | Jul 22 08:00:30 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-481d8303-770d-42b8-976a-3517efe22137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508118395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.508118395 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2629927923 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 553309544 ps |
| CPU time | 43.58 seconds |
| Started | Jul 22 07:44:53 PM PDT 24 |
| Finished | Jul 22 07:45:38 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-bc623a87-7048-4d82-aa9e-5ec44d9c465f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629927923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2629927923 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.1216337721 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 478233193 ps |
| CPU time | 16.35 seconds |
| Started | Jul 22 07:42:57 PM PDT 24 |
| Finished | Jul 22 07:43:14 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-f886ac33-d8af-4615-a7ee-91201cae8d2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216337721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1216337721 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.318818635 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 231577356 ps |
| CPU time | 9.44 seconds |
| Started | Jul 22 07:42:44 PM PDT 24 |
| Finished | Jul 22 07:42:54 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-e96b5895-f5d0-40b4-a58e-7804f743ddd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318818635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.318818635 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3954921070 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 8663806249 ps |
| CPU time | 84.41 seconds |
| Started | Jul 22 07:42:53 PM PDT 24 |
| Finished | Jul 22 07:44:18 PM PDT 24 |
| Peak memory | 574912 kb |
| Host | smart-152871d4-457e-4234-88fd-352023107b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954921070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3954921070 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3229147385 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5373966544 ps |
| CPU time | 88.98 seconds |
| Started | Jul 22 07:42:54 PM PDT 24 |
| Finished | Jul 22 07:44:24 PM PDT 24 |
| Peak memory | 574944 kb |
| Host | smart-b58f8441-98eb-4201-bf88-29693c74a2c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229147385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3229147385 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2673700793 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 44919593 ps |
| CPU time | 6.53 seconds |
| Started | Jul 22 07:43:46 PM PDT 24 |
| Finished | Jul 22 07:43:56 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-0a1012fd-ecb1-466f-8283-c972cf30b36c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673700793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .2673700793 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.4072111251 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 1394296217 ps |
| CPU time | 118.95 seconds |
| Started | Jul 22 07:42:53 PM PDT 24 |
| Finished | Jul 22 07:44:53 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-9ce4e8ea-5454-4d9b-ba66-e5bbf9b87ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072111251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4072111251 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.915932690 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 6014679950 ps |
| CPU time | 219.96 seconds |
| Started | Jul 22 07:43:05 PM PDT 24 |
| Finished | Jul 22 07:46:46 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-784bf8f8-8ba4-406f-ab6c-69fcb5c440c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915932690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.915932690 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2079543853 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 71564445 ps |
| CPU time | 30.7 seconds |
| Started | Jul 22 07:42:54 PM PDT 24 |
| Finished | Jul 22 07:43:26 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-bde90a95-d541-4545-b753-b8b93aef8239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079543853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.2079543853 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.326520788 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 3336000715 ps |
| CPU time | 318.17 seconds |
| Started | Jul 22 07:42:52 PM PDT 24 |
| Finished | Jul 22 07:48:11 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-992754a0-f2aa-4a88-b9db-2571f6490760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326520788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_reset_error.326520788 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.548744287 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 101296563 ps |
| CPU time | 7.58 seconds |
| Started | Jul 22 07:42:53 PM PDT 24 |
| Finished | Jul 22 07:43:01 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-16ce2bf3-1528-4aae-9c81-296f80aeec0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548744287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.548744287 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1419866359 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 1032116756 ps |
| CPU time | 61.49 seconds |
| Started | Jul 22 07:54:48 PM PDT 24 |
| Finished | Jul 22 07:55:53 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-05fda9b2-18df-4b5e-9e4c-c2ebe50632ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419866359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1419866359 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3059258944 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 19758680896 ps |
| CPU time | 340.34 seconds |
| Started | Jul 22 07:54:48 PM PDT 24 |
| Finished | Jul 22 08:00:33 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-8c666c72-0c0c-4e4b-b095-cb536c9aea49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059258944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.3059258944 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.174155390 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 158980981 ps |
| CPU time | 10.43 seconds |
| Started | Jul 22 07:54:48 PM PDT 24 |
| Finished | Jul 22 07:55:03 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-ad2ae6e6-e4d1-45a0-adcb-bd643e295710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174155390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr .174155390 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.3596880936 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 49034510 ps |
| CPU time | 7.18 seconds |
| Started | Jul 22 07:54:55 PM PDT 24 |
| Finished | Jul 22 07:55:04 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-2160f995-a343-4262-9435-4075d53631e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596880936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3596880936 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.4092738674 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 1249039068 ps |
| CPU time | 48.1 seconds |
| Started | Jul 22 07:54:52 PM PDT 24 |
| Finished | Jul 22 07:55:44 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-24b9b917-b799-4ad3-877d-83e755af071d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092738674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.4092738674 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.898813842 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 31968265104 ps |
| CPU time | 297.26 seconds |
| Started | Jul 22 07:55:26 PM PDT 24 |
| Finished | Jul 22 08:00:23 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-25367a08-b625-4743-902e-0c3a54bf1022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898813842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.898813842 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.3582098645 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 18499421438 ps |
| CPU time | 320.73 seconds |
| Started | Jul 22 07:54:50 PM PDT 24 |
| Finished | Jul 22 08:00:16 PM PDT 24 |
| Peak memory | 576900 kb |
| Host | smart-27182b79-3d92-4bd8-bcfb-748f45fe0784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582098645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.3582098645 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2031846780 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 220770316 ps |
| CPU time | 23.91 seconds |
| Started | Jul 22 07:54:51 PM PDT 24 |
| Finished | Jul 22 07:55:19 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-f021ebd5-a492-4957-95de-fff3ec1ecff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031846780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.2031846780 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.3101822396 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 149710314 ps |
| CPU time | 13.66 seconds |
| Started | Jul 22 07:54:51 PM PDT 24 |
| Finished | Jul 22 07:55:09 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-437d4640-40c3-4403-bac9-db72a52702f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101822396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3101822396 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.1079677828 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 56435185 ps |
| CPU time | 6.68 seconds |
| Started | Jul 22 07:54:48 PM PDT 24 |
| Finished | Jul 22 07:54:59 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-399f612e-3b86-46c6-9a13-c9322a6c2f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079677828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.1079677828 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.33783992 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 9045612285 ps |
| CPU time | 88.95 seconds |
| Started | Jul 22 07:54:54 PM PDT 24 |
| Finished | Jul 22 07:56:26 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-bde78935-5e91-4d94-aaa9-c65e181efa17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.33783992 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2590242634 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 3785210965 ps |
| CPU time | 63.05 seconds |
| Started | Jul 22 07:54:50 PM PDT 24 |
| Finished | Jul 22 07:55:57 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-f469faa5-477c-4528-9f58-f086fe785ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590242634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2590242634 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3162086736 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 46934443 ps |
| CPU time | 6.39 seconds |
| Started | Jul 22 07:54:49 PM PDT 24 |
| Finished | Jul 22 07:55:01 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c4af6ac3-9e64-4aac-a983-78cd9b7139c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162086736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3162086736 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.751514528 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 4523847669 ps |
| CPU time | 320.21 seconds |
| Started | Jul 22 07:54:49 PM PDT 24 |
| Finished | Jul 22 08:00:14 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-19ff0add-802a-430d-aad2-49cb90300f4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751514528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.751514528 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1456472161 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 1878513498 ps |
| CPU time | 154.12 seconds |
| Started | Jul 22 07:54:49 PM PDT 24 |
| Finished | Jul 22 07:57:27 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-07099c98-5454-405d-ae42-bf6f1d878dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456472161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1456472161 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.116015888 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 59304506 ps |
| CPU time | 41.07 seconds |
| Started | Jul 22 07:54:49 PM PDT 24 |
| Finished | Jul 22 07:55:34 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-394cfaae-56c4-42ce-aeb5-749d509ed0a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116015888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_ with_rand_reset.116015888 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2208498837 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 3192682638 ps |
| CPU time | 260.39 seconds |
| Started | Jul 22 07:54:49 PM PDT 24 |
| Finished | Jul 22 07:59:15 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-d4119aa6-87b4-460b-8cab-154e4899847b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208498837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.2208498837 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1288190670 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 253667435 ps |
| CPU time | 23.85 seconds |
| Started | Jul 22 07:54:52 PM PDT 24 |
| Finished | Jul 22 07:55:20 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-7bc68127-b85e-4525-abb4-dc9961c6e168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288190670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1288190670 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2511732029 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 751159899 ps |
| CPU time | 52.1 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 07:55:56 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-6d80d91e-a101-46e5-bfaf-91002ba83500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511732029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .2511732029 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3517392396 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 66019888941 ps |
| CPU time | 1246.95 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 08:15:52 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-91aab3f1-23fe-40d3-a64e-17d06418425d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517392396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.3517392396 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3207515399 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 188022554 ps |
| CPU time | 19.96 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 07:55:24 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-f834e0c2-1791-4737-b599-cbafaca50974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207515399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3207515399 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.2735174123 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 2274979886 ps |
| CPU time | 82.46 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 07:56:26 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-597d7bf2-9f6b-4bdf-9703-f57b27a060af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735174123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.2735174123 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.1230820979 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 621148804 ps |
| CPU time | 25.18 seconds |
| Started | Jul 22 07:56:17 PM PDT 24 |
| Finished | Jul 22 07:56:44 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-cff60ae8-c66e-4484-b3d6-da6f97fbc00c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230820979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1230820979 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1166276252 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 17411875407 ps |
| CPU time | 176.39 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 07:58:01 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-51e9ef66-83bb-4c56-aea2-224c08c5de03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166276252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1166276252 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.4084821193 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 61315460593 ps |
| CPU time | 1127.54 seconds |
| Started | Jul 22 07:55:04 PM PDT 24 |
| Finished | Jul 22 08:13:56 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-e2b3411d-412f-4daa-bb0a-f5ce3cc26622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084821193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.4084821193 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2944857500 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 520908084 ps |
| CPU time | 39.46 seconds |
| Started | Jul 22 07:55:15 PM PDT 24 |
| Finished | Jul 22 07:55:55 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-44ff7a21-2a3e-4382-875f-f9e6cf959434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944857500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.2944857500 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.1621221065 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1554206153 ps |
| CPU time | 44.2 seconds |
| Started | Jul 22 07:55:10 PM PDT 24 |
| Finished | Jul 22 07:55:56 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-e40b7aed-a517-4510-9307-7fb60bba88e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621221065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.1621221065 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.2318119709 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 46577213 ps |
| CPU time | 6.44 seconds |
| Started | Jul 22 07:55:09 PM PDT 24 |
| Finished | Jul 22 07:55:18 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-7679e6ea-1333-4fb0-b584-f3cc5b934434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318119709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2318119709 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.4234465321 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 8399828388 ps |
| CPU time | 92 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 07:56:37 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-182234c5-9fda-47e4-8081-50d5a19dffbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234465321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.4234465321 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1703423879 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 5263606107 ps |
| CPU time | 88.15 seconds |
| Started | Jul 22 07:55:04 PM PDT 24 |
| Finished | Jul 22 07:56:36 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-f750cb8d-1bef-4dca-987c-b531af936d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703423879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1703423879 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.486525178 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 45572073 ps |
| CPU time | 6.33 seconds |
| Started | Jul 22 07:55:04 PM PDT 24 |
| Finished | Jul 22 07:55:14 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-57d819a1-962c-4db7-98d5-50b5a6e14c04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486525178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .486525178 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1972380236 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 1586924219 ps |
| CPU time | 60.53 seconds |
| Started | Jul 22 07:55:04 PM PDT 24 |
| Finished | Jul 22 07:56:08 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-f8440317-b65a-4e6a-afd4-a2df82564b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972380236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1972380236 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3945188181 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 1292704684 ps |
| CPU time | 43.58 seconds |
| Started | Jul 22 07:55:04 PM PDT 24 |
| Finished | Jul 22 07:55:51 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-0a91cde7-595d-47cc-9476-6edc79800a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945188181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3945188181 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1196428897 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5935267865 ps |
| CPU time | 504.1 seconds |
| Started | Jul 22 07:55:21 PM PDT 24 |
| Finished | Jul 22 08:03:47 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-692dd8d4-e197-4266-9035-caafa06d8250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196428897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1196428897 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.3482946976 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 1981915966 ps |
| CPU time | 189.33 seconds |
| Started | Jul 22 07:55:09 PM PDT 24 |
| Finished | Jul 22 07:58:20 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1f0c073d-77f0-4f03-9e00-174f670bdd1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482946976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.3482946976 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2803744968 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 832758558 ps |
| CPU time | 35.97 seconds |
| Started | Jul 22 07:55:07 PM PDT 24 |
| Finished | Jul 22 07:55:46 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-f960ec4b-a4cd-482c-8855-4721a35c4a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803744968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2803744968 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2624857994 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 666737934 ps |
| CPU time | 58.26 seconds |
| Started | Jul 22 07:55:03 PM PDT 24 |
| Finished | Jul 22 07:56:04 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-03e3d852-85f4-4c40-908c-5c3a3f7a7b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624857994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .2624857994 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3224297911 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 22056285047 ps |
| CPU time | 420.24 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 08:02:05 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-c55ab336-b1b7-40f2-99b3-81cf0bd2a3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224297911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3224297911 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1620774114 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 287480648 ps |
| CPU time | 27.73 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:55:41 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-6bb5e484-8205-4bed-a746-9bbeb710909d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620774114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.1620774114 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.2840752830 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 2256833668 ps |
| CPU time | 81.05 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:56:45 PM PDT 24 |
| Peak memory | 576952 kb |
| Host | smart-b8fec485-2e0d-4f29-b9ad-ab3ddbc22380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840752830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.2840752830 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1357598290 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 2583024680 ps |
| CPU time | 85.54 seconds |
| Started | Jul 22 07:55:06 PM PDT 24 |
| Finished | Jul 22 07:56:35 PM PDT 24 |
| Peak memory | 576964 kb |
| Host | smart-e47af633-7c2f-44e4-af05-7686803ddfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357598290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1357598290 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2389307725 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 4163901869 ps |
| CPU time | 43.88 seconds |
| Started | Jul 22 07:55:03 PM PDT 24 |
| Finished | Jul 22 07:55:50 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-778b1c62-d439-4462-bfae-96625d2cb754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389307725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2389307725 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.382682353 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 35337792278 ps |
| CPU time | 642.89 seconds |
| Started | Jul 22 07:55:04 PM PDT 24 |
| Finished | Jul 22 08:05:50 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-dc314351-982e-405d-8821-b648c4632c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382682353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.382682353 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1956710327 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 288870629 ps |
| CPU time | 26.75 seconds |
| Started | Jul 22 07:55:01 PM PDT 24 |
| Finished | Jul 22 07:55:30 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-d7ac4508-e4f1-4fe6-8eb9-adca5b823a9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956710327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.1956710327 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2352122745 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 270476522 ps |
| CPU time | 11.77 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:35 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-c01eb8cd-f92f-48e0-b55c-3dcbcc3e3940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352122745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2352122745 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3169268602 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 199818820 ps |
| CPU time | 8.77 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:56:33 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-13b1a69d-3080-4216-b367-045d21c43e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169268602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3169268602 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3740013366 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 5334279468 ps |
| CPU time | 55.12 seconds |
| Started | Jul 22 07:55:07 PM PDT 24 |
| Finished | Jul 22 07:56:05 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-c5792e10-a146-48fe-94ac-bacdf6757d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740013366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3740013366 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3351001672 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 5164930158 ps |
| CPU time | 88.43 seconds |
| Started | Jul 22 07:55:03 PM PDT 24 |
| Finished | Jul 22 07:56:35 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-f67dc63f-77e0-4711-8076-37410818e2df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351001672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3351001672 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1084893918 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 52349279 ps |
| CPU time | 6.79 seconds |
| Started | Jul 22 07:55:02 PM PDT 24 |
| Finished | Jul 22 07:55:12 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-3228ade8-8269-47fb-a90c-efac11532c85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084893918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.1084893918 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.658557820 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1564074153 ps |
| CPU time | 117.67 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:57:10 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-04d9707c-5ddd-458a-894f-a1791f7110fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658557820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.658557820 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.4262084833 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 2981547325 ps |
| CPU time | 113.23 seconds |
| Started | Jul 22 07:55:13 PM PDT 24 |
| Finished | Jul 22 07:57:07 PM PDT 24 |
| Peak memory | 576920 kb |
| Host | smart-a101adb2-2b45-4b22-950d-6b46cc375be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262084833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.4262084833 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3358655302 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 487712974 ps |
| CPU time | 278.83 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:59:52 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-f367392a-a30f-44bd-b04a-6110941c587d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358655302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.3358655302 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1036629515 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 850750515 ps |
| CPU time | 138.43 seconds |
| Started | Jul 22 07:55:13 PM PDT 24 |
| Finished | Jul 22 07:57:33 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-9184c79c-78ee-4556-930c-7f661678e225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036629515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1036629515 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1847613721 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 101943900 ps |
| CPU time | 14.36 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:55:28 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-5001032d-d0d5-4505-956f-5ff3c546cb54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847613721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1847613721 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3579678879 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 473581594 ps |
| CPU time | 46.8 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:56:00 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-d8ffb176-0447-48c2-ace9-90bbdc02f001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579678879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3579678879 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3105659981 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 267155460 ps |
| CPU time | 24.45 seconds |
| Started | Jul 22 07:55:17 PM PDT 24 |
| Finished | Jul 22 07:55:42 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5edc9de2-332b-4a74-bb4e-5eeaa9621213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105659981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3105659981 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.73078702 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 253670249 ps |
| CPU time | 11.14 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:35 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-ebfe88f7-c623-4afb-ab73-9eeb84b46636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73078702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.73078702 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.1615412446 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 952902695 ps |
| CPU time | 31.37 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:55:45 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-c9182555-a4f7-45f6-be94-db8d65317335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615412446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1615412446 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3081869049 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 104648205277 ps |
| CPU time | 1072.5 seconds |
| Started | Jul 22 07:55:13 PM PDT 24 |
| Finished | Jul 22 08:13:07 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-aad3225c-cf40-462f-aa5c-35bb9dcff396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081869049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3081869049 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.96786025 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 63007724831 ps |
| CPU time | 1032.72 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 08:12:26 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-50685412-7775-4ff9-8d5f-43d8a9eba9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96786025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.96786025 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3483929107 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 205562872 ps |
| CPU time | 19.51 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:43 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-230d22e7-0d11-460d-aeae-dfb90ceaab77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483929107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.3483929107 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.3684712960 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 367299765 ps |
| CPU time | 24.43 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:48 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-45fc7c82-1e67-4051-839d-6a20a0f623f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684712960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3684712960 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.2408171297 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 54450468 ps |
| CPU time | 6.57 seconds |
| Started | Jul 22 07:56:52 PM PDT 24 |
| Finished | Jul 22 07:57:00 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-51ba3c4c-15e9-4043-bd27-3b952eb79edd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408171297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2408171297 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.967027278 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 7341915491 ps |
| CPU time | 75.21 seconds |
| Started | Jul 22 07:55:14 PM PDT 24 |
| Finished | Jul 22 07:56:30 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-7e334123-42ff-474e-a694-52f158e78ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967027278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.967027278 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.753049666 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 6189860370 ps |
| CPU time | 109.66 seconds |
| Started | Jul 22 07:55:13 PM PDT 24 |
| Finished | Jul 22 07:57:04 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-aff5dfa5-b3cb-40c5-b7fc-94c48a247cf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753049666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.753049666 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.357652547 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 45860988 ps |
| CPU time | 5.91 seconds |
| Started | Jul 22 07:55:14 PM PDT 24 |
| Finished | Jul 22 07:55:21 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-5f33ac4c-5188-4df0-b056-1b15b062c7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357652547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .357652547 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.107351384 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 6115286996 ps |
| CPU time | 200.56 seconds |
| Started | Jul 22 07:55:23 PM PDT 24 |
| Finished | Jul 22 07:58:45 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-12746c55-236b-45b5-843a-ce96623905be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107351384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.107351384 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3900163977 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 8114664294 ps |
| CPU time | 283.73 seconds |
| Started | Jul 22 07:55:11 PM PDT 24 |
| Finished | Jul 22 07:59:56 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-861758b9-a2c7-4634-837c-1719dede1f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900163977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3900163977 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1529042604 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1557060652 ps |
| CPU time | 137.06 seconds |
| Started | Jul 22 07:56:52 PM PDT 24 |
| Finished | Jul 22 07:59:11 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-8cd80d83-12d2-4e07-adf7-46987e9fbe1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529042604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1529042604 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1707467132 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 113018936 ps |
| CPU time | 47.3 seconds |
| Started | Jul 22 07:55:23 PM PDT 24 |
| Finished | Jul 22 07:56:12 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-6cc66797-0737-45b4-bc8a-3dbdbbf9a941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707467132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.1707467132 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2200885905 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 498183958 ps |
| CPU time | 21.85 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:45 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-c995f9c1-e2f8-47ea-8d5f-1530fdb0fd2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200885905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2200885905 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.366142197 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 1070755040 ps |
| CPU time | 78.37 seconds |
| Started | Jul 22 07:55:21 PM PDT 24 |
| Finished | Jul 22 07:56:40 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-05cde10d-eb17-40d2-93c9-f0dfb91d1ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366142197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device. 366142197 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1466996515 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 44709093950 ps |
| CPU time | 755.31 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 08:07:59 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-f8bdd475-10b5-4509-bcfa-256e149201b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466996515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.1466996515 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.4284913917 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 812726909 ps |
| CPU time | 31.33 seconds |
| Started | Jul 22 07:55:24 PM PDT 24 |
| Finished | Jul 22 07:55:57 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-1261fd02-c24c-4bac-97f3-eefcde932eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284913917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.4284913917 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2963558615 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 1210958287 ps |
| CPU time | 39.05 seconds |
| Started | Jul 22 07:57:31 PM PDT 24 |
| Finished | Jul 22 07:58:11 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-36baf53f-7adb-47d5-aa1f-5be7fbec6ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963558615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2963558615 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3124525323 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 1421004047 ps |
| CPU time | 48.46 seconds |
| Started | Jul 22 07:55:23 PM PDT 24 |
| Finished | Jul 22 07:56:13 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-4487feba-3d0a-4b39-ae67-7cf2bec91e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124525323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3124525323 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3507316985 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 83475791852 ps |
| CPU time | 918.28 seconds |
| Started | Jul 22 07:55:24 PM PDT 24 |
| Finished | Jul 22 08:10:44 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-9037f5d5-f0d0-433f-831e-e62b15364cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507316985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3507316985 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2924188495 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 53759184563 ps |
| CPU time | 820.47 seconds |
| Started | Jul 22 07:55:42 PM PDT 24 |
| Finished | Jul 22 08:09:25 PM PDT 24 |
| Peak memory | 576872 kb |
| Host | smart-f11adb31-9f60-44ea-b2bb-17e304732161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924188495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2924188495 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2633071091 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 227911277 ps |
| CPU time | 22.14 seconds |
| Started | Jul 22 07:55:21 PM PDT 24 |
| Finished | Jul 22 07:55:45 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-b1e8f7e1-e69e-4351-924f-51f2ff3d1b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633071091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2633071091 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.2436696918 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 91215638 ps |
| CPU time | 9.64 seconds |
| Started | Jul 22 07:55:23 PM PDT 24 |
| Finished | Jul 22 07:55:34 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-427a90cf-feac-472c-9dc1-ca3b08a77c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436696918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2436696918 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.4081273322 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 242813765 ps |
| CPU time | 10.48 seconds |
| Started | Jul 22 07:55:12 PM PDT 24 |
| Finished | Jul 22 07:55:24 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-ac06f8d1-7431-4b16-9486-5f84b6cde7cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081273322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.4081273322 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3831802336 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 9589849861 ps |
| CPU time | 101.19 seconds |
| Started | Jul 22 07:55:24 PM PDT 24 |
| Finished | Jul 22 07:57:07 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-3f96f454-7ee6-4c57-a2c9-df7ce04a7593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831802336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3831802336 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1265434076 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 5787158055 ps |
| CPU time | 93.94 seconds |
| Started | Jul 22 07:55:23 PM PDT 24 |
| Finished | Jul 22 07:56:59 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-776b4183-0b34-42a2-93dc-c240cd25086d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265434076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1265434076 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2895311047 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 58483795 ps |
| CPU time | 6.9 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:31 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-d0278e3e-cb45-434c-873f-ba872fcddca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895311047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.2895311047 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3255267087 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 115065382 ps |
| CPU time | 12.99 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:36 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-78d8dbd9-5d3b-40dd-b06a-18e38ee08e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255267087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3255267087 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1802280167 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 3465190889 ps |
| CPU time | 126.87 seconds |
| Started | Jul 22 07:55:21 PM PDT 24 |
| Finished | Jul 22 07:57:29 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-bf62bd7b-85b2-4773-8407-03064ec2e6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802280167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1802280167 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.530018864 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 1617713389 ps |
| CPU time | 255.85 seconds |
| Started | Jul 22 07:55:24 PM PDT 24 |
| Finished | Jul 22 07:59:41 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-ee716c23-dcbe-474a-b615-a47cbab03af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530018864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.530018864 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1692244705 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 57583655 ps |
| CPU time | 19.09 seconds |
| Started | Jul 22 07:55:42 PM PDT 24 |
| Finished | Jul 22 07:56:02 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-7550cc3e-73a2-41bd-a3a9-0e8be8cec712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692244705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1692244705 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2906229553 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 215038963 ps |
| CPU time | 12.33 seconds |
| Started | Jul 22 07:55:22 PM PDT 24 |
| Finished | Jul 22 07:55:36 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-259b87d5-10b3-418c-a967-4815e1214a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906229553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2906229553 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.2944684543 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 482668209 ps |
| CPU time | 52.02 seconds |
| Started | Jul 22 07:55:54 PM PDT 24 |
| Finished | Jul 22 07:56:48 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-e035cbf5-ad11-4838-8861-2f0a6f336bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944684543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2944684543 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2337201785 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 36132796910 ps |
| CPU time | 621.07 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 08:06:19 PM PDT 24 |
| Peak memory | 577016 kb |
| Host | smart-b0f5af78-77fa-4960-95b1-dc1312a96799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337201785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.2337201785 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.176406123 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 76302637 ps |
| CPU time | 9.29 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 07:56:06 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-4044c47a-5fe2-4e5b-98fb-08d2c52f07c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176406123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .176406123 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.2784420905 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 1491687780 ps |
| CPU time | 47.22 seconds |
| Started | Jul 22 07:55:58 PM PDT 24 |
| Finished | Jul 22 07:56:47 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-9f931381-5523-4607-a193-135ca5b07c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784420905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.2784420905 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.2179177509 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 487337623 ps |
| CPU time | 41.04 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 07:56:38 PM PDT 24 |
| Peak memory | 576156 kb |
| Host | smart-27725edd-0697-4888-bc24-7ea43c8acd6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179177509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2179177509 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3769608278 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 7774598138 ps |
| CPU time | 77.35 seconds |
| Started | Jul 22 07:58:33 PM PDT 24 |
| Finished | Jul 22 07:59:51 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-65ed96e2-c7ce-4998-b7ce-aefca3e77735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769608278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3769608278 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3396093622 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 24959088294 ps |
| CPU time | 425.59 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 08:03:03 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-041dd6a2-aa50-418d-b97e-f79a23791094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396093622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3396093622 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1336764993 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 399107551 ps |
| CPU time | 35.35 seconds |
| Started | Jul 22 07:55:58 PM PDT 24 |
| Finished | Jul 22 07:56:35 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-e7d4030a-eff3-4032-aa31-a87ee8d5f36d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336764993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1336764993 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1476354696 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 80562087 ps |
| CPU time | 9.13 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 07:56:06 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-a5101012-edf7-4c0c-82d7-0bf046696702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476354696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1476354696 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.2446616171 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 232992611 ps |
| CPU time | 9.36 seconds |
| Started | Jul 22 07:55:45 PM PDT 24 |
| Finished | Jul 22 07:55:55 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-aafd174f-6441-4a02-a330-a64db31fe11d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446616171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.2446616171 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1451885740 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 7563099345 ps |
| CPU time | 77.79 seconds |
| Started | Jul 22 07:55:40 PM PDT 24 |
| Finished | Jul 22 07:56:58 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-bad8dff2-c4bf-441d-a53e-f60cd52ab52a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451885740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1451885740 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3148454439 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 6005144577 ps |
| CPU time | 102.57 seconds |
| Started | Jul 22 07:55:58 PM PDT 24 |
| Finished | Jul 22 07:57:42 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-3732d502-16a9-4f0f-bb14-4915a561ca94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148454439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.3148454439 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.41405194 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 50925406 ps |
| CPU time | 6.68 seconds |
| Started | Jul 22 07:55:40 PM PDT 24 |
| Finished | Jul 22 07:55:47 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-f314bd11-99b1-4774-9a81-8876d900ed45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41405194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays.41405194 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.1903304066 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 10893818513 ps |
| CPU time | 394.41 seconds |
| Started | Jul 22 07:55:58 PM PDT 24 |
| Finished | Jul 22 08:02:34 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-05ea891a-462f-425d-8444-261b41c4b035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903304066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.1903304066 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3402538951 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 2742924602 ps |
| CPU time | 226.84 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 07:59:45 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-77939009-b927-49fa-ba13-a0ee6e91a85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402538951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3402538951 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.4197265175 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2956701090 ps |
| CPU time | 467.2 seconds |
| Started | Jul 22 07:55:58 PM PDT 24 |
| Finished | Jul 22 08:03:46 PM PDT 24 |
| Peak memory | 577124 kb |
| Host | smart-36f52f47-f8b2-457c-9da8-5f1966fe59dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197265175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.4197265175 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.791119473 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 17538533337 ps |
| CPU time | 725.51 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 08:08:02 PM PDT 24 |
| Peak memory | 578060 kb |
| Host | smart-e61caff3-fce7-4b8b-8599-4de349482e80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791119473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.791119473 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.2231578371 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 1318602274 ps |
| CPU time | 56.27 seconds |
| Started | Jul 22 07:55:57 PM PDT 24 |
| Finished | Jul 22 07:56:55 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-7a16368d-e55f-4cc4-b2c4-a588aa7ceb83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231578371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.2231578371 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1439872607 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 801981208 ps |
| CPU time | 38.87 seconds |
| Started | Jul 22 07:56:01 PM PDT 24 |
| Finished | Jul 22 07:56:41 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-128a7934-28b4-48c3-b3b7-fbdf31cb1e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439872607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1439872607 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2148112415 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 136612553272 ps |
| CPU time | 2650.3 seconds |
| Started | Jul 22 07:55:57 PM PDT 24 |
| Finished | Jul 22 08:40:09 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-577db913-2d25-42dd-be18-69d9db5b8771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148112415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2148112415 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.149100475 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 171640776 ps |
| CPU time | 20.8 seconds |
| Started | Jul 22 07:56:33 PM PDT 24 |
| Finished | Jul 22 07:56:55 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-ee743902-ecc1-4c03-89ca-c2bda9df3464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149100475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr .149100475 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3526013296 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 510990704 ps |
| CPU time | 21.45 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 07:56:17 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-281f16c9-65bd-4018-927b-69998697ba35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526013296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3526013296 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.1775562792 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 812553849 ps |
| CPU time | 30.9 seconds |
| Started | Jul 22 07:55:57 PM PDT 24 |
| Finished | Jul 22 07:56:29 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-22c0ae72-ec52-4dba-a6aa-92eccab1fdd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775562792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1775562792 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2006159355 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 52995722844 ps |
| CPU time | 575.33 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 08:05:33 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-d089550f-3c6f-4200-bf01-bcceec1a1472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006159355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2006159355 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.943267153 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 44173180129 ps |
| CPU time | 786.02 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 08:09:05 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-9c8c9420-ab12-4b27-9f42-f406161b9b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943267153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.943267153 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3539343122 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 374037152 ps |
| CPU time | 34.94 seconds |
| Started | Jul 22 07:55:57 PM PDT 24 |
| Finished | Jul 22 07:56:33 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-1d4fea18-a664-4512-9fb1-53ec42680430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539343122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3539343122 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.2053368943 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 2019540132 ps |
| CPU time | 57.7 seconds |
| Started | Jul 22 07:55:54 PM PDT 24 |
| Finished | Jul 22 07:56:53 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-9527974c-7aa6-4789-826f-e6963a1a7577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053368943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2053368943 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.1757578882 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 229189002 ps |
| CPU time | 9.22 seconds |
| Started | Jul 22 07:55:59 PM PDT 24 |
| Finished | Jul 22 07:56:09 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-2b11a9ab-1618-4fdf-82c9-8f45a7d70afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757578882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1757578882 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.913767013 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 6222979556 ps |
| CPU time | 68.82 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 07:57:07 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-b5a65f95-8dbf-4795-b975-854e489f092f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913767013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.913767013 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.318403082 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 5750254357 ps |
| CPU time | 94.87 seconds |
| Started | Jul 22 07:55:54 PM PDT 24 |
| Finished | Jul 22 07:57:30 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-b87f18c3-e078-4c25-be98-cd43013222d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318403082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.318403082 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3756550633 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 48124906 ps |
| CPU time | 6.78 seconds |
| Started | Jul 22 07:55:54 PM PDT 24 |
| Finished | Jul 22 07:56:02 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-1ff15c84-17ea-4066-8fcb-4d7507eea5ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756550633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3756550633 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.2151922879 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 635593097 ps |
| CPU time | 57.97 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 07:56:56 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-45f5979c-09d5-40a6-a325-1f280cb1d434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151922879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.2151922879 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.185208382 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 1305797240 ps |
| CPU time | 100.79 seconds |
| Started | Jul 22 07:56:33 PM PDT 24 |
| Finished | Jul 22 07:58:15 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-e19d50c4-92be-4d6c-8fb3-e27b56497490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185208382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.185208382 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.35101303 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 14533386164 ps |
| CPU time | 802.08 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 08:09:19 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-085dcc54-5002-4f16-b9d1-32a014cd0c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35101303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_w ith_rand_reset.35101303 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3294056058 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 21449786116 ps |
| CPU time | 994.48 seconds |
| Started | Jul 22 07:55:55 PM PDT 24 |
| Finished | Jul 22 08:12:32 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-63cf57d5-f228-4de0-8b75-5ab74a771092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294056058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.3294056058 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3344346430 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 618613536 ps |
| CPU time | 26.92 seconds |
| Started | Jul 22 07:56:01 PM PDT 24 |
| Finished | Jul 22 07:56:29 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-f6a72f80-ced9-4d04-b970-bd9e3b2613c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344346430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3344346430 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.4222469973 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 2097802004 ps |
| CPU time | 77.88 seconds |
| Started | Jul 22 07:56:16 PM PDT 24 |
| Finished | Jul 22 07:57:35 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-12075ddd-a687-42b1-9779-6371d8b52954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222469973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .4222469973 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2961252120 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 28837515727 ps |
| CPU time | 486.9 seconds |
| Started | Jul 22 07:56:14 PM PDT 24 |
| Finished | Jul 22 08:04:21 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-5c7e5ded-771d-4ba5-b683-7b46f69b830d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961252120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2961252120 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.495425101 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 62550104 ps |
| CPU time | 6.15 seconds |
| Started | Jul 22 07:56:17 PM PDT 24 |
| Finished | Jul 22 07:56:24 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-a2e37203-29ca-4eb0-977d-d8f3c8edafe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495425101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr .495425101 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.786677745 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 222523754 ps |
| CPU time | 17.25 seconds |
| Started | Jul 22 07:56:46 PM PDT 24 |
| Finished | Jul 22 07:57:05 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-8b7d4ffb-29fc-4365-8069-11d351c1238e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786677745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.786677745 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.2056884687 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1605070306 ps |
| CPU time | 52.6 seconds |
| Started | Jul 22 07:55:58 PM PDT 24 |
| Finished | Jul 22 07:56:52 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-75f339b1-f70e-4e16-8363-200b399a8eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056884687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.2056884687 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.4049009916 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 7111309129 ps |
| CPU time | 70.37 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 07:57:23 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-a7ae0356-33e8-4759-bf7d-52e4ad7235dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049009916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.4049009916 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3941952779 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 12141811244 ps |
| CPU time | 211.7 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 07:59:44 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-182a9720-bc9b-40e1-a8bc-c1fb54440f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941952779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3941952779 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.683957853 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 238378813 ps |
| CPU time | 23.3 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 07:56:37 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-b2a5306b-f5a8-40c6-a02b-b09d353ef6ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683957853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.683957853 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2541588817 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 183289311 ps |
| CPU time | 16.06 seconds |
| Started | Jul 22 07:57:28 PM PDT 24 |
| Finished | Jul 22 07:57:46 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-14674a74-7425-412d-99a0-9cd124d39b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541588817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2541588817 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.2422582738 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 45156799 ps |
| CPU time | 6.78 seconds |
| Started | Jul 22 07:55:59 PM PDT 24 |
| Finished | Jul 22 07:56:07 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-962d5dbc-c435-4e97-aa74-b17132d6bcd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422582738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2422582738 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.4238152891 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 8687090085 ps |
| CPU time | 95.62 seconds |
| Started | Jul 22 07:56:03 PM PDT 24 |
| Finished | Jul 22 07:57:40 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-539ec592-8d67-4c11-823c-2be8df6546b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238152891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.4238152891 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.321825116 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 3477157283 ps |
| CPU time | 58.48 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 07:56:57 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-3f990851-00b8-4c68-bbef-07814a4f89fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321825116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.321825116 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2098789938 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 48209987 ps |
| CPU time | 6.09 seconds |
| Started | Jul 22 07:55:56 PM PDT 24 |
| Finished | Jul 22 07:56:04 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-9e8a0e09-dcd0-4563-a16a-0e47dd1f1de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098789938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2098789938 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.1403581518 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 18356242303 ps |
| CPU time | 601.07 seconds |
| Started | Jul 22 08:04:54 PM PDT 24 |
| Finished | Jul 22 08:14:57 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-aa398afe-ad78-4a45-a8a5-72e27bed448d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403581518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1403581518 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.46205312 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 8643362892 ps |
| CPU time | 313.79 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 08:01:28 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-87cbe6a6-7a55-4f7c-83f2-584a2f028360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46205312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.46205312 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3468405650 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3587424615 ps |
| CPU time | 267.78 seconds |
| Started | Jul 22 08:04:53 PM PDT 24 |
| Finished | Jul 22 08:09:26 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-27a8dcb7-1a1a-4e34-9950-c10c1bb16b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468405650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3468405650 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1770457382 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 8086651536 ps |
| CPU time | 417.13 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 08:03:11 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-90810c2c-5786-46df-a7f3-ed56ed75eef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770457382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1770457382 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2628464807 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 256340276 ps |
| CPU time | 33.96 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 07:56:45 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-f4a16f26-8715-453c-9562-2f7ae7ecec6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628464807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2628464807 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.2681035605 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1457990324 ps |
| CPU time | 73.24 seconds |
| Started | Jul 22 07:56:10 PM PDT 24 |
| Finished | Jul 22 07:57:24 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-764b9867-2de6-4820-9a06-85a021e32ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681035605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .2681035605 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1279015256 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 10339962026 ps |
| CPU time | 168.52 seconds |
| Started | Jul 22 07:56:17 PM PDT 24 |
| Finished | Jul 22 07:59:07 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-28ef06d9-eb4e-4272-9b9f-9987b3c0c68a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279015256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.1279015256 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2460204798 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 103938295 ps |
| CPU time | 12.95 seconds |
| Started | Jul 22 07:56:12 PM PDT 24 |
| Finished | Jul 22 07:56:25 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-c39ae39e-1bea-4274-9adf-46460f70a073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460204798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2460204798 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3116599586 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 445708831 ps |
| CPU time | 36.26 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 07:56:50 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d9a211f9-2d00-4fb4-a04b-4c3731302852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116599586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3116599586 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1040089374 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 1737617937 ps |
| CPU time | 61.18 seconds |
| Started | Jul 22 07:58:35 PM PDT 24 |
| Finished | Jul 22 07:59:37 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-7bd4c8d2-c19c-491f-bcec-4f22f76d7bc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040089374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1040089374 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.462118436 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 28600812846 ps |
| CPU time | 318.83 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 08:01:33 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-57977091-0db5-4b3e-8a3f-c12351d82790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462118436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.462118436 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2697170990 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 47579831730 ps |
| CPU time | 816.26 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 08:09:48 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-55b74e99-ebdb-4353-9af4-7a35b039207e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697170990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2697170990 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2913412137 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 554982794 ps |
| CPU time | 46.29 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 07:56:58 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-f64ec9c2-71af-41e0-b950-491c8712e47a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913412137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.2913412137 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.579229142 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 72593898 ps |
| CPU time | 8.67 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 07:56:20 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-3391a7c5-9881-4d24-b5a9-3c0bbec801d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579229142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.579229142 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.1251087174 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 177916429 ps |
| CPU time | 8.67 seconds |
| Started | Jul 22 07:56:17 PM PDT 24 |
| Finished | Jul 22 07:56:26 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-0b866c42-dd9d-49d4-ade7-267f1583542a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251087174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1251087174 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1941343534 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 9839123691 ps |
| CPU time | 93.31 seconds |
| Started | Jul 22 07:58:56 PM PDT 24 |
| Finished | Jul 22 08:00:33 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-289213b1-ce9b-4004-b60b-63dd3e378c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941343534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1941343534 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1572333318 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 5494189132 ps |
| CPU time | 87.67 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 07:57:41 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-d06e59e0-0a8c-40c2-ab43-d7523d883ebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572333318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1572333318 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1603569993 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 53575370 ps |
| CPU time | 6.32 seconds |
| Started | Jul 22 07:56:12 PM PDT 24 |
| Finished | Jul 22 07:56:19 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-061bfcbe-61e8-4b2e-b8f0-b6b9b06d1e15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603569993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1603569993 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.695869042 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3043977614 ps |
| CPU time | 115.26 seconds |
| Started | Jul 22 08:04:40 PM PDT 24 |
| Finished | Jul 22 08:06:36 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-33dd9c4f-c91e-4bd2-b19d-155e0daf398d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695869042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.695869042 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2553319506 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 22204677521 ps |
| CPU time | 725.7 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 08:08:18 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-2b5027e7-ee75-4cb9-bdfd-0ad442ba971a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553319506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2553319506 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3486566322 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 5350120223 ps |
| CPU time | 370.72 seconds |
| Started | Jul 22 07:56:11 PM PDT 24 |
| Finished | Jul 22 08:02:23 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-14455ed7-7926-4b29-b313-bd9b88ad1275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486566322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3486566322 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.170360883 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 10814845042 ps |
| CPU time | 586.07 seconds |
| Started | Jul 22 07:57:52 PM PDT 24 |
| Finished | Jul 22 08:07:42 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-9b53ba40-1551-4b1c-a885-bae8a443dc20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170360883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_reset_error.170360883 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3043765516 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 509174943 ps |
| CPU time | 21.93 seconds |
| Started | Jul 22 07:56:14 PM PDT 24 |
| Finished | Jul 22 07:56:36 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-cb2d737c-8cf6-4586-abde-918c35d1e9ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043765516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3043765516 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2927000171 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 137040299 ps |
| CPU time | 9.67 seconds |
| Started | Jul 22 07:56:21 PM PDT 24 |
| Finished | Jul 22 07:56:32 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-7b7e2727-65f1-4ef3-a455-f14b765ca130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927000171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2927000171 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1195147275 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 114891400144 ps |
| CPU time | 2148.09 seconds |
| Started | Jul 22 07:56:23 PM PDT 24 |
| Finished | Jul 22 08:32:13 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-4b2301b1-f330-4ea2-9748-79787de04316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195147275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.1195147275 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3759991238 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 554175689 ps |
| CPU time | 24.84 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:56:48 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-f6960455-1bb9-4d4d-9044-112ad9a4623b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759991238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3759991238 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.404864874 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 428915472 ps |
| CPU time | 33.97 seconds |
| Started | Jul 22 07:56:28 PM PDT 24 |
| Finished | Jul 22 07:57:03 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-15e8d189-73f7-4960-8ccc-b2aaed3266e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404864874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.404864874 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.3556532714 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 769065816 ps |
| CPU time | 24.43 seconds |
| Started | Jul 22 08:04:53 PM PDT 24 |
| Finished | Jul 22 08:05:20 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-78af001d-d056-4eec-a8d2-83d5713c6787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556532714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3556532714 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.209594586 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 103713219861 ps |
| CPU time | 1040.88 seconds |
| Started | Jul 22 07:56:27 PM PDT 24 |
| Finished | Jul 22 08:13:49 PM PDT 24 |
| Peak memory | 576900 kb |
| Host | smart-27058003-3c44-48e3-b055-4a3bbc55cdf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209594586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.209594586 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1204618801 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 26208531994 ps |
| CPU time | 474.59 seconds |
| Started | Jul 22 07:56:24 PM PDT 24 |
| Finished | Jul 22 08:04:20 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-bc2be500-37c0-4d11-8f40-0ac8788c1b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204618801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1204618801 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3460168833 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 429281480 ps |
| CPU time | 37.35 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:57:01 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-9c87019b-c8a2-4115-b8e0-31762d3a15bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460168833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3460168833 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1335980702 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 471967300 ps |
| CPU time | 15.6 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:56:40 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-abf45030-2d88-4064-8a6a-2085de17dcca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335980702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1335980702 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.2521528394 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 239551160 ps |
| CPU time | 9.19 seconds |
| Started | Jul 22 07:56:13 PM PDT 24 |
| Finished | Jul 22 07:56:23 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-2019bc51-6313-407d-8863-e886e0cc6b3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521528394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.2521528394 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3337330796 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 8066546844 ps |
| CPU time | 88.82 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:57:53 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-4f9f8501-ab4b-491e-9052-3b73701287b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337330796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.3337330796 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1861831789 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 6346487414 ps |
| CPU time | 111.67 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:58:15 PM PDT 24 |
| Peak memory | 574892 kb |
| Host | smart-4e10b899-74e4-4621-b056-697322e7f8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861831789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1861831789 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1561145132 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 51352612 ps |
| CPU time | 7.01 seconds |
| Started | Jul 22 07:56:12 PM PDT 24 |
| Finished | Jul 22 07:56:20 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-a7d7764e-69a4-4d8e-aa08-ad0d67ba1c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561145132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1561145132 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1773916544 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 1439256405 ps |
| CPU time | 124.22 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:58:27 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-83b8beb5-4cbe-4db9-879f-4ad46707781a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773916544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1773916544 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3753328298 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 4609627607 ps |
| CPU time | 180.19 seconds |
| Started | Jul 22 07:56:27 PM PDT 24 |
| Finished | Jul 22 07:59:28 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-7792a0fa-266c-44d6-9a97-3ba8b5a17d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753328298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3753328298 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2857428864 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 208168205 ps |
| CPU time | 173 seconds |
| Started | Jul 22 08:04:54 PM PDT 24 |
| Finished | Jul 22 08:07:50 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-de53ab4e-ed2c-460f-9f8c-b197fb9982be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857428864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.2857428864 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.451038320 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 322204490 ps |
| CPU time | 41.16 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:57:05 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-6092671a-d3fc-450e-911c-f13b5fc36081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451038320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.451038320 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.220881095 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 7253809000 ps |
| CPU time | 482.18 seconds |
| Started | Jul 22 07:43:34 PM PDT 24 |
| Finished | Jul 22 07:51:37 PM PDT 24 |
| Peak memory | 638076 kb |
| Host | smart-ba8ff4da-7f39-4a64-b255-9788b1020cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220881095 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.220881095 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.2094257844 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 5051930446 ps |
| CPU time | 629.33 seconds |
| Started | Jul 22 07:43:26 PM PDT 24 |
| Finished | Jul 22 07:53:56 PM PDT 24 |
| Peak memory | 597532 kb |
| Host | smart-f08ff193-86e8-4603-b016-1c61c04ae79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094257844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2094257844 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1367941493 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 27478020928 ps |
| CPU time | 3912.72 seconds |
| Started | Jul 22 07:43:06 PM PDT 24 |
| Finished | Jul 22 08:48:20 PM PDT 24 |
| Peak memory | 594300 kb |
| Host | smart-293aedb5-9e13-4b1d-94dd-aa52b15ab953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367941493 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1367941493 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1921706809 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4288406054 ps |
| CPU time | 282.48 seconds |
| Started | Jul 22 07:43:13 PM PDT 24 |
| Finished | Jul 22 07:47:57 PM PDT 24 |
| Peak memory | 600456 kb |
| Host | smart-f0bd9014-dc3a-40d0-8a5c-76ab17955c58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921706809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1921706809 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3639014942 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 2954417426 ps |
| CPU time | 122.96 seconds |
| Started | Jul 22 07:43:16 PM PDT 24 |
| Finished | Jul 22 07:45:20 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-bf627f7a-35d6-4bf2-81ea-efbf40c627bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639014942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3639014942 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1379508418 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 43501951545 ps |
| CPU time | 720.75 seconds |
| Started | Jul 22 07:43:18 PM PDT 24 |
| Finished | Jul 22 07:55:20 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-c8223b83-2043-4545-b14e-af8a1fe07156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379508418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.1379508418 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2828618008 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 269247855 ps |
| CPU time | 24.68 seconds |
| Started | Jul 22 07:43:25 PM PDT 24 |
| Finished | Jul 22 07:43:50 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-268c4d74-c008-4287-ac73-8b68c318cda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828618008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .2828618008 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.88708152 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 59661670 ps |
| CPU time | 8.56 seconds |
| Started | Jul 22 07:44:05 PM PDT 24 |
| Finished | Jul 22 07:44:16 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-f602f357-e081-4968-bb08-07b238480ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88708152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.88708152 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2600312098 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 871355255 ps |
| CPU time | 38.62 seconds |
| Started | Jul 22 07:43:13 PM PDT 24 |
| Finished | Jul 22 07:43:53 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-906685c2-ae08-4b5b-8b81-1bdb838cefa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600312098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2600312098 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1102452336 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 97241242934 ps |
| CPU time | 1052.4 seconds |
| Started | Jul 22 07:43:14 PM PDT 24 |
| Finished | Jul 22 08:00:48 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-1dbc2c79-e1fc-469c-8557-8b4110313e47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102452336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1102452336 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2201663682 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 11351184161 ps |
| CPU time | 192.42 seconds |
| Started | Jul 22 07:43:35 PM PDT 24 |
| Finished | Jul 22 07:46:49 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-ceaa9aef-7caa-4303-a350-c524e2994f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201663682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2201663682 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3222371209 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 105662914 ps |
| CPU time | 10.94 seconds |
| Started | Jul 22 07:44:04 PM PDT 24 |
| Finished | Jul 22 07:44:18 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-14e75de1-70ef-4919-8048-e926370d076f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222371209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.3222371209 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.171086771 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 1630841945 ps |
| CPU time | 51.67 seconds |
| Started | Jul 22 07:43:24 PM PDT 24 |
| Finished | Jul 22 07:44:16 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-a48e9d21-e164-4317-9d86-1f0de61cca6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171086771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.171086771 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.3472712869 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 173780415 ps |
| CPU time | 8.17 seconds |
| Started | Jul 22 07:43:06 PM PDT 24 |
| Finished | Jul 22 07:43:15 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-cc760d86-64ff-47db-a9f6-e56f0c57a111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472712869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3472712869 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3733167996 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 8976733014 ps |
| CPU time | 94.85 seconds |
| Started | Jul 22 07:43:09 PM PDT 24 |
| Finished | Jul 22 07:44:45 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-df04dd63-55ec-4d14-af7f-837b11130c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733167996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3733167996 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2833244074 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 6704875989 ps |
| CPU time | 116.86 seconds |
| Started | Jul 22 07:43:46 PM PDT 24 |
| Finished | Jul 22 07:45:44 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-61466f4f-6962-48cd-8fe3-a948c2a66e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833244074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2833244074 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2562630346 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 37276852 ps |
| CPU time | 5.98 seconds |
| Started | Jul 22 07:43:35 PM PDT 24 |
| Finished | Jul 22 07:43:43 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-31676f52-0025-4808-bd99-11e34dc3c11f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562630346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2562630346 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.82691733 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 6919282 ps |
| CPU time | 3.74 seconds |
| Started | Jul 22 07:43:53 PM PDT 24 |
| Finished | Jul 22 07:43:57 PM PDT 24 |
| Peak memory | 566400 kb |
| Host | smart-add199fe-ed77-453d-902d-4ff224c59d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82691733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.82691733 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.313420705 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 2952960774 ps |
| CPU time | 228.55 seconds |
| Started | Jul 22 07:43:44 PM PDT 24 |
| Finished | Jul 22 07:47:33 PM PDT 24 |
| Peak memory | 576956 kb |
| Host | smart-84e7c9f5-d33d-4f24-a07c-37bd10a81f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313420705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.313420705 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3976306119 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 6017481746 ps |
| CPU time | 555.63 seconds |
| Started | Jul 22 07:44:11 PM PDT 24 |
| Finished | Jul 22 07:53:29 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-710ad3eb-c6c4-4810-b894-742ee6ba2fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976306119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3976306119 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3845097820 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 102533697 ps |
| CPU time | 15.35 seconds |
| Started | Jul 22 07:43:14 PM PDT 24 |
| Finished | Jul 22 07:43:31 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-b63cbe1a-23d4-4a1c-9e0e-56e7fa241fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845097820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3845097820 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1947330599 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 276599899 ps |
| CPU time | 10.87 seconds |
| Started | Jul 22 07:56:23 PM PDT 24 |
| Finished | Jul 22 07:56:36 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-f9cf1221-cac3-4297-b28c-cc92f8a290c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947330599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1947330599 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2513523718 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 185637200 ps |
| CPU time | 22.03 seconds |
| Started | Jul 22 07:56:40 PM PDT 24 |
| Finished | Jul 22 07:57:03 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-cfd8ae31-13f0-4746-8a2d-f557db630017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513523718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2513523718 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2160162031 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 2099961505 ps |
| CPU time | 70.09 seconds |
| Started | Jul 22 08:04:54 PM PDT 24 |
| Finished | Jul 22 08:06:06 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-349d19b0-9bd9-47a0-9db8-dbc3c0f35ff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160162031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2160162031 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.1325092519 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 590415712 ps |
| CPU time | 21.61 seconds |
| Started | Jul 22 07:56:29 PM PDT 24 |
| Finished | Jul 22 07:56:51 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-ad7fd5ed-542b-406b-82f7-9c2bdf2cdcc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325092519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1325092519 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.4008468642 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 88705634468 ps |
| CPU time | 949.49 seconds |
| Started | Jul 22 07:56:24 PM PDT 24 |
| Finished | Jul 22 08:12:15 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-36b9644e-0c12-466d-a12d-37aaa1c06088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008468642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.4008468642 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.2357297603 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 11439098944 ps |
| CPU time | 193.24 seconds |
| Started | Jul 22 07:56:24 PM PDT 24 |
| Finished | Jul 22 07:59:39 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-041ae27a-fd9c-4178-ba85-557fac823ef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357297603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.2357297603 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3239956061 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 472754769 ps |
| CPU time | 44.99 seconds |
| Started | Jul 22 07:56:27 PM PDT 24 |
| Finished | Jul 22 07:57:13 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-12108447-7b00-4ca6-84d1-b99a840153a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239956061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3239956061 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.1689917881 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 2364847906 ps |
| CPU time | 61.64 seconds |
| Started | Jul 22 08:04:53 PM PDT 24 |
| Finished | Jul 22 08:05:57 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-a647381b-efe5-49d4-87e5-cf8abb63bacc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689917881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1689917881 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.3812197681 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 45904568 ps |
| CPU time | 6.03 seconds |
| Started | Jul 22 07:56:22 PM PDT 24 |
| Finished | Jul 22 07:56:30 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-d3bb769f-ce68-4585-931e-fca56a23ba10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812197681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3812197681 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1871107013 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 8920863955 ps |
| CPU time | 91.94 seconds |
| Started | Jul 22 07:56:24 PM PDT 24 |
| Finished | Jul 22 07:57:58 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-65392d1c-288b-48df-b81c-f68bae09476f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871107013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1871107013 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.220053815 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 6129475716 ps |
| CPU time | 107.96 seconds |
| Started | Jul 22 07:56:25 PM PDT 24 |
| Finished | Jul 22 07:58:14 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-296a657c-a897-4999-a492-7701fcb2ae64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220053815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.220053815 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2036013657 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 44695572 ps |
| CPU time | 6.49 seconds |
| Started | Jul 22 07:56:29 PM PDT 24 |
| Finished | Jul 22 07:56:37 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-62df7666-4889-48ba-b656-92ed973dfd3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036013657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2036013657 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.3818075965 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 814122389 ps |
| CPU time | 69.66 seconds |
| Started | Jul 22 07:56:41 PM PDT 24 |
| Finished | Jul 22 07:57:52 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-75eab25a-f8cc-4d05-837b-61380da91903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818075965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3818075965 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.63108702 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1951917587 ps |
| CPU time | 129.26 seconds |
| Started | Jul 22 07:56:40 PM PDT 24 |
| Finished | Jul 22 07:58:50 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-ef4e7b87-163f-4633-b59f-a52c99db0fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63108702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.63108702 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.4046509448 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 78833931 ps |
| CPU time | 70.19 seconds |
| Started | Jul 22 07:57:37 PM PDT 24 |
| Finished | Jul 22 07:58:48 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-6d72e2a6-c612-4033-829c-205bcc7dc20e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046509448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.4046509448 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3115870846 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 573699002 ps |
| CPU time | 157.7 seconds |
| Started | Jul 22 07:56:39 PM PDT 24 |
| Finished | Jul 22 07:59:17 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-091f60e1-49c5-4b01-a2d8-de2eae831003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115870846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3115870846 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2855209050 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 1127971213 ps |
| CPU time | 45.26 seconds |
| Started | Jul 22 08:04:48 PM PDT 24 |
| Finished | Jul 22 08:05:36 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-4c9fa044-a40c-425f-bd66-187ab3fa593d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855209050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2855209050 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.342652120 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 122783105 ps |
| CPU time | 11.82 seconds |
| Started | Jul 22 07:56:41 PM PDT 24 |
| Finished | Jul 22 07:56:53 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-f26fd028-ccd9-48fa-b014-632eeba5806c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342652120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 342652120 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1314858743 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 120095070275 ps |
| CPU time | 2022.15 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 08:30:51 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-5618e9f6-c37d-49cb-acdd-fcc7a716d84f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314858743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1314858743 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1360612992 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 188179379 ps |
| CPU time | 18.79 seconds |
| Started | Jul 22 07:56:59 PM PDT 24 |
| Finished | Jul 22 07:57:19 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-c30519d6-c6dd-41db-b577-9ab1d71ab217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360612992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.1360612992 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.1984106496 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 1591026364 ps |
| CPU time | 53.28 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:59:14 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-c496c072-5250-447b-89e2-ed5c20834c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984106496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1984106496 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2116219006 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 2062195546 ps |
| CPU time | 74.66 seconds |
| Started | Jul 22 07:56:40 PM PDT 24 |
| Finished | Jul 22 07:57:55 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-7ef2376d-8a05-4201-812d-d2113240868d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116219006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2116219006 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1314395624 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 69205716071 ps |
| CPU time | 719.86 seconds |
| Started | Jul 22 07:56:41 PM PDT 24 |
| Finished | Jul 22 08:08:42 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-fb9bc376-ac1f-4ea2-a3c3-5d4649f5d4a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314395624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1314395624 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3813224939 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 13308205126 ps |
| CPU time | 230.77 seconds |
| Started | Jul 22 07:56:41 PM PDT 24 |
| Finished | Jul 22 08:00:33 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-979ae47b-6c3c-4679-9929-3ed55cd859ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813224939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3813224939 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2850689081 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 539934326 ps |
| CPU time | 46.56 seconds |
| Started | Jul 22 07:56:42 PM PDT 24 |
| Finished | Jul 22 07:57:29 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-9f0f2504-9149-48cc-b52b-c9b3fdf93204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850689081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.2850689081 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2148758081 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 360367437 ps |
| CPU time | 27.13 seconds |
| Started | Jul 22 07:56:57 PM PDT 24 |
| Finished | Jul 22 07:57:25 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-4863e0fd-d365-40c2-8d8c-a3097d015af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148758081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2148758081 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3778413628 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 46914160 ps |
| CPU time | 6.3 seconds |
| Started | Jul 22 07:56:39 PM PDT 24 |
| Finished | Jul 22 07:56:46 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-7e42aa2e-cf86-46fd-98ee-ec8bc869440f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778413628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3778413628 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2398165661 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 10164672243 ps |
| CPU time | 105.62 seconds |
| Started | Jul 22 07:56:40 PM PDT 24 |
| Finished | Jul 22 07:58:27 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-eb050089-4067-48fc-a32a-c84187cd8192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398165661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2398165661 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.1614502138 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 5053141802 ps |
| CPU time | 82.54 seconds |
| Started | Jul 22 07:56:42 PM PDT 24 |
| Finished | Jul 22 07:58:05 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-78a224df-9d00-4b0f-b698-79d26099c8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614502138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.1614502138 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.1116154048 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 56828272 ps |
| CPU time | 6.95 seconds |
| Started | Jul 22 07:56:41 PM PDT 24 |
| Finished | Jul 22 07:56:49 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-640d3b8e-b43f-42b6-a061-65554ae7ec66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116154048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.1116154048 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.72217540 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 7838084398 ps |
| CPU time | 271.55 seconds |
| Started | Jul 22 07:59:07 PM PDT 24 |
| Finished | Jul 22 08:03:40 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-c9f0b4f7-0c8e-4ab8-b96a-7b315bc2fc0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72217540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.72217540 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2075419737 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 2058201711 ps |
| CPU time | 141.05 seconds |
| Started | Jul 22 07:56:56 PM PDT 24 |
| Finished | Jul 22 07:59:18 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-a921552a-1a87-47f7-bf98-d1a6553f12cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075419737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2075419737 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.726958388 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 111155705 ps |
| CPU time | 27.52 seconds |
| Started | Jul 22 07:58:43 PM PDT 24 |
| Finished | Jul 22 07:59:13 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-9254424b-c728-4103-9211-2843d7363c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726958388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_ with_rand_reset.726958388 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.4203623897 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 6483222379 ps |
| CPU time | 401.8 seconds |
| Started | Jul 22 07:57:01 PM PDT 24 |
| Finished | Jul 22 08:03:43 PM PDT 24 |
| Peak memory | 577024 kb |
| Host | smart-1fff5d05-87fb-4c9b-9ae3-1147ff691825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203623897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.4203623897 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2145155132 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 60773622 ps |
| CPU time | 6.18 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 07:57:14 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-5794bcf8-e062-4b07-b1c7-ae13bed34d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145155132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2145155132 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2708824075 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 2403718866 ps |
| CPU time | 109.99 seconds |
| Started | Jul 22 07:57:01 PM PDT 24 |
| Finished | Jul 22 07:58:52 PM PDT 24 |
| Peak memory | 576956 kb |
| Host | smart-0abdeca6-1e2d-4513-b7cd-81bedc29bfc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708824075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2708824075 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1933354845 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 120501226175 ps |
| CPU time | 2116.81 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 08:32:26 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-2fb951f9-88c2-48f1-8cbf-fe34a6d08aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933354845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1933354845 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1700989062 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 348328593 ps |
| CPU time | 34.08 seconds |
| Started | Jul 22 07:56:56 PM PDT 24 |
| Finished | Jul 22 07:57:31 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-5672da97-27e9-49d5-8b83-7dbb2a17daf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700989062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.1700989062 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1843697087 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2136157968 ps |
| CPU time | 74.57 seconds |
| Started | Jul 22 07:56:56 PM PDT 24 |
| Finished | Jul 22 07:58:12 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-18460b5e-dfb7-446f-9965-931ccf673a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843697087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1843697087 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.688912657 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 457289137 ps |
| CPU time | 39.54 seconds |
| Started | Jul 22 07:57:06 PM PDT 24 |
| Finished | Jul 22 07:57:46 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-f196a1e7-609b-44a9-88b9-fa577a81f358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688912657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.688912657 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2733903343 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 104989471037 ps |
| CPU time | 1108.2 seconds |
| Started | Jul 22 07:56:57 PM PDT 24 |
| Finished | Jul 22 08:15:26 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-bf0c2167-6abf-4bd0-a6d9-52293a7ac108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733903343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2733903343 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1359069496 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 55628980969 ps |
| CPU time | 894.6 seconds |
| Started | Jul 22 07:57:01 PM PDT 24 |
| Finished | Jul 22 08:11:56 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-46564f86-42b0-4f58-8c51-5d8649e97555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359069496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1359069496 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.784470434 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 476744681 ps |
| CPU time | 42 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 07:57:50 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-daffd8de-a660-4448-aaa3-5a8532a0cc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784470434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_dela ys.784470434 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.3089116351 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 898186838 ps |
| CPU time | 27.86 seconds |
| Started | Jul 22 07:56:58 PM PDT 24 |
| Finished | Jul 22 07:57:27 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-d1014b2f-e493-415e-8073-5fe6e276e945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089116351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3089116351 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.771474343 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 179415402 ps |
| CPU time | 8.34 seconds |
| Started | Jul 22 07:57:06 PM PDT 24 |
| Finished | Jul 22 07:57:15 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-172c16c6-f805-450b-8b9e-a5e63e292937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771474343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.771474343 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.835861248 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 6922684685 ps |
| CPU time | 74.96 seconds |
| Started | Jul 22 07:56:57 PM PDT 24 |
| Finished | Jul 22 07:58:13 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-57f3751e-8959-4999-a23e-0246b6635c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835861248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.835861248 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.806704958 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 6140352597 ps |
| CPU time | 95.12 seconds |
| Started | Jul 22 07:57:02 PM PDT 24 |
| Finished | Jul 22 07:58:37 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-7feaa846-3c69-4a80-a750-37d8b5595c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806704958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.806704958 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1165304661 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 46466568 ps |
| CPU time | 6.46 seconds |
| Started | Jul 22 07:56:58 PM PDT 24 |
| Finished | Jul 22 07:57:06 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-319ff7dd-bee0-4a42-a5f8-d01408beddd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165304661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1165304661 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2550266032 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 5042671973 ps |
| CPU time | 213.26 seconds |
| Started | Jul 22 07:56:58 PM PDT 24 |
| Finished | Jul 22 08:00:32 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-3712648b-052a-40de-b5e3-43dde43c06b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550266032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2550266032 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2743393569 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 3793050508 ps |
| CPU time | 123.22 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 07:59:12 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-7363cd3a-64fd-4ab8-aae2-bf4043a895ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743393569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2743393569 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2328016306 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2921234813 ps |
| CPU time | 142.4 seconds |
| Started | Jul 22 07:57:00 PM PDT 24 |
| Finished | Jul 22 07:59:23 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-7ad6b020-1348-4874-8978-6a6045ce1b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328016306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2328016306 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3871005621 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 137183093 ps |
| CPU time | 18.5 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 07:57:27 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-5159ab59-2cc9-4777-a057-0ae0150ec4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871005621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3871005621 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.2880199149 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 536148561 ps |
| CPU time | 39.91 seconds |
| Started | Jul 22 07:56:56 PM PDT 24 |
| Finished | Jul 22 07:57:36 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-10997ef1-6744-47c7-98fa-6b462dbee210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880199149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2880199149 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.705356614 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 106298098794 ps |
| CPU time | 2072.04 seconds |
| Started | Jul 22 07:56:59 PM PDT 24 |
| Finished | Jul 22 08:31:32 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-784d6b86-2b79-451f-8389-501d938142b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705356614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.705356614 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3265071327 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 201271670 ps |
| CPU time | 22.8 seconds |
| Started | Jul 22 07:56:58 PM PDT 24 |
| Finished | Jul 22 07:57:21 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-f56fd00a-2b5f-4988-a422-7c2fb06d6918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265071327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3265071327 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.273891829 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 2259782803 ps |
| CPU time | 74.82 seconds |
| Started | Jul 22 07:56:56 PM PDT 24 |
| Finished | Jul 22 07:58:11 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-af883a38-e2ec-4967-97b5-8141175b0eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273891829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.273891829 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1932492446 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 1601718261 ps |
| CPU time | 49.23 seconds |
| Started | Jul 22 07:57:01 PM PDT 24 |
| Finished | Jul 22 07:57:51 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-849d5595-cafb-4064-ada6-7bb164eeaf81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932492446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1932492446 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1332380541 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 92566941607 ps |
| CPU time | 1047.93 seconds |
| Started | Jul 22 07:57:05 PM PDT 24 |
| Finished | Jul 22 08:14:34 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-e030fdf5-a171-42ec-ad7b-0270f18db05e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332380541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1332380541 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.510365883 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 3416633829 ps |
| CPU time | 58.08 seconds |
| Started | Jul 22 07:57:00 PM PDT 24 |
| Finished | Jul 22 07:57:59 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-a963aadc-eaee-44ca-a7fa-df5a9d581538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510365883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.510365883 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.702976917 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 501351891 ps |
| CPU time | 42.61 seconds |
| Started | Jul 22 07:57:07 PM PDT 24 |
| Finished | Jul 22 07:57:51 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-b85e4d66-9955-4296-9abe-2f98af1a6400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702976917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.702976917 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.655841408 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 2312152074 ps |
| CPU time | 62.31 seconds |
| Started | Jul 22 07:56:58 PM PDT 24 |
| Finished | Jul 22 07:58:01 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-38659485-f7e8-4f5c-af94-0ffe735839e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655841408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.655841408 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2988611141 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 45868345 ps |
| CPU time | 5.53 seconds |
| Started | Jul 22 07:57:06 PM PDT 24 |
| Finished | Jul 22 07:57:13 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-60e50322-ea4a-4b56-9999-e25308ce6f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988611141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2988611141 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.185701196 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 9859013496 ps |
| CPU time | 93.59 seconds |
| Started | Jul 22 07:58:43 PM PDT 24 |
| Finished | Jul 22 08:00:18 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-698345a9-f56a-478f-9a48-353baa1c73d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185701196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.185701196 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.345264472 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 4163533845 ps |
| CPU time | 65.84 seconds |
| Started | Jul 22 07:57:01 PM PDT 24 |
| Finished | Jul 22 07:58:08 PM PDT 24 |
| Peak memory | 574824 kb |
| Host | smart-1c416607-f0b0-47ee-aed3-4d2d7ef2d3b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345264472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.345264472 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.539012583 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 55349666 ps |
| CPU time | 6.59 seconds |
| Started | Jul 22 07:56:57 PM PDT 24 |
| Finished | Jul 22 07:57:04 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-81b8052e-6890-4ac1-9262-33e18a9c6649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539012583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .539012583 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.4003013279 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 1627178036 ps |
| CPU time | 118.45 seconds |
| Started | Jul 22 07:57:01 PM PDT 24 |
| Finished | Jul 22 07:59:00 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-f7e7221a-b780-417f-8792-bc2591fd27e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003013279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.4003013279 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2165238480 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 6548778143 ps |
| CPU time | 212.6 seconds |
| Started | Jul 22 07:57:09 PM PDT 24 |
| Finished | Jul 22 08:00:42 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-1896a684-a7d2-4054-ac64-ad703a977da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165238480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2165238480 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4029402945 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 145569869 ps |
| CPU time | 37.35 seconds |
| Started | Jul 22 07:56:56 PM PDT 24 |
| Finished | Jul 22 07:57:34 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-4b92116c-06f9-4456-a74c-032e28361b6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029402945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.4029402945 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3231443069 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 1256928284 ps |
| CPU time | 49.62 seconds |
| Started | Jul 22 07:56:57 PM PDT 24 |
| Finished | Jul 22 07:57:47 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-2552d867-b0f6-4b74-95ec-adb58b49e29b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231443069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3231443069 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1925987951 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 782321862 ps |
| CPU time | 51.76 seconds |
| Started | Jul 22 07:57:14 PM PDT 24 |
| Finished | Jul 22 07:58:07 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-44d60ecf-554c-490d-a88c-43dec7ffb3d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925987951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1925987951 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3655353659 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 179853035045 ps |
| CPU time | 3053.21 seconds |
| Started | Jul 22 07:57:14 PM PDT 24 |
| Finished | Jul 22 08:48:08 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-c27847a7-6046-4362-a7ca-a4750aa17919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655353659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.3655353659 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1821283256 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 156973175 ps |
| CPU time | 17.56 seconds |
| Started | Jul 22 07:57:10 PM PDT 24 |
| Finished | Jul 22 07:57:29 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-2c8839a7-6491-41eb-9a71-901ec00c8b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821283256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.1821283256 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.3220414277 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 352502896 ps |
| CPU time | 27.87 seconds |
| Started | Jul 22 07:57:24 PM PDT 24 |
| Finished | Jul 22 07:57:53 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-8ece5b81-c1af-4cc3-8070-9955cd470aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220414277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3220414277 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.4265736749 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 287869217 ps |
| CPU time | 28.77 seconds |
| Started | Jul 22 07:57:13 PM PDT 24 |
| Finished | Jul 22 07:57:42 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-05f33b22-8531-4b3d-957c-b9067ccf18a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265736749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.4265736749 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3400435366 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 59145570006 ps |
| CPU time | 598.1 seconds |
| Started | Jul 22 07:57:15 PM PDT 24 |
| Finished | Jul 22 08:07:14 PM PDT 24 |
| Peak memory | 577012 kb |
| Host | smart-300f61ad-82b8-4595-b9d5-a7ddf7b2b4a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400435366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3400435366 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.178190653 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 60241406078 ps |
| CPU time | 1108.68 seconds |
| Started | Jul 22 07:57:12 PM PDT 24 |
| Finished | Jul 22 08:15:42 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-70daee37-ce35-47a5-b5ad-aac2169d6aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178190653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.178190653 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3751410425 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 388822805 ps |
| CPU time | 33.59 seconds |
| Started | Jul 22 07:57:11 PM PDT 24 |
| Finished | Jul 22 07:57:46 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-9961d1d2-de48-41c0-8d6e-ec47f2b622f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751410425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.3751410425 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2318348585 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 346792732 ps |
| CPU time | 12.66 seconds |
| Started | Jul 22 07:57:11 PM PDT 24 |
| Finished | Jul 22 07:57:25 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-024d5835-e4d1-4dcf-9107-c600128e21de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318348585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2318348585 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.3492340022 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 42362417 ps |
| CPU time | 5.92 seconds |
| Started | Jul 22 07:57:11 PM PDT 24 |
| Finished | Jul 22 07:57:18 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-0ed7687b-1a12-4fec-8a95-c0f039c46fbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492340022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3492340022 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3585236462 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 5318591733 ps |
| CPU time | 53.48 seconds |
| Started | Jul 22 07:57:10 PM PDT 24 |
| Finished | Jul 22 07:58:04 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-94901a88-9963-4cab-8935-894ea7a070a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585236462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3585236462 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1924063212 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 4804898401 ps |
| CPU time | 79.81 seconds |
| Started | Jul 22 07:57:13 PM PDT 24 |
| Finished | Jul 22 07:58:34 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-ef8e4a5f-a4db-4eb4-b763-1c423660bdd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924063212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1924063212 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2155964470 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 50278110 ps |
| CPU time | 5.95 seconds |
| Started | Jul 22 07:57:16 PM PDT 24 |
| Finished | Jul 22 07:57:22 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-7544149d-d0db-4e71-a2b2-f7c3555a36d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155964470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.2155964470 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.1668752932 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 2883159723 ps |
| CPU time | 227.07 seconds |
| Started | Jul 22 07:57:09 PM PDT 24 |
| Finished | Jul 22 08:00:57 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-755198b6-1a57-4573-ba91-6cba122e24c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668752932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1668752932 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1479503741 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 1789115704 ps |
| CPU time | 149.85 seconds |
| Started | Jul 22 07:57:24 PM PDT 24 |
| Finished | Jul 22 07:59:55 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-bdde8db9-f4c0-443d-9905-83a2cab95cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479503741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1479503741 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1454047490 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 17332958803 ps |
| CPU time | 814.26 seconds |
| Started | Jul 22 07:57:13 PM PDT 24 |
| Finished | Jul 22 08:10:48 PM PDT 24 |
| Peak memory | 576976 kb |
| Host | smart-0b5d4101-17c0-4a0a-be14-f74d8e6942f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454047490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.1454047490 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.4268874744 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 2188676707 ps |
| CPU time | 317.12 seconds |
| Started | Jul 22 07:57:24 PM PDT 24 |
| Finished | Jul 22 08:02:42 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-835d6513-89fe-4904-a49e-65835eb106a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268874744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.4268874744 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.4041882208 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 87874233 ps |
| CPU time | 7.15 seconds |
| Started | Jul 22 07:57:24 PM PDT 24 |
| Finished | Jul 22 07:57:32 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-877f9030-c641-4c3a-ba80-4e5b4d77dfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041882208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.4041882208 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3449069890 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 1894986681 ps |
| CPU time | 62.78 seconds |
| Started | Jul 22 07:57:14 PM PDT 24 |
| Finished | Jul 22 07:58:17 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-20f9b8f9-eee2-4da2-a1b0-595a252347cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449069890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3449069890 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2739220773 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 139413739532 ps |
| CPU time | 2465.57 seconds |
| Started | Jul 22 07:57:12 PM PDT 24 |
| Finished | Jul 22 08:38:19 PM PDT 24 |
| Peak memory | 577088 kb |
| Host | smart-eba72688-fa84-416b-8af0-8e2ba357a2de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739220773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2739220773 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.219940407 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 812831781 ps |
| CPU time | 35.58 seconds |
| Started | Jul 22 07:57:26 PM PDT 24 |
| Finished | Jul 22 07:58:02 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-78722169-a1d2-48e1-86ea-ede7bf895277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219940407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .219940407 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.679017985 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 227723625 ps |
| CPU time | 9.46 seconds |
| Started | Jul 22 07:57:25 PM PDT 24 |
| Finished | Jul 22 07:57:35 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-29f595e2-f15c-4cb7-a601-46b127203033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679017985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.679017985 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2206411454 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 200093767 ps |
| CPU time | 19.54 seconds |
| Started | Jul 22 07:57:14 PM PDT 24 |
| Finished | Jul 22 07:57:34 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-7129d18a-ab33-4e60-a053-b2f6d1a3c807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206411454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2206411454 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.4279319496 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 47747840422 ps |
| CPU time | 497.64 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 08:07:33 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-12d52d8a-a88c-46df-a83a-84c28e43b885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279319496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4279319496 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3038578444 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 20335873233 ps |
| CPU time | 340.22 seconds |
| Started | Jul 22 07:57:11 PM PDT 24 |
| Finished | Jul 22 08:02:52 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-970130de-103a-4616-a885-5a67ad9a3b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038578444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3038578444 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3023107460 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 41025464 ps |
| CPU time | 6.78 seconds |
| Started | Jul 22 07:57:10 PM PDT 24 |
| Finished | Jul 22 07:57:18 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-d50b1744-c5be-4e74-9e32-24799ef70a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023107460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3023107460 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.3114022871 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 570977117 ps |
| CPU time | 41.93 seconds |
| Started | Jul 22 07:57:24 PM PDT 24 |
| Finished | Jul 22 07:58:07 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-b6962930-c48f-4f44-9ae5-637b8813ea0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114022871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.3114022871 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.2765338938 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 249654639 ps |
| CPU time | 10.45 seconds |
| Started | Jul 22 07:57:13 PM PDT 24 |
| Finished | Jul 22 07:57:24 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-7ec9158c-130b-4824-88aa-a0750e602c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765338938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2765338938 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3472607884 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 8874754517 ps |
| CPU time | 82.41 seconds |
| Started | Jul 22 07:57:15 PM PDT 24 |
| Finished | Jul 22 07:58:38 PM PDT 24 |
| Peak memory | 574916 kb |
| Host | smart-c6d78b75-59ac-4ddf-8672-f57051518f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472607884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3472607884 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.4202452468 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 3701919576 ps |
| CPU time | 63.99 seconds |
| Started | Jul 22 07:57:13 PM PDT 24 |
| Finished | Jul 22 07:58:17 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-4b19b311-731b-4a86-b143-20224b11317a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202452468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.4202452468 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1082213574 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 39673095 ps |
| CPU time | 6.43 seconds |
| Started | Jul 22 07:57:12 PM PDT 24 |
| Finished | Jul 22 07:57:19 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-f720ecb8-eb54-4227-8289-1c60aac6160f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082213574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1082213574 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.2318605123 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 9828187471 ps |
| CPU time | 322.95 seconds |
| Started | Jul 22 07:57:29 PM PDT 24 |
| Finished | Jul 22 08:02:53 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-e882208d-ed3d-4abc-84f3-6008891cc8a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318605123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2318605123 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.283989028 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 13670174022 ps |
| CPU time | 410.03 seconds |
| Started | Jul 22 07:57:28 PM PDT 24 |
| Finished | Jul 22 08:04:20 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-86d409a7-1dc7-4a02-acbb-bdaaa6620edd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283989028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.283989028 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.927050235 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 1521482883 ps |
| CPU time | 210.56 seconds |
| Started | Jul 22 07:57:27 PM PDT 24 |
| Finished | Jul 22 08:00:58 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-44cd2595-994a-485e-93e5-f324abe78c6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927050235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.927050235 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2298358501 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 770667017 ps |
| CPU time | 224.51 seconds |
| Started | Jul 22 07:57:33 PM PDT 24 |
| Finished | Jul 22 08:01:18 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-eec1a612-87e2-477a-aef0-9d4b2712c624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298358501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2298358501 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1403551213 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 638160196 ps |
| CPU time | 31.09 seconds |
| Started | Jul 22 07:57:26 PM PDT 24 |
| Finished | Jul 22 07:57:58 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-a7593e3d-365a-408e-8d24-c7822ba61983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403551213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1403551213 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.4232439630 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 1257386015 ps |
| CPU time | 79.33 seconds |
| Started | Jul 22 07:57:26 PM PDT 24 |
| Finished | Jul 22 07:58:46 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-e1e2e0ff-e728-4bdf-baa8-68214f6ddfea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232439630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .4232439630 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.842258749 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 48219659573 ps |
| CPU time | 924.68 seconds |
| Started | Jul 22 07:57:30 PM PDT 24 |
| Finished | Jul 22 08:12:55 PM PDT 24 |
| Peak memory | 576984 kb |
| Host | smart-e631997d-d318-4667-a764-623839ee0ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842258749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.842258749 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1411584094 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 566720134 ps |
| CPU time | 26.23 seconds |
| Started | Jul 22 07:57:39 PM PDT 24 |
| Finished | Jul 22 07:58:08 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-54d72010-4055-40df-b68a-e71172a865ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411584094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1411584094 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.3623674137 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 1988539011 ps |
| CPU time | 67.35 seconds |
| Started | Jul 22 07:57:28 PM PDT 24 |
| Finished | Jul 22 07:58:36 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-f4fb544a-0221-4c3c-ad3b-431dacfbabae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623674137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3623674137 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.2768401002 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 1947216284 ps |
| CPU time | 64.13 seconds |
| Started | Jul 22 07:57:26 PM PDT 24 |
| Finished | Jul 22 07:58:31 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-40dd9b60-38ba-46b5-a0e1-9c95ea33e2ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768401002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2768401002 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3011115428 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 11109221591 ps |
| CPU time | 113 seconds |
| Started | Jul 22 07:57:29 PM PDT 24 |
| Finished | Jul 22 07:59:23 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-6f797970-2df0-4a64-99ad-8d92f3509d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011115428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3011115428 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.693135602 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 60292836511 ps |
| CPU time | 1058.5 seconds |
| Started | Jul 22 07:57:29 PM PDT 24 |
| Finished | Jul 22 08:15:09 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-b912af60-8d8b-49f6-9111-d734c8f423b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693135602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.693135602 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1419945657 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 391069779 ps |
| CPU time | 33.15 seconds |
| Started | Jul 22 07:57:26 PM PDT 24 |
| Finished | Jul 22 07:58:00 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-81d41731-9d35-4edc-8c4a-e47ed3abcde7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419945657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.1419945657 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.887459131 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 437623403 ps |
| CPU time | 32.74 seconds |
| Started | Jul 22 07:57:28 PM PDT 24 |
| Finished | Jul 22 07:58:01 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-e98cfabd-1840-4ab7-bd99-de565820c2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887459131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.887459131 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1602475123 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 159049587 ps |
| CPU time | 7.67 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 07:59:23 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-97f84cba-9d37-4971-b693-cd722b21cb79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602475123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1602475123 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3225400917 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 7563179751 ps |
| CPU time | 73.78 seconds |
| Started | Jul 22 07:57:31 PM PDT 24 |
| Finished | Jul 22 07:58:47 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-45746312-6f86-4c6c-9ef2-05b341031816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225400917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3225400917 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2507530048 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 4006220845 ps |
| CPU time | 64.74 seconds |
| Started | Jul 22 07:57:33 PM PDT 24 |
| Finished | Jul 22 07:58:40 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-7a52cad7-d030-4303-8585-58c3743a71c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507530048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2507530048 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.195721525 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 38608887 ps |
| CPU time | 5.9 seconds |
| Started | Jul 22 07:57:28 PM PDT 24 |
| Finished | Jul 22 07:57:35 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-eba55159-3afa-40dd-80cf-79a6b0aed0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195721525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .195721525 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.1682066137 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 5710271893 ps |
| CPU time | 205.54 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 08:01:09 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-4d4b147f-96b0-4ec2-8b90-1064c2ffaaca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682066137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1682066137 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3007982832 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 803455798 ps |
| CPU time | 60.21 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 07:58:43 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-fa5e801b-73bb-4146-a0bd-049ecbb5fe15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007982832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3007982832 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2500180003 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 4731207356 ps |
| CPU time | 238.04 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 08:01:40 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-307e59ee-c78c-4a86-a035-7aeb194b26df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500180003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2500180003 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1932747803 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 64913608 ps |
| CPU time | 5.73 seconds |
| Started | Jul 22 07:57:27 PM PDT 24 |
| Finished | Jul 22 07:57:34 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-36fd87e0-6054-4ec7-8c58-ccd60ad8ebdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932747803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1932747803 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2297093897 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 928004986 ps |
| CPU time | 74.83 seconds |
| Started | Jul 22 07:57:41 PM PDT 24 |
| Finished | Jul 22 07:58:59 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-a561b17d-29e7-470c-9bea-8612fe6e272b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297093897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .2297093897 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4121770582 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 61275694554 ps |
| CPU time | 999.3 seconds |
| Started | Jul 22 07:58:55 PM PDT 24 |
| Finished | Jul 22 08:15:39 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-ca672af2-a1de-466e-84ba-6ca793cdbb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121770582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.4121770582 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3857155990 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 1149411845 ps |
| CPU time | 46.68 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 07:58:28 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-54eeb7ea-91b6-4612-862c-e26617b30c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857155990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3857155990 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2252416736 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 597114256 ps |
| CPU time | 53.55 seconds |
| Started | Jul 22 07:57:43 PM PDT 24 |
| Finished | Jul 22 07:58:40 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-26b08ded-418a-4fdd-9ba6-750f0d95abaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252416736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2252416736 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.4088430169 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 1663695601 ps |
| CPU time | 59.83 seconds |
| Started | Jul 22 07:57:41 PM PDT 24 |
| Finished | Jul 22 07:58:45 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-d057319e-1b67-437c-a8a9-debcf998524c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088430169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.4088430169 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3972710964 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 79815456796 ps |
| CPU time | 832.34 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 08:11:35 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-cafe0197-ac5e-4a55-a5d4-dc1480dc98e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972710964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3972710964 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3641283570 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 3527071427 ps |
| CPU time | 59.79 seconds |
| Started | Jul 22 07:57:41 PM PDT 24 |
| Finished | Jul 22 07:58:45 PM PDT 24 |
| Peak memory | 574888 kb |
| Host | smart-dccb0db9-69cd-4e55-83fb-fe96b2b168ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641283570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3641283570 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2596783624 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 606059253 ps |
| CPU time | 50.62 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 07:58:33 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-500556e7-e6ba-4f81-a2dd-2ce4947164b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596783624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.2596783624 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.1622080898 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1172278123 ps |
| CPU time | 31.68 seconds |
| Started | Jul 22 07:57:41 PM PDT 24 |
| Finished | Jul 22 07:58:16 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-da84c656-bff6-40ea-a1ba-0485ab2f5c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622080898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1622080898 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3043390494 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 250514875 ps |
| CPU time | 9.66 seconds |
| Started | Jul 22 07:57:40 PM PDT 24 |
| Finished | Jul 22 07:57:52 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-e197031c-a1b9-4dd6-b552-a4c219577078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043390494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3043390494 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.362190627 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 5613926903 ps |
| CPU time | 58.34 seconds |
| Started | Jul 22 07:57:39 PM PDT 24 |
| Finished | Jul 22 07:58:40 PM PDT 24 |
| Peak memory | 574956 kb |
| Host | smart-e09f0db2-d559-42fa-9f81-584145640d61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362190627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.362190627 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1827588720 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 5659310202 ps |
| CPU time | 92.25 seconds |
| Started | Jul 22 07:57:42 PM PDT 24 |
| Finished | Jul 22 07:59:17 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-b8d9b15f-b18d-4549-9324-8d8589621286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827588720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.1827588720 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3087087494 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 57904024 ps |
| CPU time | 6.52 seconds |
| Started | Jul 22 07:57:47 PM PDT 24 |
| Finished | Jul 22 07:57:55 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f2b8e09f-1743-42e2-a6ea-79ceaefb26af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087087494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.3087087494 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1350220334 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 12998523285 ps |
| CPU time | 477.92 seconds |
| Started | Jul 22 07:57:42 PM PDT 24 |
| Finished | Jul 22 08:05:43 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-37555595-f2f8-4944-926c-263f4569b93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350220334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1350220334 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2778589290 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 2159212614 ps |
| CPU time | 158.17 seconds |
| Started | Jul 22 07:57:41 PM PDT 24 |
| Finished | Jul 22 08:00:23 PM PDT 24 |
| Peak memory | 577108 kb |
| Host | smart-8ddd6f26-1718-4d63-8865-31912c448b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778589290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2778589290 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.2749515067 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 439035409 ps |
| CPU time | 198.45 seconds |
| Started | Jul 22 07:57:42 PM PDT 24 |
| Finished | Jul 22 08:01:04 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-cea19f92-0dc9-485f-a0e1-ca33b2d81b95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749515067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.2749515067 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1800618621 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 459487009 ps |
| CPU time | 161 seconds |
| Started | Jul 22 07:57:53 PM PDT 24 |
| Finished | Jul 22 08:00:39 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-3f34ff47-8d6d-4fc0-b892-db444b6458e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800618621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1800618621 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.78754256 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 911124255 ps |
| CPU time | 41.55 seconds |
| Started | Jul 22 07:57:43 PM PDT 24 |
| Finished | Jul 22 07:58:28 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-bf4f0cbd-43d1-4f6d-b1c8-8f997e90aa72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78754256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.78754256 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1782483078 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 3178329266 ps |
| CPU time | 126.37 seconds |
| Started | Jul 22 07:57:53 PM PDT 24 |
| Finished | Jul 22 08:00:05 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-7deb54e3-71a3-4027-8cf4-d9dd85a06d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782483078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1782483078 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2839760337 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 46533327293 ps |
| CPU time | 862.03 seconds |
| Started | Jul 22 07:57:53 PM PDT 24 |
| Finished | Jul 22 08:12:20 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-3711a189-1636-43df-8620-d1b466a48005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839760337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.2839760337 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1073098112 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 159643212 ps |
| CPU time | 16.93 seconds |
| Started | Jul 22 07:57:56 PM PDT 24 |
| Finished | Jul 22 07:58:18 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-f8b8ee2e-4199-4264-af39-ad91e6f62bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073098112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.1073098112 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.3827647803 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 393409733 ps |
| CPU time | 34.94 seconds |
| Started | Jul 22 07:57:53 PM PDT 24 |
| Finished | Jul 22 07:58:33 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-67aac277-586f-4aa2-92fb-c13ac7a83780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827647803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.3827647803 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.2484928749 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 295991436 ps |
| CPU time | 26.2 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 07:58:26 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-5870a6cf-c9e9-41e7-86b6-79f1313cfa78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484928749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2484928749 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.92365494 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 101565240748 ps |
| CPU time | 1098.43 seconds |
| Started | Jul 22 07:57:54 PM PDT 24 |
| Finished | Jul 22 08:16:18 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-f8fccd8d-1ac8-47ad-b88a-c56d7def4166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92365494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.92365494 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.2016482354 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 26357089914 ps |
| CPU time | 431.1 seconds |
| Started | Jul 22 07:58:55 PM PDT 24 |
| Finished | Jul 22 08:06:10 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-0f19e224-9fdb-4356-944f-f851fff15d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016482354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.2016482354 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.4176401975 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 164179511 ps |
| CPU time | 17.27 seconds |
| Started | Jul 22 07:57:53 PM PDT 24 |
| Finished | Jul 22 07:58:15 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-8a4946c1-504e-468a-981f-e9ff619a07a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176401975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.4176401975 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1023179859 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 267779203 ps |
| CPU time | 10.71 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 07:58:10 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-297d7aec-6b5f-4cbf-8491-a0a7a1f498f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023179859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1023179859 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.59302933 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 196688952 ps |
| CPU time | 7.82 seconds |
| Started | Jul 22 07:57:54 PM PDT 24 |
| Finished | Jul 22 07:58:07 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-81da6cb8-1101-47bc-9413-b502e87e0f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59302933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.59302933 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1412151346 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 7028934088 ps |
| CPU time | 74.09 seconds |
| Started | Jul 22 07:57:54 PM PDT 24 |
| Finished | Jul 22 07:59:13 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-053fb0e5-a251-4263-bdf8-a0036d7f2992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412151346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1412151346 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3122971880 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 6067713071 ps |
| CPU time | 104.17 seconds |
| Started | Jul 22 07:57:56 PM PDT 24 |
| Finished | Jul 22 07:59:45 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-e8699a92-0f80-4ccc-b555-6d033a3028fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122971880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3122971880 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2396094622 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 45172935 ps |
| CPU time | 6.47 seconds |
| Started | Jul 22 07:57:54 PM PDT 24 |
| Finished | Jul 22 07:58:05 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-858f680b-2088-439b-b07e-08ffb9adce93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396094622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2396094622 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.2860494845 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 1596478140 ps |
| CPU time | 145.76 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 08:00:26 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-1d32efc9-64cc-4608-9717-a993f4230396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860494845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2860494845 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3228059967 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 727621288 ps |
| CPU time | 51.42 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 07:58:51 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-4db2b7df-c60e-4fef-88f9-9fbefa9514b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228059967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3228059967 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.1268350766 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 962271594 ps |
| CPU time | 335.03 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 08:03:35 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-b6cfde80-72c2-4b74-9a49-7c58fbedcda3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268350766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.1268350766 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3268893496 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 226399530 ps |
| CPU time | 64.84 seconds |
| Started | Jul 22 07:57:56 PM PDT 24 |
| Finished | Jul 22 07:59:05 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-00723498-493b-457e-9656-43c2c8cdd0b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268893496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3268893496 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.1183823144 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 177881150 ps |
| CPU time | 24.38 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 07:58:24 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-b015d2ed-717b-4703-973a-b499be46b609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183823144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.1183823144 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.605953676 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 611518569 ps |
| CPU time | 40.49 seconds |
| Started | Jul 22 08:00:01 PM PDT 24 |
| Finished | Jul 22 08:00:44 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-14332a87-94c4-42b3-9fee-efa67852e22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605953676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 605953676 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.766638859 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 17931009412 ps |
| CPU time | 296.85 seconds |
| Started | Jul 22 07:58:10 PM PDT 24 |
| Finished | Jul 22 08:03:08 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-5c8dea85-2f1a-4cad-a55f-abca12dc8161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766638859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_d evice_slow_rsp.766638859 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1831256255 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 43868150 ps |
| CPU time | 7.23 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 07:58:16 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-40d9e40e-314c-4c09-a995-f96063061323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831256255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.1831256255 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.84160629 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 206101278 ps |
| CPU time | 17.54 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 07:58:26 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-22be75b2-c1f6-4421-897d-4b971f407b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84160629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.84160629 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1325379993 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 150330121 ps |
| CPU time | 14.41 seconds |
| Started | Jul 22 07:57:55 PM PDT 24 |
| Finished | Jul 22 07:58:14 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-16adb444-cfb9-4444-9d7e-100cc26b94cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325379993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1325379993 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2562107534 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 6412190071 ps |
| CPU time | 61.3 seconds |
| Started | Jul 22 07:58:00 PM PDT 24 |
| Finished | Jul 22 07:59:03 PM PDT 24 |
| Peak memory | 574920 kb |
| Host | smart-62f8fff8-f795-4188-b89c-6e1fa1af7bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562107534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2562107534 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.733812723 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 7265488889 ps |
| CPU time | 120.57 seconds |
| Started | Jul 22 07:57:54 PM PDT 24 |
| Finished | Jul 22 08:00:00 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-de074af3-747b-41cb-848b-343051d9b071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733812723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.733812723 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.653208648 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 608683154 ps |
| CPU time | 48.79 seconds |
| Started | Jul 22 07:58:00 PM PDT 24 |
| Finished | Jul 22 07:58:51 PM PDT 24 |
| Peak memory | 576876 kb |
| Host | smart-31ba758c-5484-496e-bfec-6356d506e3be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653208648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.653208648 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.657734588 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 1786692678 ps |
| CPU time | 51.04 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 07:58:59 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-b59e612e-4905-4c3c-83ac-6d85fbd04df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657734588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.657734588 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.2633666306 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 209857202 ps |
| CPU time | 8.83 seconds |
| Started | Jul 22 07:57:57 PM PDT 24 |
| Finished | Jul 22 07:58:10 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-170c71c9-99e5-4a4a-9082-21c6bfd2726a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633666306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2633666306 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1666800618 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 8243202799 ps |
| CPU time | 86.24 seconds |
| Started | Jul 22 07:57:56 PM PDT 24 |
| Finished | Jul 22 07:59:27 PM PDT 24 |
| Peak memory | 574896 kb |
| Host | smart-ba7114ce-a85e-42b7-90a3-f0d76f7a8cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666800618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1666800618 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.4243690159 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 5407889643 ps |
| CPU time | 91.29 seconds |
| Started | Jul 22 07:57:54 PM PDT 24 |
| Finished | Jul 22 07:59:31 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-b3a18425-3bf8-4459-9a16-ada048d09810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243690159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.4243690159 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2725855096 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 42448344 ps |
| CPU time | 6.15 seconds |
| Started | Jul 22 07:58:01 PM PDT 24 |
| Finished | Jul 22 07:58:08 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-925ff5a9-dda6-42ff-9bfd-8d368ec92972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725855096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2725855096 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.820081659 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 9309002995 ps |
| CPU time | 325.43 seconds |
| Started | Jul 22 07:59:03 PM PDT 24 |
| Finished | Jul 22 08:04:32 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-ce621539-9548-4364-8b21-59e3116f0b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820081659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.820081659 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3186780567 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 7678516313 ps |
| CPU time | 262.09 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 08:02:30 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-07eb38f5-b627-4592-9cc3-48d8b298cb68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186780567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3186780567 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1149054086 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 2325010192 ps |
| CPU time | 249.86 seconds |
| Started | Jul 22 07:58:09 PM PDT 24 |
| Finished | Jul 22 08:02:20 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-0bf40975-c5ea-4867-b111-6ad7c607221e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149054086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.1149054086 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.35964212 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 4261015774 ps |
| CPU time | 406.22 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 08:04:54 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d114f5c6-61ee-4b93-8c17-8890b747a5ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35964212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_ with_reset_error.35964212 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3194968125 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 170629111 ps |
| CPU time | 23.79 seconds |
| Started | Jul 22 07:58:06 PM PDT 24 |
| Finished | Jul 22 07:58:31 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-6d1536dc-a267-4612-9287-e4b468327872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194968125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3194968125 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1495808985 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 6351130976 ps |
| CPU time | 518.2 seconds |
| Started | Jul 22 07:43:51 PM PDT 24 |
| Finished | Jul 22 07:52:31 PM PDT 24 |
| Peak memory | 638264 kb |
| Host | smart-625f006a-e305-4c51-aa2b-09d64bd61ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495808985 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1495808985 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.1366063259 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 3831861360 ps |
| CPU time | 340.78 seconds |
| Started | Jul 22 07:43:52 PM PDT 24 |
| Finished | Jul 22 07:49:34 PM PDT 24 |
| Peak memory | 599004 kb |
| Host | smart-6772bbd4-8097-4cee-a714-2246032a6088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366063259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1366063259 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.508483932 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 16694249424 ps |
| CPU time | 2184.11 seconds |
| Started | Jul 22 07:44:12 PM PDT 24 |
| Finished | Jul 22 08:20:39 PM PDT 24 |
| Peak memory | 593440 kb |
| Host | smart-7903a32f-c89f-480b-9aa7-e6d0d8d47670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508483932 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.chip_same_csr_outstanding.508483932 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1122853434 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 291025108 ps |
| CPU time | 24.77 seconds |
| Started | Jul 22 07:43:37 PM PDT 24 |
| Finished | Jul 22 07:44:02 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-ac7ccda4-d8a0-4b4b-8a6a-be5781acc28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122853434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 1122853434 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2692352550 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 23205621351 ps |
| CPU time | 390.77 seconds |
| Started | Jul 22 07:43:38 PM PDT 24 |
| Finished | Jul 22 07:50:10 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-3f9512f6-8b17-4f18-abfa-1b74dfd13b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692352550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2692352550 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2424842774 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 1317963794 ps |
| CPU time | 52.66 seconds |
| Started | Jul 22 07:43:38 PM PDT 24 |
| Finished | Jul 22 07:44:31 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-4a15921f-7124-4584-8d47-b547f53fee64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424842774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .2424842774 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1449653730 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 104856037 ps |
| CPU time | 9.65 seconds |
| Started | Jul 22 07:43:39 PM PDT 24 |
| Finished | Jul 22 07:43:49 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-67882b66-d373-42f9-9060-64465ffd77b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449653730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1449653730 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.524594705 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 269074248 ps |
| CPU time | 12.15 seconds |
| Started | Jul 22 07:44:10 PM PDT 24 |
| Finished | Jul 22 07:44:24 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-e09c1052-c4b2-4ade-8b1b-c6215d52d6b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524594705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.524594705 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.558930962 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 14776027229 ps |
| CPU time | 159.68 seconds |
| Started | Jul 22 07:43:39 PM PDT 24 |
| Finished | Jul 22 07:46:19 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-e4911bc2-4f58-4bcc-8248-c1671313b5ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558930962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.558930962 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1110942135 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 53707221226 ps |
| CPU time | 932.21 seconds |
| Started | Jul 22 07:43:36 PM PDT 24 |
| Finished | Jul 22 07:59:09 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-967bc9f2-f7af-4492-8fa3-2299ff9f44ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110942135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1110942135 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2908798480 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 520598557 ps |
| CPU time | 45.7 seconds |
| Started | Jul 22 07:44:12 PM PDT 24 |
| Finished | Jul 22 07:45:00 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-d7729e79-b4b3-4d01-8349-7d284a0f20f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908798480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.2908798480 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.237440118 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1024260622 ps |
| CPU time | 33.27 seconds |
| Started | Jul 22 07:43:36 PM PDT 24 |
| Finished | Jul 22 07:44:11 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-3bc426c6-ff4e-4a4a-b7d5-ad33d1e5e915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237440118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.237440118 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3798069341 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 265719484 ps |
| CPU time | 10.18 seconds |
| Started | Jul 22 07:44:02 PM PDT 24 |
| Finished | Jul 22 07:44:14 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-494bbcc1-8c2b-4fc8-aff2-1538d762b8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798069341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3798069341 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.22833506 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 9999374907 ps |
| CPU time | 96.63 seconds |
| Started | Jul 22 07:44:11 PM PDT 24 |
| Finished | Jul 22 07:45:50 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-6c4b80c0-5a4a-4121-9c94-8a8695658159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.22833506 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1371053620 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 3210469642 ps |
| CPU time | 49.33 seconds |
| Started | Jul 22 07:43:27 PM PDT 24 |
| Finished | Jul 22 07:44:17 PM PDT 24 |
| Peak memory | 574820 kb |
| Host | smart-16ba3d69-df7b-4725-b830-c14c681e52af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371053620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1371053620 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2050816024 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 41877217 ps |
| CPU time | 5.74 seconds |
| Started | Jul 22 07:43:27 PM PDT 24 |
| Finished | Jul 22 07:43:34 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-af41cf81-e7b5-4fcc-92da-7626f8220480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050816024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .2050816024 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1417836012 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 9295163062 ps |
| CPU time | 324.28 seconds |
| Started | Jul 22 07:43:40 PM PDT 24 |
| Finished | Jul 22 07:49:05 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-3c6ed7ce-d8f7-4b60-b93c-eae16ba26835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417836012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1417836012 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.770574032 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 1314797727 ps |
| CPU time | 86.83 seconds |
| Started | Jul 22 07:43:36 PM PDT 24 |
| Finished | Jul 22 07:45:04 PM PDT 24 |
| Peak memory | 576876 kb |
| Host | smart-7ebbb4a4-cddb-42a5-b573-c6b20fb21598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770574032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.770574032 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2007429814 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 3696981601 ps |
| CPU time | 544.57 seconds |
| Started | Jul 22 07:44:17 PM PDT 24 |
| Finished | Jul 22 07:53:23 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-68c89aec-6a8d-4b0c-94b8-e77ab2cd8582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007429814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.2007429814 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2081688292 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 8713537623 ps |
| CPU time | 501.3 seconds |
| Started | Jul 22 07:43:54 PM PDT 24 |
| Finished | Jul 22 07:52:16 PM PDT 24 |
| Peak memory | 578076 kb |
| Host | smart-12593d57-84a9-47d0-8680-ed7b8d388574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081688292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.2081688292 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2249246524 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 626038639 ps |
| CPU time | 27.79 seconds |
| Started | Jul 22 07:43:38 PM PDT 24 |
| Finished | Jul 22 07:44:06 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-957b47d9-238a-4a42-8a43-fd170053b28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249246524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2249246524 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2896019026 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 297142393 ps |
| CPU time | 27.71 seconds |
| Started | Jul 22 07:58:39 PM PDT 24 |
| Finished | Jul 22 07:59:09 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-2fce5124-0510-4084-87cb-9cf4b6fb491a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896019026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2896019026 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2423883707 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 64230044183 ps |
| CPU time | 1109.7 seconds |
| Started | Jul 22 07:58:09 PM PDT 24 |
| Finished | Jul 22 08:16:39 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-a86c3d40-9513-4edd-bfea-bc2da8834ad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423883707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2423883707 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.4102262639 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 532852943 ps |
| CPU time | 21.18 seconds |
| Started | Jul 22 07:58:05 PM PDT 24 |
| Finished | Jul 22 07:58:28 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-c5823a12-64df-4831-ac84-2ad93d3e63a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102262639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.4102262639 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2103366731 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 165642000 ps |
| CPU time | 16.18 seconds |
| Started | Jul 22 07:58:08 PM PDT 24 |
| Finished | Jul 22 07:58:25 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-13296b50-b690-4790-a1fc-6ac3c767cb7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103366731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2103366731 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.839880221 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 766756481 ps |
| CPU time | 32.06 seconds |
| Started | Jul 22 07:58:10 PM PDT 24 |
| Finished | Jul 22 07:58:43 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-93b10797-3615-4794-92d9-358b19deb63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839880221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.839880221 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.4292453427 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 5149147478 ps |
| CPU time | 55.13 seconds |
| Started | Jul 22 07:58:10 PM PDT 24 |
| Finished | Jul 22 07:59:06 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-d913b4ca-a618-4ac0-bb3b-4f265bdd4b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292453427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.4292453427 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2792381736 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 20106434786 ps |
| CPU time | 333.7 seconds |
| Started | Jul 22 07:58:09 PM PDT 24 |
| Finished | Jul 22 08:03:44 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-da8afa9e-01e1-4174-b5d8-f0ac3e439669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792381736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2792381736 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.916684573 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 504466525 ps |
| CPU time | 44.89 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 07:58:53 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-87986837-6371-4b0c-9af1-98142ed69460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916684573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.916684573 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.2293913653 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 1765363304 ps |
| CPU time | 52.26 seconds |
| Started | Jul 22 07:58:06 PM PDT 24 |
| Finished | Jul 22 07:58:59 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-a6fc495a-bed7-41e9-be25-a438271963c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293913653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2293913653 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1644219420 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 50547542 ps |
| CPU time | 5.65 seconds |
| Started | Jul 22 07:58:07 PM PDT 24 |
| Finished | Jul 22 07:58:14 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-be7fce66-6009-4ac6-b480-22b48e968dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644219420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1644219420 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1149760148 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 10666657019 ps |
| CPU time | 104.48 seconds |
| Started | Jul 22 07:58:09 PM PDT 24 |
| Finished | Jul 22 07:59:55 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-2342b185-6a3e-4dfd-bfe5-167c3a62a34a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149760148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.1149760148 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3995396111 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 4459777407 ps |
| CPU time | 71.29 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:01:19 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-6fa07b9f-a25f-443e-a6bf-78f6b913f7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995396111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3995396111 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2556821829 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 45370064 ps |
| CPU time | 6.32 seconds |
| Started | Jul 22 07:59:02 PM PDT 24 |
| Finished | Jul 22 07:59:12 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-325a1e21-92cc-4245-8c67-61e803ccffa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556821829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.2556821829 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1791529545 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 3411468580 ps |
| CPU time | 271.34 seconds |
| Started | Jul 22 07:58:19 PM PDT 24 |
| Finished | Jul 22 08:02:53 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-0b5368f4-4274-44c5-8735-c9f8bbbe55de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791529545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1791529545 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2638877463 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 2025131340 ps |
| CPU time | 145.57 seconds |
| Started | Jul 22 07:59:16 PM PDT 24 |
| Finished | Jul 22 08:01:44 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-a8cff038-21bc-458f-87cc-8c13bc979ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638877463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2638877463 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3107328313 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 5242398513 ps |
| CPU time | 319.74 seconds |
| Started | Jul 22 07:58:14 PM PDT 24 |
| Finished | Jul 22 08:03:35 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-a70c1756-5455-4ddf-ac53-75f52a1b6d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107328313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3107328313 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.757205551 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 94653275 ps |
| CPU time | 22.45 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:58:44 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-42be4857-5b3a-48fa-954d-1f2268c5d3bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757205551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_reset_error.757205551 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2746832893 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 1336166538 ps |
| CPU time | 50.57 seconds |
| Started | Jul 22 07:58:08 PM PDT 24 |
| Finished | Jul 22 07:58:59 PM PDT 24 |
| Peak memory | 576876 kb |
| Host | smart-f86e2021-3b2a-4e63-9632-74266ef94563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746832893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2746832893 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.2351764260 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1546030681 ps |
| CPU time | 66.92 seconds |
| Started | Jul 22 07:58:17 PM PDT 24 |
| Finished | Jul 22 07:59:27 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-1c13edaf-ea9d-4b86-8099-6d7a79e5e640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351764260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2351764260 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.4195964038 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 81842576103 ps |
| CPU time | 1433.12 seconds |
| Started | Jul 22 07:58:19 PM PDT 24 |
| Finished | Jul 22 08:22:15 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-d5dcbc83-cc91-41d8-be44-67af305fb249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195964038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.4195964038 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2330329279 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 112202171 ps |
| CPU time | 13.26 seconds |
| Started | Jul 22 07:59:32 PM PDT 24 |
| Finished | Jul 22 07:59:47 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-0a47fdc8-9693-467d-ba77-64a569dc815a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330329279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.2330329279 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.3251791772 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 1559498145 ps |
| CPU time | 43.13 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:59:04 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-0a257759-3af6-44b1-9347-7e587ce1978b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251791772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.3251791772 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.3216440695 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 2213940436 ps |
| CPU time | 88.06 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:59:49 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-597a5ed4-deb0-4bc0-aeaa-847fe8008b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216440695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3216440695 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1294731119 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 33867424027 ps |
| CPU time | 354.25 seconds |
| Started | Jul 22 07:58:58 PM PDT 24 |
| Finished | Jul 22 08:04:56 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-0acf24f8-1bf2-45af-8a3d-dee3131b8f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294731119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1294731119 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1311558753 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 44860109994 ps |
| CPU time | 869.76 seconds |
| Started | Jul 22 07:58:19 PM PDT 24 |
| Finished | Jul 22 08:12:52 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-b9651e17-016e-4459-ada1-29f7043bb255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311558753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1311558753 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3493030224 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 451777205 ps |
| CPU time | 36.15 seconds |
| Started | Jul 22 07:58:20 PM PDT 24 |
| Finished | Jul 22 07:58:58 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-0d5d71c8-950f-4904-a2f3-48101b5659a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493030224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3493030224 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3744454217 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 2498494858 ps |
| CPU time | 65.29 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:59:26 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-2b1e2e81-9888-4d1a-ac46-1bb3dcb3d55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744454217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3744454217 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.3330772378 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 236989134 ps |
| CPU time | 9.95 seconds |
| Started | Jul 22 07:58:19 PM PDT 24 |
| Finished | Jul 22 07:58:31 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-b3b84531-a02d-4742-9fb4-4475a23b06eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330772378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3330772378 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2622216220 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 10761159806 ps |
| CPU time | 104.61 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 08:00:05 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-65eb5f49-a9e6-4323-873d-fcde22d25a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622216220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2622216220 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2676132755 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 3752339818 ps |
| CPU time | 63.79 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:59:24 PM PDT 24 |
| Peak memory | 574880 kb |
| Host | smart-97483910-bbd4-4a1b-9ed6-c6c0255c0993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676132755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2676132755 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2455747789 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 41421734 ps |
| CPU time | 6 seconds |
| Started | Jul 22 07:59:16 PM PDT 24 |
| Finished | Jul 22 07:59:24 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-db13749a-e460-4c12-b558-9090cb277221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455747789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2455747789 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2086480757 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 14232719437 ps |
| CPU time | 494.77 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 08:06:35 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-e11c985c-2a4a-463d-bc6e-67dd87404ab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086480757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2086480757 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1885594319 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 1082564233 ps |
| CPU time | 85.63 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 07:59:47 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-e7dd42a1-94fc-484f-810e-d34942bb50a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885594319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1885594319 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2557987299 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 464176623 ps |
| CPU time | 112.07 seconds |
| Started | Jul 22 07:58:18 PM PDT 24 |
| Finished | Jul 22 08:00:13 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-73e431f5-31e3-47b9-91db-c74612f40ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557987299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2557987299 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.2886468450 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 125242809 ps |
| CPU time | 8.65 seconds |
| Started | Jul 22 07:58:20 PM PDT 24 |
| Finished | Jul 22 07:58:31 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-4f4d015f-5a70-4f01-ba6c-936c9e704321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886468450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.2886468450 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.811334305 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 1378674812 ps |
| CPU time | 98.43 seconds |
| Started | Jul 22 07:58:39 PM PDT 24 |
| Finished | Jul 22 08:00:18 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-cdbb68c2-bac9-4202-bb71-634e88bb3c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811334305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 811334305 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2030457231 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 74105366293 ps |
| CPU time | 1206.6 seconds |
| Started | Jul 22 07:58:32 PM PDT 24 |
| Finished | Jul 22 08:18:40 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-6563064b-01b4-406d-8552-aad66bbc2079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030457231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2030457231 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1005600981 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 99762935 ps |
| CPU time | 12.65 seconds |
| Started | Jul 22 07:58:40 PM PDT 24 |
| Finished | Jul 22 07:58:54 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-a3956007-9e88-44fa-8699-5e06b6bd2472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005600981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1005600981 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.4120144262 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 854647768 ps |
| CPU time | 27.9 seconds |
| Started | Jul 22 07:58:32 PM PDT 24 |
| Finished | Jul 22 07:59:01 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-d30fdc1a-c932-47a5-95a9-6a9b23c31a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120144262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.4120144262 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.2019792794 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 2113951696 ps |
| CPU time | 78.87 seconds |
| Started | Jul 22 07:58:39 PM PDT 24 |
| Finished | Jul 22 08:00:00 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-a68834dc-a249-43b6-9376-6de62269ba73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019792794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2019792794 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.3021994157 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 23380817409 ps |
| CPU time | 243.64 seconds |
| Started | Jul 22 07:58:38 PM PDT 24 |
| Finished | Jul 22 08:02:43 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-0a6a08e9-5096-4838-a50f-63eb50f1a402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021994157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.3021994157 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.926451438 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 54772864935 ps |
| CPU time | 937.58 seconds |
| Started | Jul 22 07:58:39 PM PDT 24 |
| Finished | Jul 22 08:14:18 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-addc821d-044a-4628-99b1-aab433c0391d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926451438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.926451438 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1710631280 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 58584831 ps |
| CPU time | 7.47 seconds |
| Started | Jul 22 07:58:41 PM PDT 24 |
| Finished | Jul 22 07:58:50 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-0c679147-efef-4e89-a9d7-a57ac5972f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710631280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1710631280 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.1299696908 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 566448954 ps |
| CPU time | 41.56 seconds |
| Started | Jul 22 07:59:16 PM PDT 24 |
| Finished | Jul 22 08:00:00 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-b475247b-f9ef-4883-a771-227981304a39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299696908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.1299696908 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.2937556310 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 168446260 ps |
| CPU time | 8.31 seconds |
| Started | Jul 22 08:00:57 PM PDT 24 |
| Finished | Jul 22 08:01:08 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-2f226aa5-efd6-4fdc-901c-a0d995dad7c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937556310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2937556310 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.791781572 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 7982433255 ps |
| CPU time | 82.78 seconds |
| Started | Jul 22 07:59:32 PM PDT 24 |
| Finished | Jul 22 08:00:56 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-f8f6e59c-d810-4699-8bab-8376b3f4081d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791781572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.791781572 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.894267117 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 3808502731 ps |
| CPU time | 63.7 seconds |
| Started | Jul 22 07:58:41 PM PDT 24 |
| Finished | Jul 22 07:59:46 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-7de5e61c-20cc-4f77-9839-f954f9a68902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894267117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.894267117 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.3574047427 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 46208055 ps |
| CPU time | 6.41 seconds |
| Started | Jul 22 07:58:17 PM PDT 24 |
| Finished | Jul 22 07:58:26 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-edb7a9a4-14f9-4338-968f-16e9f341d121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574047427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.3574047427 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3358389452 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 13018062475 ps |
| CPU time | 521.96 seconds |
| Started | Jul 22 07:58:39 PM PDT 24 |
| Finished | Jul 22 08:07:22 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-dd58b8a4-5677-4ba4-ac3e-4e9d86cd9dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358389452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3358389452 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.1930310016 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 210123715 ps |
| CPU time | 18.28 seconds |
| Started | Jul 22 07:58:38 PM PDT 24 |
| Finished | Jul 22 07:58:58 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-b948c640-d3b6-4748-bbaa-d69aaf9b6411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930310016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.1930310016 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2375477389 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 95638082 ps |
| CPU time | 40.06 seconds |
| Started | Jul 22 07:58:33 PM PDT 24 |
| Finished | Jul 22 07:59:14 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-1a3d941c-d84a-4012-844b-3f33ed22ae0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375477389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2375477389 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4161801714 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 410094461 ps |
| CPU time | 137.28 seconds |
| Started | Jul 22 07:58:31 PM PDT 24 |
| Finished | Jul 22 08:00:49 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-80cde9ab-e2ff-4f4c-adcd-a8ae439610fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161801714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.4161801714 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2396005513 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 337031114 ps |
| CPU time | 16.8 seconds |
| Started | Jul 22 07:58:40 PM PDT 24 |
| Finished | Jul 22 07:58:58 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-178d69e1-375d-4acd-a218-6a4d857c5465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396005513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2396005513 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.3041496268 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 1644913451 ps |
| CPU time | 70.33 seconds |
| Started | Jul 22 07:58:45 PM PDT 24 |
| Finished | Jul 22 07:59:58 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-22fe6521-b460-44f1-8b1c-2ee7c112a4a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041496268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3041496268 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.4049923148 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 79165402383 ps |
| CPU time | 1446.44 seconds |
| Started | Jul 22 07:58:45 PM PDT 24 |
| Finished | Jul 22 08:22:56 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-cc968a4c-e2a0-4455-a03a-d8f00a458a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049923148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.4049923148 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3568684224 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 1134567656 ps |
| CPU time | 47.47 seconds |
| Started | Jul 22 07:58:54 PM PDT 24 |
| Finished | Jul 22 07:59:45 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-c14b19af-2280-402e-b20e-9570f79b88ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568684224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3568684224 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.661198254 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 167751939 ps |
| CPU time | 15.6 seconds |
| Started | Jul 22 07:58:46 PM PDT 24 |
| Finished | Jul 22 07:59:06 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-195244dc-d2d4-4c27-92e5-c1b7302ca1e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661198254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.661198254 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.3034154849 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 505924331 ps |
| CPU time | 45.55 seconds |
| Started | Jul 22 07:58:43 PM PDT 24 |
| Finished | Jul 22 07:59:31 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-2f6a9a7f-23a3-4418-ab21-e4e00b2c3896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034154849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3034154849 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1796038705 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 105128678341 ps |
| CPU time | 1057.34 seconds |
| Started | Jul 22 07:58:53 PM PDT 24 |
| Finished | Jul 22 08:16:34 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-5fbcefea-8679-4728-b6ad-710602e474e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796038705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1796038705 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2115552251 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 51615251341 ps |
| CPU time | 943.08 seconds |
| Started | Jul 22 07:58:46 PM PDT 24 |
| Finished | Jul 22 08:14:32 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-012f3638-bd18-4598-b280-ab729c60628e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115552251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2115552251 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3481963270 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 531709864 ps |
| CPU time | 42.33 seconds |
| Started | Jul 22 07:58:47 PM PDT 24 |
| Finished | Jul 22 07:59:33 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-a82edfe7-6a06-450e-b6c7-982773c697fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481963270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3481963270 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3159326045 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 538472617 ps |
| CPU time | 41.11 seconds |
| Started | Jul 22 07:58:44 PM PDT 24 |
| Finished | Jul 22 07:59:27 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-20b3601b-ef86-474c-86ca-13d4bb60694a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159326045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3159326045 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3913335731 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 142054938 ps |
| CPU time | 7.31 seconds |
| Started | Jul 22 07:59:36 PM PDT 24 |
| Finished | Jul 22 07:59:44 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-4c0a461f-6c8a-484b-9c56-8f183e57d668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913335731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3913335731 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1512600439 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 9685800419 ps |
| CPU time | 98.3 seconds |
| Started | Jul 22 07:58:38 PM PDT 24 |
| Finished | Jul 22 08:00:17 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-e529999b-6746-4615-9a9c-4c253df84a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512600439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1512600439 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1719537544 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 6403342170 ps |
| CPU time | 109.62 seconds |
| Started | Jul 22 07:58:43 PM PDT 24 |
| Finished | Jul 22 08:00:34 PM PDT 24 |
| Peak memory | 574856 kb |
| Host | smart-46ad61dd-b847-4f9b-a0ab-bbd956d4f38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719537544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1719537544 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.693997203 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 50011248 ps |
| CPU time | 6.78 seconds |
| Started | Jul 22 07:58:39 PM PDT 24 |
| Finished | Jul 22 07:58:47 PM PDT 24 |
| Peak memory | 574836 kb |
| Host | smart-f871b3db-a91d-4cdf-ac7f-95b5af681602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693997203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .693997203 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.1201608399 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 3711421622 ps |
| CPU time | 286.44 seconds |
| Started | Jul 22 07:58:43 PM PDT 24 |
| Finished | Jul 22 08:03:32 PM PDT 24 |
| Peak memory | 577008 kb |
| Host | smart-ceb2eeed-8831-4916-b37e-d6cbee9df8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201608399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1201608399 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2112223766 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 6130647370 ps |
| CPU time | 225.56 seconds |
| Started | Jul 22 07:58:47 PM PDT 24 |
| Finished | Jul 22 08:02:36 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-c5ec11ea-eb39-4b25-a381-6a4af1a01bfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112223766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2112223766 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3855096375 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 215690571 ps |
| CPU time | 83.53 seconds |
| Started | Jul 22 07:58:52 PM PDT 24 |
| Finished | Jul 22 08:00:20 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-2474fc4d-de92-4916-a302-24a68802d14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855096375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3855096375 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.126901846 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 4158528464 ps |
| CPU time | 316.96 seconds |
| Started | Jul 22 08:00:57 PM PDT 24 |
| Finished | Jul 22 08:06:16 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-d3fd1725-eec9-4bc8-94f8-5656e6cd3a6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126901846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_reset_error.126901846 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.4251987572 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 57658856 ps |
| CPU time | 9.27 seconds |
| Started | Jul 22 07:58:44 PM PDT 24 |
| Finished | Jul 22 07:58:55 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-f9b437b1-13f2-4781-9335-a0d0e2018f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251987572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.4251987572 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3886557599 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 2255145123 ps |
| CPU time | 88.34 seconds |
| Started | Jul 22 07:58:46 PM PDT 24 |
| Finished | Jul 22 08:00:18 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-6df989e6-10eb-4683-965a-74f8883cf64c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886557599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3886557599 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3814458794 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 23773658029 ps |
| CPU time | 435.59 seconds |
| Started | Jul 22 07:58:45 PM PDT 24 |
| Finished | Jul 22 08:06:05 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-3f2b6853-2ab4-468e-ba6c-47528a9a8b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814458794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.3814458794 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3295376608 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 86861461 ps |
| CPU time | 11.59 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 07:59:15 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-79cc650c-7502-4849-a1ca-48161a9df6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295376608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3295376608 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.2198238601 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 1345058584 ps |
| CPU time | 42.94 seconds |
| Started | Jul 22 07:59:05 PM PDT 24 |
| Finished | Jul 22 07:59:51 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-34ec49eb-1d01-4cad-b40d-955c26a2d185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198238601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2198238601 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.3365893744 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 262114321 ps |
| CPU time | 11.93 seconds |
| Started | Jul 22 07:58:45 PM PDT 24 |
| Finished | Jul 22 07:59:01 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-0307b7da-85e0-4524-9c13-01f206199b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365893744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3365893744 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1896021166 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 77473126801 ps |
| CPU time | 884.41 seconds |
| Started | Jul 22 07:58:44 PM PDT 24 |
| Finished | Jul 22 08:13:31 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-07927506-8a03-4520-a3a0-b4e08582ea60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896021166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1896021166 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1641233770 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 50981243152 ps |
| CPU time | 885.42 seconds |
| Started | Jul 22 07:58:46 PM PDT 24 |
| Finished | Jul 22 08:13:35 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-280b3681-c807-4b43-94d9-33415e1b57ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641233770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1641233770 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.25224529 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 402980818 ps |
| CPU time | 32.21 seconds |
| Started | Jul 22 07:58:45 PM PDT 24 |
| Finished | Jul 22 07:59:20 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-d10ea411-1d98-499e-be9c-6a97a2bc1d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_delay s.25224529 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.704979798 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 329165694 ps |
| CPU time | 11.95 seconds |
| Started | Jul 22 07:58:59 PM PDT 24 |
| Finished | Jul 22 07:59:15 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-de3e98bb-5f81-4cc0-8b59-249a00d87fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704979798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.704979798 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.597516136 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 212277377 ps |
| CPU time | 8.87 seconds |
| Started | Jul 22 07:58:43 PM PDT 24 |
| Finished | Jul 22 07:58:54 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-e3f93f7f-cd4d-4fc3-955a-5ee0c71e8df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597516136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.597516136 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3771567330 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 9665483041 ps |
| CPU time | 106.86 seconds |
| Started | Jul 22 07:58:46 PM PDT 24 |
| Finished | Jul 22 08:00:37 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-4c52b57b-ab5b-4309-b57a-d6aa8338f0a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771567330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3771567330 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.4267093950 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 4434700501 ps |
| CPU time | 71.9 seconds |
| Started | Jul 22 07:58:52 PM PDT 24 |
| Finished | Jul 22 08:00:08 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-73321aa1-1083-4c90-89c8-f15ea3a5de4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267093950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.4267093950 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1894697868 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 47374246 ps |
| CPU time | 6.57 seconds |
| Started | Jul 22 07:58:44 PM PDT 24 |
| Finished | Jul 22 07:58:52 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-2ca0c6ea-802d-4e97-a4d3-efda39a24886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894697868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1894697868 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.1763576483 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 11020797788 ps |
| CPU time | 365.55 seconds |
| Started | Jul 22 07:59:05 PM PDT 24 |
| Finished | Jul 22 08:05:13 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-72888b27-40c8-4fdd-9422-bcabd68214ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763576483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.1763576483 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1616087810 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 1590470301 ps |
| CPU time | 126.97 seconds |
| Started | Jul 22 07:58:59 PM PDT 24 |
| Finished | Jul 22 08:01:10 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-e6239125-37f6-4250-846c-815f50da4de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616087810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1616087810 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.759829253 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 6180381752 ps |
| CPU time | 471.55 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 08:06:56 PM PDT 24 |
| Peak memory | 576956 kb |
| Host | smart-53d29a2f-2b87-402d-981d-0ddadfe39379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759829253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.759829253 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.214444978 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 3242791412 ps |
| CPU time | 379.56 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 08:05:24 PM PDT 24 |
| Peak memory | 577032 kb |
| Host | smart-632815a0-731e-44b5-bba7-c4f4d42e31c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214444978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_reset_error.214444978 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.4137829263 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 259688566 ps |
| CPU time | 13.52 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 07:59:17 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-306c5c81-11f9-475b-89e0-b2d75c0a8731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137829263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.4137829263 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.759746197 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 165888144 ps |
| CPU time | 12.69 seconds |
| Started | Jul 22 07:59:15 PM PDT 24 |
| Finished | Jul 22 07:59:30 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-13713612-c109-4934-99c1-85384ae440a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759746197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 759746197 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1157528851 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 102257556724 ps |
| CPU time | 1933.56 seconds |
| Started | Jul 22 07:59:19 PM PDT 24 |
| Finished | Jul 22 08:31:35 PM PDT 24 |
| Peak memory | 577020 kb |
| Host | smart-3c975a9c-c3d3-40b7-b1bf-79c078f9d520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157528851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.1157528851 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3977919355 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 46801992 ps |
| CPU time | 5.2 seconds |
| Started | Jul 22 08:00:54 PM PDT 24 |
| Finished | Jul 22 08:01:00 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-affe9f7d-bd85-470a-b23d-3b2e29a206f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977919355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3977919355 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.442132971 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 377968294 ps |
| CPU time | 30.77 seconds |
| Started | Jul 22 07:59:14 PM PDT 24 |
| Finished | Jul 22 07:59:47 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-c768121a-0d7b-49ff-b16b-2c6777b47b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442132971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.442132971 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.2203042485 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 89259981 ps |
| CPU time | 11.56 seconds |
| Started | Jul 22 07:58:59 PM PDT 24 |
| Finished | Jul 22 07:59:15 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-271ec168-63c0-493b-b7be-cc5cc48536cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203042485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2203042485 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.61928842 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 88377851620 ps |
| CPU time | 925.2 seconds |
| Started | Jul 22 07:59:01 PM PDT 24 |
| Finished | Jul 22 08:14:30 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-690e8e94-fcc1-404a-8ede-113a406463af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61928842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.61928842 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2342728359 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 24149838126 ps |
| CPU time | 426.81 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 08:06:11 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-4f73a506-6261-4fdc-9251-210c528f9bbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342728359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2342728359 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1562570014 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 429905058 ps |
| CPU time | 41.53 seconds |
| Started | Jul 22 07:59:05 PM PDT 24 |
| Finished | Jul 22 07:59:49 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-94a9bd0f-3c02-4f42-83c5-a1c2dc81757b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562570014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1562570014 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3156460532 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 504898989 ps |
| CPU time | 33.34 seconds |
| Started | Jul 22 07:59:19 PM PDT 24 |
| Finished | Jul 22 07:59:54 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-49044418-6979-48f6-aab9-acab2c1834c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156460532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3156460532 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.1374692291 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 52056497 ps |
| CPU time | 6.63 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 07:59:10 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-d2653942-4549-44d4-a758-7e3a219eaaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374692291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1374692291 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.268226369 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 10663490138 ps |
| CPU time | 102.34 seconds |
| Started | Jul 22 07:59:01 PM PDT 24 |
| Finished | Jul 22 08:00:47 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-f46794db-318c-4ca0-8bae-493fb3ec703b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268226369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.268226369 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2063521836 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 6106368038 ps |
| CPU time | 103.13 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 08:00:47 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-b16434b3-57f0-42d4-b96f-05df47ba2106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063521836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2063521836 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1490405208 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 58442596 ps |
| CPU time | 6.69 seconds |
| Started | Jul 22 07:59:00 PM PDT 24 |
| Finished | Jul 22 07:59:10 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-50c0b1d8-ab00-4241-a562-5fb41629413f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490405208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.1490405208 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2708957248 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 2480187831 ps |
| CPU time | 197.95 seconds |
| Started | Jul 22 07:59:14 PM PDT 24 |
| Finished | Jul 22 08:02:34 PM PDT 24 |
| Peak memory | 577132 kb |
| Host | smart-9b60ae28-80be-4e4d-a498-2a65f8b2b6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708957248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2708957248 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1173317210 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 164156432 ps |
| CPU time | 8.96 seconds |
| Started | Jul 22 07:59:50 PM PDT 24 |
| Finished | Jul 22 08:00:00 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-30d1fab9-ae90-4668-8e29-c68824dbac6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173317210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1173317210 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1088083970 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 11014855757 ps |
| CPU time | 1050.53 seconds |
| Started | Jul 22 07:59:15 PM PDT 24 |
| Finished | Jul 22 08:16:48 PM PDT 24 |
| Peak memory | 582420 kb |
| Host | smart-02d79bed-0dc4-432e-bc49-06428720cc39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088083970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.1088083970 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2678865933 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 531769604 ps |
| CPU time | 107.29 seconds |
| Started | Jul 22 08:00:57 PM PDT 24 |
| Finished | Jul 22 08:02:46 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-6550b6d5-f753-4fae-b9f7-8bdf737d3c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678865933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2678865933 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.3335337149 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 483439779 ps |
| CPU time | 21.99 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 07:59:37 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-76fcfa7b-4149-432f-b938-dc108d17433f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335337149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.3335337149 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1294332697 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 732768338 ps |
| CPU time | 33.08 seconds |
| Started | Jul 22 07:59:14 PM PDT 24 |
| Finished | Jul 22 07:59:49 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-d9d8e6d5-7b5a-4fed-93dd-1406b721afb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294332697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1294332697 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2650644763 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 172111817 ps |
| CPU time | 20.46 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 07:59:47 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-ba519120-9795-4654-8c70-58d4ecbba720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650644763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2650644763 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3428793812 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 347654968 ps |
| CPU time | 25.67 seconds |
| Started | Jul 22 08:00:24 PM PDT 24 |
| Finished | Jul 22 08:00:54 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-e3efeae2-9502-4c6b-baa8-3fecd8418d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428793812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3428793812 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2671249374 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 186599482 ps |
| CPU time | 17.76 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 07:59:33 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-1ada6094-7b85-4f35-b56b-8541a66b661e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671249374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2671249374 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3261002069 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 23642722680 ps |
| CPU time | 243.36 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 08:03:19 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-38160aba-96ca-428a-8c54-3df14e38677c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261002069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3261002069 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.312825019 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 47098693581 ps |
| CPU time | 820.74 seconds |
| Started | Jul 22 07:59:16 PM PDT 24 |
| Finished | Jul 22 08:12:59 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-0dd36af6-86a2-4f11-8a62-b28c92c046ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312825019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.312825019 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2643523125 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 82876276 ps |
| CPU time | 11.45 seconds |
| Started | Jul 22 07:59:13 PM PDT 24 |
| Finished | Jul 22 07:59:26 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-689f443e-ff88-44ab-b74f-e1b38ecb85b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643523125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.2643523125 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.3933958322 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 1808994969 ps |
| CPU time | 53.63 seconds |
| Started | Jul 22 07:59:28 PM PDT 24 |
| Finished | Jul 22 08:00:24 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-9ed31dab-924c-4dc0-895d-f730e3bb73b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933958322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3933958322 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.1574887747 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 38799874 ps |
| CPU time | 5.94 seconds |
| Started | Jul 22 07:59:16 PM PDT 24 |
| Finished | Jul 22 07:59:24 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-45934d1d-04cc-4b4f-976f-e52833af2f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574887747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1574887747 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.2917774119 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 8883747438 ps |
| CPU time | 92.17 seconds |
| Started | Jul 22 07:59:16 PM PDT 24 |
| Finished | Jul 22 08:00:50 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-e945156b-4bba-47e1-9a74-01cf5e98eb0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917774119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.2917774119 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.829552239 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 5857702317 ps |
| CPU time | 97.16 seconds |
| Started | Jul 22 07:59:14 PM PDT 24 |
| Finished | Jul 22 08:00:54 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-66ed6894-0fb2-4135-b539-18feb07d1758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829552239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.829552239 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3973039781 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 41339578 ps |
| CPU time | 5.92 seconds |
| Started | Jul 22 07:59:19 PM PDT 24 |
| Finished | Jul 22 07:59:27 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-4356c71b-5fe2-42eb-bea0-fd546472645d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973039781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.3973039781 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1782440357 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1471668638 ps |
| CPU time | 111.28 seconds |
| Started | Jul 22 08:00:54 PM PDT 24 |
| Finished | Jul 22 08:02:46 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-4a02485c-ad9e-4b41-8ef1-95e1b25b3320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782440357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1782440357 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3126607586 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 2652505613 ps |
| CPU time | 216.16 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 08:03:04 PM PDT 24 |
| Peak memory | 577056 kb |
| Host | smart-fe44c79c-8c8b-472d-bd90-dc10f369f3fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126607586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3126607586 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3307714008 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 373566319 ps |
| CPU time | 67.29 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 08:00:36 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-76a932ba-2e51-4721-85fc-42910fac9fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307714008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.3307714008 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3090601333 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 1142873270 ps |
| CPU time | 182.86 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 08:02:30 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-1e059b87-1a80-4ca1-9671-8544be73359e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090601333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.3090601333 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.3092791492 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1267068453 ps |
| CPU time | 49.53 seconds |
| Started | Jul 22 07:59:32 PM PDT 24 |
| Finished | Jul 22 08:00:23 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-d1832509-7de2-477e-b06b-8dc8e32bddb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092791492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.3092791492 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.195022130 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 1226545415 ps |
| CPU time | 43.88 seconds |
| Started | Jul 22 08:00:54 PM PDT 24 |
| Finished | Jul 22 08:01:39 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-f6eec5cc-6e86-436e-8b09-3a91bb31f843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195022130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device. 195022130 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2562239481 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 162400307135 ps |
| CPU time | 3163.63 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 08:52:14 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-4ff9a299-a25c-40f5-b08c-9b6df9901032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562239481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2562239481 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2400529080 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 94546840 ps |
| CPU time | 11.64 seconds |
| Started | Jul 22 07:59:29 PM PDT 24 |
| Finished | Jul 22 07:59:44 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-47d4ac82-2e06-4326-9dac-74a113f11873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400529080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2400529080 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.2146823275 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 2013051668 ps |
| CPU time | 71.1 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 08:00:38 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-af17a708-6fa0-476a-821b-f5901eea9857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146823275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.2146823275 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1939573460 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 85971309 ps |
| CPU time | 6.37 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 07:59:35 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-c7f13eae-b4ca-4570-a5cb-8228c81a6a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939573460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1939573460 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1654496611 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 100073649805 ps |
| CPU time | 1064.64 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 08:17:13 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-a681d3dd-5d81-4df3-b063-57440dbb16da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654496611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1654496611 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3850359588 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 41796133265 ps |
| CPU time | 723.56 seconds |
| Started | Jul 22 08:00:11 PM PDT 24 |
| Finished | Jul 22 08:12:15 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-fffd3664-5ddc-48bd-b8fd-2a402ef7ae83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850359588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3850359588 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3530489964 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 268513202 ps |
| CPU time | 23.36 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 07:59:51 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-83b24b2e-b5e1-40b5-b408-e33dbaa07326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530489964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3530489964 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3315418372 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 1920282922 ps |
| CPU time | 61.88 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 08:00:30 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-24b64cb1-d6a1-44f2-83a0-8a1a36ff33c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315418372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3315418372 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.2990596567 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 46064120 ps |
| CPU time | 6.14 seconds |
| Started | Jul 22 07:59:28 PM PDT 24 |
| Finished | Jul 22 07:59:37 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-44ed1cd6-3c00-4e0a-aaa1-42ef5c627877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990596567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.2990596567 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2485573307 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 6925240044 ps |
| CPU time | 74.5 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 08:00:43 PM PDT 24 |
| Peak memory | 574904 kb |
| Host | smart-6031dfcf-4504-41a5-ae3e-9317fb2b1bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485573307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2485573307 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1824137274 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 6741957334 ps |
| CPU time | 104.06 seconds |
| Started | Jul 22 07:59:27 PM PDT 24 |
| Finished | Jul 22 08:01:15 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-7d8f12b2-4a00-41eb-bde3-5b18cd54822d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824137274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1824137274 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3170151422 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 44312354 ps |
| CPU time | 5.86 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 07:59:34 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-a1b4f287-b4f2-43e2-af34-95fb2edd6aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170151422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.3170151422 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.3790767125 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 16863522793 ps |
| CPU time | 646.03 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 08:10:15 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-96cb674d-a597-4f75-9a2f-3efe0bf0a335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790767125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3790767125 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.53494756 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 8204517181 ps |
| CPU time | 240.87 seconds |
| Started | Jul 22 07:59:28 PM PDT 24 |
| Finished | Jul 22 08:03:33 PM PDT 24 |
| Peak memory | 577096 kb |
| Host | smart-2bf38de4-11e4-4538-aaa0-66875c00b9ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53494756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.53494756 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1705719249 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 916914086 ps |
| CPU time | 242.47 seconds |
| Started | Jul 22 07:59:48 PM PDT 24 |
| Finished | Jul 22 08:03:51 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-2533621f-6bcf-4063-a701-13d925c700e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705719249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.1705719249 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1635355980 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 1785707065 ps |
| CPU time | 248.19 seconds |
| Started | Jul 22 07:59:28 PM PDT 24 |
| Finished | Jul 22 08:03:39 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-701b5d99-4089-4dc6-b0e7-b32bfbfdf357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635355980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1635355980 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1121536529 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 1204668862 ps |
| CPU time | 45.97 seconds |
| Started | Jul 22 07:59:25 PM PDT 24 |
| Finished | Jul 22 08:00:14 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-68b62ab1-01b8-4ac1-9255-a764c1ba6f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121536529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1121536529 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2924308947 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 678774628 ps |
| CPU time | 51.74 seconds |
| Started | Jul 22 07:59:40 PM PDT 24 |
| Finished | Jul 22 08:00:32 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-85145c0c-c863-4428-a509-dd41d295de3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924308947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2924308947 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.363509559 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 36359654559 ps |
| CPU time | 611.97 seconds |
| Started | Jul 22 07:59:48 PM PDT 24 |
| Finished | Jul 22 08:10:01 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-0fb58855-0f39-4407-9b7a-05cd6fc433de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363509559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.363509559 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.4145200806 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 162254670 ps |
| CPU time | 17.36 seconds |
| Started | Jul 22 07:59:42 PM PDT 24 |
| Finished | Jul 22 08:00:00 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-854829b4-23f4-4248-9da6-ba2db8021374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145200806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.4145200806 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3982895550 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1505884283 ps |
| CPU time | 42.72 seconds |
| Started | Jul 22 07:59:47 PM PDT 24 |
| Finished | Jul 22 08:00:31 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-225da3ef-fb1e-445b-bf43-f3b018b6a772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982895550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3982895550 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.1194374706 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 352689117 ps |
| CPU time | 28.59 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:00:09 PM PDT 24 |
| Peak memory | 576800 kb |
| Host | smart-709e5fee-fc00-4c52-b8cf-74415d8915cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194374706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.1194374706 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1629772560 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 36985853540 ps |
| CPU time | 388.61 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:06:09 PM PDT 24 |
| Peak memory | 577032 kb |
| Host | smart-63c9a62c-ef6e-48f2-b0fe-079bf5da8768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629772560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1629772560 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3210572641 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 32322622559 ps |
| CPU time | 550.73 seconds |
| Started | Jul 22 07:59:47 PM PDT 24 |
| Finished | Jul 22 08:08:59 PM PDT 24 |
| Peak memory | 576848 kb |
| Host | smart-8c062c53-3810-46a1-912a-ec36b3d70a89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210572641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3210572641 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.879885634 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 432549022 ps |
| CPU time | 30.76 seconds |
| Started | Jul 22 07:59:42 PM PDT 24 |
| Finished | Jul 22 08:00:13 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-defa7d6c-2873-411e-9339-cfc45d689a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879885634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela ys.879885634 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.1770866842 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 522939116 ps |
| CPU time | 36.19 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:00:17 PM PDT 24 |
| Peak memory | 576820 kb |
| Host | smart-0409acc6-2d92-4a93-91b3-c643b32cb60a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770866842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.1770866842 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.2197161654 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 159553435 ps |
| CPU time | 7.35 seconds |
| Started | Jul 22 07:59:27 PM PDT 24 |
| Finished | Jul 22 07:59:38 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-8e745027-285d-4ac6-b97b-f461576a4c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197161654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2197161654 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1934886654 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 7867298264 ps |
| CPU time | 72.98 seconds |
| Started | Jul 22 07:59:27 PM PDT 24 |
| Finished | Jul 22 08:00:43 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-525a93e9-b683-4813-a5f8-55f3c37ae789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934886654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1934886654 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.677701226 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 4524654737 ps |
| CPU time | 70.91 seconds |
| Started | Jul 22 07:59:26 PM PDT 24 |
| Finished | Jul 22 08:00:39 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-6d4efc45-689c-4995-b0cd-f2b36d070163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677701226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.677701226 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4000714718 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 48796621 ps |
| CPU time | 6.33 seconds |
| Started | Jul 22 07:59:45 PM PDT 24 |
| Finished | Jul 22 07:59:52 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-3e603fed-23ae-4a7b-95af-978ffa767758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000714718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.4000714718 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.3003012658 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 3880468926 ps |
| CPU time | 147.98 seconds |
| Started | Jul 22 07:59:38 PM PDT 24 |
| Finished | Jul 22 08:02:07 PM PDT 24 |
| Peak memory | 576192 kb |
| Host | smart-b3e3c4f5-2939-4c8e-85c7-15fc7eee02a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003012658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3003012658 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2537594482 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 4351243327 ps |
| CPU time | 137.79 seconds |
| Started | Jul 22 07:59:41 PM PDT 24 |
| Finished | Jul 22 08:01:59 PM PDT 24 |
| Peak memory | 577028 kb |
| Host | smart-5cf1b12c-7b72-457a-b849-dd503c56474e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537594482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2537594482 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2015833699 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 1428438341 ps |
| CPU time | 296.69 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:04:37 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-e033d6cd-1f7f-4c3c-8ce7-2a8ab7842cf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015833699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2015833699 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3402283635 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 1515647419 ps |
| CPU time | 184.91 seconds |
| Started | Jul 22 07:59:48 PM PDT 24 |
| Finished | Jul 22 08:02:54 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-77cad43f-e195-410a-9a2e-951c35266f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402283635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3402283635 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.1394916620 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 191124806 ps |
| CPU time | 27.53 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:00:08 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-f07212de-6064-4400-98ac-1afe35aef8aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394916620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1394916620 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3580363661 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 2175447219 ps |
| CPU time | 100.69 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:01:21 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-46c4eac5-44fb-4747-a843-7161fc43564b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580363661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .3580363661 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.803346586 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 76732599462 ps |
| CPU time | 1360.43 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:22:21 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-0a6c1929-6e3b-4c55-a4c7-3c1699919bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803346586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.803346586 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.419071036 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 1425084354 ps |
| CPU time | 50.97 seconds |
| Started | Jul 22 07:59:51 PM PDT 24 |
| Finished | Jul 22 08:00:43 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-3ae703ca-b5e4-44b7-a5fc-3569562f58d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419071036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr .419071036 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.4212052755 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 169782529 ps |
| CPU time | 15.28 seconds |
| Started | Jul 22 07:59:53 PM PDT 24 |
| Finished | Jul 22 08:00:10 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-556a146d-0323-4385-b040-feb58ec8f252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212052755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.4212052755 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.2136145449 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 439287581 ps |
| CPU time | 36.19 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:00:17 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-b8037347-2b49-44a5-bf60-9aa7265f26b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136145449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2136145449 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.606707368 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 11703052762 ps |
| CPU time | 121.73 seconds |
| Started | Jul 22 07:59:42 PM PDT 24 |
| Finished | Jul 22 08:01:44 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-00fe229c-052e-4d0e-8407-090e8ab61061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606707368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.606707368 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.676476823 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 24866693976 ps |
| CPU time | 413.71 seconds |
| Started | Jul 22 07:59:39 PM PDT 24 |
| Finished | Jul 22 08:06:34 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-4282826e-59ed-414f-9f6d-dbba6da4fd99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676476823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.676476823 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.803057586 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 591778794 ps |
| CPU time | 52.85 seconds |
| Started | Jul 22 07:59:42 PM PDT 24 |
| Finished | Jul 22 08:00:36 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-9736421e-b8b0-4879-a914-221e644ae729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803057586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_dela ys.803057586 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2253749714 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 308614900 ps |
| CPU time | 24.39 seconds |
| Started | Jul 22 07:59:42 PM PDT 24 |
| Finished | Jul 22 08:00:07 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-79d19173-b4e5-4e0c-aadf-b943402455f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253749714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2253749714 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.604407745 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 50444935 ps |
| CPU time | 6.23 seconds |
| Started | Jul 22 07:59:41 PM PDT 24 |
| Finished | Jul 22 07:59:48 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-c64e64c3-8575-4120-81c5-d33d2270b7d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604407745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.604407745 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3909245341 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 9524535038 ps |
| CPU time | 91.54 seconds |
| Started | Jul 22 07:59:38 PM PDT 24 |
| Finished | Jul 22 08:01:11 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-128d5be6-b2b9-449e-9fe5-ab7cff09d97f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909245341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3909245341 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2984225998 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 3857812603 ps |
| CPU time | 61.5 seconds |
| Started | Jul 22 07:59:40 PM PDT 24 |
| Finished | Jul 22 08:00:42 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-b6f493ee-bdb5-42d6-9d28-731833088709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984225998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2984225998 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3349265398 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 51329542 ps |
| CPU time | 6.67 seconds |
| Started | Jul 22 07:59:40 PM PDT 24 |
| Finished | Jul 22 07:59:47 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-b2a93125-f9d0-4503-af0a-889c5d1a8439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349265398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3349265398 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.1089594300 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 2685426140 ps |
| CPU time | 237.99 seconds |
| Started | Jul 22 07:59:52 PM PDT 24 |
| Finished | Jul 22 08:03:52 PM PDT 24 |
| Peak memory | 577100 kb |
| Host | smart-35f8be27-1fed-408d-930e-77a963dbaff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089594300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.1089594300 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3467094007 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 9240355150 ps |
| CPU time | 323.32 seconds |
| Started | Jul 22 08:00:27 PM PDT 24 |
| Finished | Jul 22 08:05:53 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-03abba5e-c887-49fe-a1ee-afabbe88474b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467094007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3467094007 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.741743399 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 213983143 ps |
| CPU time | 62.89 seconds |
| Started | Jul 22 07:59:51 PM PDT 24 |
| Finished | Jul 22 08:00:56 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-eb9b512a-7d4c-415a-93b6-df18814f5940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741743399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_ with_rand_reset.741743399 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3892963531 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 203819365 ps |
| CPU time | 26.33 seconds |
| Started | Jul 22 07:59:51 PM PDT 24 |
| Finished | Jul 22 08:00:18 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-12618376-4b4f-4d40-8a0d-ad875dc0e466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892963531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3892963531 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2115568499 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 12646641440 ps |
| CPU time | 799.55 seconds |
| Started | Jul 22 07:44:12 PM PDT 24 |
| Finished | Jul 22 07:57:34 PM PDT 24 |
| Peak memory | 646324 kb |
| Host | smart-48316d51-d0c2-4d3a-b4fb-d5ace6aad19c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115568499 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.2115568499 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2317414110 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 6122744975 ps |
| CPU time | 661.82 seconds |
| Started | Jul 22 07:44:03 PM PDT 24 |
| Finished | Jul 22 07:55:07 PM PDT 24 |
| Peak memory | 599984 kb |
| Host | smart-563230fa-f738-4818-bf88-ee278972720f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317414110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2317414110 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2351191469 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 15082178708 ps |
| CPU time | 2016.18 seconds |
| Started | Jul 22 07:43:52 PM PDT 24 |
| Finished | Jul 22 08:17:30 PM PDT 24 |
| Peak memory | 593400 kb |
| Host | smart-4af02a82-9385-4443-9374-faaea2f5ee7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351191469 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2351191469 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1193069093 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 4448211964 ps |
| CPU time | 346.76 seconds |
| Started | Jul 22 07:44:18 PM PDT 24 |
| Finished | Jul 22 07:50:06 PM PDT 24 |
| Peak memory | 598236 kb |
| Host | smart-f600e25d-7b56-46c1-884a-0550c6999ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193069093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1193069093 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3991443488 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 1530192686 ps |
| CPU time | 56.91 seconds |
| Started | Jul 22 07:43:56 PM PDT 24 |
| Finished | Jul 22 07:44:54 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-f1e7aac4-0b61-4fe9-8c96-28d307146d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991443488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3991443488 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.155668236 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 89199034003 ps |
| CPU time | 1385.97 seconds |
| Started | Jul 22 07:43:51 PM PDT 24 |
| Finished | Jul 22 08:06:58 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-7e0facc0-e760-46b1-9310-7400f8edccc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155668236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.155668236 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1695994914 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 336225260 ps |
| CPU time | 32.81 seconds |
| Started | Jul 22 07:44:03 PM PDT 24 |
| Finished | Jul 22 07:44:37 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-aa90124c-8e51-44f8-a0db-1a01933104c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695994914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .1695994914 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.947704105 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 1411044050 ps |
| CPU time | 41.02 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:46:28 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-59a1093f-b673-4341-858c-1b9cd6bdd6f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947704105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.947704105 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.771968387 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 122041223 ps |
| CPU time | 14.42 seconds |
| Started | Jul 22 07:43:55 PM PDT 24 |
| Finished | Jul 22 07:44:10 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c35acc4d-72b6-4c7b-a9ff-4acd88401f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771968387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.771968387 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3858732319 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 32109519369 ps |
| CPU time | 340.69 seconds |
| Started | Jul 22 07:43:56 PM PDT 24 |
| Finished | Jul 22 07:49:37 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-ff6a0e82-1740-4a4c-8a1a-3a9753aa50ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858732319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3858732319 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3897983820 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 32157858542 ps |
| CPU time | 514.19 seconds |
| Started | Jul 22 07:43:49 PM PDT 24 |
| Finished | Jul 22 07:52:25 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-1b7071b9-8e18-420f-894d-46c996e2c182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897983820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3897983820 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3650222018 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 96977815 ps |
| CPU time | 11.13 seconds |
| Started | Jul 22 07:43:52 PM PDT 24 |
| Finished | Jul 22 07:44:04 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-2dc458ac-99ac-40cd-8aa2-4e3401a5c9bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650222018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3650222018 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.4114657150 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 2628244037 ps |
| CPU time | 80.1 seconds |
| Started | Jul 22 07:44:02 PM PDT 24 |
| Finished | Jul 22 07:45:24 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-cdb393e8-1655-4914-a113-b0e920e1109f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114657150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4114657150 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3706138057 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 38844925 ps |
| CPU time | 5.99 seconds |
| Started | Jul 22 07:44:08 PM PDT 24 |
| Finished | Jul 22 07:44:15 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-a7207a41-0407-40bd-a378-351d0480ef2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706138057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3706138057 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.4228088061 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5136475650 ps |
| CPU time | 52.08 seconds |
| Started | Jul 22 07:43:50 PM PDT 24 |
| Finished | Jul 22 07:44:44 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-4f5d2f36-d430-4d54-96e1-2ebb7fca9af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228088061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4228088061 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3252087950 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 5077098963 ps |
| CPU time | 86.24 seconds |
| Started | Jul 22 07:43:50 PM PDT 24 |
| Finished | Jul 22 07:45:18 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-07f94c95-041d-4d4b-b9ab-69c882deaf0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252087950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3252087950 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.4026458955 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 42192002 ps |
| CPU time | 5.66 seconds |
| Started | Jul 22 07:44:37 PM PDT 24 |
| Finished | Jul 22 07:44:44 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-5c883078-e495-4098-9c22-6b2d37f80868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026458955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .4026458955 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1868183847 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 1121392610 ps |
| CPU time | 88.01 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:47:15 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-d371982e-83f4-449f-847e-049bc558f7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868183847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1868183847 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1222279496 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2254886306 ps |
| CPU time | 150.75 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:48:27 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-600ee1eb-544e-4473-8c63-c80cbcdf204f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222279496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1222279496 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2875780894 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 65717458 ps |
| CPU time | 43.27 seconds |
| Started | Jul 22 07:45:18 PM PDT 24 |
| Finished | Jul 22 07:46:02 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-21ccca78-c17c-42db-8238-22e6a63336c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875780894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2875780894 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.4035859296 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 6151024899 ps |
| CPU time | 360.25 seconds |
| Started | Jul 22 07:44:11 PM PDT 24 |
| Finished | Jul 22 07:50:13 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-3e7f77be-472e-4d33-8707-82a29ff48998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035859296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.4035859296 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.89964475 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 247035443 ps |
| CPU time | 28.07 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:46:15 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-64c04217-be25-4e52-a710-ad16de00c301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89964475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.89964475 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.3707134391 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 3084385470 ps |
| CPU time | 143.96 seconds |
| Started | Jul 22 07:59:51 PM PDT 24 |
| Finished | Jul 22 08:02:16 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-49ff4c74-ee1a-4869-a12b-d42d56f85e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707134391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .3707134391 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1630033263 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 117113542140 ps |
| CPU time | 2117.72 seconds |
| Started | Jul 22 07:59:56 PM PDT 24 |
| Finished | Jul 22 08:35:15 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-6fac160c-8bc1-41d3-8be8-88a06590dda5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630033263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1630033263 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.174541675 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 199514622 ps |
| CPU time | 21.4 seconds |
| Started | Jul 22 08:00:04 PM PDT 24 |
| Finished | Jul 22 08:00:28 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-069fbf28-b0f8-427d-8f4b-a0a190adfe1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174541675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .174541675 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.1176786823 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 71974325 ps |
| CPU time | 6.13 seconds |
| Started | Jul 22 08:00:06 PM PDT 24 |
| Finished | Jul 22 08:00:14 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-b8017af0-85d3-4561-aab4-d16e98874089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176786823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1176786823 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.3024114096 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 2043859843 ps |
| CPU time | 65.54 seconds |
| Started | Jul 22 07:59:52 PM PDT 24 |
| Finished | Jul 22 08:00:59 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-c6c171a7-4356-4260-a34f-24520d59913b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024114096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3024114096 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.724693210 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 16927998730 ps |
| CPU time | 183.82 seconds |
| Started | Jul 22 07:59:52 PM PDT 24 |
| Finished | Jul 22 08:02:58 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-a853ca53-e049-4bb3-9278-3c462a1a176f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724693210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.724693210 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.559707685 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 32689385814 ps |
| CPU time | 551.2 seconds |
| Started | Jul 22 08:00:37 PM PDT 24 |
| Finished | Jul 22 08:09:56 PM PDT 24 |
| Peak memory | 576912 kb |
| Host | smart-84144924-6a82-44fa-9c0b-3d35b7f116bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559707685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.559707685 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2813973080 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 193525422 ps |
| CPU time | 17.45 seconds |
| Started | Jul 22 07:59:52 PM PDT 24 |
| Finished | Jul 22 08:00:11 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-362bc54e-2748-49ec-ba78-37ac33310feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813973080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2813973080 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3014083909 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 384344075 ps |
| CPU time | 27.89 seconds |
| Started | Jul 22 07:59:51 PM PDT 24 |
| Finished | Jul 22 08:00:21 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-fbea673b-4ac3-4fbb-99df-b30a318ad417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014083909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3014083909 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1497274726 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 174580758 ps |
| CPU time | 8.55 seconds |
| Started | Jul 22 07:59:54 PM PDT 24 |
| Finished | Jul 22 08:00:03 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-b0f34213-1a49-4947-b811-c4ef150665ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497274726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1497274726 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1602324842 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 11174821319 ps |
| CPU time | 110.68 seconds |
| Started | Jul 22 07:59:57 PM PDT 24 |
| Finished | Jul 22 08:01:48 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-7a482a80-606a-418a-9b26-3334fdbfa6de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602324842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1602324842 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.100079946 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 5482987340 ps |
| CPU time | 84.13 seconds |
| Started | Jul 22 07:59:51 PM PDT 24 |
| Finished | Jul 22 08:01:17 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-47b905d8-8e08-4ecc-813b-ea57f8487b4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100079946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.100079946 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1326609391 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 47754679 ps |
| CPU time | 6.3 seconds |
| Started | Jul 22 07:59:52 PM PDT 24 |
| Finished | Jul 22 08:00:00 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-fe9c9516-fa0a-4399-ac95-7ae815a4d5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326609391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.1326609391 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.3522001827 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 1815399113 ps |
| CPU time | 154.63 seconds |
| Started | Jul 22 08:00:07 PM PDT 24 |
| Finished | Jul 22 08:02:44 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-6760ee90-58ca-458b-aa5f-25ef9812af4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522001827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3522001827 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.759698602 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 169964999 ps |
| CPU time | 61.13 seconds |
| Started | Jul 22 08:00:04 PM PDT 24 |
| Finished | Jul 22 08:01:07 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-20574365-ee59-49a7-9ea5-5bff4505655c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759698602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_ with_rand_reset.759698602 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2140752230 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 79277607 ps |
| CPU time | 16.43 seconds |
| Started | Jul 22 08:00:09 PM PDT 24 |
| Finished | Jul 22 08:00:27 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-b641f88c-65c7-415a-a171-56ce886fb155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140752230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2140752230 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3032026175 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 1072383888 ps |
| CPU time | 47.12 seconds |
| Started | Jul 22 08:00:09 PM PDT 24 |
| Finished | Jul 22 08:00:57 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-950f08ac-320f-4584-89f4-396c07bf6ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032026175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3032026175 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1566354521 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 560360279 ps |
| CPU time | 44.1 seconds |
| Started | Jul 22 08:00:04 PM PDT 24 |
| Finished | Jul 22 08:00:50 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-88ce1d98-db40-406e-80f6-ae9fe7f1b55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566354521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1566354521 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2840680184 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 197875483 ps |
| CPU time | 23.57 seconds |
| Started | Jul 22 08:00:06 PM PDT 24 |
| Finished | Jul 22 08:00:32 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-5be0b5ad-0cc6-46e5-80ba-2cca7b4c6929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840680184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2840680184 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.999763654 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 1617539151 ps |
| CPU time | 62.93 seconds |
| Started | Jul 22 08:00:08 PM PDT 24 |
| Finished | Jul 22 08:01:13 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d43b49ff-cf90-4404-918c-d80d76b1e37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999763654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.999763654 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.806953039 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 360609573 ps |
| CPU time | 33.75 seconds |
| Started | Jul 22 08:00:04 PM PDT 24 |
| Finished | Jul 22 08:00:41 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-00650192-ba84-474a-9f4f-9ee0b913eea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806953039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.806953039 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.88899245 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 23299175138 ps |
| CPU time | 220.4 seconds |
| Started | Jul 22 08:00:11 PM PDT 24 |
| Finished | Jul 22 08:03:53 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-50ce0362-04c9-4bdc-83d5-e6ebe4f66024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88899245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.88899245 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2641728828 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 46327684512 ps |
| CPU time | 802.68 seconds |
| Started | Jul 22 08:00:11 PM PDT 24 |
| Finished | Jul 22 08:13:35 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-7c618b3d-d054-47fd-b412-029fac0e87f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641728828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2641728828 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2084306421 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 349973480 ps |
| CPU time | 29.6 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:00:37 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-95d1ab3a-0f38-4d14-b183-757daa719242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084306421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2084306421 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1278904243 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 294650160 ps |
| CPU time | 12.07 seconds |
| Started | Jul 22 08:00:06 PM PDT 24 |
| Finished | Jul 22 08:00:20 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-53a88cf4-63ab-470a-9074-0bbc6a998517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278904243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1278904243 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.1982972469 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 46830288 ps |
| CPU time | 6.12 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:00:14 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-7403152d-65ee-4e5a-a729-3a3ec1601e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982972469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.1982972469 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.87682279 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 6645419381 ps |
| CPU time | 67.54 seconds |
| Started | Jul 22 08:00:09 PM PDT 24 |
| Finished | Jul 22 08:01:18 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-db23fac3-15bf-43bd-92bf-027465207660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87682279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.87682279 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.1673651693 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 5798137173 ps |
| CPU time | 95.94 seconds |
| Started | Jul 22 08:00:10 PM PDT 24 |
| Finished | Jul 22 08:01:47 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-7b6e9ddd-cda9-4bb6-8950-aacbe2b3311f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673651693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.1673651693 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2690630015 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 37521046 ps |
| CPU time | 5.72 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:00:13 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-2845fe6c-6495-496e-88d4-0b076ef2e908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690630015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2690630015 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.773465500 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 3590473751 ps |
| CPU time | 148.22 seconds |
| Started | Jul 22 08:00:07 PM PDT 24 |
| Finished | Jul 22 08:02:38 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-ef31f6b1-28be-41bd-9ddf-fae15ca5f89d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773465500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.773465500 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.4261616375 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 3583304973 ps |
| CPU time | 120.55 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:02:08 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-61d4153d-7785-4345-9181-07e04bb85151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261616375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.4261616375 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.16729759 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 2901719167 ps |
| CPU time | 570.23 seconds |
| Started | Jul 22 08:00:11 PM PDT 24 |
| Finished | Jul 22 08:09:43 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-e16a34db-b81e-4ca5-b3cd-50f1e50ff1ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_w ith_rand_reset.16729759 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.452101007 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1533152956 ps |
| CPU time | 293.34 seconds |
| Started | Jul 22 08:00:11 PM PDT 24 |
| Finished | Jul 22 08:05:05 PM PDT 24 |
| Peak memory | 576816 kb |
| Host | smart-a35af557-9f4e-4d12-a6e3-3a52e93d23c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452101007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_reset_error.452101007 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2916374215 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 585816677 ps |
| CPU time | 25.11 seconds |
| Started | Jul 22 08:00:05 PM PDT 24 |
| Finished | Jul 22 08:00:33 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-c4d571ca-0949-4818-8c26-41153192ba38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916374215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2916374215 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1046016773 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 1707831820 ps |
| CPU time | 71.87 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:01:33 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-6d9c2832-310a-4a55-b329-25d78c8cd672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046016773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1046016773 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2548895771 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 61050559263 ps |
| CPU time | 1098.59 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:18:59 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-2c2b003b-216e-4d7d-9bcc-a362ab0d398c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548895771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.2548895771 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3449393803 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 396573034 ps |
| CPU time | 19.67 seconds |
| Started | Jul 22 08:00:18 PM PDT 24 |
| Finished | Jul 22 08:00:40 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-ab8676dd-bf2f-477f-aee5-fb53c3b2b323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449393803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3449393803 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3837316068 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 373940267 ps |
| CPU time | 29.21 seconds |
| Started | Jul 22 08:00:22 PM PDT 24 |
| Finished | Jul 22 08:00:53 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-1d3a118b-49b1-4071-8853-9a81af0db42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837316068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3837316068 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.2086029873 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 71503998 ps |
| CPU time | 8.77 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:00:30 PM PDT 24 |
| Peak memory | 574788 kb |
| Host | smart-1e31ffc6-5143-4cc7-979b-078dcf50a232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086029873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2086029873 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3418122746 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 8468299615 ps |
| CPU time | 84 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:01:45 PM PDT 24 |
| Peak memory | 576100 kb |
| Host | smart-8410fb89-be65-4c07-8b0a-52fb261cbc24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418122746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3418122746 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.4118764624 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 65272916836 ps |
| CPU time | 1170.4 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:19:51 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-c11991ec-a74a-41bc-ad79-002c673508d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118764624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.4118764624 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3740268964 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 193463281 ps |
| CPU time | 19.22 seconds |
| Started | Jul 22 08:00:53 PM PDT 24 |
| Finished | Jul 22 08:01:15 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-924e6529-1e4b-4c02-b4a5-ce3dc678ed59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740268964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.3740268964 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2070314733 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 254571152 ps |
| CPU time | 19.65 seconds |
| Started | Jul 22 08:00:22 PM PDT 24 |
| Finished | Jul 22 08:00:43 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-0035f41c-a401-480f-a390-ec1a54098277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070314733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2070314733 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3058918561 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 212579174 ps |
| CPU time | 9.12 seconds |
| Started | Jul 22 08:00:12 PM PDT 24 |
| Finished | Jul 22 08:00:22 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-22953092-6597-4e73-891a-7539a4f4dc9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058918561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3058918561 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3570086064 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 8458398315 ps |
| CPU time | 89.04 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:01:50 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-1ce0a267-8cd7-43f3-841e-4b6dab9bf2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570086064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3570086064 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.605917130 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 5261560731 ps |
| CPU time | 86.18 seconds |
| Started | Jul 22 08:00:18 PM PDT 24 |
| Finished | Jul 22 08:01:46 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-e1456bae-d7ac-4ec0-90a8-d630eb1dc61e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605917130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.605917130 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4228897886 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 51993448 ps |
| CPU time | 6.1 seconds |
| Started | Jul 22 08:00:22 PM PDT 24 |
| Finished | Jul 22 08:00:29 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-341501c4-e02f-4682-973f-80d5a5286c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228897886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.4228897886 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3081927451 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2485091015 ps |
| CPU time | 209.59 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:03:51 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-8a97433b-e004-4166-92af-f149abcc6db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081927451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3081927451 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.316802945 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 2769754531 ps |
| CPU time | 179.56 seconds |
| Started | Jul 22 08:01:05 PM PDT 24 |
| Finished | Jul 22 08:04:07 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-ddf3c482-7006-4c77-b5fc-8e35fb368286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316802945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.316802945 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1754199209 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4080891600 ps |
| CPU time | 346.11 seconds |
| Started | Jul 22 08:00:20 PM PDT 24 |
| Finished | Jul 22 08:06:08 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-f70e2637-0f16-4cd2-b544-3750776a44f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754199209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1754199209 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3775624705 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 150457873 ps |
| CPU time | 66.28 seconds |
| Started | Jul 22 08:00:19 PM PDT 24 |
| Finished | Jul 22 08:01:27 PM PDT 24 |
| Peak memory | 576888 kb |
| Host | smart-4aae5364-154b-46a3-a820-e0376b44cbaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775624705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.3775624705 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2813003373 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 179368161 ps |
| CPU time | 22.83 seconds |
| Started | Jul 22 08:00:26 PM PDT 24 |
| Finished | Jul 22 08:00:51 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-9cb31cf7-915d-4b49-8b99-9b9a79993766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813003373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2813003373 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.2181439593 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 2746191613 ps |
| CPU time | 100.32 seconds |
| Started | Jul 22 08:00:37 PM PDT 24 |
| Finished | Jul 22 08:02:22 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-8f838a21-5f65-4f4b-beef-afdce8b93933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181439593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2181439593 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.4215910449 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 69852728654 ps |
| CPU time | 1310.19 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:22:31 PM PDT 24 |
| Peak memory | 577012 kb |
| Host | smart-9c09505c-12ca-4069-8a58-52c0244d2a52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215910449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.4215910449 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3069051139 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 75679835 ps |
| CPU time | 9.46 seconds |
| Started | Jul 22 08:00:41 PM PDT 24 |
| Finished | Jul 22 08:00:53 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-dd881fba-4fde-4979-846c-13570afb4f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069051139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3069051139 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.175478077 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 1648403790 ps |
| CPU time | 58.89 seconds |
| Started | Jul 22 08:00:35 PM PDT 24 |
| Finished | Jul 22 08:01:38 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-27dc5672-cd09-4b29-a608-19b8ee9d0eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175478077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.175478077 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.2768651579 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 2072292812 ps |
| CPU time | 69.49 seconds |
| Started | Jul 22 08:00:26 PM PDT 24 |
| Finished | Jul 22 08:01:37 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-753bc090-715b-48ed-8aa7-11c0e580052a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768651579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2768651579 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1304659143 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 84924550429 ps |
| CPU time | 964.55 seconds |
| Started | Jul 22 08:00:38 PM PDT 24 |
| Finished | Jul 22 08:16:47 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-20eab696-981b-42e3-af4a-1d2ffe396964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304659143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1304659143 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1967411213 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 47850690625 ps |
| CPU time | 891.94 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:15:32 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-8fbb1cf9-7d90-4481-bd4a-97fc225e7417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967411213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1967411213 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1582479623 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 349129853 ps |
| CPU time | 32.48 seconds |
| Started | Jul 22 08:00:24 PM PDT 24 |
| Finished | Jul 22 08:00:58 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-08516cea-9f91-44c4-aa7b-d6c5c36d74f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582479623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1582479623 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.4102305263 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 400998798 ps |
| CPU time | 31.25 seconds |
| Started | Jul 22 08:00:35 PM PDT 24 |
| Finished | Jul 22 08:01:11 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-07a9969a-88db-49e3-bf4e-3145158bb78e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102305263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.4102305263 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2658816055 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 130024849 ps |
| CPU time | 7.4 seconds |
| Started | Jul 22 08:00:18 PM PDT 24 |
| Finished | Jul 22 08:00:27 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-d2997f63-51af-4c55-8968-a8d1ab1301ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658816055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2658816055 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2869687242 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 8101546259 ps |
| CPU time | 79.14 seconds |
| Started | Jul 22 08:00:24 PM PDT 24 |
| Finished | Jul 22 08:01:46 PM PDT 24 |
| Peak memory | 575004 kb |
| Host | smart-e293961a-d14d-4621-835f-c30132ecb0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869687242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2869687242 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1102021937 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 3698187653 ps |
| CPU time | 59.48 seconds |
| Started | Jul 22 08:00:22 PM PDT 24 |
| Finished | Jul 22 08:01:23 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-96fa7830-9efa-4efb-844b-6d4ed38345af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102021937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1102021937 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.723420068 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 38742424 ps |
| CPU time | 5.71 seconds |
| Started | Jul 22 08:00:25 PM PDT 24 |
| Finished | Jul 22 08:00:33 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-f76a46f9-7931-432e-a0dc-710906f16612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723420068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays .723420068 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.2474380354 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 2227532273 ps |
| CPU time | 166.39 seconds |
| Started | Jul 22 08:00:35 PM PDT 24 |
| Finished | Jul 22 08:03:25 PM PDT 24 |
| Peak memory | 577104 kb |
| Host | smart-25e0a0db-b5d2-4fed-9945-072d52db6f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474380354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.2474380354 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.1623973812 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 3020907421 ps |
| CPU time | 106.74 seconds |
| Started | Jul 22 08:00:35 PM PDT 24 |
| Finished | Jul 22 08:02:26 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-3beb1a72-0aac-4846-a057-a3a5d2786b59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623973812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.1623973812 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2376262007 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 13979761469 ps |
| CPU time | 794.49 seconds |
| Started | Jul 22 08:04:39 PM PDT 24 |
| Finished | Jul 22 08:17:55 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-76cad70d-b593-4485-bb15-91973484a77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376262007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.2376262007 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.369267880 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 800680414 ps |
| CPU time | 161.96 seconds |
| Started | Jul 22 08:00:37 PM PDT 24 |
| Finished | Jul 22 08:03:23 PM PDT 24 |
| Peak memory | 576892 kb |
| Host | smart-1dca2b0a-b558-449e-965c-1f81d8a60db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369267880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_reset_error.369267880 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2218707731 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 124464029 ps |
| CPU time | 17.17 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:00:57 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-6cff8dc2-7605-438a-beaa-a2a908c648d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218707731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2218707731 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3794826056 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 3484878156 ps |
| CPU time | 143.32 seconds |
| Started | Jul 22 08:00:40 PM PDT 24 |
| Finished | Jul 22 08:03:06 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-72701acd-6ce4-4109-973d-aad2111dad37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794826056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3794826056 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2451995691 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 37144104576 ps |
| CPU time | 713.04 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:12:33 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-05540636-30ff-47b5-84f0-b4812657b88f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451995691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2451995691 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2538861658 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 187942911 ps |
| CPU time | 20.19 seconds |
| Started | Jul 22 08:00:55 PM PDT 24 |
| Finished | Jul 22 08:01:17 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-b37a9127-77c1-4a90-96ca-356ce6210e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538861658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2538861658 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2011578396 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 331924236 ps |
| CPU time | 26.69 seconds |
| Started | Jul 22 08:00:35 PM PDT 24 |
| Finished | Jul 22 08:01:06 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-73403317-64ab-46a8-abbb-a45e28dcc491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011578396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2011578396 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.2898511338 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 66149619 ps |
| CPU time | 8.51 seconds |
| Started | Jul 22 08:00:34 PM PDT 24 |
| Finished | Jul 22 08:00:46 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-9c82a3b6-2177-479b-be50-93d98de7d18f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898511338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2898511338 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.4234288921 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 29598937248 ps |
| CPU time | 324.4 seconds |
| Started | Jul 22 08:00:37 PM PDT 24 |
| Finished | Jul 22 08:06:05 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-04b74582-18f7-45f5-a8d3-f7358e2dcd9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234288921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.4234288921 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3655598276 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 19629355958 ps |
| CPU time | 339.04 seconds |
| Started | Jul 22 08:00:35 PM PDT 24 |
| Finished | Jul 22 08:06:17 PM PDT 24 |
| Peak memory | 576828 kb |
| Host | smart-49d34e4a-7595-4f67-a2d2-105d6a71bfb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655598276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3655598276 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.175176557 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 400924495 ps |
| CPU time | 31.41 seconds |
| Started | Jul 22 08:00:51 PM PDT 24 |
| Finished | Jul 22 08:01:24 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-89825cb1-b36e-4b2d-908e-c77784030879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175176557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.175176557 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.1440689408 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 354386540 ps |
| CPU time | 12.48 seconds |
| Started | Jul 22 08:00:38 PM PDT 24 |
| Finished | Jul 22 08:00:55 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-2028455f-2927-4a51-9edc-10f7f2b5567f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440689408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1440689408 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.2371055339 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 42478816 ps |
| CPU time | 5.7 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:00:46 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-16afd586-9342-4a6d-8a37-8354806cb48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371055339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2371055339 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.3787017422 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 6374971230 ps |
| CPU time | 62.05 seconds |
| Started | Jul 22 08:00:41 PM PDT 24 |
| Finished | Jul 22 08:01:46 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-48214c9c-bf43-49de-99d8-60bc0c22032a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787017422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.3787017422 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.704658154 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 4821055970 ps |
| CPU time | 83.63 seconds |
| Started | Jul 22 08:00:36 PM PDT 24 |
| Finished | Jul 22 08:02:04 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-8b8a1a3e-8ba3-4ca4-b543-3aca4c4c9cb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704658154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.704658154 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2385221772 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 57863515 ps |
| CPU time | 6.63 seconds |
| Started | Jul 22 08:00:51 PM PDT 24 |
| Finished | Jul 22 08:00:59 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-582fd398-cf39-40e3-a940-65bb9396de25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385221772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.2385221772 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2509845744 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1645173974 ps |
| CPU time | 139.19 seconds |
| Started | Jul 22 08:00:53 PM PDT 24 |
| Finished | Jul 22 08:03:13 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-6969731b-7f63-4945-beb6-f8cd8ceef42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509845744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2509845744 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3420387891 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 423810176 ps |
| CPU time | 36.25 seconds |
| Started | Jul 22 08:00:50 PM PDT 24 |
| Finished | Jul 22 08:01:27 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-c8522754-0537-4135-a3c7-aeaf706b063b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420387891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3420387891 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.26453426 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 651529193 ps |
| CPU time | 238.92 seconds |
| Started | Jul 22 08:00:54 PM PDT 24 |
| Finished | Jul 22 08:04:54 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-8bbad414-b94b-4c75-8401-12c5ba32977c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26453426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_w ith_rand_reset.26453426 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2594109272 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 70509690 ps |
| CPU time | 39.13 seconds |
| Started | Jul 22 08:00:53 PM PDT 24 |
| Finished | Jul 22 08:01:33 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-388a8ba7-7c0a-4890-9b9a-b8aba3d25dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594109272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2594109272 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2866126403 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 967927369 ps |
| CPU time | 37.52 seconds |
| Started | Jul 22 08:00:48 PM PDT 24 |
| Finished | Jul 22 08:01:27 PM PDT 24 |
| Peak memory | 576844 kb |
| Host | smart-1ae8377a-a8ef-435e-902f-73abda29f4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866126403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2866126403 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2024744313 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 575655188 ps |
| CPU time | 33.54 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:01:24 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-d5347dba-1487-4b37-832f-7936cea2fd25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024744313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2024744313 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3584675169 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 8409394120 ps |
| CPU time | 144.36 seconds |
| Started | Jul 22 08:01:53 PM PDT 24 |
| Finished | Jul 22 08:04:19 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-aebb91b7-3166-44fc-84b0-e560b516abc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584675169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3584675169 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.879456517 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 275910384 ps |
| CPU time | 12.75 seconds |
| Started | Jul 22 08:00:52 PM PDT 24 |
| Finished | Jul 22 08:01:06 PM PDT 24 |
| Peak memory | 576832 kb |
| Host | smart-38f56c55-26ac-46fc-bf6d-30c3b32b21e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879456517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr .879456517 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3087776583 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 125427436 ps |
| CPU time | 11.52 seconds |
| Started | Jul 22 08:00:50 PM PDT 24 |
| Finished | Jul 22 08:01:03 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-ab7903c6-a68c-42da-8398-6f6f4ba3b3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087776583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3087776583 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.608351203 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 396554558 ps |
| CPU time | 35.29 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:01:25 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-b77d001e-fd9e-41ec-a9c5-7e0b9c50a95b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608351203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.608351203 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1942380545 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 47706335089 ps |
| CPU time | 564.07 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:10:14 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-45557d23-9b55-4484-a3df-0c5dc709ac74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942380545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1942380545 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3511160744 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 35961339076 ps |
| CPU time | 664.09 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:11:55 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-a156574f-10aa-45a6-b8c9-e605c4f9176c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511160744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3511160744 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1875359450 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 606175641 ps |
| CPU time | 55.49 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:01:46 PM PDT 24 |
| Peak memory | 576760 kb |
| Host | smart-f570ac5b-6646-4a3c-a98f-af8da33f296d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875359450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.1875359450 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1253492655 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 2317700669 ps |
| CPU time | 68.15 seconds |
| Started | Jul 22 08:00:52 PM PDT 24 |
| Finished | Jul 22 08:02:01 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-cdd9818c-ff1b-427f-8e85-1822c5dc9cbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253492655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1253492655 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.849365898 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 53259879 ps |
| CPU time | 6.59 seconds |
| Started | Jul 22 08:00:50 PM PDT 24 |
| Finished | Jul 22 08:00:58 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-dd8e94fb-4493-4111-9f36-b46528ab7ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849365898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.849365898 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2725959239 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 7252457471 ps |
| CPU time | 75.49 seconds |
| Started | Jul 22 08:00:53 PM PDT 24 |
| Finished | Jul 22 08:02:10 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-6c03e1ca-b3e3-467f-9c21-6f67d8526dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725959239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2725959239 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.1528797469 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 6135687088 ps |
| CPU time | 97.03 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:02:28 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-727c37fd-3b52-4386-999d-8623875fb20a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528797469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.1528797469 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2120313292 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 33363570 ps |
| CPU time | 5.81 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:00:57 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-59806a40-d3e2-4ce8-9ab9-e45d70022c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120313292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2120313292 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.2050225830 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 5900222375 ps |
| CPU time | 206.49 seconds |
| Started | Jul 22 08:00:51 PM PDT 24 |
| Finished | Jul 22 08:04:19 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-c5859f09-2e2f-47b0-81f0-52a3327fc938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050225830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.2050225830 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.4087700899 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 7908764622 ps |
| CPU time | 263.75 seconds |
| Started | Jul 22 08:02:37 PM PDT 24 |
| Finished | Jul 22 08:07:21 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-946cf82e-8c2d-4f73-81ac-e4e0a82fc164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087700899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.4087700899 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3421103907 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 297928556 ps |
| CPU time | 112.34 seconds |
| Started | Jul 22 08:00:50 PM PDT 24 |
| Finished | Jul 22 08:02:43 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-8df5786e-74dd-4ee7-b2cd-2be0e64ba148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421103907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3421103907 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2897041020 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 4027909342 ps |
| CPU time | 286.88 seconds |
| Started | Jul 22 08:00:48 PM PDT 24 |
| Finished | Jul 22 08:05:35 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-2bf117dd-6dc8-44f7-8f1c-cca3388132a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897041020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.2897041020 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3084922213 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1229127644 ps |
| CPU time | 47.24 seconds |
| Started | Jul 22 08:00:49 PM PDT 24 |
| Finished | Jul 22 08:01:37 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-141e7e0e-8a01-4820-a4fa-e122bfe645ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084922213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3084922213 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1344602755 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 808458302 ps |
| CPU time | 35.85 seconds |
| Started | Jul 22 08:01:06 PM PDT 24 |
| Finished | Jul 22 08:01:46 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-62917e31-12bf-4301-920b-bc5c7d821a7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344602755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1344602755 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2351660552 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 318233693 ps |
| CPU time | 16 seconds |
| Started | Jul 22 08:01:10 PM PDT 24 |
| Finished | Jul 22 08:01:30 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-5092e799-1ef7-42e3-94f6-e4656c764124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351660552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2351660552 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2713203 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 1023940586 ps |
| CPU time | 33.25 seconds |
| Started | Jul 22 08:01:07 PM PDT 24 |
| Finished | Jul 22 08:01:45 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-c62a480f-2ef7-449c-839a-95bc47f5a310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2713203 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1988760324 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 2305157755 ps |
| CPU time | 81.45 seconds |
| Started | Jul 22 08:02:47 PM PDT 24 |
| Finished | Jul 22 08:04:23 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-c1e37421-c8ce-469b-838e-53f21195a79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988760324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1988760324 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4288771562 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 37737711805 ps |
| CPU time | 404.45 seconds |
| Started | Jul 22 08:01:06 PM PDT 24 |
| Finished | Jul 22 08:07:55 PM PDT 24 |
| Peak memory | 577012 kb |
| Host | smart-0e0db0b5-f3c3-493c-8f85-51b0dffffe7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288771562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4288771562 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.396292979 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 25297507432 ps |
| CPU time | 441.15 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:08:34 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-367b2fa1-5d1a-4b43-b950-39f9a4ec0bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396292979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.396292979 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3553242889 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 439756289 ps |
| CPU time | 43.47 seconds |
| Started | Jul 22 08:01:07 PM PDT 24 |
| Finished | Jul 22 08:01:55 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-7201c073-6fc1-45bc-9442-73867e39ab16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553242889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3553242889 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.2123364971 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 261203900 ps |
| CPU time | 19.81 seconds |
| Started | Jul 22 08:01:10 PM PDT 24 |
| Finished | Jul 22 08:01:34 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-01bb3b90-870b-429e-8821-42bd9e98e4ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123364971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.2123364971 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.121795496 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 249687568 ps |
| CPU time | 9.66 seconds |
| Started | Jul 22 08:00:51 PM PDT 24 |
| Finished | Jul 22 08:01:02 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-897ea46b-32f3-44ac-a29c-18fbdbafa420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121795496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.121795496 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3140690415 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 8298325482 ps |
| CPU time | 85.47 seconds |
| Started | Jul 22 08:01:07 PM PDT 24 |
| Finished | Jul 22 08:02:37 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-905ad75e-d8da-432b-b5b3-e9858b2d39d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140690415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3140690415 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1304781740 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 5334481275 ps |
| CPU time | 85.13 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:02:37 PM PDT 24 |
| Peak memory | 574872 kb |
| Host | smart-6967c2de-3239-4d39-a9f1-37615d2a82b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304781740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1304781740 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1976237329 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 43461050 ps |
| CPU time | 6.02 seconds |
| Started | Jul 22 08:01:06 PM PDT 24 |
| Finished | Jul 22 08:01:16 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-d549c62a-8a85-4a06-805c-34844d930496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976237329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1976237329 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2639737882 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 8000286731 ps |
| CPU time | 286.43 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:05:59 PM PDT 24 |
| Peak memory | 577000 kb |
| Host | smart-edbd0256-0bea-40a0-b4e4-86855564fc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639737882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2639737882 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.256807788 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 1956999636 ps |
| CPU time | 458.47 seconds |
| Started | Jul 22 08:01:19 PM PDT 24 |
| Finished | Jul 22 08:08:59 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-88e3118f-9f71-4aee-9a60-24a8285d0d7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256807788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.256807788 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3703428968 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 721767021 ps |
| CPU time | 202.35 seconds |
| Started | Jul 22 08:01:09 PM PDT 24 |
| Finished | Jul 22 08:04:36 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-0e3a5bf0-8fe0-4ba9-b12b-4bc1ed6415a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703428968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3703428968 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.1313968821 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 612362172 ps |
| CPU time | 23.72 seconds |
| Started | Jul 22 08:01:06 PM PDT 24 |
| Finished | Jul 22 08:01:34 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-c826814a-96cb-45b7-b5f5-929a133521bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313968821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.1313968821 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.38811717 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 192835286 ps |
| CPU time | 14.15 seconds |
| Started | Jul 22 08:01:12 PM PDT 24 |
| Finished | Jul 22 08:01:30 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-ecfeb4c0-8e85-45d2-bb4f-1c947af1f20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device.38811717 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1199909771 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 105821310576 ps |
| CPU time | 2071.32 seconds |
| Started | Jul 22 08:01:11 PM PDT 24 |
| Finished | Jul 22 08:35:47 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-cad4a20e-74ec-49f7-9399-4180068ecd5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199909771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1199909771 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.492195998 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 1037174118 ps |
| CPU time | 38.24 seconds |
| Started | Jul 22 08:01:13 PM PDT 24 |
| Finished | Jul 22 08:01:54 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-f96efefd-ce98-4337-8d89-22f943aa130f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492195998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .492195998 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1847912574 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 984548948 ps |
| CPU time | 35.96 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:01:49 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-41fd3a0c-152c-40cc-b4e7-915de37aec19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847912574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1847912574 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.2898347809 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 110398889 ps |
| CPU time | 12.13 seconds |
| Started | Jul 22 08:01:12 PM PDT 24 |
| Finished | Jul 22 08:01:28 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-8931ce32-5305-4503-b4e8-36b44d8fd64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898347809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2898347809 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1828745332 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 85371628030 ps |
| CPU time | 977.3 seconds |
| Started | Jul 22 08:01:12 PM PDT 24 |
| Finished | Jul 22 08:17:33 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-9bcb2c6f-36aa-4364-be3f-bdef97893030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828745332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1828745332 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2020251129 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 10026538937 ps |
| CPU time | 169.55 seconds |
| Started | Jul 22 08:01:10 PM PDT 24 |
| Finished | Jul 22 08:04:03 PM PDT 24 |
| Peak memory | 576904 kb |
| Host | smart-a84dc06a-c2f3-41f1-a46b-2d82287318d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020251129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2020251129 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.3607525493 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 35182758 ps |
| CPU time | 5.95 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:01:18 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-03ff6d85-1a98-4585-80d8-ff512964624c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607525493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.3607525493 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2806470227 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 571171408 ps |
| CPU time | 37.33 seconds |
| Started | Jul 22 08:01:13 PM PDT 24 |
| Finished | Jul 22 08:01:53 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-eb36527b-1910-4106-9d71-1f2f12b717b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806470227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2806470227 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.4204835026 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 159132949 ps |
| CPU time | 7.8 seconds |
| Started | Jul 22 08:01:06 PM PDT 24 |
| Finished | Jul 22 08:01:18 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-9ffb8d56-749c-4680-b29d-af5ce8673c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204835026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.4204835026 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1138690438 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 7875679270 ps |
| CPU time | 77.18 seconds |
| Started | Jul 22 08:01:13 PM PDT 24 |
| Finished | Jul 22 08:02:33 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-e90737e1-6123-46e6-85be-22ff1d88aad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138690438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1138690438 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.204691524 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 5766994651 ps |
| CPU time | 95.44 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:02:48 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-dc8e60a3-1567-4836-9c12-d476fa73ad05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204691524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.204691524 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3416541168 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 52727939 ps |
| CPU time | 6.51 seconds |
| Started | Jul 22 08:01:08 PM PDT 24 |
| Finished | Jul 22 08:01:20 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-b77da75f-d5ba-4f8b-8c2b-e182be792807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416541168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3416541168 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.76198194 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 6113953731 ps |
| CPU time | 216.19 seconds |
| Started | Jul 22 08:01:13 PM PDT 24 |
| Finished | Jul 22 08:04:52 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-014b91d7-a68b-41c9-b22b-c3502dc1582c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76198194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.76198194 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2861569624 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 4057080967 ps |
| CPU time | 110.17 seconds |
| Started | Jul 22 08:01:10 PM PDT 24 |
| Finished | Jul 22 08:03:04 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-696ba36e-e60b-493c-a4db-abca25d7d177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861569624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2861569624 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2937236209 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 100390879 ps |
| CPU time | 39.16 seconds |
| Started | Jul 22 08:01:13 PM PDT 24 |
| Finished | Jul 22 08:01:55 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-56c2173a-cc81-4727-9a13-3f64d43c7eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937236209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.2937236209 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.860910678 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 190753027 ps |
| CPU time | 32.71 seconds |
| Started | Jul 22 08:01:13 PM PDT 24 |
| Finished | Jul 22 08:01:49 PM PDT 24 |
| Peak memory | 576928 kb |
| Host | smart-94d7e093-4780-4e6e-82ce-618ca0517837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860910678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.860910678 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1776049168 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 323727967 ps |
| CPU time | 34.73 seconds |
| Started | Jul 22 08:01:11 PM PDT 24 |
| Finished | Jul 22 08:01:50 PM PDT 24 |
| Peak memory | 576824 kb |
| Host | smart-ca98aa68-9956-49f0-bfa5-10500fa6d34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776049168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1776049168 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2076148488 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 2352408824 ps |
| CPU time | 97.16 seconds |
| Started | Jul 22 08:01:22 PM PDT 24 |
| Finished | Jul 22 08:02:59 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-4fec65d9-8b67-4a26-bf8d-9eec0991ff42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076148488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2076148488 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2394409307 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 74332731470 ps |
| CPU time | 1442.62 seconds |
| Started | Jul 22 08:01:20 PM PDT 24 |
| Finished | Jul 22 08:25:23 PM PDT 24 |
| Peak memory | 576988 kb |
| Host | smart-faef85d7-b8f7-41b5-8f8a-703b6d3fd884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394409307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2394409307 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2105767715 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 360339827 ps |
| CPU time | 16.58 seconds |
| Started | Jul 22 08:01:23 PM PDT 24 |
| Finished | Jul 22 08:01:41 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-730eb4b1-e4e0-422d-9b59-dabb966e4418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105767715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2105767715 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.2852785810 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 565604945 ps |
| CPU time | 43.63 seconds |
| Started | Jul 22 08:01:27 PM PDT 24 |
| Finished | Jul 22 08:02:11 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-30dd43d8-a529-4788-b9a4-aa17b1e71d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852785810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2852785810 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.1175701934 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 576695385 ps |
| CPU time | 20.32 seconds |
| Started | Jul 22 08:01:24 PM PDT 24 |
| Finished | Jul 22 08:01:45 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-920c592d-8c6c-4abc-9d44-c20e957a78ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175701934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.1175701934 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2689350297 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 9621230294 ps |
| CPU time | 92.52 seconds |
| Started | Jul 22 08:05:26 PM PDT 24 |
| Finished | Jul 22 08:07:01 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-3183e252-502b-446c-82c3-d48dd378b18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689350297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2689350297 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3639118796 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 44531110177 ps |
| CPU time | 836.66 seconds |
| Started | Jul 22 08:01:23 PM PDT 24 |
| Finished | Jul 22 08:15:20 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-428b3543-db63-4dd5-99e7-5a5cd1dacc86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639118796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3639118796 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.209606381 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 229821960 ps |
| CPU time | 19.76 seconds |
| Started | Jul 22 08:01:21 PM PDT 24 |
| Finished | Jul 22 08:01:41 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-6a2c5c08-9ebe-4680-b6b5-52302d81754e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209606381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.209606381 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.4011255843 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 142572676 ps |
| CPU time | 13.46 seconds |
| Started | Jul 22 08:01:22 PM PDT 24 |
| Finished | Jul 22 08:01:37 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-b22643c3-23ab-4b3c-a05a-00f450dac8d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011255843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.4011255843 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.2862304808 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 54353429 ps |
| CPU time | 6.32 seconds |
| Started | Jul 22 08:01:10 PM PDT 24 |
| Finished | Jul 22 08:01:21 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-63c8fab7-484a-44ee-ab8e-e12f005ba694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862304808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2862304808 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1446710030 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 9431931542 ps |
| CPU time | 94.57 seconds |
| Started | Jul 22 08:01:23 PM PDT 24 |
| Finished | Jul 22 08:02:58 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-48c566c5-cf83-4410-aa3e-d2a9a3fa4505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446710030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1446710030 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1197786586 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 4331559086 ps |
| CPU time | 75.98 seconds |
| Started | Jul 22 08:01:21 PM PDT 24 |
| Finished | Jul 22 08:02:38 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-8b589e9f-7def-463f-a091-0d3642241fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197786586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1197786586 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1084749601 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 52152023 ps |
| CPU time | 6.25 seconds |
| Started | Jul 22 08:01:21 PM PDT 24 |
| Finished | Jul 22 08:01:28 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-12f0b406-dc0e-47ee-adaf-c4d9213bd87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084749601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1084749601 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2177702237 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 1212344123 ps |
| CPU time | 84.4 seconds |
| Started | Jul 22 08:01:43 PM PDT 24 |
| Finished | Jul 22 08:03:10 PM PDT 24 |
| Peak memory | 576864 kb |
| Host | smart-2c0a69ce-4610-48bb-a4f5-b07889956ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177702237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2177702237 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.476166138 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 6967064957 ps |
| CPU time | 270.36 seconds |
| Started | Jul 22 08:01:26 PM PDT 24 |
| Finished | Jul 22 08:05:58 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-4fecdfdc-f974-48a7-9ea6-87c2bbfe2b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476166138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.476166138 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.4278912230 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1530598832 ps |
| CPU time | 178.81 seconds |
| Started | Jul 22 08:01:23 PM PDT 24 |
| Finished | Jul 22 08:04:23 PM PDT 24 |
| Peak memory | 576948 kb |
| Host | smart-8516db94-7c9e-4a27-aaa1-478cc80f46c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278912230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.4278912230 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.435232811 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 12908504119 ps |
| CPU time | 673.94 seconds |
| Started | Jul 22 08:03:26 PM PDT 24 |
| Finished | Jul 22 08:14:41 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-3351bad9-682d-4b90-95cf-996d02d1b52a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435232811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_reset_error.435232811 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.209749517 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 65339696 ps |
| CPU time | 6.58 seconds |
| Started | Jul 22 08:01:23 PM PDT 24 |
| Finished | Jul 22 08:01:30 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-e955d06a-64bb-4f74-a30c-8c4fcbb586ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209749517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.209749517 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2104352749 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 961154156 ps |
| CPU time | 56.21 seconds |
| Started | Jul 22 08:01:22 PM PDT 24 |
| Finished | Jul 22 08:02:19 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-7d833f3d-5be2-4bdd-b6e9-cc7be1999dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104352749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .2104352749 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3767012584 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 62485424726 ps |
| CPU time | 1206.74 seconds |
| Started | Jul 22 08:01:24 PM PDT 24 |
| Finished | Jul 22 08:21:31 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-08ec5372-1a64-4b82-8777-518d235cd684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767012584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.3767012584 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1268512059 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 360589266 ps |
| CPU time | 17.28 seconds |
| Started | Jul 22 08:02:32 PM PDT 24 |
| Finished | Jul 22 08:03:10 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-d4128f73-1b59-432f-b51e-ba183c311cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268512059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.1268512059 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.717642937 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 120172437 ps |
| CPU time | 7.51 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:02:39 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-755375aa-558b-4088-b8ac-57cc2a7a9549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717642937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.717642937 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1859661064 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 1526378062 ps |
| CPU time | 55.01 seconds |
| Started | Jul 22 08:01:27 PM PDT 24 |
| Finished | Jul 22 08:02:23 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-2ede9b3e-a62d-42bf-b35d-f8c479e244b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859661064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1859661064 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3763033790 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 71575039848 ps |
| CPU time | 744.92 seconds |
| Started | Jul 22 08:01:26 PM PDT 24 |
| Finished | Jul 22 08:13:51 PM PDT 24 |
| Peak memory | 576936 kb |
| Host | smart-8b2810f9-09e5-479a-bd6a-dda9450353c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763033790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3763033790 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.2418473511 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 54378333936 ps |
| CPU time | 1054.43 seconds |
| Started | Jul 22 08:01:26 PM PDT 24 |
| Finished | Jul 22 08:19:01 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-109412e1-58f5-4f47-857e-1ddbdd5e9382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418473511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2418473511 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3094360238 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 99330930 ps |
| CPU time | 11.22 seconds |
| Started | Jul 22 08:01:27 PM PDT 24 |
| Finished | Jul 22 08:01:39 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-b8edb62a-97e1-43ac-b08e-60139316b22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094360238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3094360238 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2583825931 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 1974741610 ps |
| CPU time | 56.83 seconds |
| Started | Jul 22 08:02:29 PM PDT 24 |
| Finished | Jul 22 08:03:44 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-5964ae77-adf9-4d71-b2c3-38f5e4c3e0a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583825931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2583825931 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.183682215 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 250804239 ps |
| CPU time | 9.53 seconds |
| Started | Jul 22 08:01:27 PM PDT 24 |
| Finished | Jul 22 08:01:37 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-e1a47a72-b53a-40ac-ada2-cd10a5b0db72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183682215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.183682215 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.831947585 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 9372562826 ps |
| CPU time | 96.5 seconds |
| Started | Jul 22 08:03:26 PM PDT 24 |
| Finished | Jul 22 08:05:04 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-55d9b946-ad29-42f7-b1f3-d42ac5c968ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831947585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.831947585 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.268477919 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 5668570311 ps |
| CPU time | 97.13 seconds |
| Started | Jul 22 08:01:23 PM PDT 24 |
| Finished | Jul 22 08:03:01 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-318ba7a2-144d-48d5-a64d-4307ad2d3bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268477919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.268477919 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.624634413 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 44790943 ps |
| CPU time | 5.91 seconds |
| Started | Jul 22 08:01:26 PM PDT 24 |
| Finished | Jul 22 08:01:33 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-2144b3db-004e-4447-a5ef-bb01f37fc61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624634413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .624634413 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3050523940 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 13495973509 ps |
| CPU time | 541.75 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:11:37 PM PDT 24 |
| Peak memory | 576988 kb |
| Host | smart-0de92c19-7bac-434c-bf76-e2ff953e8d3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050523940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3050523940 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2603660010 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 1227487322 ps |
| CPU time | 38.52 seconds |
| Started | Jul 22 08:02:28 PM PDT 24 |
| Finished | Jul 22 08:03:25 PM PDT 24 |
| Peak memory | 576792 kb |
| Host | smart-a731433e-5a22-4e82-8d08-e4adfaba8a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603660010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2603660010 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2462075676 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1125397177 ps |
| CPU time | 474.02 seconds |
| Started | Jul 22 08:02:28 PM PDT 24 |
| Finished | Jul 22 08:10:40 PM PDT 24 |
| Peak memory | 576956 kb |
| Host | smart-6da99f4c-3a2f-4948-91ff-8a8032da1180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462075676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2462075676 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1235507658 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 8484328343 ps |
| CPU time | 915.63 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:17:51 PM PDT 24 |
| Peak memory | 583196 kb |
| Host | smart-f04df7bd-0088-4a21-949d-81002274f9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235507658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1235507658 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.156020277 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 754390979 ps |
| CPU time | 29.64 seconds |
| Started | Jul 22 08:02:26 PM PDT 24 |
| Finished | Jul 22 08:03:09 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-f7b23e9b-bda9-4ff5-bc9b-f50f9971133b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156020277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.156020277 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3215743311 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 10460130510 ps |
| CPU time | 668.76 seconds |
| Started | Jul 22 07:44:27 PM PDT 24 |
| Finished | Jul 22 07:55:38 PM PDT 24 |
| Peak memory | 653508 kb |
| Host | smart-f8e56ea4-4046-44c7-8e5b-44c89d72f301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215743311 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.3215743311 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2342452938 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 5778541507 ps |
| CPU time | 646.94 seconds |
| Started | Jul 22 07:44:19 PM PDT 24 |
| Finished | Jul 22 07:55:08 PM PDT 24 |
| Peak memory | 599124 kb |
| Host | smart-4266f517-0596-4421-9282-88787dac71ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342452938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2342452938 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.1457866271 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 32651940836 ps |
| CPU time | 3712.49 seconds |
| Started | Jul 22 07:44:03 PM PDT 24 |
| Finished | Jul 22 08:45:58 PM PDT 24 |
| Peak memory | 593756 kb |
| Host | smart-de9d1cea-fe99-4b75-9834-faca0afe6404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457866271 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.1457866271 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3653257810 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 3076935756 ps |
| CPU time | 211 seconds |
| Started | Jul 22 07:44:05 PM PDT 24 |
| Finished | Jul 22 07:47:37 PM PDT 24 |
| Peak memory | 599304 kb |
| Host | smart-d4b49408-1ac9-4e39-a0aa-5920d1632555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653257810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3653257810 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.3118166073 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 303871134 ps |
| CPU time | 20.58 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:46:17 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-dd443f33-bf60-42aa-bdf1-835f58957cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118166073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 3118166073 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1712242999 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 44811625262 ps |
| CPU time | 655.2 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:56:42 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-d805f4b9-5771-4171-8147-6286569d049b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712242999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.1712242999 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1608904163 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 1208391223 ps |
| CPU time | 39 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:46:26 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-5962cb68-7c20-4e4c-a6e1-01e5dfede245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608904163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .1608904163 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.702641613 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 459737284 ps |
| CPU time | 19.29 seconds |
| Started | Jul 22 07:44:18 PM PDT 24 |
| Finished | Jul 22 07:44:39 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-260d29ab-9458-4513-bebc-322ea08d929c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702641613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.702641613 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.3989542486 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 1868535356 ps |
| CPU time | 59.27 seconds |
| Started | Jul 22 07:44:40 PM PDT 24 |
| Finished | Jul 22 07:45:40 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-735fe740-8d17-4baf-97e8-d9669db972ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989542486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3989542486 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1527689883 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 94304722310 ps |
| CPU time | 854.83 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 08:00:02 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c8d60e02-b0d9-4aa7-8467-bbd90af54f5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527689883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1527689883 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1970400150 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 45774370604 ps |
| CPU time | 732.63 seconds |
| Started | Jul 22 07:44:45 PM PDT 24 |
| Finished | Jul 22 07:57:00 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-5e46707b-811b-4dc2-879a-bad60b6b363b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970400150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1970400150 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.4000677683 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 163043318 ps |
| CPU time | 16.08 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:46:03 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-8df3ed80-4562-4555-91e3-3fc0bdac772d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000677683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.4000677683 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.324725654 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 446349917 ps |
| CPU time | 29.66 seconds |
| Started | Jul 22 07:44:19 PM PDT 24 |
| Finished | Jul 22 07:44:50 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-cf9b11a0-321a-4058-ad6e-c351c994c65f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324725654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.324725654 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.1577862315 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 248376789 ps |
| CPU time | 10.42 seconds |
| Started | Jul 22 07:44:38 PM PDT 24 |
| Finished | Jul 22 07:44:50 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-526362b2-c96f-4676-bf5d-50baf20f0c53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577862315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1577862315 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2858286928 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 7024700743 ps |
| CPU time | 75.2 seconds |
| Started | Jul 22 07:44:10 PM PDT 24 |
| Finished | Jul 22 07:45:27 PM PDT 24 |
| Peak memory | 574828 kb |
| Host | smart-f67a4051-a921-4802-b2c2-4274a52b28b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858286928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2858286928 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.2596674597 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 4514559739 ps |
| CPU time | 77.2 seconds |
| Started | Jul 22 07:44:17 PM PDT 24 |
| Finished | Jul 22 07:45:35 PM PDT 24 |
| Peak memory | 574832 kb |
| Host | smart-ca1d3d12-ed03-4683-81f0-23d5b5cc1f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596674597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.2596674597 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3549987211 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 50287988 ps |
| CPU time | 6.63 seconds |
| Started | Jul 22 07:44:08 PM PDT 24 |
| Finished | Jul 22 07:44:17 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-086fe2f6-98b5-45b0-a2f3-823cbcc22cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549987211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .3549987211 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.569750956 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 14899815221 ps |
| CPU time | 460.64 seconds |
| Started | Jul 22 07:45:45 PM PDT 24 |
| Finished | Jul 22 07:53:27 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-49afca7c-d621-49f9-8fd6-68f5ce6ffc4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569750956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.569750956 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1424379042 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 2689669719 ps |
| CPU time | 180.63 seconds |
| Started | Jul 22 07:45:55 PM PDT 24 |
| Finished | Jul 22 07:48:58 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-53c89803-55d5-4109-b975-58ba7223ced4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424379042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1424379042 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2454104028 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 5807889801 ps |
| CPU time | 554.22 seconds |
| Started | Jul 22 07:44:17 PM PDT 24 |
| Finished | Jul 22 07:53:33 PM PDT 24 |
| Peak memory | 577076 kb |
| Host | smart-04661323-dfd8-4078-889e-4e1309101faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454104028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2454104028 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2166635925 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 4812510602 ps |
| CPU time | 298.4 seconds |
| Started | Jul 22 07:44:17 PM PDT 24 |
| Finished | Jul 22 07:49:17 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-9ddeb7a1-ca5c-4032-82b2-89d38c2e0577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166635925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.2166635925 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.908095251 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 1052560506 ps |
| CPU time | 46.51 seconds |
| Started | Jul 22 07:44:18 PM PDT 24 |
| Finished | Jul 22 07:45:07 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-ff2d7eb3-f0b6-4f81-9e5a-f83c9df9e748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908095251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.908095251 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1808639956 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 709315136 ps |
| CPU time | 32.73 seconds |
| Started | Jul 22 08:02:02 PM PDT 24 |
| Finished | Jul 22 08:02:35 PM PDT 24 |
| Peak memory | 576776 kb |
| Host | smart-13d73717-e342-4536-8c25-a5ae07d9a5af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808639956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .1808639956 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3486794258 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 159881607832 ps |
| CPU time | 2752.63 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:48:28 PM PDT 24 |
| Peak memory | 577012 kb |
| Host | smart-659ef307-00b6-4a3a-9863-9b54b4af42ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486794258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3486794258 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2364780535 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 1219644332 ps |
| CPU time | 44.25 seconds |
| Started | Jul 22 08:06:19 PM PDT 24 |
| Finished | Jul 22 08:07:06 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-a18b2722-c007-42b6-a768-990c63d02775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364780535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.2364780535 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.2491558796 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 442029409 ps |
| CPU time | 33.29 seconds |
| Started | Jul 22 08:05:17 PM PDT 24 |
| Finished | Jul 22 08:05:55 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-a5a2aec1-0603-4795-a412-724aeb83aa17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491558796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2491558796 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.1169993319 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 126303867 ps |
| CPU time | 13.07 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:02:48 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-c91e23b1-e551-412f-ad67-286a3584f77f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169993319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1169993319 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2651676020 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 41873164503 ps |
| CPU time | 436.12 seconds |
| Started | Jul 22 08:02:29 PM PDT 24 |
| Finished | Jul 22 08:10:04 PM PDT 24 |
| Peak memory | 576812 kb |
| Host | smart-571e7ddc-8e70-4f58-92e3-8c3401c5a4c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651676020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2651676020 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1258888738 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 26241443683 ps |
| CPU time | 431.78 seconds |
| Started | Jul 22 08:02:26 PM PDT 24 |
| Finished | Jul 22 08:09:50 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-68919a01-ca04-4737-b6ba-70c3565d0a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258888738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1258888738 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1585893364 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 344516608 ps |
| CPU time | 35.62 seconds |
| Started | Jul 22 08:02:23 PM PDT 24 |
| Finished | Jul 22 08:03:02 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-0c1aebbd-3d17-40cb-b8ba-863ed63355b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585893364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1585893364 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.3162297929 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 29560058 ps |
| CPU time | 5.67 seconds |
| Started | Jul 22 08:02:26 PM PDT 24 |
| Finished | Jul 22 08:02:41 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-9c310959-480e-4a37-bcac-a6be4a78a27b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162297929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3162297929 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.2354530328 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 217048426 ps |
| CPU time | 8.49 seconds |
| Started | Jul 22 08:02:28 PM PDT 24 |
| Finished | Jul 22 08:02:54 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-937920e8-4f0e-4709-be95-525d8cded6a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354530328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2354530328 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.4287879377 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 6486373099 ps |
| CPU time | 66.15 seconds |
| Started | Jul 22 08:02:28 PM PDT 24 |
| Finished | Jul 22 08:03:52 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-c75fdf77-c9f0-4a6f-bf14-47ec220f7002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287879377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.4287879377 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.635361288 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 4763562736 ps |
| CPU time | 81.08 seconds |
| Started | Jul 22 08:02:28 PM PDT 24 |
| Finished | Jul 22 08:04:06 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-5a24e047-9b35-45ab-8622-89c33f4c31f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635361288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.635361288 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2301684353 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 57180174 ps |
| CPU time | 6.98 seconds |
| Started | Jul 22 08:02:23 PM PDT 24 |
| Finished | Jul 22 08:02:34 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-2e0b72ef-b48e-4749-a674-d78bae9a1484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301684353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2301684353 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.3322523918 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 8537966888 ps |
| CPU time | 326.74 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:08:00 PM PDT 24 |
| Peak memory | 577052 kb |
| Host | smart-c6e66316-2e01-48cd-ab3f-069c49e85fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322523918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.3322523918 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2938870231 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 384405557 ps |
| CPU time | 32.51 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:03:06 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-cd512ac2-53cc-42ce-80f4-b744a5dd0023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938870231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2938870231 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.4285783888 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2800142350 ps |
| CPU time | 392.97 seconds |
| Started | Jul 22 08:06:20 PM PDT 24 |
| Finished | Jul 22 08:12:55 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-ace5c8c1-8472-4aa4-a0b0-9285995343a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285783888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.4285783888 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.697785293 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 5909102300 ps |
| CPU time | 358.61 seconds |
| Started | Jul 22 08:02:29 PM PDT 24 |
| Finished | Jul 22 08:08:47 PM PDT 24 |
| Peak memory | 576240 kb |
| Host | smart-f744667d-048f-4532-a90d-9db59589dd48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697785293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.697785293 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.571594800 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 215752094 ps |
| CPU time | 26.41 seconds |
| Started | Jul 22 08:02:24 PM PDT 24 |
| Finished | Jul 22 08:02:58 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-2e31f860-f7f7-40e3-88f8-49f4e3c6918e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571594800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.571594800 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.535202528 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 263110419 ps |
| CPU time | 12.06 seconds |
| Started | Jul 22 08:02:52 PM PDT 24 |
| Finished | Jul 22 08:03:15 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-c00e1bc2-ff27-4809-ba44-dbaaaada9c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535202528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device. 535202528 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1160824038 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 43357009360 ps |
| CPU time | 814.46 seconds |
| Started | Jul 22 08:02:51 PM PDT 24 |
| Finished | Jul 22 08:16:37 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-4d0811a4-ed46-499c-bc87-b9f52687f447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160824038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.1160824038 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3163514654 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 962319560 ps |
| CPU time | 35.64 seconds |
| Started | Jul 22 08:02:54 PM PDT 24 |
| Finished | Jul 22 08:03:40 PM PDT 24 |
| Peak memory | 576784 kb |
| Host | smart-13808c58-4eee-40fd-9f83-6835374dec33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163514654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.3163514654 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.929268172 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 1539560856 ps |
| CPU time | 56.87 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:04:02 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-750a8da0-e793-48c9-a824-dd142e374ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929268172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.929268172 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.3419960019 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 563386883 ps |
| CPU time | 49.65 seconds |
| Started | Jul 22 08:02:26 PM PDT 24 |
| Finished | Jul 22 08:03:27 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-46b35324-2065-434a-902f-261f7fd076f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419960019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.3419960019 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3747376203 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 13848049584 ps |
| CPU time | 153.11 seconds |
| Started | Jul 22 08:02:54 PM PDT 24 |
| Finished | Jul 22 08:05:38 PM PDT 24 |
| Peak memory | 576124 kb |
| Host | smart-deebef54-3d2b-46bf-80f0-5137ee454df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747376203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3747376203 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.609320254 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 2870774645 ps |
| CPU time | 45.34 seconds |
| Started | Jul 22 08:02:53 PM PDT 24 |
| Finished | Jul 22 08:03:49 PM PDT 24 |
| Peak memory | 574812 kb |
| Host | smart-02f1d9c4-d9ce-4f05-b5d7-fff4e834b23a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609320254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.609320254 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1634846407 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 33612068 ps |
| CPU time | 5.88 seconds |
| Started | Jul 22 08:04:05 PM PDT 24 |
| Finished | Jul 22 08:04:12 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-c6787cf7-f675-44ac-b786-00aaae9d710f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634846407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.1634846407 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3013904330 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 87719825 ps |
| CPU time | 8.74 seconds |
| Started | Jul 22 08:02:52 PM PDT 24 |
| Finished | Jul 22 08:03:12 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-14cb9fc2-fd6f-4ffa-84db-34733f6a0d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013904330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3013904330 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.1641011414 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 224537622 ps |
| CPU time | 8.73 seconds |
| Started | Jul 22 08:02:24 PM PDT 24 |
| Finished | Jul 22 08:02:39 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-1bd0e24f-2363-4896-8e6b-943745ff5899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641011414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1641011414 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2886216334 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 8397680334 ps |
| CPU time | 76.42 seconds |
| Started | Jul 22 08:03:33 PM PDT 24 |
| Finished | Jul 22 08:04:51 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-ef3ce933-be1d-4bdc-bbe2-177359ba6ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886216334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2886216334 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.647983532 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 5244703562 ps |
| CPU time | 82.51 seconds |
| Started | Jul 22 08:02:25 PM PDT 24 |
| Finished | Jul 22 08:03:58 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-63d8195a-2db9-43e6-a73b-286ddc5373dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647983532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.647983532 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2523956872 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 38479256 ps |
| CPU time | 5.37 seconds |
| Started | Jul 22 08:02:28 PM PDT 24 |
| Finished | Jul 22 08:02:52 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-9a3754b4-35eb-45f4-8b44-453e657e421f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523956872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2523956872 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.663295931 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 14194149330 ps |
| CPU time | 470.61 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:11:00 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-bfa79a4e-3b23-4bf8-9b59-11cab15c02c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663295931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.663295931 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.40192168 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 1254564690 ps |
| CPU time | 94.31 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:04:41 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-9666438c-9075-40c5-9c13-3a4a2899ccdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.40192168 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1911904129 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 366444272 ps |
| CPU time | 127.57 seconds |
| Started | Jul 22 08:04:45 PM PDT 24 |
| Finished | Jul 22 08:06:54 PM PDT 24 |
| Peak memory | 576868 kb |
| Host | smart-23795c80-5d97-4cd4-b44c-6cf95874c8c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911904129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.1911904129 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.427487193 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 81164345 ps |
| CPU time | 6.34 seconds |
| Started | Jul 22 08:02:57 PM PDT 24 |
| Finished | Jul 22 08:03:12 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-cfbf1e3f-daa9-4f28-8d67-58a23ee79498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427487193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.427487193 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.928771390 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1091318410 ps |
| CPU time | 83.23 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:04:33 PM PDT 24 |
| Peak memory | 576764 kb |
| Host | smart-a886f725-cce8-4369-9044-009bd776a083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928771390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device. 928771390 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3519286454 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 130594374958 ps |
| CPU time | 2484.18 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:44:31 PM PDT 24 |
| Peak memory | 576896 kb |
| Host | smart-2d6f50b1-0898-4b55-9be7-b9b120e7e058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519286454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.3519286454 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2741973480 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 18241414 ps |
| CPU time | 5.07 seconds |
| Started | Jul 22 08:05:41 PM PDT 24 |
| Finished | Jul 22 08:05:47 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-f4fd3010-4564-4b51-8d94-7613c53391a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741973480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.2741973480 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.3503498840 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 1675920483 ps |
| CPU time | 53.17 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:04:03 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-fff0d5ec-84ab-4c9d-93f9-9aa23b4831f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503498840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.3503498840 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.1277581572 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 140341899 ps |
| CPU time | 15.08 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:24 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-f771d8a3-c788-4fd7-9d91-574bd1396829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277581572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1277581572 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2742362894 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 54107568688 ps |
| CPU time | 599.57 seconds |
| Started | Jul 22 08:03:00 PM PDT 24 |
| Finished | Jul 22 08:13:07 PM PDT 24 |
| Peak memory | 576092 kb |
| Host | smart-49ea1b80-17e1-460e-bcf0-2182b55a8ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742362894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2742362894 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1755293078 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 60746827650 ps |
| CPU time | 1150.47 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:22:18 PM PDT 24 |
| Peak memory | 576996 kb |
| Host | smart-4985a691-a11f-4ae5-8b22-486f4b2b7731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755293078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1755293078 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.4001514764 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 398382432 ps |
| CPU time | 38.08 seconds |
| Started | Jul 22 08:02:56 PM PDT 24 |
| Finished | Jul 22 08:03:43 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-90a4b367-0f7a-4277-9f52-e8ccbd3792fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001514764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.4001514764 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2806360597 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 1895341894 ps |
| CPU time | 58.88 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:04:07 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-74d2d5a8-3cee-4c9f-a4ee-3985b9a74528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806360597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2806360597 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.3258800115 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 229211360 ps |
| CPU time | 9.63 seconds |
| Started | Jul 22 08:04:45 PM PDT 24 |
| Finished | Jul 22 08:04:56 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-8b78b9c7-2ee8-4dc3-870f-c413e82a4513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258800115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3258800115 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2142581186 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 6841832390 ps |
| CPU time | 70.34 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:04:16 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-bfe6806d-5039-4fc9-8512-5c9bafc4413f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142581186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2142581186 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1411052333 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 5227977424 ps |
| CPU time | 86.3 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:04:36 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-9438775c-8535-4d95-860d-0863bf0164aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411052333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1411052333 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3213346439 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 43823925 ps |
| CPU time | 6.12 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:03:11 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-4ee2eff9-5543-4d93-a641-f1de99056c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213346439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3213346439 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2185220148 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 770915450 ps |
| CPU time | 63.03 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:04:16 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-f902bd50-df2c-4760-9c3f-3bc221678f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185220148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2185220148 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1853290064 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 4835616484 ps |
| CPU time | 193.71 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:06:22 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-381a3e44-7faf-49be-a443-b2fb1e0b0880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853290064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1853290064 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.117207711 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 877571726 ps |
| CPU time | 132.61 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:05:21 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-8e09d981-be43-4c4d-9e76-563c6d432c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117207711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.117207711 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.4168934771 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 4901323657 ps |
| CPU time | 249.37 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:07:22 PM PDT 24 |
| Peak memory | 577044 kb |
| Host | smart-d84908a2-b293-4a6d-b489-89e2f3f513ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168934771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.4168934771 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.1134112029 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 766796854 ps |
| CPU time | 33.07 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:03:42 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-adec1496-7f52-49be-9624-e8bc97dac3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134112029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1134112029 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2934735658 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 611167049 ps |
| CPU time | 22.65 seconds |
| Started | Jul 22 08:03:03 PM PDT 24 |
| Finished | Jul 22 08:03:33 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-60e85362-e72a-490f-82e5-cf30726592a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934735658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2934735658 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1669527595 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 135644666581 ps |
| CPU time | 2370.24 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:42:41 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-a69c8268-9344-499e-8d2f-2b1dc64d27ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669527595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.1669527595 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2814964607 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 941442414 ps |
| CPU time | 34.82 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:44 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-651327f5-e4fd-4dcc-bf43-978c99f2fc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814964607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2814964607 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1509733639 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 1721332968 ps |
| CPU time | 55.02 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:04:07 PM PDT 24 |
| Peak memory | 576836 kb |
| Host | smart-f9b6c21e-6464-4709-88ea-b40e4c138ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509733639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1509733639 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3337345121 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 1710690872 ps |
| CPU time | 62.91 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:04:15 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-5eb56576-95ef-4767-812a-ab7bf364fb57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337345121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3337345121 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1558850135 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 31345717494 ps |
| CPU time | 334.48 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:08:46 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-6b4c9c5c-5c91-42b1-9893-97046937b329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558850135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1558850135 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1619116018 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 46519843580 ps |
| CPU time | 837.1 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:17:09 PM PDT 24 |
| Peak memory | 576160 kb |
| Host | smart-35ed6c66-f3fd-4bfd-bdfe-599b33420614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619116018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1619116018 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2759538902 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 57702162 ps |
| CPU time | 7.38 seconds |
| Started | Jul 22 08:03:03 PM PDT 24 |
| Finished | Jul 22 08:03:17 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-2bd717e7-31fc-4a16-808d-32eed83bee63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759538902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2759538902 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.110638405 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 564669755 ps |
| CPU time | 36.03 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:03:48 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-eee52396-b96b-48c6-84bc-ad65eef565f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110638405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.110638405 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3055313417 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 45176011 ps |
| CPU time | 6.14 seconds |
| Started | Jul 22 08:05:42 PM PDT 24 |
| Finished | Jul 22 08:05:49 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-dc64b55f-10b5-44a6-bf11-8de68d98a157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055313417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3055313417 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.3950856749 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 8093258744 ps |
| CPU time | 81.39 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:04:34 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-af152421-8f54-4676-95ac-cf7da0e204eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950856749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.3950856749 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3425749205 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 6073925507 ps |
| CPU time | 96.91 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:04:48 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-d2367202-7ea3-4883-bc7b-26f665303224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425749205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3425749205 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2163727063 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 59956525 ps |
| CPU time | 7 seconds |
| Started | Jul 22 08:05:42 PM PDT 24 |
| Finished | Jul 22 08:05:50 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-ae0b384c-5aee-40d5-8bc2-d22482598dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163727063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2163727063 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1352197188 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 2110480500 ps |
| CPU time | 169.28 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:06:01 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-da328955-1496-4dbc-a7be-2fffe24145f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352197188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1352197188 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2474779318 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 3395526739 ps |
| CPU time | 138.68 seconds |
| Started | Jul 22 08:03:10 PM PDT 24 |
| Finished | Jul 22 08:05:34 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-8a85504b-a020-4b6b-9616-86e2fa98288a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474779318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2474779318 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.825797233 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 14719243784 ps |
| CPU time | 1479.92 seconds |
| Started | Jul 22 08:03:10 PM PDT 24 |
| Finished | Jul 22 08:27:56 PM PDT 24 |
| Peak memory | 577004 kb |
| Host | smart-96fc4f58-193f-4b70-83e3-91a96e5e7f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825797233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_reset_error.825797233 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2481016864 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 48459665 ps |
| CPU time | 9.38 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:19 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-69ff994e-aebc-4f64-813b-64c053712e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481016864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2481016864 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.2035278863 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 531234565 ps |
| CPU time | 24.78 seconds |
| Started | Jul 22 08:02:52 PM PDT 24 |
| Finished | Jul 22 08:03:28 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-6b58609c-f18d-4710-9129-a36aaf09a589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035278863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .2035278863 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.769280966 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 75772794948 ps |
| CPU time | 1343.98 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:25:29 PM PDT 24 |
| Peak memory | 576940 kb |
| Host | smart-fe367e7b-4445-4218-a06a-8b481651d12d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769280966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d evice_slow_rsp.769280966 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.59119730 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 186327893 ps |
| CPU time | 19.62 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:03:27 PM PDT 24 |
| Peak memory | 576772 kb |
| Host | smart-e25fb775-82d9-49ed-b63c-ab540759f32d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59119730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr.59119730 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.3419712688 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 732345299 ps |
| CPU time | 25.89 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:35 PM PDT 24 |
| Peak memory | 576736 kb |
| Host | smart-7b44754c-6f7a-4ac1-826f-e61e494a5915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419712688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3419712688 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.348775104 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 195116459 ps |
| CPU time | 17.44 seconds |
| Started | Jul 22 08:04:04 PM PDT 24 |
| Finished | Jul 22 08:04:23 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-6ced4640-7642-42cd-a4e3-25e460222e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348775104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.348775104 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.711357778 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 84501608559 ps |
| CPU time | 838.18 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:17:03 PM PDT 24 |
| Peak memory | 576952 kb |
| Host | smart-764ccf74-8fd7-4579-9d7b-f727037573a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711357778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.711357778 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3148205287 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 33063518075 ps |
| CPU time | 536.75 seconds |
| Started | Jul 22 08:05:17 PM PDT 24 |
| Finished | Jul 22 08:14:19 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-9dbb067e-d065-4adf-a677-d160e029cc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148205287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3148205287 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1270782560 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 159204002 ps |
| CPU time | 15.1 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:03:20 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-bebd068d-a392-41c0-a61c-8f475c69bdf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270782560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1270782560 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.2098444673 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 116785689 ps |
| CPU time | 11 seconds |
| Started | Jul 22 08:02:53 PM PDT 24 |
| Finished | Jul 22 08:03:15 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-a4c65b0b-b9a4-4919-9370-1dce3d17e88d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098444673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.2098444673 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3814113443 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 191197180 ps |
| CPU time | 8.73 seconds |
| Started | Jul 22 08:02:52 PM PDT 24 |
| Finished | Jul 22 08:03:12 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-cd68e400-46e0-4a07-b2a0-19f1e3065920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814113443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3814113443 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3445927943 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 5185886352 ps |
| CPU time | 54.05 seconds |
| Started | Jul 22 08:02:56 PM PDT 24 |
| Finished | Jul 22 08:03:59 PM PDT 24 |
| Peak memory | 574852 kb |
| Host | smart-c0e1b537-e3c7-460f-a0ac-93117cbdcf82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445927943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3445927943 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2011031167 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 5109362103 ps |
| CPU time | 84.61 seconds |
| Started | Jul 22 08:02:57 PM PDT 24 |
| Finished | Jul 22 08:04:30 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-4337f081-70b6-492a-b369-ecafbbd44e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011031167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2011031167 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1040725828 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 51360323 ps |
| CPU time | 7.1 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:16 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-5d20619a-8385-4a30-91ec-cfc1d9210a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040725828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1040725828 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.2096085847 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 13410052636 ps |
| CPU time | 510.97 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:11:38 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-cd82a5b1-947a-4cba-a881-a3fb355cd607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096085847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.2096085847 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.1749065369 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 407050972 ps |
| CPU time | 30.19 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:03:39 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-3944b9a0-3dc9-4dba-a5af-a8d60102aec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749065369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1749065369 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3884581944 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 3689334560 ps |
| CPU time | 485.71 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:11:13 PM PDT 24 |
| Peak memory | 577040 kb |
| Host | smart-0195b521-2ec4-4c8e-a509-fc9f0a07aefe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884581944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3884581944 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1089135927 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 103427587 ps |
| CPU time | 19.67 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:03:28 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-087c7725-54f7-4182-809b-ed22263c9b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089135927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.1089135927 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.3230314085 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 304399590 ps |
| CPU time | 16.55 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:03:23 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-99183f2d-427a-4ea6-8d1b-f7c45c406141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230314085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.3230314085 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2762747001 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 2283990403 ps |
| CPU time | 80.44 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:04:27 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-c75603ff-44f0-4a33-8582-613fe89946da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762747001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2762747001 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.606808319 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 14300392223 ps |
| CPU time | 222.92 seconds |
| Started | Jul 22 08:05:40 PM PDT 24 |
| Finished | Jul 22 08:09:27 PM PDT 24 |
| Peak memory | 576860 kb |
| Host | smart-a45a0dd8-8225-4f65-a24b-46f91d73c5ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606808319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d evice_slow_rsp.606808319 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.461725734 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 159852064 ps |
| CPU time | 8.51 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:18 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-6fd3dc47-0418-4a9b-ab95-d5326095b95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461725734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr .461725734 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.546820160 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 405340620 ps |
| CPU time | 17.22 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:26 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-7db942d0-cf9e-4218-bb80-f3aa0959477e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546820160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.546820160 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1018111221 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 2240068249 ps |
| CPU time | 88.51 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:04:35 PM PDT 24 |
| Peak memory | 576884 kb |
| Host | smart-ced7f6b0-5e72-47f7-aa9e-cf333e99dcac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018111221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1018111221 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2430096522 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 39490739906 ps |
| CPU time | 447.11 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:10:36 PM PDT 24 |
| Peak memory | 576808 kb |
| Host | smart-276dffd3-1f1b-4d6a-bd03-2c8ff1371d75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430096522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2430096522 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3693910052 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 37080841805 ps |
| CPU time | 683.29 seconds |
| Started | Jul 22 08:02:57 PM PDT 24 |
| Finished | Jul 22 08:14:29 PM PDT 24 |
| Peak memory | 576924 kb |
| Host | smart-fb27f41f-e058-45cd-8db1-25f891896ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693910052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3693910052 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.772827533 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 320486097 ps |
| CPU time | 27.42 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:37 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-d772d337-9e3a-4b59-a3c6-e8b9e10436c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772827533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.772827533 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1238268877 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 517697267 ps |
| CPU time | 17.82 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:03:27 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-8c41e551-8cba-4251-b539-fccb70cce26e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238268877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1238268877 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.3830796026 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 45508788 ps |
| CPU time | 6.14 seconds |
| Started | Jul 22 08:04:45 PM PDT 24 |
| Finished | Jul 22 08:04:53 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-1c26e227-052e-4570-acf2-58ae290e455e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830796026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3830796026 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.814078594 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 9807169646 ps |
| CPU time | 98.75 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:04:46 PM PDT 24 |
| Peak memory | 574808 kb |
| Host | smart-11edc6b0-d80a-4b07-8ae5-3e0ba6fcfd12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814078594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.814078594 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1928850291 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 5742538811 ps |
| CPU time | 99.39 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:04:46 PM PDT 24 |
| Peak memory | 574788 kb |
| Host | smart-34428ac6-74a2-43b7-801d-474b40dd8125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928850291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1928850291 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3736783255 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 56132696 ps |
| CPU time | 6.89 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:03:14 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-72bc1e04-b77d-4119-a364-fe6bc5ec6e23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736783255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3736783255 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.959452410 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4678148700 ps |
| CPU time | 151.38 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:05:42 PM PDT 24 |
| Peak memory | 577044 kb |
| Host | smart-0f72a09a-a959-4e2f-8281-11abee8feab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959452410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.959452410 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4290110656 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 3683558202 ps |
| CPU time | 261.01 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:07:34 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-cae1d478-f73b-4735-9fba-9c6e8ab4e6ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290110656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.4290110656 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.970470733 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 865070427 ps |
| CPU time | 77.62 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:04:27 PM PDT 24 |
| Peak memory | 576900 kb |
| Host | smart-434fed36-5109-4cf0-b277-4129600bc45b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970470733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_ with_rand_reset.970470733 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1988973828 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 186277749 ps |
| CPU time | 8.03 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:03:20 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-9e2e826a-4434-49fb-afbf-225bb57cc38d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988973828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1988973828 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2543181336 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 242367240 ps |
| CPU time | 27.79 seconds |
| Started | Jul 22 08:05:42 PM PDT 24 |
| Finished | Jul 22 08:06:10 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-45b16f8f-3fdb-4711-a022-1617ba88879f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543181336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2543181336 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.73527740 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 765447243 ps |
| CPU time | 60.65 seconds |
| Started | Jul 22 08:03:09 PM PDT 24 |
| Finished | Jul 22 08:04:15 PM PDT 24 |
| Peak memory | 576980 kb |
| Host | smart-a36946a2-a48f-4296-8857-8b68259a4fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73527740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.73527740 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1318859779 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 41232845845 ps |
| CPU time | 758.06 seconds |
| Started | Jul 22 08:03:09 PM PDT 24 |
| Finished | Jul 22 08:15:52 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-6d152d13-4749-4b57-a1ae-9bcc2f144360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318859779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1318859779 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3964011813 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 894140905 ps |
| CPU time | 37.98 seconds |
| Started | Jul 22 08:03:39 PM PDT 24 |
| Finished | Jul 22 08:04:18 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-cb763eb7-3a49-4eb7-af8a-7f714d3d7bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964011813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3964011813 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3420779120 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 2028429030 ps |
| CPU time | 73.55 seconds |
| Started | Jul 22 08:03:09 PM PDT 24 |
| Finished | Jul 22 08:04:28 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-fb703c70-1c1e-4918-92bf-0224f7602e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420779120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3420779120 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.744806849 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 1133952766 ps |
| CPU time | 37.96 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:03:49 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-4899b03b-7e2d-4f12-9dac-b22d24230720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744806849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.744806849 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2281849397 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 48920528855 ps |
| CPU time | 524.91 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:11:57 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-4f6587e7-f43f-40e8-b9eb-bc84aeb9a167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281849397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2281849397 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2838119327 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 50155047857 ps |
| CPU time | 938.44 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:18:50 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-7b358dbe-61e2-40b7-bd6a-c803b892a1e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838119327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2838119327 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3859380150 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 294424948 ps |
| CPU time | 26.08 seconds |
| Started | Jul 22 08:03:09 PM PDT 24 |
| Finished | Jul 22 08:03:40 PM PDT 24 |
| Peak memory | 576960 kb |
| Host | smart-45eafdb9-5f52-4502-96a9-ed54c825f324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859380150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3859380150 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.1877203004 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 457558512 ps |
| CPU time | 29.97 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:39 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-1d6f02b2-7667-435d-b592-fc3c82f5877f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877203004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.1877203004 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.3525639845 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 47814846 ps |
| CPU time | 6.01 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:03:18 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-34a20f50-32b8-4c2c-8bde-58a7f48bd6f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525639845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.3525639845 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2755209089 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 10881967935 ps |
| CPU time | 122.13 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:05:11 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-bd920a8d-c8c1-4bcf-ad89-f996951150cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755209089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2755209089 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4229543467 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 3870842959 ps |
| CPU time | 60.6 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:04:13 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-f12d7902-3caf-4ac7-b528-75701dc1c852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229543467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4229543467 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3917887647 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 41201471 ps |
| CPU time | 5.96 seconds |
| Started | Jul 22 08:03:05 PM PDT 24 |
| Finished | Jul 22 08:03:18 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-b682a037-0775-4f22-95b4-8e8b9d479d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917887647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3917887647 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.2282282213 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 1626878450 ps |
| CPU time | 121.37 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:05:06 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-64829f15-d653-44ff-ad13-d835d7c42cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282282213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.2282282213 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3543246026 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 362650032 ps |
| CPU time | 157.48 seconds |
| Started | Jul 22 08:02:55 PM PDT 24 |
| Finished | Jul 22 08:05:43 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-e1501155-dafc-46ff-a3b3-421b1d2ab078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543246026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3543246026 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3876194812 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 1977254154 ps |
| CPU time | 217.2 seconds |
| Started | Jul 22 08:02:53 PM PDT 24 |
| Finished | Jul 22 08:06:41 PM PDT 24 |
| Peak memory | 576944 kb |
| Host | smart-4301329d-8cbe-4efd-9546-17b9dd24fcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876194812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3876194812 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3320510777 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 218156527 ps |
| CPU time | 25.48 seconds |
| Started | Jul 22 08:03:09 PM PDT 24 |
| Finished | Jul 22 08:03:40 PM PDT 24 |
| Peak memory | 577020 kb |
| Host | smart-db75b999-633c-4e5d-9432-56ddae5755de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320510777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3320510777 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2234883878 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1118397160 ps |
| CPU time | 89.12 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:04:36 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-bbd286ef-e04a-4e03-afa5-a4c6054d6c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234883878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2234883878 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2140236558 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 47563446828 ps |
| CPU time | 874.78 seconds |
| Started | Jul 22 08:02:57 PM PDT 24 |
| Finished | Jul 22 08:17:40 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-95643f41-322b-413b-8c4c-3f864cc36b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140236558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2140236558 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3326393079 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 410809876 ps |
| CPU time | 18.14 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:03:24 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-c966883f-0768-43db-830f-94c9b76b993f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326393079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3326393079 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2648955280 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 238779886 ps |
| CPU time | 20.68 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:03:27 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-49d1732f-0edb-4693-bc67-6625852519b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648955280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2648955280 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.1403753467 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 220275863 ps |
| CPU time | 21.1 seconds |
| Started | Jul 22 08:02:56 PM PDT 24 |
| Finished | Jul 22 08:03:26 PM PDT 24 |
| Peak memory | 576804 kb |
| Host | smart-45d4baea-e3db-4a9c-a49b-7172e11cd6a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403753467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.1403753467 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.2533067367 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 52323977007 ps |
| CPU time | 538.61 seconds |
| Started | Jul 22 08:03:00 PM PDT 24 |
| Finished | Jul 22 08:12:06 PM PDT 24 |
| Peak memory | 576032 kb |
| Host | smart-61372e4b-fe25-4bb9-b773-7aeddea677f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533067367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.2533067367 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1758624875 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 7510847969 ps |
| CPU time | 132.87 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:05:21 PM PDT 24 |
| Peak memory | 576112 kb |
| Host | smart-9c5a1899-7465-44bd-8d92-e50f7a96b8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758624875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1758624875 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3572642741 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 406620605 ps |
| CPU time | 39.87 seconds |
| Started | Jul 22 08:02:54 PM PDT 24 |
| Finished | Jul 22 08:03:45 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-5081273e-4d85-4474-b66d-9b9118fbed25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572642741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3572642741 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2278429253 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 253224647 ps |
| CPU time | 9.88 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:03:16 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-117c8e2a-03e9-4aa3-bd59-665dd4a65475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278429253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2278429253 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.1084079662 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 198348833 ps |
| CPU time | 9.22 seconds |
| Started | Jul 22 08:02:52 PM PDT 24 |
| Finished | Jul 22 08:03:13 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-cd2e421e-1ec2-48d2-95fe-6b717afae142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084079662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1084079662 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1450576980 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 8722105307 ps |
| CPU time | 88.9 seconds |
| Started | Jul 22 08:02:59 PM PDT 24 |
| Finished | Jul 22 08:04:36 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-c50010f2-a072-4998-bda0-8a2164429bd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450576980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1450576980 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1238431712 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 5012161094 ps |
| CPU time | 83.81 seconds |
| Started | Jul 22 08:02:54 PM PDT 24 |
| Finished | Jul 22 08:04:28 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-15077e18-4193-4891-9cb7-a076245d6120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238431712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1238431712 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.1407339537 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 49803783 ps |
| CPU time | 6.69 seconds |
| Started | Jul 22 08:03:42 PM PDT 24 |
| Finished | Jul 22 08:03:50 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-7ff8b434-6a24-43ff-84ba-3c81608c3438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407339537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.1407339537 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3982605264 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 12551793411 ps |
| CPU time | 579.69 seconds |
| Started | Jul 22 08:03:00 PM PDT 24 |
| Finished | Jul 22 08:12:47 PM PDT 24 |
| Peak memory | 577060 kb |
| Host | smart-5bcc333a-92f5-4b37-a099-ccfd2c170878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982605264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3982605264 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3764625334 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 1254177903 ps |
| CPU time | 83.05 seconds |
| Started | Jul 22 08:03:03 PM PDT 24 |
| Finished | Jul 22 08:04:33 PM PDT 24 |
| Peak memory | 576900 kb |
| Host | smart-bb2367a2-3939-4f35-ab13-3ba674c12d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764625334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3764625334 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1666749515 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 931319438 ps |
| CPU time | 371.97 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:09:19 PM PDT 24 |
| Peak memory | 576132 kb |
| Host | smart-92529e47-64f4-4d24-871a-c8b2db3b3694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666749515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1666749515 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3498297148 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 5302944476 ps |
| CPU time | 726.17 seconds |
| Started | Jul 22 08:02:38 PM PDT 24 |
| Finished | Jul 22 08:15:03 PM PDT 24 |
| Peak memory | 579172 kb |
| Host | smart-bef992b5-1adc-49a8-ad3c-5f92a7ee3c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498297148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3498297148 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.320127817 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 94927839 ps |
| CPU time | 13.42 seconds |
| Started | Jul 22 08:03:01 PM PDT 24 |
| Finished | Jul 22 08:03:22 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-aa08e1f9-f78d-486a-a1a4-0c02d0bb4815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320127817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.320127817 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.2490214093 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 199248561 ps |
| CPU time | 13.6 seconds |
| Started | Jul 22 08:03:10 PM PDT 24 |
| Finished | Jul 22 08:03:29 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-d513495f-5cd9-4124-89ef-3b41a455b90e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490214093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2490214093 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2292526754 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 140988458837 ps |
| CPU time | 2707.55 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:48:21 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-2f6e66b7-b1cd-40d6-870d-4dc4a06109c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292526754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2292526754 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.970636829 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 933098401 ps |
| CPU time | 39.6 seconds |
| Started | Jul 22 08:03:10 PM PDT 24 |
| Finished | Jul 22 08:03:55 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-2aa3461c-78eb-48bc-ad7c-f734f978d99b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970636829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .970636829 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.1285770046 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 129708375 ps |
| CPU time | 13.93 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:03:27 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-916cc1e7-fc1f-4eaa-8a19-704fd708a9c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285770046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1285770046 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1829461874 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1722826706 ps |
| CPU time | 65.1 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:04:16 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-cfd25a01-a52c-42ac-adfb-35cb9573ca5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829461874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1829461874 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.273027457 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 91560985320 ps |
| CPU time | 943.5 seconds |
| Started | Jul 22 08:03:07 PM PDT 24 |
| Finished | Jul 22 08:18:57 PM PDT 24 |
| Peak memory | 576856 kb |
| Host | smart-5739b09f-9d07-4734-a596-2d4b3577ba42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273027457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.273027457 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.3457119629 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 40431239146 ps |
| CPU time | 725.78 seconds |
| Started | Jul 22 08:03:11 PM PDT 24 |
| Finished | Jul 22 08:15:22 PM PDT 24 |
| Peak memory | 576052 kb |
| Host | smart-0695b760-2ea1-46b3-9747-d5b04249dc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457119629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3457119629 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1539052073 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 308580710 ps |
| CPU time | 28.23 seconds |
| Started | Jul 22 08:02:58 PM PDT 24 |
| Finished | Jul 22 08:03:35 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-73ba3fb9-b02a-4a33-a38a-2c3f6ad4767f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539052073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1539052073 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.262874494 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1834342859 ps |
| CPU time | 55.16 seconds |
| Started | Jul 22 08:02:57 PM PDT 24 |
| Finished | Jul 22 08:04:01 PM PDT 24 |
| Peak memory | 576768 kb |
| Host | smart-338e1c60-732b-4402-8c8a-baaf311cbe48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262874494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.262874494 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.2767285876 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 121530378 ps |
| CPU time | 7.02 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:03:16 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-9dec5885-698b-4c36-873c-fb107dc1aadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767285876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2767285876 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3548114318 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 7691927823 ps |
| CPU time | 78.33 seconds |
| Started | Jul 22 08:03:02 PM PDT 24 |
| Finished | Jul 22 08:04:28 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-25079b70-352c-44af-a487-760229d61ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548114318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3548114318 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.4112400580 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 5486812300 ps |
| CPU time | 81.68 seconds |
| Started | Jul 22 08:03:03 PM PDT 24 |
| Finished | Jul 22 08:04:32 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-58b70b16-97fa-4a20-a703-a0b365601d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112400580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.4112400580 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.3039679628 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 43182210 ps |
| CPU time | 5.9 seconds |
| Started | Jul 22 08:03:04 PM PDT 24 |
| Finished | Jul 22 08:03:17 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-929eb32c-ed23-440f-ba73-58a4452d9eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039679628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.3039679628 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2559234534 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 4149081314 ps |
| CPU time | 304.02 seconds |
| Started | Jul 22 08:03:11 PM PDT 24 |
| Finished | Jul 22 08:08:21 PM PDT 24 |
| Peak memory | 576208 kb |
| Host | smart-d2cb3194-9619-45c9-93cc-0172b6bae4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559234534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2559234534 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.1513073386 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 1171519117 ps |
| CPU time | 94.73 seconds |
| Started | Jul 22 08:03:03 PM PDT 24 |
| Finished | Jul 22 08:04:45 PM PDT 24 |
| Peak memory | 576880 kb |
| Host | smart-afc94c05-1575-4b3e-95b4-5a8cdba83065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513073386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.1513073386 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2432475110 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3606061161 ps |
| CPU time | 307.54 seconds |
| Started | Jul 22 08:03:07 PM PDT 24 |
| Finished | Jul 22 08:08:21 PM PDT 24 |
| Peak memory | 576972 kb |
| Host | smart-04c4b50e-9a80-4451-93ef-d10fe8a2b425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432475110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2432475110 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2959964850 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 10678104546 ps |
| CPU time | 533.14 seconds |
| Started | Jul 22 08:03:14 PM PDT 24 |
| Finished | Jul 22 08:12:10 PM PDT 24 |
| Peak memory | 577044 kb |
| Host | smart-79a56e7e-8302-472c-ba5b-c47f8e6e5155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959964850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2959964850 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1186673658 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 964129993 ps |
| CPU time | 34.87 seconds |
| Started | Jul 22 08:04:46 PM PDT 24 |
| Finished | Jul 22 08:05:22 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-ee055355-c86b-424f-bc1b-75bf61c766dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186673658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1186673658 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1612686071 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 940102264 ps |
| CPU time | 56.31 seconds |
| Started | Jul 22 08:04:45 PM PDT 24 |
| Finished | Jul 22 08:05:44 PM PDT 24 |
| Peak memory | 576788 kb |
| Host | smart-71826b92-7f49-424f-891e-8e5dbe635358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612686071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1612686071 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.713238003 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 106224967670 ps |
| CPU time | 1917.42 seconds |
| Started | Jul 22 08:03:13 PM PDT 24 |
| Finished | Jul 22 08:35:14 PM PDT 24 |
| Peak memory | 576916 kb |
| Host | smart-f5d3a9e9-c630-4daf-a0e1-7d430eb9c5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713238003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.713238003 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.4182637389 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 139563352 ps |
| CPU time | 14.03 seconds |
| Started | Jul 22 08:03:07 PM PDT 24 |
| Finished | Jul 22 08:03:27 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-38b3da4e-273e-4a6f-97ea-f2b0e672f16c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182637389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.4182637389 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.3941213409 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 396358406 ps |
| CPU time | 14.54 seconds |
| Started | Jul 22 08:04:46 PM PDT 24 |
| Finished | Jul 22 08:05:02 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-c7bd03cf-947f-4743-a450-0dc1cca6ae3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941213409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3941213409 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.1401265159 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 267293367 ps |
| CPU time | 23.13 seconds |
| Started | Jul 22 08:03:14 PM PDT 24 |
| Finished | Jul 22 08:03:40 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-ba89b354-599c-43d3-acef-95b30373775a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401265159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1401265159 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2041133964 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 7782868010 ps |
| CPU time | 84.87 seconds |
| Started | Jul 22 08:03:11 PM PDT 24 |
| Finished | Jul 22 08:04:40 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-a58c98eb-bc62-485c-9b0c-8fdd94a077c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041133964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2041133964 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2234054018 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 31895650733 ps |
| CPU time | 537.76 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:12:10 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-ece14f3f-d9f0-4548-b9b0-275bb3cce41d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234054018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2234054018 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.39965973 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 249567277 ps |
| CPU time | 21.24 seconds |
| Started | Jul 22 08:03:13 PM PDT 24 |
| Finished | Jul 22 08:03:38 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-14845531-d88f-4ab1-9c1a-32ca0bbb2268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39965973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_delay s.39965973 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.2661655120 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 1196225357 ps |
| CPU time | 36.29 seconds |
| Started | Jul 22 08:03:13 PM PDT 24 |
| Finished | Jul 22 08:03:53 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-3f677c63-4110-48dd-a2b7-6a60ba227a76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661655120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2661655120 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3082173576 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 41319307 ps |
| CPU time | 5.41 seconds |
| Started | Jul 22 08:04:46 PM PDT 24 |
| Finished | Jul 22 08:04:53 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-e4f3b7b8-8ffa-44b8-a91b-5cfe3ee25ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082173576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3082173576 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.3808464709 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 9712453647 ps |
| CPU time | 102.69 seconds |
| Started | Jul 22 08:03:10 PM PDT 24 |
| Finished | Jul 22 08:04:58 PM PDT 24 |
| Peak memory | 574896 kb |
| Host | smart-14828a18-13f7-4ddd-a928-bdb0d97ba18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808464709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.3808464709 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.4085469583 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 4879293959 ps |
| CPU time | 74.38 seconds |
| Started | Jul 22 08:04:46 PM PDT 24 |
| Finished | Jul 22 08:06:02 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-3ceac8df-9aa2-468a-80aa-9f7171b3efbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085469583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.4085469583 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2003216244 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 38495583 ps |
| CPU time | 5.65 seconds |
| Started | Jul 22 08:03:13 PM PDT 24 |
| Finished | Jul 22 08:03:22 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-c715d6a6-f606-4d99-9faf-c1ff3fdba860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003216244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2003216244 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.3399070904 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 4797636946 ps |
| CPU time | 171.37 seconds |
| Started | Jul 22 08:03:14 PM PDT 24 |
| Finished | Jul 22 08:06:08 PM PDT 24 |
| Peak memory | 577048 kb |
| Host | smart-457ce6e6-c0ed-4802-ba30-f6cfaabffcf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399070904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3399070904 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.839734646 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 15500034171 ps |
| CPU time | 603.44 seconds |
| Started | Jul 22 08:03:06 PM PDT 24 |
| Finished | Jul 22 08:13:16 PM PDT 24 |
| Peak memory | 577116 kb |
| Host | smart-74ef384e-7f92-4152-8cdf-7e4c81a215ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839734646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.839734646 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1164376020 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 3264776911 ps |
| CPU time | 308.68 seconds |
| Started | Jul 22 08:03:10 PM PDT 24 |
| Finished | Jul 22 08:08:24 PM PDT 24 |
| Peak memory | 577104 kb |
| Host | smart-3c3b88b8-5b0e-44a8-83ae-98d6b6acaa83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164376020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1164376020 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2973740113 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 55421447 ps |
| CPU time | 27.63 seconds |
| Started | Jul 22 08:03:11 PM PDT 24 |
| Finished | Jul 22 08:03:43 PM PDT 24 |
| Peak memory | 576908 kb |
| Host | smart-b506fcb3-1489-4214-93de-259ea676d491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973740113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.2973740113 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.941644208 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 599109009 ps |
| CPU time | 24 seconds |
| Started | Jul 22 08:03:12 PM PDT 24 |
| Finished | Jul 22 08:03:40 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-729d0a85-a84d-498e-a9dd-885226781f3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941644208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.941644208 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2089761611 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 12666520646 ps |
| CPU time | 1527.56 seconds |
| Started | Jul 22 08:05:18 PM PDT 24 |
| Finished | Jul 22 08:30:50 PM PDT 24 |
| Peak memory | 604276 kb |
| Host | smart-ff64f8e9-0b89-4a54-9b5f-8d3bff4bcc7b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089761611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2089761611 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3311250739 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 13422017800 ps |
| CPU time | 1685.69 seconds |
| Started | Jul 22 08:05:14 PM PDT 24 |
| Finished | Jul 22 08:33:25 PM PDT 24 |
| Peak memory | 608156 kb |
| Host | smart-677f8d5f-a321-49c6-b574-f3bbd4fdef3a |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311250739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 311250739 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.725547541 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 5305818846 ps |
| CPU time | 476.56 seconds |
| Started | Jul 22 08:13:59 PM PDT 24 |
| Finished | Jul 22 08:21:57 PM PDT 24 |
| Peak memory | 621512 kb |
| Host | smart-d696f9b1-9a26-4853-ab33-b65734d9674a |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7 25547541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.725547541 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3681126806 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3464366230 ps |
| CPU time | 270.93 seconds |
| Started | Jul 22 08:20:05 PM PDT 24 |
| Finished | Jul 22 08:24:38 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-76742803-8509-4d2e-a6e7-148cf13970ac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3681126806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3681126806 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.601446531 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 3194116208 ps |
| CPU time | 352.51 seconds |
| Started | Jul 22 08:13:31 PM PDT 24 |
| Finished | Jul 22 08:19:24 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-777ff1f5-1aec-4990-84e5-022051ed9494 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6014 46531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.601446531 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1014974534 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 2884515314 ps |
| CPU time | 301.53 seconds |
| Started | Jul 22 08:14:44 PM PDT 24 |
| Finished | Jul 22 08:19:47 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-b1c31c86-e805-4581-a858-a234a672539d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014974534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1014974534 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.1737954526 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 2764085490 ps |
| CPU time | 292.62 seconds |
| Started | Jul 22 08:12:30 PM PDT 24 |
| Finished | Jul 22 08:17:23 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-2b22b2a2-a70e-4b51-adb8-6aff4ad258aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737954526 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1737954526 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.2125754030 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 1905171892 ps |
| CPU time | 188.46 seconds |
| Started | Jul 22 08:11:56 PM PDT 24 |
| Finished | Jul 22 08:15:05 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-0acb084b-c06f-4580-b4a3-d36196a52253 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125754030 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2125754030 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.1284473114 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3265164311 ps |
| CPU time | 307.36 seconds |
| Started | Jul 22 08:19:12 PM PDT 24 |
| Finished | Jul 22 08:24:21 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-16563c5d-fce0-4cc9-9798-525887650dad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284473114 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.1284473114 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2492426518 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2338982014 ps |
| CPU time | 238.18 seconds |
| Started | Jul 22 08:15:40 PM PDT 24 |
| Finished | Jul 22 08:19:39 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-a5814a42-eb8f-42a2-a4c9-8a37579295e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492426518 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2492426518 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1827902917 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3543923460 ps |
| CPU time | 243.41 seconds |
| Started | Jul 22 08:12:31 PM PDT 24 |
| Finished | Jul 22 08:16:36 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-044a3776-3742-4236-884c-16fae375b217 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1827902917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1827902917 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3219187552 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 6130658878 ps |
| CPU time | 656.62 seconds |
| Started | Jul 22 08:23:53 PM PDT 24 |
| Finished | Jul 22 08:34:52 PM PDT 24 |
| Peak memory | 619932 kb |
| Host | smart-a71a53a7-4593-43c9-990b-f9ee4a32b6b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3219187552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3219187552 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1014447080 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 8606491208 ps |
| CPU time | 1993.9 seconds |
| Started | Jul 22 08:13:26 PM PDT 24 |
| Finished | Jul 22 08:46:40 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-ea4e44bf-2533-468f-8cad-1ef0944e8e1c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1014447080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1014447080 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4248947395 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 8718493652 ps |
| CPU time | 2080.75 seconds |
| Started | Jul 22 08:13:54 PM PDT 24 |
| Finished | Jul 22 08:48:36 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-7a062acf-9c3e-4f49-80a6-0b4aaa1b4740 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248947395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.4248947395 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3951131040 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8571342360 ps |
| CPU time | 1674.74 seconds |
| Started | Jul 22 08:13:25 PM PDT 24 |
| Finished | Jul 22 08:41:22 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-27d73fa8-b2c0-4e26-8e47-e6c97a34c213 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3951131040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3951131040 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2237362345 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 5433925428 ps |
| CPU time | 581.51 seconds |
| Started | Jul 22 08:14:17 PM PDT 24 |
| Finished | Jul 22 08:24:01 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-ed86665b-2650-4de4-a418-6519c091477e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2237362345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2237362345 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4062400879 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 255071220630 ps |
| CPU time | 12652.2 seconds |
| Started | Jul 22 08:13:46 PM PDT 24 |
| Finished | Jul 22 11:44:42 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-ccd0ddb5-9c0b-42a1-99f1-82f0c3accea7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062400879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4062400879 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.3176166196 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2786287520 ps |
| CPU time | 305.42 seconds |
| Started | Jul 22 08:13:16 PM PDT 24 |
| Finished | Jul 22 08:18:23 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-39869682-8fee-4be9-b858-e90eecb1e064 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176166196 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3176166196 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.1177162829 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 3358661718 ps |
| CPU time | 406.82 seconds |
| Started | Jul 22 08:12:51 PM PDT 24 |
| Finished | Jul 22 08:19:47 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-c9148edd-cfbd-443f-ae2c-b41758b8a8cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177162829 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.1177162829 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1076790653 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 7926917120 ps |
| CPU time | 354.41 seconds |
| Started | Jul 22 08:23:55 PM PDT 24 |
| Finished | Jul 22 08:29:52 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-5cb54aae-c7e1-4ec1-8dbb-6825ee89718b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1076790653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1076790653 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3413850847 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3089481720 ps |
| CPU time | 278.09 seconds |
| Started | Jul 22 08:14:30 PM PDT 24 |
| Finished | Jul 22 08:19:09 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-8561e6f1-de1a-4786-bc13-88904c9b0c55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413850847 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.3413850847 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2144033968 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 7444496730 ps |
| CPU time | 648.17 seconds |
| Started | Jul 22 08:12:28 PM PDT 24 |
| Finished | Jul 22 08:23:17 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-779a7f27-17d9-4030-aac6-52cc37ce0d32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2144033968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2144033968 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3715613053 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5088235696 ps |
| CPU time | 757.03 seconds |
| Started | Jul 22 08:11:04 PM PDT 24 |
| Finished | Jul 22 08:23:44 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-2eb1a134-862e-4e3e-b739-ed9b33301d4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3715613053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3715613053 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2962727879 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 21049762818 ps |
| CPU time | 2865.18 seconds |
| Started | Jul 22 08:16:10 PM PDT 24 |
| Finished | Jul 22 09:03:56 PM PDT 24 |
| Peak memory | 611584 kb |
| Host | smart-8c971e2c-e49d-49d6-937a-b61bc7d2f38a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962727879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2962727879 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2951791752 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9003446204 ps |
| CPU time | 1040.67 seconds |
| Started | Jul 22 08:15:30 PM PDT 24 |
| Finished | Jul 22 08:32:52 PM PDT 24 |
| Peak memory | 623608 kb |
| Host | smart-0d6bdb2e-1903-4cf8-8b27-3c17f19b7ab9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2951791752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2951791752 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2422058794 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4875217146 ps |
| CPU time | 655.79 seconds |
| Started | Jul 22 08:15:38 PM PDT 24 |
| Finished | Jul 22 08:26:35 PM PDT 24 |
| Peak memory | 613472 kb |
| Host | smart-a2f26b47-1d22-4988-87bd-c851ec438dc3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422058794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2422058794 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.775149031 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4482927080 ps |
| CPU time | 651.72 seconds |
| Started | Jul 22 08:13:52 PM PDT 24 |
| Finished | Jul 22 08:24:45 PM PDT 24 |
| Peak memory | 613460 kb |
| Host | smart-9b5e3ed6-da3f-4369-af0d-f3cca4cfb3f2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775149031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.775149031 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1775152815 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4112053992 ps |
| CPU time | 658.3 seconds |
| Started | Jul 22 08:14:49 PM PDT 24 |
| Finished | Jul 22 08:25:49 PM PDT 24 |
| Peak memory | 613292 kb |
| Host | smart-e3d97bbf-95c7-42d1-bbff-d1cbd7d2a4fa |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775152815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1775152815 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2034355555 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4855978232 ps |
| CPU time | 579.99 seconds |
| Started | Jul 22 08:12:12 PM PDT 24 |
| Finished | Jul 22 08:21:53 PM PDT 24 |
| Peak memory | 613392 kb |
| Host | smart-7b819677-e36a-4b89-a0c4-40e547bdbb2b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034355555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2034355555 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3774010328 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 5518378390 ps |
| CPU time | 660.56 seconds |
| Started | Jul 22 08:17:36 PM PDT 24 |
| Finished | Jul 22 08:28:38 PM PDT 24 |
| Peak memory | 613392 kb |
| Host | smart-3d8cf284-ea6c-4f0e-a3f2-ba1c6f6f6cde |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774010328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3774010328 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.4135366757 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3459964020 ps |
| CPU time | 233.92 seconds |
| Started | Jul 22 08:19:11 PM PDT 24 |
| Finished | Jul 22 08:23:06 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-52e60472-1938-4469-9e68-21ad169390e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135366757 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.4135366757 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.729020110 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 3675447160 ps |
| CPU time | 402.6 seconds |
| Started | Jul 22 08:15:02 PM PDT 24 |
| Finished | Jul 22 08:21:45 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-d2f47f80-72eb-4e17-8f3c-4618df2b80d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729020110 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.729020110 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4084460730 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2630904159 ps |
| CPU time | 251.18 seconds |
| Started | Jul 22 08:14:15 PM PDT 24 |
| Finished | Jul 22 08:18:29 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-f4ab209a-1355-4850-8bb1-3262267dd14e |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084460730 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.4084460730 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3100829644 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3938561524 ps |
| CPU time | 511.26 seconds |
| Started | Jul 22 08:13:20 PM PDT 24 |
| Finished | Jul 22 08:21:52 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-a78795dc-0fe0-4965-b565-0cb399c029fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100829644 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3100829644 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1709753609 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5416010276 ps |
| CPU time | 677.38 seconds |
| Started | Jul 22 08:14:43 PM PDT 24 |
| Finished | Jul 22 08:26:02 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-76f298de-003b-4732-9d30-4b5291eb77cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709753609 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1709753609 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2408427036 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5414510300 ps |
| CPU time | 556.14 seconds |
| Started | Jul 22 08:15:35 PM PDT 24 |
| Finished | Jul 22 08:24:52 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-0200e1b3-f3b9-4c6b-96e7-b897e8a97a16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408427036 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2408427036 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2441779539 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 5194869072 ps |
| CPU time | 611.75 seconds |
| Started | Jul 22 08:13:35 PM PDT 24 |
| Finished | Jul 22 08:23:47 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-17ffdc86-7553-44f7-8923-7b767f175b8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441779539 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2441779539 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.14507117 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 8586192288 ps |
| CPU time | 1209.49 seconds |
| Started | Jul 22 08:14:11 PM PDT 24 |
| Finished | Jul 22 08:34:23 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-f849feea-580b-44bd-9bb7-d0f435585835 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14507117 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.14507117 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1041101224 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3412946856 ps |
| CPU time | 420.74 seconds |
| Started | Jul 22 08:25:02 PM PDT 24 |
| Finished | Jul 22 08:32:05 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-bb8f0c24-8e31-4b64-bf7a-60dd91a763a1 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041101224 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1041101224 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1241803911 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 4772608890 ps |
| CPU time | 638.58 seconds |
| Started | Jul 22 08:12:57 PM PDT 24 |
| Finished | Jul 22 08:23:41 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-ea6e2ddb-fbd7-4313-8db8-e2c98bd767ba |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241803911 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1241803911 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1584410561 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 2853893960 ps |
| CPU time | 255.58 seconds |
| Started | Jul 22 08:13:52 PM PDT 24 |
| Finished | Jul 22 08:18:09 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-512fb891-3f94-4870-adef-e80e8e19dd1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584410561 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.1584410561 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1616357659 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 71878356568 ps |
| CPU time | 13988.1 seconds |
| Started | Jul 22 08:12:44 PM PDT 24 |
| Finished | Jul 23 12:06:06 AM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-c5e46f47-71f9-43e3-8265-dfa4c6a7dfc9 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1616357659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1616357659 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.912575358 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 18755982500 ps |
| CPU time | 4863.91 seconds |
| Started | Jul 22 08:14:07 PM PDT 24 |
| Finished | Jul 22 09:35:13 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-ea052d6a-05e0-41e2-a352-780af5713dd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912575358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.912575358 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3275818768 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3909376780 ps |
| CPU time | 421.31 seconds |
| Started | Jul 22 08:15:29 PM PDT 24 |
| Finished | Jul 22 08:22:34 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-765d13d7-07a2-4724-a723-55b121223d9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32758 18768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3275818768 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.1460738606 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 3092106056 ps |
| CPU time | 227.91 seconds |
| Started | Jul 22 08:14:18 PM PDT 24 |
| Finished | Jul 22 08:18:08 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-154b0bfb-506f-4e2e-8db7-c2762f183e15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460738606 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1460738606 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.245636327 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 7485938248 ps |
| CPU time | 656.91 seconds |
| Started | Jul 22 08:14:57 PM PDT 24 |
| Finished | Jul 22 08:25:54 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-28a86752-fa14-4c8c-b035-4c4be4f6d90e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245636327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.245636327 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3264721203 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2589049528 ps |
| CPU time | 299.39 seconds |
| Started | Jul 22 08:16:45 PM PDT 24 |
| Finished | Jul 22 08:21:45 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-eae0504b-2e4d-40ae-8a21-a447ad875cc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264721203 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3264721203 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.3467123868 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 4874106304 ps |
| CPU time | 1144.13 seconds |
| Started | Jul 22 08:14:48 PM PDT 24 |
| Finished | Jul 22 08:33:54 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-f7e97d64-2cf7-4562-bac1-df665f21bf88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467123868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3467123868 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3699856290 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 5759153620 ps |
| CPU time | 1022.41 seconds |
| Started | Jul 22 08:11:56 PM PDT 24 |
| Finished | Jul 22 08:28:59 PM PDT 24 |
| Peak memory | 611340 kb |
| Host | smart-e9204bcb-a3a7-4aa6-ba7e-baa7a417f9d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3699856290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3699856290 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.1430980508 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3253891180 ps |
| CPU time | 559.99 seconds |
| Started | Jul 22 08:18:14 PM PDT 24 |
| Finished | Jul 22 08:27:35 PM PDT 24 |
| Peak memory | 615800 kb |
| Host | smart-73d0958f-301c-42d1-9852-8826443e95b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430980508 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.1430980508 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.2937157701 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 6974886954 ps |
| CPU time | 1602.77 seconds |
| Started | Jul 22 08:18:46 PM PDT 24 |
| Finished | Jul 22 08:45:30 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-1ba656f3-cdfb-437e-bd3a-3092f7cf226c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937157701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2937157701 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1525719595 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3251408792 ps |
| CPU time | 197.01 seconds |
| Started | Jul 22 08:13:11 PM PDT 24 |
| Finished | Jul 22 08:16:30 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-e2916df1-9b7a-4975-a773-eddc0e997d5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15 25719595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1525719595 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.173693074 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2800260200 ps |
| CPU time | 213.61 seconds |
| Started | Jul 22 08:11:50 PM PDT 24 |
| Finished | Jul 22 08:15:24 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-92b16b58-191f-42cf-ba11-5cad1fc14c87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173693074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.173693074 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2114555615 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 3727932572 ps |
| CPU time | 467.34 seconds |
| Started | Jul 22 08:16:50 PM PDT 24 |
| Finished | Jul 22 08:24:38 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-45bb91eb-cab8-4235-ae02-5ed8b6a0979f |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2114555615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2114555615 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.4244436149 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3557795420 ps |
| CPU time | 299.19 seconds |
| Started | Jul 22 08:18:22 PM PDT 24 |
| Finished | Jul 22 08:23:23 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-3ef91053-d6e9-4ca8-81e2-419525d35f13 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244436149 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.4244436149 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.632606 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2618248696 ps |
| CPU time | 267.74 seconds |
| Started | Jul 22 08:12:31 PM PDT 24 |
| Finished | Jul 22 08:17:01 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-16068608-e92c-402f-b127-b7ea55a30162 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632606 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_example_flash.632606 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2140790132 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2774728664 ps |
| CPU time | 209.78 seconds |
| Started | Jul 22 08:19:13 PM PDT 24 |
| Finished | Jul 22 08:22:44 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-fab52785-2418-4d83-a8f1-b2830f0fde62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140790132 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2140790132 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.2320766994 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2698131550 ps |
| CPU time | 117.23 seconds |
| Started | Jul 22 08:09:58 PM PDT 24 |
| Finished | Jul 22 08:11:56 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-f1f4b892-1652-4e37-9092-6df0caf4172a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320766994 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2320766994 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.395825196 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 58472373997 ps |
| CPU time | 10226.9 seconds |
| Started | Jul 22 08:11:09 PM PDT 24 |
| Finished | Jul 22 11:01:38 PM PDT 24 |
| Peak memory | 625288 kb |
| Host | smart-0b74dfc3-7d37-42ef-91b7-e816b3f26bc5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=395825196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.395825196 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.3667495252 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 5263209860 ps |
| CPU time | 885.42 seconds |
| Started | Jul 22 08:16:08 PM PDT 24 |
| Finished | Jul 22 08:30:55 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-08fe027e-15fa-4adc-87ed-922897f724b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3667495252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3667495252 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.64798986 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 5854883600 ps |
| CPU time | 1243.87 seconds |
| Started | Jul 22 08:11:22 PM PDT 24 |
| Finished | Jul 22 08:32:07 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-ba1f75ed-169f-40b0-9cdd-5167380c6bf6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64798986 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access.64798986 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3760233761 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 6270273951 ps |
| CPU time | 1304.6 seconds |
| Started | Jul 22 08:11:30 PM PDT 24 |
| Finished | Jul 22 08:33:17 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-5dc21a5b-e5c4-4e61-9192-913349528e3b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760233761 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3760233761 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1474123217 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 7253881388 ps |
| CPU time | 1038.88 seconds |
| Started | Jul 22 08:29:28 PM PDT 24 |
| Finished | Jul 22 08:46:48 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-50e6ac01-7afd-4825-b1c9-1cf6722afab8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474123217 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1474123217 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2585392538 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5637502512 ps |
| CPU time | 860.57 seconds |
| Started | Jul 22 08:11:14 PM PDT 24 |
| Finished | Jul 22 08:25:35 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-5574e1a4-35b1-4b4a-b6ad-3870cc8d6146 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585392538 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2585392538 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.95553700 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3474497008 ps |
| CPU time | 447.97 seconds |
| Started | Jul 22 08:12:05 PM PDT 24 |
| Finished | Jul 22 08:19:34 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-730d989b-9fc6-4dbd-9c94-296946a74d1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95553700 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.95553700 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2567608086 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 4795791929 ps |
| CPU time | 651.7 seconds |
| Started | Jul 22 08:11:37 PM PDT 24 |
| Finished | Jul 22 08:22:30 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-0d0ff9dd-717d-4937-9933-4aa097bbadb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 67608086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2567608086 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2891011188 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 5921632562 ps |
| CPU time | 1448.38 seconds |
| Started | Jul 22 08:15:20 PM PDT 24 |
| Finished | Jul 22 08:39:30 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-03b22814-2c83-4c47-adcd-6479e5049806 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891011188 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2891011188 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.389312390 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 4244371340 ps |
| CPU time | 762.52 seconds |
| Started | Jul 22 08:12:08 PM PDT 24 |
| Finished | Jul 22 08:24:51 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-b417d69e-f521-4d64-b33a-9cf2a2847b49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389312390 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.389312390 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.954803598 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 4307172760 ps |
| CPU time | 645.73 seconds |
| Started | Jul 22 08:11:58 PM PDT 24 |
| Finished | Jul 22 08:22:44 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-d13aff42-f6c6-4ff9-a307-fbae36c6ba68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=954803598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.954803598 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2656609679 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4786192366 ps |
| CPU time | 614.28 seconds |
| Started | Jul 22 08:13:58 PM PDT 24 |
| Finished | Jul 22 08:24:14 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-40bfcad0-27d3-44b0-bc61-692221f3e18c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2656609679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2656609679 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2229743478 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2486137640 ps |
| CPU time | 321.01 seconds |
| Started | Jul 22 08:15:06 PM PDT 24 |
| Finished | Jul 22 08:20:28 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-557a930a-79f0-48d8-83f2-b3d6445df7f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229743 478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2229743478 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.3304970836 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 22378918520 ps |
| CPU time | 2210.74 seconds |
| Started | Jul 22 08:10:50 PM PDT 24 |
| Finished | Jul 22 08:47:42 PM PDT 24 |
| Peak memory | 616896 kb |
| Host | smart-2d94b433-f211-4377-af59-3811cd8f5971 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304970836 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3304970836 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1822962635 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2718197676 ps |
| CPU time | 292.66 seconds |
| Started | Jul 22 08:22:05 PM PDT 24 |
| Finished | Jul 22 08:26:58 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-1f94a7e9-c8b1-4be7-adac-d8ef8e30149c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1822962635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1822962635 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2526163292 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3050919906 ps |
| CPU time | 262.94 seconds |
| Started | Jul 22 08:15:38 PM PDT 24 |
| Finished | Jul 22 08:20:02 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-3e89293c-d85f-4166-b4c0-01a355bd979d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526163292 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2526163292 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3418779821 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2374289418 ps |
| CPU time | 221.51 seconds |
| Started | Jul 22 08:14:29 PM PDT 24 |
| Finished | Jul 22 08:18:12 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-858b4cd1-cad4-45eb-8125-f1c524489c4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418779821 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3418779821 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.20198690 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 3575449256 ps |
| CPU time | 321.62 seconds |
| Started | Jul 22 08:15:21 PM PDT 24 |
| Finished | Jul 22 08:20:43 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-8a198254-2de0-48d7-882c-19428a6db939 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20198690 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_hmac_enc_idle.20198690 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.844970649 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2691419409 ps |
| CPU time | 323.28 seconds |
| Started | Jul 22 08:15:30 PM PDT 24 |
| Finished | Jul 22 08:20:54 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-15222a31-e0e3-4be4-bd33-90a3ef1606a0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844970649 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.844970649 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3890147519 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3575946363 ps |
| CPU time | 335.06 seconds |
| Started | Jul 22 08:23:50 PM PDT 24 |
| Finished | Jul 22 08:29:28 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-d986c228-a553-44d9-b877-2ebde6da5135 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890147519 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3890147519 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.4024789588 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 8431713000 ps |
| CPU time | 2308.69 seconds |
| Started | Jul 22 08:13:13 PM PDT 24 |
| Finished | Jul 22 08:51:43 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-2837dffb-e140-4d41-8bb5-ae25d05c3710 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024789588 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.4024789588 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.4220762075 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2894516512 ps |
| CPU time | 307.45 seconds |
| Started | Jul 22 08:13:34 PM PDT 24 |
| Finished | Jul 22 08:18:42 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-88c646dd-daba-44a8-9bd5-e664fdca8bd4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220762075 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.4220762075 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1041824001 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4507559778 ps |
| CPU time | 589.73 seconds |
| Started | Jul 22 08:12:24 PM PDT 24 |
| Finished | Jul 22 08:22:15 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-74c62c6e-4661-4e73-916b-6aa7c2048c3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041824001 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1041824001 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.303996432 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5054233172 ps |
| CPU time | 886.78 seconds |
| Started | Jul 22 08:11:55 PM PDT 24 |
| Finished | Jul 22 08:26:42 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-992a6094-ae1b-4fdb-b370-117d19a7c36f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303996432 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.303996432 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2787845087 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4912743380 ps |
| CPU time | 800.4 seconds |
| Started | Jul 22 08:15:15 PM PDT 24 |
| Finished | Jul 22 08:28:37 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-fe32adce-7900-4485-a12f-ba50e74bc240 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787845087 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2787845087 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4278995972 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 63640547817 ps |
| CPU time | 11382.1 seconds |
| Started | Jul 22 08:14:37 PM PDT 24 |
| Finished | Jul 22 11:24:23 PM PDT 24 |
| Peak memory | 625168 kb |
| Host | smart-bfabf52d-684b-479d-85f8-27a1aecdc106 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4278995972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.4278995972 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.980034148 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 6302821500 ps |
| CPU time | 1147.21 seconds |
| Started | Jul 22 08:16:46 PM PDT 24 |
| Finished | Jul 22 08:35:55 PM PDT 24 |
| Peak memory | 618344 kb |
| Host | smart-6703963f-c4b2-4b65-84d6-9a96df7029e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9800 34148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.980034148 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2080948183 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 9356678957 ps |
| CPU time | 1629.65 seconds |
| Started | Jul 22 08:14:11 PM PDT 24 |
| Finished | Jul 22 08:41:22 PM PDT 24 |
| Peak memory | 616928 kb |
| Host | smart-6751a758-5574-4aa0-8db7-724bbc5a05d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2080948183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2080948183 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2926758941 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 13551738878 ps |
| CPU time | 2578.22 seconds |
| Started | Jul 22 08:14:16 PM PDT 24 |
| Finished | Jul 22 08:57:16 PM PDT 24 |
| Peak memory | 618560 kb |
| Host | smart-d4945481-27c1-4640-a811-0bfc8240eebd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2926758941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2926758941 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3609874208 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 11450611051 ps |
| CPU time | 2867.51 seconds |
| Started | Jul 22 08:12:51 PM PDT 24 |
| Finished | Jul 22 09:00:48 PM PDT 24 |
| Peak memory | 617224 kb |
| Host | smart-db6cc75a-40c8-4b99-853c-579e63f09c99 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3609874208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3609874208 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3484462884 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 13960825144 ps |
| CPU time | 3932.99 seconds |
| Started | Jul 22 08:12:55 PM PDT 24 |
| Finished | Jul 22 09:18:34 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-eecb1cd6-6f5d-4da7-b926-d53566bc1776 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34844 62884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3484462884 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2985837061 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2987613340 ps |
| CPU time | 238.18 seconds |
| Started | Jul 22 08:14:15 PM PDT 24 |
| Finished | Jul 22 08:18:14 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-bc2aefe8-b4e1-49f5-b3f6-3a26179792fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985837061 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2985837061 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.3836954151 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3061954820 ps |
| CPU time | 327.71 seconds |
| Started | Jul 22 08:11:29 PM PDT 24 |
| Finished | Jul 22 08:16:59 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-660c8a15-c615-4b91-aada-321a074ee739 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836954151 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3836954151 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.460538246 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2155146904 ps |
| CPU time | 269.33 seconds |
| Started | Jul 22 08:15:58 PM PDT 24 |
| Finished | Jul 22 08:20:28 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-78d394e9-91c8-42a0-96e7-758aed3526e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460538246 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_idle.460538246 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3869416128 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 3124822576 ps |
| CPU time | 351.22 seconds |
| Started | Jul 22 08:15:20 PM PDT 24 |
| Finished | Jul 22 08:21:12 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-7471478f-e7cc-4d5d-8a71-954c5735e3ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869416128 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3869416128 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3851013968 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 3102560896 ps |
| CPU time | 402.17 seconds |
| Started | Jul 22 08:15:07 PM PDT 24 |
| Finished | Jul 22 08:21:51 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-45098a55-1d04-41b2-aba6-d965fdcf4070 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851013968 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3851013968 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3753662598 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3379692120 ps |
| CPU time | 406.63 seconds |
| Started | Jul 22 08:13:18 PM PDT 24 |
| Finished | Jul 22 08:20:05 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-18bcdbdd-f741-47b6-aee4-89d54587e569 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753662598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3753662598 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.484499542 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 3269086759 ps |
| CPU time | 253.35 seconds |
| Started | Jul 22 08:15:33 PM PDT 24 |
| Finished | Jul 22 08:19:47 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-d505561d-d083-4ed5-b688-ca30d74dba96 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48449954 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.484499542 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.3818800686 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3540581750 ps |
| CPU time | 312.82 seconds |
| Started | Jul 22 08:15:30 PM PDT 24 |
| Finished | Jul 22 08:20:44 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-b9ce596d-e077-4aee-9470-776bb6456c26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818800686 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.3818800686 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3318167223 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3297134826 ps |
| CPU time | 414.07 seconds |
| Started | Jul 22 08:11:43 PM PDT 24 |
| Finished | Jul 22 08:18:39 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-db2f4bfb-7355-4abd-9ebe-afaf25736d89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318167223 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3318167223 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2745869341 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2751454405 ps |
| CPU time | 155.15 seconds |
| Started | Jul 22 08:13:07 PM PDT 24 |
| Finished | Jul 22 08:15:43 PM PDT 24 |
| Peak memory | 620460 kb |
| Host | smart-7a468277-f8bc-42f9-92f8-3d592d55832c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27458693 41 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2745869341 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2429812235 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3208516008 ps |
| CPU time | 159.06 seconds |
| Started | Jul 22 08:12:07 PM PDT 24 |
| Finished | Jul 22 08:14:47 PM PDT 24 |
| Peak memory | 620468 kb |
| Host | smart-d3c348cc-f845-49cc-8455-209040cd0ee5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429812235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2429812235 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1460969459 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3954419456 ps |
| CPU time | 309.52 seconds |
| Started | Jul 22 08:13:11 PM PDT 24 |
| Finished | Jul 22 08:18:22 PM PDT 24 |
| Peak memory | 620592 kb |
| Host | smart-af2e3317-9bb6-473a-b472-6722599fa78d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460969459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1460969459 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4138542786 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2757006690 ps |
| CPU time | 158.55 seconds |
| Started | Jul 22 08:12:12 PM PDT 24 |
| Finished | Jul 22 08:14:51 PM PDT 24 |
| Peak memory | 619888 kb |
| Host | smart-0a8fa610-cbc4-4bf8-9527-731235a13c46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138542786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.4138542786 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3210592790 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 12649660409 ps |
| CPU time | 785.92 seconds |
| Started | Jul 22 08:10:51 PM PDT 24 |
| Finished | Jul 22 08:23:58 PM PDT 24 |
| Peak memory | 624388 kb |
| Host | smart-c6b031ed-aebc-40be-bf52-0d49d2899ec3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210592790 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3210592790 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3276309755 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 2855495174 ps |
| CPU time | 113.07 seconds |
| Started | Jul 22 08:19:26 PM PDT 24 |
| Finished | Jul 22 08:21:22 PM PDT 24 |
| Peak memory | 617328 kb |
| Host | smart-bea8d9a6-68ab-4c5a-bd29-99a6372b91d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3276309755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3276309755 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3324063235 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2448851403 ps |
| CPU time | 112.33 seconds |
| Started | Jul 22 08:11:14 PM PDT 24 |
| Finished | Jul 22 08:13:07 PM PDT 24 |
| Peak memory | 623416 kb |
| Host | smart-4e4af14a-e315-4b4b-8723-a049bdda5682 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324063235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3324063235 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1749522988 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 50055379615 ps |
| CPU time | 4994.09 seconds |
| Started | Jul 22 08:20:01 PM PDT 24 |
| Finished | Jul 22 09:43:17 PM PDT 24 |
| Peak memory | 620760 kb |
| Host | smart-6dc82233-0ad9-4982-86c1-b09f051c0560 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749522988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.1749522988 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1819550513 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 51337003807 ps |
| CPU time | 5237.66 seconds |
| Started | Jul 22 08:19:53 PM PDT 24 |
| Finished | Jul 22 09:47:12 PM PDT 24 |
| Peak memory | 619704 kb |
| Host | smart-7a96be04-cb2f-4938-ae9c-ab7ecc91473d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819550513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1819550513 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3446634832 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 8990356300 ps |
| CPU time | 1107.04 seconds |
| Started | Jul 22 08:11:43 PM PDT 24 |
| Finished | Jul 22 08:30:12 PM PDT 24 |
| Peak memory | 619076 kb |
| Host | smart-80f4c4a7-7018-47b3-a7d1-16775fb6fbce |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446634832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3446634832 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1585279616 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 46528340464 ps |
| CPU time | 6143.63 seconds |
| Started | Jul 22 08:12:56 PM PDT 24 |
| Finished | Jul 22 09:55:27 PM PDT 24 |
| Peak memory | 620640 kb |
| Host | smart-ceb0b7c5-d14c-4205-b9e8-41719598452a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585279616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.1585279616 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2077869759 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 17091509130 ps |
| CPU time | 3799.08 seconds |
| Started | Jul 22 08:14:00 PM PDT 24 |
| Finished | Jul 22 09:17:21 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-baa6b740-de15-4e00-b969-0f22ee679c83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2077869759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2077869759 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2586792470 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 19161540880 ps |
| CPU time | 4089.31 seconds |
| Started | Jul 22 08:13:13 PM PDT 24 |
| Finished | Jul 22 09:21:23 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-baff2f16-1b0b-4e41-a1d5-ad71ae243f65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2586792470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2586792470 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.265089981 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 25262483767 ps |
| CPU time | 3856.95 seconds |
| Started | Jul 22 08:15:19 PM PDT 24 |
| Finished | Jul 22 09:19:37 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-97982276-6a69-45d0-8fc5-c5fead7a9e92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265089981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.265089981 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2222092078 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 3558105852 ps |
| CPU time | 526.09 seconds |
| Started | Jul 22 08:12:09 PM PDT 24 |
| Finished | Jul 22 08:20:57 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-28f5ea6d-ae2d-4f5e-a887-3cc1cc78ec0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222092078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2222092078 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2062000494 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 6717449110 ps |
| CPU time | 893.94 seconds |
| Started | Jul 22 08:13:13 PM PDT 24 |
| Finished | Jul 22 08:28:08 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-09fad547-ec0c-4050-b13f-451a6d3b8bda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2062000494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2062000494 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1113522995 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 5322172680 ps |
| CPU time | 1064.67 seconds |
| Started | Jul 22 08:18:17 PM PDT 24 |
| Finished | Jul 22 08:36:02 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-42cb6adb-edce-4824-8298-52028fb64d11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113522995 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1113522995 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3459262370 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 27624395224 ps |
| CPU time | 5792.8 seconds |
| Started | Jul 22 08:12:27 PM PDT 24 |
| Finished | Jul 22 09:49:02 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-f761026c-10b9-442c-b549-2f8a30a6d222 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345926 2370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.3459262370 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1528707540 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 3150119337 ps |
| CPU time | 297.25 seconds |
| Started | Jul 22 08:12:33 PM PDT 24 |
| Finished | Jul 22 08:17:32 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-ecbb445b-cc31-4689-a388-d8da71bcfce3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528707540 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1528707540 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2829346461 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4432783280 ps |
| CPU time | 648.87 seconds |
| Started | Jul 22 08:12:39 PM PDT 24 |
| Finished | Jul 22 08:23:38 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-d99c4836-85a4-479c-acbb-6d7e7d9f2876 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2829346461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2829346461 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1349110185 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 7507658648 ps |
| CPU time | 1428.07 seconds |
| Started | Jul 22 08:11:37 PM PDT 24 |
| Finished | Jul 22 08:35:27 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-c82b4f6e-89df-4a1b-ad2b-52d3fcb6406c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1349110185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1349110185 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3653293711 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 6453887582 ps |
| CPU time | 1375.2 seconds |
| Started | Jul 22 08:12:29 PM PDT 24 |
| Finished | Jul 22 08:35:26 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-d225073b-efce-4711-a726-c34050cc482c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3653293711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3653293711 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2038580974 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 8002145964 ps |
| CPU time | 1323.29 seconds |
| Started | Jul 22 08:15:48 PM PDT 24 |
| Finished | Jul 22 08:37:53 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-70d142db-6d09-491f-9c1b-0d49021c9c5a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2038580974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2038580974 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.610406543 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 4076915800 ps |
| CPU time | 610.86 seconds |
| Started | Jul 22 08:11:27 PM PDT 24 |
| Finished | Jul 22 08:21:39 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-79a3597c-8881-46dd-8b43-1603ac3bbda3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=610406543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.610406543 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2084790466 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 2946457848 ps |
| CPU time | 227.58 seconds |
| Started | Jul 22 08:15:03 PM PDT 24 |
| Finished | Jul 22 08:18:52 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-a5020968-921a-4aa7-b622-d52c8df5835d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084790466 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2084790466 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3019377647 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 10653048432 ps |
| CPU time | 393.24 seconds |
| Started | Jul 22 08:25:35 PM PDT 24 |
| Finished | Jul 22 08:32:18 PM PDT 24 |
| Peak memory | 611316 kb |
| Host | smart-86e61109-56ed-4746-92d6-6499f0bf81be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019377647 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3019377647 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1564927222 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 10413682050 ps |
| CPU time | 1154.47 seconds |
| Started | Jul 22 08:11:03 PM PDT 24 |
| Finished | Jul 22 08:30:19 PM PDT 24 |
| Peak memory | 611736 kb |
| Host | smart-90ba0fd4-126a-47ee-98ac-ec83eff6ba92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564 927222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.1564927222 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3973466538 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 25944115456 ps |
| CPU time | 2723.07 seconds |
| Started | Jul 22 08:13:35 PM PDT 24 |
| Finished | Jul 22 08:58:59 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-cf497d19-d066-46f2-acb4-5901a78e8751 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397 3466538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3973466538 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4071423071 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 16180559293 ps |
| CPU time | 1614.4 seconds |
| Started | Jul 22 08:13:38 PM PDT 24 |
| Finished | Jul 22 08:40:33 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-cebbaf44-b36f-4275-8669-7e8333342154 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4071423071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4071423071 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1002714851 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 8927728142 ps |
| CPU time | 596.14 seconds |
| Started | Jul 22 08:12:45 PM PDT 24 |
| Finished | Jul 22 08:22:54 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-ed9b348b-2b98-418e-8bb4-07f31813ba73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002714851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1002714851 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1400383861 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 5448534430 ps |
| CPU time | 478.97 seconds |
| Started | Jul 22 08:13:46 PM PDT 24 |
| Finished | Jul 22 08:21:47 PM PDT 24 |
| Peak memory | 618004 kb |
| Host | smart-711adb3e-cde6-4750-8de8-056cff8ac13a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1400383861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1400383861 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1382550072 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 11113549797 ps |
| CPU time | 1209.05 seconds |
| Started | Jul 22 08:10:34 PM PDT 24 |
| Finished | Jul 22 08:30:44 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-2276a1e1-1d1e-43c4-b63f-ab6fcade547c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382550072 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1382550072 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4198409369 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 7603810680 ps |
| CPU time | 394.17 seconds |
| Started | Jul 22 08:15:01 PM PDT 24 |
| Finished | Jul 22 08:21:36 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-34119f6c-a541-439a-8cf3-7b9259f6b0ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198409369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4198409369 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3309427324 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 6337333332 ps |
| CPU time | 616.85 seconds |
| Started | Jul 22 08:12:16 PM PDT 24 |
| Finished | Jul 22 08:22:33 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-cf24638f-347c-4f1a-a522-559155820dec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309427324 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3309427324 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4011256068 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 19838578667 ps |
| CPU time | 2842.23 seconds |
| Started | Jul 22 08:11:07 PM PDT 24 |
| Finished | Jul 22 08:58:31 PM PDT 24 |
| Peak memory | 611720 kb |
| Host | smart-42280190-67e9-455f-adb6-0e2a99774d37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4011256068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4011256068 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3348643210 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 22267548864 ps |
| CPU time | 1597.32 seconds |
| Started | Jul 22 08:21:02 PM PDT 24 |
| Finished | Jul 22 08:47:41 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-9b876142-3476-41b2-8928-12fb27c7a026 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3348643210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3348643210 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4156137773 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 26548467014 ps |
| CPU time | 3346.6 seconds |
| Started | Jul 22 08:13:14 PM PDT 24 |
| Finished | Jul 22 09:09:02 PM PDT 24 |
| Peak memory | 612160 kb |
| Host | smart-98ab2700-a571-4c28-9fb3-91a6081f0bbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156137773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4156137773 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3607669068 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3246439192 ps |
| CPU time | 297.45 seconds |
| Started | Jul 22 08:13:07 PM PDT 24 |
| Finished | Jul 22 08:18:05 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-5d2d2a69-b4b4-475e-a7c1-79673afb1558 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607669068 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3607669068 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1056756245 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 5516547976 ps |
| CPU time | 462.18 seconds |
| Started | Jul 22 08:12:02 PM PDT 24 |
| Finished | Jul 22 08:19:45 PM PDT 24 |
| Peak memory | 617844 kb |
| Host | smart-14166c4e-0acc-44e4-bf59-bc2fe70b7c9b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1056756245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1056756245 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2682010211 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 4957372988 ps |
| CPU time | 461.6 seconds |
| Started | Jul 22 08:14:12 PM PDT 24 |
| Finished | Jul 22 08:21:56 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-f488e273-f692-474a-8a14-a34159ff29b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2682010211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2682010211 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3838535523 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 5955145704 ps |
| CPU time | 512.73 seconds |
| Started | Jul 22 08:20:39 PM PDT 24 |
| Finished | Jul 22 08:29:12 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-d3656578-9e48-442e-ba1b-22e1c03a677c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838535523 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3838535523 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1117107473 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 6811539726 ps |
| CPU time | 1151.46 seconds |
| Started | Jul 22 08:12:57 PM PDT 24 |
| Finished | Jul 22 08:32:13 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-3be133f0-a690-4bb0-b30f-2708e4fa191b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117107473 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1117107473 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4170785014 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4073068032 ps |
| CPU time | 622.1 seconds |
| Started | Jul 22 08:12:55 PM PDT 24 |
| Finished | Jul 22 08:23:23 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-39d5be78-64b8-4846-9a8a-2300e3cbbf9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170785014 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4170785014 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1440466538 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 5615285448 ps |
| CPU time | 459.43 seconds |
| Started | Jul 22 08:18:45 PM PDT 24 |
| Finished | Jul 22 08:26:27 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-90894898-bb55-494e-a64c-37843f173615 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440466538 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1440466538 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2265394627 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 5322263664 ps |
| CPU time | 527.33 seconds |
| Started | Jul 22 08:15:36 PM PDT 24 |
| Finished | Jul 22 08:24:26 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-f846d9f5-a937-4deb-a7c9-f292191eef87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226 5394627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2265394627 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1905387980 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 9400599604 ps |
| CPU time | 611.9 seconds |
| Started | Jul 22 08:14:31 PM PDT 24 |
| Finished | Jul 22 08:24:45 PM PDT 24 |
| Peak memory | 624272 kb |
| Host | smart-edb96171-2a7f-4613-b57f-df2e17881d88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905387980 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.1905387980 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2451181250 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 8788991048 ps |
| CPU time | 1556.89 seconds |
| Started | Jul 22 08:13:29 PM PDT 24 |
| Finished | Jul 22 08:39:26 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-164071ed-4b9e-491b-81a2-3bbfd79e670a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2451181250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2451181250 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2843733327 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6398105480 ps |
| CPU time | 961.2 seconds |
| Started | Jul 22 08:13:05 PM PDT 24 |
| Finished | Jul 22 08:29:07 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-8c2fe6aa-3845-4041-8971-47d12f41cbf8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843733327 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2843733327 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.783044033 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5478404782 ps |
| CPU time | 490.18 seconds |
| Started | Jul 22 08:09:39 PM PDT 24 |
| Finished | Jul 22 08:17:52 PM PDT 24 |
| Peak memory | 642048 kb |
| Host | smart-5ba4144b-dde5-4c72-89c1-1d774ce1180b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 783044033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.783044033 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.672600949 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2690918744 ps |
| CPU time | 246.43 seconds |
| Started | Jul 22 08:14:34 PM PDT 24 |
| Finished | Jul 22 08:18:41 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-30142562-f037-4f86-aef7-68240de6012b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672600949 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.672600949 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.91989723 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 3460402936 ps |
| CPU time | 375.38 seconds |
| Started | Jul 22 08:12:46 PM PDT 24 |
| Finished | Jul 22 08:19:14 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-052e9bd4-eba4-4b9b-9d5e-44150ae3e1b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91989723 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_sw_req.91989723 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1115540139 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3146511350 ps |
| CPU time | 283.17 seconds |
| Started | Jul 22 08:12:20 PM PDT 24 |
| Finished | Jul 22 08:17:04 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-d59199b4-11a9-4426-b5b4-1d815da999d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115540139 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1115540139 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2394899854 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2837373308 ps |
| CPU time | 285.4 seconds |
| Started | Jul 22 08:13:11 PM PDT 24 |
| Finished | Jul 22 08:17:57 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-5b507745-641b-48fc-b2b0-ba06e639aea5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394899854 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2394899854 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2238987222 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 5666712184 ps |
| CPU time | 1009.86 seconds |
| Started | Jul 22 08:14:07 PM PDT 24 |
| Finished | Jul 22 08:30:58 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-00c4fac3-980a-4971-a4f2-8cbdefe78719 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2238987222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2238987222 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4108632163 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6661413972 ps |
| CPU time | 534.61 seconds |
| Started | Jul 22 08:15:57 PM PDT 24 |
| Finished | Jul 22 08:24:53 PM PDT 24 |
| Peak memory | 624200 kb |
| Host | smart-8a701f05-3a8d-4128-8bec-f56cf1d1af44 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108632163 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.4108632163 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.380043192 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 2156962368 ps |
| CPU time | 192.3 seconds |
| Started | Jul 22 08:16:53 PM PDT 24 |
| Finished | Jul 22 08:20:07 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-c8e10988-5073-4a9b-8684-f4a2510c25bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380043192 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.380043192 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1284436897 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 2809178000 ps |
| CPU time | 212.14 seconds |
| Started | Jul 22 08:11:11 PM PDT 24 |
| Finished | Jul 22 08:14:44 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-47d1a3b3-f542-4ada-b2bb-603cc564094c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284436897 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1284436897 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2078433300 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2518429512 ps |
| CPU time | 223.73 seconds |
| Started | Jul 22 08:17:14 PM PDT 24 |
| Finished | Jul 22 08:20:59 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-a30a8d07-cc08-44d9-877c-3c137b8b015b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078433300 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2078433300 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.227603802 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5544062138 ps |
| CPU time | 792.87 seconds |
| Started | Jul 22 08:14:34 PM PDT 24 |
| Finished | Jul 22 08:27:48 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-e7eb70c5-f776-40d0-882b-c8f5bea36295 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22760380 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.227603802 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1299852493 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 2127259754 ps |
| CPU time | 254.15 seconds |
| Started | Jul 22 08:14:30 PM PDT 24 |
| Finished | Jul 22 08:18:45 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-a6305c56-9e2a-4101-a53d-c933e3af2da4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299852 493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1299852493 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1263648229 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 8938805074 ps |
| CPU time | 1435.28 seconds |
| Started | Jul 22 08:11:42 PM PDT 24 |
| Finished | Jul 22 08:35:39 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-cb4f3943-292b-4a7f-aba4-8bd09821b395 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263648229 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.1263648229 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1878861520 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 8050420584 ps |
| CPU time | 675.93 seconds |
| Started | Jul 22 08:16:20 PM PDT 24 |
| Finished | Jul 22 08:27:37 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-4d9cedcd-411a-4b96-9cdd-04f7c44662ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878861520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1878861520 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3579151127 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 7294853332 ps |
| CPU time | 971.98 seconds |
| Started | Jul 22 08:16:31 PM PDT 24 |
| Finished | Jul 22 08:32:44 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-c6fd8a3d-78f8-4b2b-95f1-2dd6143ae34d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579151127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.3579151127 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.557619915 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6305154858 ps |
| CPU time | 735.54 seconds |
| Started | Jul 22 08:11:42 PM PDT 24 |
| Finished | Jul 22 08:24:00 PM PDT 24 |
| Peak memory | 625308 kb |
| Host | smart-acac244a-45a3-462d-8e2d-4afab68b45d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557619915 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.557619915 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2099338646 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4682025089 ps |
| CPU time | 610.95 seconds |
| Started | Jul 22 08:12:43 PM PDT 24 |
| Finished | Jul 22 08:23:07 PM PDT 24 |
| Peak memory | 625348 kb |
| Host | smart-69f57c23-e6cf-4cff-9fcd-8c20b06d5557 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099338646 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2099338646 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2172459910 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3095938458 ps |
| CPU time | 472.1 seconds |
| Started | Jul 22 08:12:04 PM PDT 24 |
| Finished | Jul 22 08:19:57 PM PDT 24 |
| Peak memory | 620000 kb |
| Host | smart-03ea9653-98d6-4a72-8492-50c51c54986c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172459910 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2172459910 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1396402080 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3392447750 ps |
| CPU time | 347.11 seconds |
| Started | Jul 22 08:11:12 PM PDT 24 |
| Finished | Jul 22 08:17:00 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-d073ba77-5752-4fdc-a109-23ff181449f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396402080 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1396402080 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2878264649 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6656297070 ps |
| CPU time | 574.67 seconds |
| Started | Jul 22 08:16:06 PM PDT 24 |
| Finished | Jul 22 08:25:41 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-06123a84-64b8-43be-9c91-8dbbb7fa62a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878264649 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2878264649 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1043773348 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 5274000842 ps |
| CPU time | 531.74 seconds |
| Started | Jul 22 08:13:50 PM PDT 24 |
| Finished | Jul 22 08:22:43 PM PDT 24 |
| Peak memory | 611396 kb |
| Host | smart-1fb93854-f41f-4f82-865a-70dcbef5122f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043773348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.1043773348 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2468231714 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5156291184 ps |
| CPU time | 649.88 seconds |
| Started | Jul 22 08:15:09 PM PDT 24 |
| Finished | Jul 22 08:26:02 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-33ffc11f-1bbd-4fdf-98fc-9f2827da0aa2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468231714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2468231714 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1981510692 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4585483742 ps |
| CPU time | 509.58 seconds |
| Started | Jul 22 08:16:59 PM PDT 24 |
| Finished | Jul 22 08:25:31 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-20114b86-5a51-43d6-a40d-7b6aae7fc22e |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981510692 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1981510692 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.390619700 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3000124652 ps |
| CPU time | 227.1 seconds |
| Started | Jul 22 08:17:27 PM PDT 24 |
| Finished | Jul 22 08:21:15 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-40769e7a-a02d-4551-84a9-68f1ff734754 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390619700 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.390619700 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2498432030 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 21189069830 ps |
| CPU time | 3467.95 seconds |
| Started | Jul 22 08:13:28 PM PDT 24 |
| Finished | Jul 22 09:11:17 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-90dea3a4-18c0-4d45-8c59-3fd774b91bd1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498432030 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.2498432030 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2931427576 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4399595567 ps |
| CPU time | 603.15 seconds |
| Started | Jul 22 08:19:24 PM PDT 24 |
| Finished | Jul 22 08:29:30 PM PDT 24 |
| Peak memory | 614252 kb |
| Host | smart-212b1040-99df-484c-b587-f3a4659c8779 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931427576 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2931427576 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.307272206 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3434494936 ps |
| CPU time | 364.86 seconds |
| Started | Jul 22 08:11:53 PM PDT 24 |
| Finished | Jul 22 08:18:00 PM PDT 24 |
| Peak memory | 613704 kb |
| Host | smart-6dd00a3f-a8a2-42ee-9c28-1ee680bcba34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307272206 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.307272206 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2427589330 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 24478356928 ps |
| CPU time | 1704.78 seconds |
| Started | Jul 22 08:15:53 PM PDT 24 |
| Finished | Jul 22 08:44:19 PM PDT 24 |
| Peak memory | 614704 kb |
| Host | smart-bc00b467-cefe-46ed-9e4c-a38c53649435 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275893 30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2427589330 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3091451877 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5991915460 ps |
| CPU time | 514.2 seconds |
| Started | Jul 22 08:12:25 PM PDT 24 |
| Finished | Jul 22 08:21:01 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-abb3d8f7-882e-4c7e-8e07-ffbcd0d1d899 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091451877 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3091451877 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2921408192 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4687222510 ps |
| CPU time | 721.1 seconds |
| Started | Jul 22 08:11:30 PM PDT 24 |
| Finished | Jul 22 08:23:33 PM PDT 24 |
| Peak memory | 619228 kb |
| Host | smart-4e563e08-23ab-4690-a237-4e0037674d21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2921408192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2921408192 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.1152034597 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2698427768 ps |
| CPU time | 192.15 seconds |
| Started | Jul 22 08:23:26 PM PDT 24 |
| Finished | Jul 22 08:26:39 PM PDT 24 |
| Peak memory | 617568 kb |
| Host | smart-7e7598b6-f383-46a0-b851-4aafc1988dc4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152034597 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.1152034597 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2112368637 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4682692474 ps |
| CPU time | 718.39 seconds |
| Started | Jul 22 08:12:22 PM PDT 24 |
| Finished | Jul 22 08:24:22 PM PDT 24 |
| Peak memory | 625116 kb |
| Host | smart-15a2662a-4dfa-46e4-a6ed-09832d0fadee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112368637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.2112368637 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3034549078 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 5070401035 ps |
| CPU time | 550.12 seconds |
| Started | Jul 22 08:15:03 PM PDT 24 |
| Finished | Jul 22 08:24:14 PM PDT 24 |
| Peak memory | 625152 kb |
| Host | smart-6cc3f3c9-e8ad-4345-9023-629ca3f14dfe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034549078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3034549078 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.328784547 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 78217417219 ps |
| CPU time | 13572 seconds |
| Started | Jul 22 08:10:58 PM PDT 24 |
| Finished | Jul 22 11:57:13 PM PDT 24 |
| Peak memory | 634500 kb |
| Host | smart-b7ecb1c1-7345-47cf-ab4f-3750f5529768 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=328784547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.328784547 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3348439673 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3984742856 ps |
| CPU time | 581.5 seconds |
| Started | Jul 22 08:23:04 PM PDT 24 |
| Finished | Jul 22 08:32:50 PM PDT 24 |
| Peak memory | 625120 kb |
| Host | smart-d5321f02-d6aa-4471-af5a-15bcd90ac5a7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348439673 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3348439673 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3544720346 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 3775610472 ps |
| CPU time | 666.12 seconds |
| Started | Jul 22 08:10:37 PM PDT 24 |
| Finished | Jul 22 08:21:44 PM PDT 24 |
| Peak memory | 625148 kb |
| Host | smart-3efa65e7-57b2-44d8-b6c8-d23d14515e9b |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544720346 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3544720346 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1979021365 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 4098672378 ps |
| CPU time | 615.33 seconds |
| Started | Jul 22 08:19:26 PM PDT 24 |
| Finished | Jul 22 08:29:43 PM PDT 24 |
| Peak memory | 625124 kb |
| Host | smart-04391a79-fa9a-4dde-b40f-71dfcb83fab6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979021365 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1979021365 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3064522055 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3714562339 ps |
| CPU time | 378.35 seconds |
| Started | Jul 22 08:18:10 PM PDT 24 |
| Finished | Jul 22 08:24:29 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-b7df9c4a-3cd3-4c70-9187-7970445204e3 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064522055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3064522055 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2650902831 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12133171880 ps |
| CPU time | 2818.34 seconds |
| Started | Jul 22 08:11:22 PM PDT 24 |
| Finished | Jul 22 08:58:21 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-b7634603-71da-45d3-a135-518933a55d9c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2650902831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2650902831 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.828715575 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 31627487464 ps |
| CPU time | 6813.45 seconds |
| Started | Jul 22 08:24:59 PM PDT 24 |
| Finished | Jul 22 10:18:35 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-1737df4a-602d-4685-b640-6aead7aa26c0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=828715575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.828715575 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.598419932 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3680957002 ps |
| CPU time | 316.67 seconds |
| Started | Jul 22 08:12:05 PM PDT 24 |
| Finished | Jul 22 08:17:22 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-9cf17008-d7e1-49df-ab5f-aeccdacae105 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598419932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.598419932 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2370776595 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 4218718506 ps |
| CPU time | 586.61 seconds |
| Started | Jul 22 08:11:05 PM PDT 24 |
| Finished | Jul 22 08:20:55 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-2efaa74e-03db-4632-8f0a-b7d6b33cb0fe |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237077659 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2370776595 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.1322888508 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 19113765628 ps |
| CPU time | 4420.73 seconds |
| Started | Jul 22 08:10:12 PM PDT 24 |
| Finished | Jul 22 09:23:55 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-27a9d3d9-5e27-4558-8b13-44b0b8782158 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1322888508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1322888508 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.2358603354 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2870603520 ps |
| CPU time | 302.22 seconds |
| Started | Jul 22 08:10:52 PM PDT 24 |
| Finished | Jul 22 08:15:56 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-62ed151d-c650-4e05-9803-3eae05e3368a |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358603354 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.2358603354 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3284257293 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 2687276801 ps |
| CPU time | 149.79 seconds |
| Started | Jul 22 08:15:21 PM PDT 24 |
| Finished | Jul 22 08:17:52 PM PDT 24 |
| Peak memory | 621504 kb |
| Host | smart-9282a0f8-5782-4bfb-b5e7-6936764b5aa9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3284257293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3284257293 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.860109684 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 8262409008 ps |
| CPU time | 905.88 seconds |
| Started | Jul 22 08:13:03 PM PDT 24 |
| Finished | Jul 22 08:28:10 PM PDT 24 |
| Peak memory | 623040 kb |
| Host | smart-d548c60c-982c-41d3-9157-bf4fc7cd0b1d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860109684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.860109684 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.2638237731 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2945749141 ps |
| CPU time | 178 seconds |
| Started | Jul 22 08:13:35 PM PDT 24 |
| Finished | Jul 22 08:16:34 PM PDT 24 |
| Peak memory | 623560 kb |
| Host | smart-d423a7d4-9104-4d31-945f-47b137fd4aae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638237731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2638237731 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.1934389537 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 15608112138 ps |
| CPU time | 3452.7 seconds |
| Started | Jul 22 08:19:39 PM PDT 24 |
| Finished | Jul 22 09:17:14 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-3f7294ec-91e3-4cc9-b722-0dff3bd4b238 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934389537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.1934389537 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.827868008 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 15214414776 ps |
| CPU time | 4094.72 seconds |
| Started | Jul 22 08:19:08 PM PDT 24 |
| Finished | Jul 22 09:27:24 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-836eb222-3dd2-4f93-b6f0-f0309b4635d5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827868008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.827868008 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1530934474 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 15458108330 ps |
| CPU time | 3634.59 seconds |
| Started | Jul 22 08:24:55 PM PDT 24 |
| Finished | Jul 22 09:25:30 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-e99680b8-37c1-4703-8a36-c2ac839f2059 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530934474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.1530934474 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.3549479583 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 14714356871 ps |
| CPU time | 3627.12 seconds |
| Started | Jul 22 08:18:47 PM PDT 24 |
| Finished | Jul 22 09:19:15 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-ce00bec5-6164-4442-8b70-bade49a265c6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549479583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3549479583 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.543806722 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 11765147128 ps |
| CPU time | 2179.3 seconds |
| Started | Jul 22 08:16:23 PM PDT 24 |
| Finished | Jul 22 08:52:43 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-b9ab3c47-a2b4-4b00-ad5e-dc7b941929d0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543806722 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.543806722 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2722767637 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 24172067960 ps |
| CPU time | 5769.42 seconds |
| Started | Jul 22 08:24:53 PM PDT 24 |
| Finished | Jul 22 10:01:04 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-1f1e7d21-b029-4341-8602-88a663fce20d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2722767637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2722767637 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.44169525 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 24683485582 ps |
| CPU time | 7822.71 seconds |
| Started | Jul 22 08:22:19 PM PDT 24 |
| Finished | Jul 22 10:32:44 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-f189eafa-a7f5-40e8-8f6b-fa00fec5d5fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=44169525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.44169525 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1369071819 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 23278160516 ps |
| CPU time | 6164.92 seconds |
| Started | Jul 22 08:23:25 PM PDT 24 |
| Finished | Jul 22 10:06:10 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-0a741ccf-26bf-466d-80ff-d08bf209108f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1369071819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1369071819 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.571418269 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 18019970340 ps |
| CPU time | 5826.63 seconds |
| Started | Jul 22 08:32:41 PM PDT 24 |
| Finished | Jul 22 10:09:48 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-44a3f82b-4a33-4b25-a9cf-eb0415c3c50a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571418269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.571418269 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2865797996 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 15136691374 ps |
| CPU time | 3662.75 seconds |
| Started | Jul 22 08:19:58 PM PDT 24 |
| Finished | Jul 22 09:21:01 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-efc54e82-188c-46e9-b32b-fe17abfd3c81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2865797996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2865797996 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.992533508 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 16051058204 ps |
| CPU time | 5004.64 seconds |
| Started | Jul 22 08:32:16 PM PDT 24 |
| Finished | Jul 22 09:55:42 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-e0e12e0d-61f4-4853-85b7-e8506fc34711 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=992533508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.992533508 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.554216606 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 15293258982 ps |
| CPU time | 3429.67 seconds |
| Started | Jul 22 08:17:51 PM PDT 24 |
| Finished | Jul 22 09:15:02 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-93436740-fca5-48f1-867a-4bc8d0ceb5ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=554216606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.554216606 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2763081869 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 14753405712 ps |
| CPU time | 4847.98 seconds |
| Started | Jul 22 08:32:12 PM PDT 24 |
| Finished | Jul 22 09:53:02 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-51bbd141-1011-4022-9df4-a4461857e408 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2763081869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2763081869 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1472226152 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 11076135288 ps |
| CPU time | 2943.06 seconds |
| Started | Jul 22 08:19:41 PM PDT 24 |
| Finished | Jul 22 09:08:46 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-40fb7444-a507-4b52-9511-22b61804929c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472226152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1472226152 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2849136843 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 16006748020 ps |
| CPU time | 4867.17 seconds |
| Started | Jul 22 08:32:42 PM PDT 24 |
| Finished | Jul 22 09:53:50 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-e6cd681c-efb8-49f7-9451-01729ae3dfbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849136843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2849136843 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.619873367 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 15457193130 ps |
| CPU time | 3239.62 seconds |
| Started | Jul 22 08:17:53 PM PDT 24 |
| Finished | Jul 22 09:11:53 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-d47e0f11-45e7-4aa4-a754-f68e9b43df1e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619873367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.619873367 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1095169523 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 15459458500 ps |
| CPU time | 4899.71 seconds |
| Started | Jul 22 08:32:41 PM PDT 24 |
| Finished | Jul 22 09:54:21 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-2f221272-bbfe-4bc5-b5f5-edf57ff370f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109516 9523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1095169523 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.650163472 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 15134254352 ps |
| CPU time | 3717.24 seconds |
| Started | Jul 22 08:24:47 PM PDT 24 |
| Finished | Jul 22 09:26:45 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-27f966fe-2c21-4123-a7e2-642ee990daab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650163472 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.650163472 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1177045319 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 11450702972 ps |
| CPU time | 3059.35 seconds |
| Started | Jul 22 08:19:23 PM PDT 24 |
| Finished | Jul 22 09:10:24 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-01c24dcd-6d68-4bda-a21e-d65c26032eee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1177045319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1177045319 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1635790124 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 11295778626 ps |
| CPU time | 2168.35 seconds |
| Started | Jul 22 08:17:02 PM PDT 24 |
| Finished | Jul 22 08:53:12 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-88e4bf9c-1dd0-4a9c-a652-40a155605eb9 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16357 90124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1635790124 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2654566130 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 11303475935 ps |
| CPU time | 2060.94 seconds |
| Started | Jul 22 08:20:18 PM PDT 24 |
| Finished | Jul 22 08:54:41 PM PDT 24 |
| Peak memory | 624356 kb |
| Host | smart-bbfd8dba-054b-4f55-b94a-8e7229e94afb |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26545 66130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2654566130 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3176368776 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 11992054391 ps |
| CPU time | 2174.49 seconds |
| Started | Jul 22 08:14:37 PM PDT 24 |
| Finished | Jul 22 08:50:54 PM PDT 24 |
| Peak memory | 624744 kb |
| Host | smart-3b99590b-32bb-444b-8b55-947e2cdf6b5a |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3176368776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3176368776 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3201463086 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 26546897239 ps |
| CPU time | 2431.97 seconds |
| Started | Jul 22 08:15:57 PM PDT 24 |
| Finished | Jul 22 08:56:30 PM PDT 24 |
| Peak memory | 621932 kb |
| Host | smart-3d075663-2bda-4568-b1fe-52df34587a36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3201463086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3201463086 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2952538248 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 31521751866 ps |
| CPU time | 3035.19 seconds |
| Started | Jul 22 08:18:13 PM PDT 24 |
| Finished | Jul 22 09:08:50 PM PDT 24 |
| Peak memory | 622408 kb |
| Host | smart-9f9068c7-462d-4abf-9a9c-9503c12e3bd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2952538248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2952538248 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.595603321 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 34406026313 ps |
| CPU time | 2682.52 seconds |
| Started | Jul 22 08:17:27 PM PDT 24 |
| Finished | Jul 22 09:02:11 PM PDT 24 |
| Peak memory | 622764 kb |
| Host | smart-aaf90dcb-28fa-4505-82ce-aee609112cbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595603321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_ test_unlocked0.595603321 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1554893626 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 14988197616 ps |
| CPU time | 3658.88 seconds |
| Started | Jul 22 08:21:50 PM PDT 24 |
| Finished | Jul 22 09:22:50 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-adcf0ed0-1808-46fd-b302-e001233c4b3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554893626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1554893626 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2165689284 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 15216340360 ps |
| CPU time | 3553.55 seconds |
| Started | Jul 22 08:21:50 PM PDT 24 |
| Finished | Jul 22 09:21:06 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-394d1e01-c8b0-4a59-a630-61ad74261867 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165689284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2165689284 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1697633206 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 15033932484 ps |
| CPU time | 4736.39 seconds |
| Started | Jul 22 08:21:16 PM PDT 24 |
| Finished | Jul 22 09:40:13 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-215e2dcc-691b-4ea1-b6f0-487b6a171dc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697633206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1697633206 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.571064443 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 26206887450 ps |
| CPU time | 5563.17 seconds |
| Started | Jul 22 08:30:42 PM PDT 24 |
| Finished | Jul 22 10:03:28 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-fe5f03e3-fe93-4554-9727-e28486f7e1bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571064443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.571064443 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.46274188 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 14214738066 ps |
| CPU time | 4269.34 seconds |
| Started | Jul 22 08:29:29 PM PDT 24 |
| Finished | Jul 22 09:40:40 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-155e3a3b-ddf2-42a7-b7e8-f5e6042d259f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46274188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutd own_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sh utdown_exception_c.46274188 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.1101997649 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 22584405192 ps |
| CPU time | 3744.55 seconds |
| Started | Jul 22 08:21:08 PM PDT 24 |
| Finished | Jul 22 09:23:34 PM PDT 24 |
| Peak memory | 611888 kb |
| Host | smart-17b6438e-231d-4361-87e7-c6417312a6a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101997649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1101997649 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3255250126 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 23383612480 ps |
| CPU time | 6102.18 seconds |
| Started | Jul 22 08:21:12 PM PDT 24 |
| Finished | Jul 22 10:02:56 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-1d1d995e-f7b9-415f-87bf-29852b512e59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3255250126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3255250126 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3568840556 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 23778054472 ps |
| CPU time | 5699.8 seconds |
| Started | Jul 22 08:17:08 PM PDT 24 |
| Finished | Jul 22 09:52:09 PM PDT 24 |
| Peak memory | 611484 kb |
| Host | smart-8b5ab8f3-86b0-489c-972a-17ac1a76e0a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3568840556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.3568840556 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1919495124 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 22595321720 ps |
| CPU time | 6166.69 seconds |
| Started | Jul 22 08:21:52 PM PDT 24 |
| Finished | Jul 22 10:04:40 PM PDT 24 |
| Peak memory | 611888 kb |
| Host | smart-c7b2d8e0-52f8-4811-9fac-168f3274e1a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1919495124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.1919495124 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3655531952 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 17487657300 ps |
| CPU time | 4995.3 seconds |
| Started | Jul 22 08:20:00 PM PDT 24 |
| Finished | Jul 22 09:43:17 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-97a67b74-a52b-440f-9971-2b5558df70fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3655531952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.3655531952 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.154162293 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 14562965363 ps |
| CPU time | 3838.54 seconds |
| Started | Jul 22 08:20:35 PM PDT 24 |
| Finished | Jul 22 09:24:35 PM PDT 24 |
| Peak memory | 611420 kb |
| Host | smart-c964e835-88f4-45a3-bcfe-074e3377c955 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154162293 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.154162293 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.786236756 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 14934200973 ps |
| CPU time | 3949.95 seconds |
| Started | Jul 22 08:22:22 PM PDT 24 |
| Finished | Jul 22 09:28:14 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-9bab98b1-ef69-49d7-82d4-973d58017c04 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786236756 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.786236756 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3751055462 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 14648289684 ps |
| CPU time | 3440.17 seconds |
| Started | Jul 22 08:22:08 PM PDT 24 |
| Finished | Jul 22 09:19:29 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-d240593f-491a-4401-8a05-fb321c75f352 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751055462 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3751055462 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1205342556 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 14189241334 ps |
| CPU time | 3427.61 seconds |
| Started | Jul 22 08:18:55 PM PDT 24 |
| Finished | Jul 22 09:16:04 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-ac28880e-6ab7-4160-ad77-a53daa6b0bfc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205342556 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1205342556 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1697873183 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 11612920114 ps |
| CPU time | 3162.41 seconds |
| Started | Jul 22 08:21:27 PM PDT 24 |
| Finished | Jul 22 09:14:11 PM PDT 24 |
| Peak memory | 612108 kb |
| Host | smart-a0fa17b8-82c8-4c33-a7d4-41bc1ca59ed3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697873183 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1697873183 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2571915966 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15238046289 ps |
| CPU time | 3506.7 seconds |
| Started | Jul 22 08:22:32 PM PDT 24 |
| Finished | Jul 22 09:20:59 PM PDT 24 |
| Peak memory | 611456 kb |
| Host | smart-ed5293fa-e87a-401f-b183-9cd9a4303e3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571915966 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2571915966 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1277159814 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 14559644052 ps |
| CPU time | 3593.77 seconds |
| Started | Jul 22 08:21:26 PM PDT 24 |
| Finished | Jul 22 09:21:21 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-1725e3dc-39ea-4cec-ab23-1885ce97338a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277159814 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1277159814 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.768596432 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 14389229570 ps |
| CPU time | 4260.4 seconds |
| Started | Jul 22 08:20:39 PM PDT 24 |
| Finished | Jul 22 09:31:41 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-67ad5a25-a283-470c-a86e-c29ddeef30b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768596432 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.768596432 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4026517361 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 14431233902 ps |
| CPU time | 4085.54 seconds |
| Started | Jul 22 08:22:16 PM PDT 24 |
| Finished | Jul 22 09:30:23 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-64724405-2271-41d3-9ea0-93bf3cc25ab7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026517361 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4026517361 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3231085957 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 10800848458 ps |
| CPU time | 3309.74 seconds |
| Started | Jul 22 08:21:47 PM PDT 24 |
| Finished | Jul 22 09:16:59 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-4cc5f9ac-6991-4e18-8d4f-19425cd823dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231085957 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3231085957 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.3157610395 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 15123476360 ps |
| CPU time | 4339.1 seconds |
| Started | Jul 22 08:29:28 PM PDT 24 |
| Finished | Jul 22 09:41:50 PM PDT 24 |
| Peak memory | 611788 kb |
| Host | smart-7abe419c-659a-4fcd-bc36-a76cf37ab196 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3157610395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3157610395 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2991654277 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 17297818776 ps |
| CPU time | 3490.68 seconds |
| Started | Jul 22 08:21:25 PM PDT 24 |
| Finished | Jul 22 09:19:37 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-bf1ac31d-ecbe-438a-84e7-65cec845b7ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991654277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2991654277 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.1583607615 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 4571296324 ps |
| CPU time | 712.68 seconds |
| Started | Jul 22 08:17:53 PM PDT 24 |
| Finished | Jul 22 08:29:47 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-aaff6d7d-c50b-445e-b8af-37a9f9d7ce71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583607615 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1583607615 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.3571135388 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4350781868 ps |
| CPU time | 241.85 seconds |
| Started | Jul 22 08:16:03 PM PDT 24 |
| Finished | Jul 22 08:20:06 PM PDT 24 |
| Peak memory | 619976 kb |
| Host | smart-7d42f23d-e66d-4784-b6d3-e114e362a671 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3571135388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3571135388 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2337701808 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 2545571161 ps |
| CPU time | 96.8 seconds |
| Started | Jul 22 08:14:35 PM PDT 24 |
| Finished | Jul 22 08:16:12 PM PDT 24 |
| Peak memory | 623440 kb |
| Host | smart-d4c59e75-7117-450b-81fc-1d37a68d6a62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337701808 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2337701808 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1171460072 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 12302964696 ps |
| CPU time | 1360.08 seconds |
| Started | Jul 22 08:18:31 PM PDT 24 |
| Finished | Jul 22 08:41:13 PM PDT 24 |
| Peak memory | 608344 kb |
| Host | smart-7a44982f-b53a-498f-9eb1-2e21d413aa91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171460072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1171460072 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.6847598 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 13423946911 ps |
| CPU time | 1920.22 seconds |
| Started | Jul 22 08:14:23 PM PDT 24 |
| Finished | Jul 22 08:46:25 PM PDT 24 |
| Peak memory | 608120 kb |
| Host | smart-dacdf5ff-1879-4fcc-ae7e-02667350d2a5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6847598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_mem _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.6847598 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1786772298 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4443766088 ps |
| CPU time | 536 seconds |
| Started | Jul 22 08:24:16 PM PDT 24 |
| Finished | Jul 22 08:33:13 PM PDT 24 |
| Peak memory | 620212 kb |
| Host | smart-4427632c-9bee-4aa7-b109-933d3a274c62 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 786772298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1786772298 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1124149620 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2556498026 ps |
| CPU time | 287.09 seconds |
| Started | Jul 22 08:17:16 PM PDT 24 |
| Finished | Jul 22 08:22:05 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-aca71530-025d-4817-a4f3-3e7caab039de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1124149620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1124149620 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2330743043 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 19529470124 ps |
| CPU time | 670.81 seconds |
| Started | Jul 22 08:30:50 PM PDT 24 |
| Finished | Jul 22 08:42:03 PM PDT 24 |
| Peak memory | 620024 kb |
| Host | smart-f225e241-2a50-40fa-9a94-8890058e25ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2330743043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2330743043 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2535498384 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 2609709800 ps |
| CPU time | 243.43 seconds |
| Started | Jul 22 08:19:47 PM PDT 24 |
| Finished | Jul 22 08:23:52 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-4357e51c-ea9b-4e95-bfce-4dacba16f7d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535498384 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2535498384 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2702804036 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 3202219991 ps |
| CPU time | 301.56 seconds |
| Started | Jul 22 08:18:04 PM PDT 24 |
| Finished | Jul 22 08:23:06 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-68901c74-ecfe-4178-a48e-a70d11680b51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702 804036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2702804036 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1406767185 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3029689853 ps |
| CPU time | 321.31 seconds |
| Started | Jul 22 08:23:14 PM PDT 24 |
| Finished | Jul 22 08:28:36 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-7eca50b5-1910-4b4e-81a4-cecfd27dfe83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406767185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.1406767185 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.4291116109 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 2403059380 ps |
| CPU time | 293.47 seconds |
| Started | Jul 22 08:19:53 PM PDT 24 |
| Finished | Jul 22 08:24:48 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-296f6ad9-1ba0-4564-b462-f8555b3758cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291116109 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.4291116109 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.2267046606 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 2849515256 ps |
| CPU time | 214.29 seconds |
| Started | Jul 22 08:20:11 PM PDT 24 |
| Finished | Jul 22 08:23:46 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-fb993829-3bcd-4791-b43a-67cbf73a3293 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267046606 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2267046606 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3387126490 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 3586493557 ps |
| CPU time | 259.54 seconds |
| Started | Jul 22 08:17:43 PM PDT 24 |
| Finished | Jul 22 08:22:03 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-70360056-bb67-4414-8800-a15c50395bef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387126490 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3387126490 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2171290192 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2767409466 ps |
| CPU time | 319.93 seconds |
| Started | Jul 22 08:24:30 PM PDT 24 |
| Finished | Jul 22 08:29:52 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-274c5113-20eb-4719-b316-1a23d2ffee3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171290192 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2171290192 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.210496777 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3045795935 ps |
| CPU time | 362.59 seconds |
| Started | Jul 22 08:22:56 PM PDT 24 |
| Finished | Jul 22 08:29:00 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-57103626-1df7-4287-859e-a11877baa1bd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=210496777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.210496777 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1418367765 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 5454322784 ps |
| CPU time | 435.79 seconds |
| Started | Jul 22 08:17:45 PM PDT 24 |
| Finished | Jul 22 08:25:01 PM PDT 24 |
| Peak memory | 619980 kb |
| Host | smart-fe04b8cd-fc21-4fcb-bdc0-61261227d0d2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1418367765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1418367765 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3136151247 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 7138342056 ps |
| CPU time | 1576.56 seconds |
| Started | Jul 22 08:21:13 PM PDT 24 |
| Finished | Jul 22 08:47:31 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-890617eb-1aed-49d5-ad63-eecec8a4ba24 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3136151247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3136151247 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2111413833 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 7495619026 ps |
| CPU time | 1518.2 seconds |
| Started | Jul 22 08:20:13 PM PDT 24 |
| Finished | Jul 22 08:45:32 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-5d9f1198-c5d8-4a89-b1cc-4222b82eb182 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111413833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.2111413833 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1843423046 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 13379864560 ps |
| CPU time | 1675.84 seconds |
| Started | Jul 22 08:28:32 PM PDT 24 |
| Finished | Jul 22 08:56:29 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-c6f93c7f-0337-48c0-8d3c-8983e0a94b7d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843423046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1843423046 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1391678956 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 8172714656 ps |
| CPU time | 1713.84 seconds |
| Started | Jul 22 08:20:44 PM PDT 24 |
| Finished | Jul 22 08:49:18 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-a07f1217-df64-4680-ab6d-718f8ee96827 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1391678956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1391678956 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3079405858 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4572273908 ps |
| CPU time | 555.94 seconds |
| Started | Jul 22 08:21:11 PM PDT 24 |
| Finished | Jul 22 08:30:28 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-61d55b25-0dbc-4aad-82ce-227cabbed68c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3079405858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3079405858 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.172065427 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 254631301096 ps |
| CPU time | 12419.9 seconds |
| Started | Jul 22 08:20:48 PM PDT 24 |
| Finished | Jul 22 11:47:50 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-537584cb-b974-4af4-a464-a0e66b4ed24f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172065427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.172065427 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.1106858161 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 3648659904 ps |
| CPU time | 378.88 seconds |
| Started | Jul 22 08:27:37 PM PDT 24 |
| Finished | Jul 22 08:33:59 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-856f4ce3-584b-4fcc-bec5-045d0f7abd79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106858161 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1106858161 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1491831150 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 6934934906 ps |
| CPU time | 317.1 seconds |
| Started | Jul 22 08:18:50 PM PDT 24 |
| Finished | Jul 22 08:24:08 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-6bf205ff-5238-46cd-a3c5-c4adeb92dd3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1491831150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1491831150 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3275189083 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3267703090 ps |
| CPU time | 347.45 seconds |
| Started | Jul 22 08:26:11 PM PDT 24 |
| Finished | Jul 22 08:32:00 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-0b05c17b-2ffd-45f1-9a48-7bfeada86695 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275189083 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3275189083 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2855179991 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 7710669580 ps |
| CPU time | 812.69 seconds |
| Started | Jul 22 08:18:52 PM PDT 24 |
| Finished | Jul 22 08:32:26 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-bcbaa277-229f-4ca7-9ef8-038072866dd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2855179991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2855179991 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4030786329 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 5232492824 ps |
| CPU time | 613.08 seconds |
| Started | Jul 22 08:25:33 PM PDT 24 |
| Finished | Jul 22 08:35:47 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-b2414f92-2344-43d5-a44f-52f5e6989ef5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4030786329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.4030786329 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2680878717 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 8821326538 ps |
| CPU time | 1090.24 seconds |
| Started | Jul 22 08:24:32 PM PDT 24 |
| Finished | Jul 22 08:42:43 PM PDT 24 |
| Peak memory | 617680 kb |
| Host | smart-958e1e2b-503a-42c1-87d2-2162559e48fe |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680878717 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2680878717 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2627325810 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 5635945123 ps |
| CPU time | 409.28 seconds |
| Started | Jul 22 08:21:55 PM PDT 24 |
| Finished | Jul 22 08:28:45 PM PDT 24 |
| Peak memory | 622952 kb |
| Host | smart-46ba77f5-f30b-45e6-881d-2267adfa7426 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2627325810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2627325810 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3231659995 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3388983164 ps |
| CPU time | 676.75 seconds |
| Started | Jul 22 08:21:40 PM PDT 24 |
| Finished | Jul 22 08:32:58 PM PDT 24 |
| Peak memory | 613416 kb |
| Host | smart-1bc69327-018f-49ff-b2c9-a208cbe482d1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231659995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3231659995 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2761534099 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 3858367948 ps |
| CPU time | 647.28 seconds |
| Started | Jul 22 08:22:09 PM PDT 24 |
| Finished | Jul 22 08:32:57 PM PDT 24 |
| Peak memory | 613416 kb |
| Host | smart-861e4ef8-49d7-47c0-9364-796257b82ecd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761534099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2761534099 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2928462066 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 4090423468 ps |
| CPU time | 748.53 seconds |
| Started | Jul 22 08:23:00 PM PDT 24 |
| Finished | Jul 22 08:35:29 PM PDT 24 |
| Peak memory | 613348 kb |
| Host | smart-1f7dd2f1-3cd8-4721-a81e-26124dc4baeb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928462066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2928462066 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2664788097 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 4288197344 ps |
| CPU time | 716.06 seconds |
| Started | Jul 22 08:20:34 PM PDT 24 |
| Finished | Jul 22 08:32:30 PM PDT 24 |
| Peak memory | 613308 kb |
| Host | smart-7c009502-8167-4922-86c6-c8b02422d4c9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664788097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2664788097 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3117933265 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 5095582070 ps |
| CPU time | 658.28 seconds |
| Started | Jul 22 08:20:50 PM PDT 24 |
| Finished | Jul 22 08:31:49 PM PDT 24 |
| Peak memory | 613276 kb |
| Host | smart-e14a1338-5e4b-4750-aa52-91b1aee1b494 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117933265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3117933265 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1268659474 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4593654924 ps |
| CPU time | 665.76 seconds |
| Started | Jul 22 08:21:06 PM PDT 24 |
| Finished | Jul 22 08:32:12 PM PDT 24 |
| Peak memory | 613376 kb |
| Host | smart-d5a08e7a-df09-4946-a648-a95ee7073476 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268659474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1268659474 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1825713735 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2377280991 ps |
| CPU time | 196.56 seconds |
| Started | Jul 22 08:31:16 PM PDT 24 |
| Finished | Jul 22 08:34:34 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-12a0e62d-30ef-48dc-bbc9-9ef70f77470d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825713735 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1825713735 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2876822136 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3878492438 ps |
| CPU time | 473.5 seconds |
| Started | Jul 22 08:21:43 PM PDT 24 |
| Finished | Jul 22 08:29:38 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-837043f3-26f8-4887-9c8d-b334ae7afbe9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876822136 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2876822136 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3286213996 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2802161631 ps |
| CPU time | 210.57 seconds |
| Started | Jul 22 08:24:30 PM PDT 24 |
| Finished | Jul 22 08:28:02 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-1000a286-e2c5-4f2d-b1ce-20d8f5a3701c |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286213996 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3286213996 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2522368642 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 4830049900 ps |
| CPU time | 568.24 seconds |
| Started | Jul 22 08:21:23 PM PDT 24 |
| Finished | Jul 22 08:30:52 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-f6506636-b9e2-43b6-95af-77666533304d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522368642 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2522368642 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3671692246 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 4876984828 ps |
| CPU time | 638.63 seconds |
| Started | Jul 22 08:20:49 PM PDT 24 |
| Finished | Jul 22 08:31:29 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-7f1c951e-96f0-4136-90a8-4470fbb47e40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671692246 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3671692246 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.406171318 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 5410246430 ps |
| CPU time | 607.43 seconds |
| Started | Jul 22 08:28:28 PM PDT 24 |
| Finished | Jul 22 08:38:36 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-b8950062-8667-4b8b-8601-42ba1e13d49e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406171318 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.406171318 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2600144509 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 4114518688 ps |
| CPU time | 429.03 seconds |
| Started | Jul 22 08:23:33 PM PDT 24 |
| Finished | Jul 22 08:30:44 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-52e21ac3-7bec-4d49-b1c1-78607f590233 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600144509 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2600144509 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3768645484 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 9494952486 ps |
| CPU time | 1281.69 seconds |
| Started | Jul 22 08:26:27 PM PDT 24 |
| Finished | Jul 22 08:47:50 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-f81863bd-7919-4cb3-b257-21ffdf558c61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768645484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3768645484 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2381041874 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3323669502 ps |
| CPU time | 560 seconds |
| Started | Jul 22 08:22:38 PM PDT 24 |
| Finished | Jul 22 08:31:59 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-fc5b077f-147e-4f0d-bb30-dd321a229866 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381041874 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2381041874 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.745558655 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4799101392 ps |
| CPU time | 573.25 seconds |
| Started | Jul 22 08:21:03 PM PDT 24 |
| Finished | Jul 22 08:30:38 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-8efa01b2-36af-464d-af66-68f0f0c0c103 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745558655 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.745558655 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2977521090 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 3436354988 ps |
| CPU time | 242.22 seconds |
| Started | Jul 22 08:26:43 PM PDT 24 |
| Finished | Jul 22 08:30:46 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-192592a4-f67a-443c-895b-55ca6b98e84f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977521090 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2977521090 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.893652504 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 21603805148 ps |
| CPU time | 5228.29 seconds |
| Started | Jul 22 08:21:10 PM PDT 24 |
| Finished | Jul 22 09:48:20 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-c4ec8aae-52a2-4210-98f1-485f32849da1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893652504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.893652504 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2286759170 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 13336770946 ps |
| CPU time | 2347.08 seconds |
| Started | Jul 22 08:23:57 PM PDT 24 |
| Finished | Jul 22 09:03:06 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-2560cd06-f4d8-4c2b-8f7d-2106481a05dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2286759170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2286759170 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3400007631 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 4620546754 ps |
| CPU time | 495.1 seconds |
| Started | Jul 22 08:33:07 PM PDT 24 |
| Finished | Jul 22 08:41:22 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-d8295b3f-41e1-4963-acb3-e8dbca9a63f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34000 07631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3400007631 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4180586027 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 2788346028 ps |
| CPU time | 236.09 seconds |
| Started | Jul 22 08:19:12 PM PDT 24 |
| Finished | Jul 22 08:23:08 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-9e56c5e2-5b34-4666-870b-c99b2fc74098 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180586027 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4180586027 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2617672044 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 5294144280 ps |
| CPU time | 653.04 seconds |
| Started | Jul 22 08:19:23 PM PDT 24 |
| Finished | Jul 22 08:30:17 PM PDT 24 |
| Peak memory | 611420 kb |
| Host | smart-66ed9723-83c8-4acb-a3c8-52fafefa5751 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617672044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.2617672044 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2168904806 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2888837950 ps |
| CPU time | 220.67 seconds |
| Started | Jul 22 08:25:13 PM PDT 24 |
| Finished | Jul 22 08:28:54 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-6af5007d-7e41-42be-b8f2-5d92450b79ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168904806 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2168904806 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.339257727 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 5897972628 ps |
| CPU time | 764.81 seconds |
| Started | Jul 22 08:25:48 PM PDT 24 |
| Finished | Jul 22 08:38:36 PM PDT 24 |
| Peak memory | 611460 kb |
| Host | smart-e2858f3e-5960-44c0-8694-89004b9bdaa4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=339257727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.339257727 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3108634919 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 5390675572 ps |
| CPU time | 1298.94 seconds |
| Started | Jul 22 08:21:35 PM PDT 24 |
| Finished | Jul 22 08:43:14 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-f8e8a600-0874-4ef6-854d-189981df1c2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108634919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3108634919 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2725751072 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2810291422 ps |
| CPU time | 538.13 seconds |
| Started | Jul 22 08:33:10 PM PDT 24 |
| Finished | Jul 22 08:42:09 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-654335bb-1edd-4bef-8bc3-a2fd40172f64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725751072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2725751072 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2920931676 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5522785021 ps |
| CPU time | 1084.12 seconds |
| Started | Jul 22 08:20:11 PM PDT 24 |
| Finished | Jul 22 08:38:17 PM PDT 24 |
| Peak memory | 611356 kb |
| Host | smart-c4e35dce-2117-4def-a4c4-77a33f9eb2b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920931676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.2920931676 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3938171495 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3768076800 ps |
| CPU time | 736.68 seconds |
| Started | Jul 22 08:29:01 PM PDT 24 |
| Finished | Jul 22 08:41:23 PM PDT 24 |
| Peak memory | 616836 kb |
| Host | smart-c2e02879-2528-44ab-84a9-92197bfbdf2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938171495 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3938171495 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1197346163 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 8321172664 ps |
| CPU time | 1791.6 seconds |
| Started | Jul 22 08:19:27 PM PDT 24 |
| Finished | Jul 22 08:49:19 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-587a9d61-6c4b-43d5-98ef-e88b1ad9f27b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197346163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1197346163 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.618805138 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 2467304728 ps |
| CPU time | 210.17 seconds |
| Started | Jul 22 08:21:28 PM PDT 24 |
| Finished | Jul 22 08:24:59 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-aa292b69-e9d3-4797-af13-3d6043422db0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61 8805138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.618805138 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2377155595 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 7349077848 ps |
| CPU time | 1708.25 seconds |
| Started | Jul 22 08:20:51 PM PDT 24 |
| Finished | Jul 22 08:49:20 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-a46d070a-2635-435e-9e07-7fa3b7d47fef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2377155595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2377155595 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1271956931 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 3182093272 ps |
| CPU time | 196.21 seconds |
| Started | Jul 22 08:18:11 PM PDT 24 |
| Finished | Jul 22 08:21:29 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-609d2dbf-f739-4c3d-9ba2-fced3969e822 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271956931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1271956931 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1303801052 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3918446772 ps |
| CPU time | 320.57 seconds |
| Started | Jul 22 08:26:38 PM PDT 24 |
| Finished | Jul 22 08:31:59 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-a16cbb25-4352-40a9-a996-0c432b172b3e |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1303801052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1303801052 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1093750953 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2629254080 ps |
| CPU time | 256.22 seconds |
| Started | Jul 22 08:18:48 PM PDT 24 |
| Finished | Jul 22 08:23:05 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-2f78de6d-00f7-4c59-a72d-015efccba1d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093750953 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1093750953 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.745621253 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2130543424 ps |
| CPU time | 154.51 seconds |
| Started | Jul 22 08:17:36 PM PDT 24 |
| Finished | Jul 22 08:20:11 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-4cf01df0-29f1-4ae3-b4ce-eedd34458890 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745621253 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.745621253 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.3682412043 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 2572171910 ps |
| CPU time | 196.72 seconds |
| Started | Jul 22 08:14:44 PM PDT 24 |
| Finished | Jul 22 08:18:02 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-3e7ca630-60b5-4d1e-ace6-628cfdf949f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682412043 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3682412043 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.612258742 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2060595032 ps |
| CPU time | 107.65 seconds |
| Started | Jul 22 08:14:01 PM PDT 24 |
| Finished | Jul 22 08:15:50 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-cdc1cd61-e2ae-47a9-96f1-4575d4ecd0e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612258742 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.612258742 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.1677144379 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 5042799690 ps |
| CPU time | 522.2 seconds |
| Started | Jul 22 08:25:26 PM PDT 24 |
| Finished | Jul 22 08:34:09 PM PDT 24 |
| Peak memory | 611520 kb |
| Host | smart-3ee0c9bc-8ee0-4b9d-9ee0-431cc3208436 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1677144379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1677144379 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4076895641 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5489204760 ps |
| CPU time | 1258.07 seconds |
| Started | Jul 22 08:16:36 PM PDT 24 |
| Finished | Jul 22 08:37:35 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-6f1abbe6-d295-4b88-a787-cdf3d434fa6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076895641 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.4076895641 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1111664346 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 5329943246 ps |
| CPU time | 1005.63 seconds |
| Started | Jul 22 08:16:37 PM PDT 24 |
| Finished | Jul 22 08:33:25 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-9cf21513-bcc9-4586-a7aa-5c6cf846df89 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111664346 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1111664346 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1785860167 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 7299288589 ps |
| CPU time | 1469.91 seconds |
| Started | Jul 22 08:24:05 PM PDT 24 |
| Finished | Jul 22 08:48:37 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-3e3718eb-2b9f-46fd-b57a-a9d24dec3e85 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785860167 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1785860167 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1373597096 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 5775786572 ps |
| CPU time | 1117.86 seconds |
| Started | Jul 22 08:24:01 PM PDT 24 |
| Finished | Jul 22 08:42:41 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-278d9281-532d-4f5b-b0d1-d05462a2f8d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373597096 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1373597096 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.936232828 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 3295246616 ps |
| CPU time | 367.39 seconds |
| Started | Jul 22 08:19:15 PM PDT 24 |
| Finished | Jul 22 08:25:24 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-9f35d836-a7b4-447f-8b22-247dbc14f4ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936232828 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.936232828 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2561870511 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3785589977 ps |
| CPU time | 530.22 seconds |
| Started | Jul 22 08:34:07 PM PDT 24 |
| Finished | Jul 22 08:42:59 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-9d2411fe-c2a4-4ae0-8630-fa29441f41a0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 61870511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2561870511 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2553004458 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 5579914876 ps |
| CPU time | 1351.19 seconds |
| Started | Jul 22 08:26:23 PM PDT 24 |
| Finished | Jul 22 08:48:55 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-9e9ae30e-fb08-493c-9093-70dfa58c5e60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553004458 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2553004458 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1229619737 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4102274216 ps |
| CPU time | 782.21 seconds |
| Started | Jul 22 08:19:26 PM PDT 24 |
| Finished | Jul 22 08:32:30 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-b4a2af38-5360-40a1-94a7-593f20997f64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229619737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1229619737 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2822848314 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4318019661 ps |
| CPU time | 690.37 seconds |
| Started | Jul 22 08:21:01 PM PDT 24 |
| Finished | Jul 22 08:32:32 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-755ce886-ea9a-444e-9e46-7e93c8f3481d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2822848314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2822848314 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.803956946 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 5418239675 ps |
| CPU time | 725.62 seconds |
| Started | Jul 22 08:22:25 PM PDT 24 |
| Finished | Jul 22 08:34:32 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-c15adfde-f0ad-452b-9d34-a83c7f9d3134 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=803956946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.803956946 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3612541395 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 2657093944 ps |
| CPU time | 306.81 seconds |
| Started | Jul 22 08:22:35 PM PDT 24 |
| Finished | Jul 22 08:27:42 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-1e3a07cb-022c-4319-be7a-eb8dbf97c1d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612541 395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.3612541395 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1002981140 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 22258896423 ps |
| CPU time | 2147.08 seconds |
| Started | Jul 22 08:13:45 PM PDT 24 |
| Finished | Jul 22 08:49:34 PM PDT 24 |
| Peak memory | 616900 kb |
| Host | smart-f5ec8440-a2f1-4f53-b6b0-8a0a50c2b3e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002981140 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1002981140 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3850346292 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 23849666831 ps |
| CPU time | 1875.35 seconds |
| Started | Jul 22 08:22:09 PM PDT 24 |
| Finished | Jul 22 08:53:26 PM PDT 24 |
| Peak memory | 612936 kb |
| Host | smart-0a4fa599-1084-46b8-9bea-64733c1d7995 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3850346292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3850346292 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.640964305 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2574057108 ps |
| CPU time | 175.52 seconds |
| Started | Jul 22 08:30:25 PM PDT 24 |
| Finished | Jul 22 08:33:21 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-be90b7a3-d4fe-4c79-a5c3-181486743f2f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=640964305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.640964305 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.2368933812 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 3232933983 ps |
| CPU time | 273.94 seconds |
| Started | Jul 22 08:26:17 PM PDT 24 |
| Finished | Jul 22 08:30:51 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-9925c0c5-1712-4d71-9106-4a1945d984ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368933812 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.2368933812 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.1262677877 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2573565992 ps |
| CPU time | 307.61 seconds |
| Started | Jul 22 08:20:22 PM PDT 24 |
| Finished | Jul 22 08:25:30 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-25f12ff0-f321-444a-9c6e-42747ec0d806 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262677877 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.1262677877 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2886967130 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 2917296884 ps |
| CPU time | 266.28 seconds |
| Started | Jul 22 08:20:18 PM PDT 24 |
| Finished | Jul 22 08:24:46 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-b3fe9a00-5d89-4485-8d20-023f03c02d23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886967130 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.2886967130 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.472330807 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3819790873 ps |
| CPU time | 340.81 seconds |
| Started | Jul 22 08:20:14 PM PDT 24 |
| Finished | Jul 22 08:25:56 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-42b557f0-9ef3-4267-9235-1f906558e616 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472330807 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.472330807 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1150288617 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2890637163 ps |
| CPU time | 296.34 seconds |
| Started | Jul 22 08:26:13 PM PDT 24 |
| Finished | Jul 22 08:31:10 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-f203d672-5a07-4675-8f52-810a9ba53980 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150288617 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1150288617 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.11485667 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8257736680 ps |
| CPU time | 1591.98 seconds |
| Started | Jul 22 08:32:47 PM PDT 24 |
| Finished | Jul 22 08:59:20 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-59c7c55e-e255-420c-bb86-4076d82ac35a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11485667 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_multistream.11485667 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2597192755 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2715398784 ps |
| CPU time | 262.78 seconds |
| Started | Jul 22 08:19:14 PM PDT 24 |
| Finished | Jul 22 08:23:38 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-4e3b5421-c020-4358-a301-c9c9db6cc9f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597192755 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2597192755 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.574042837 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3646507764 ps |
| CPU time | 434.17 seconds |
| Started | Jul 22 08:27:38 PM PDT 24 |
| Finished | Jul 22 08:34:53 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-69c06e35-bc02-4ab8-8a2a-46b9b6bc91d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574042837 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.574042837 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2116866899 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4057755196 ps |
| CPU time | 525.24 seconds |
| Started | Jul 22 08:21:13 PM PDT 24 |
| Finished | Jul 22 08:30:00 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-7cd1f7b7-a62c-40e0-8570-738e87287df0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116866899 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2116866899 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.800223950 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4249951520 ps |
| CPU time | 690.14 seconds |
| Started | Jul 22 08:28:29 PM PDT 24 |
| Finished | Jul 22 08:40:00 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-e8a4f82e-8509-4fcf-b852-cba619a4116f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800223950 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.800223950 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3287781347 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5884489496 ps |
| CPU time | 670.93 seconds |
| Started | Jul 22 08:17:10 PM PDT 24 |
| Finished | Jul 22 08:28:22 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-8af87e86-6b12-4d12-9855-cb7e1133c69e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287781347 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3287781347 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1967718608 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 63326333137 ps |
| CPU time | 11316 seconds |
| Started | Jul 22 08:17:12 PM PDT 24 |
| Finished | Jul 22 11:25:50 PM PDT 24 |
| Peak memory | 625252 kb |
| Host | smart-0f101b4c-f4b4-4e3f-ad5d-d739112ee1c6 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1967718608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1967718608 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1131213553 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 11361739370 ps |
| CPU time | 2243.2 seconds |
| Started | Jul 22 08:18:50 PM PDT 24 |
| Finished | Jul 22 08:56:14 PM PDT 24 |
| Peak memory | 617980 kb |
| Host | smart-61760479-806f-41d0-8671-41f206f0c716 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131 213553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1131213553 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2890214385 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 10147723755 ps |
| CPU time | 2354.31 seconds |
| Started | Jul 22 08:19:14 PM PDT 24 |
| Finished | Jul 22 08:58:30 PM PDT 24 |
| Peak memory | 618076 kb |
| Host | smart-0eb150a8-9029-4d22-81c5-e038968df8d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2890214385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2890214385 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3524601418 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 9980050261 ps |
| CPU time | 1658.08 seconds |
| Started | Jul 22 08:24:56 PM PDT 24 |
| Finished | Jul 22 08:52:36 PM PDT 24 |
| Peak memory | 617056 kb |
| Host | smart-466582bb-9bf5-4c3f-b8fc-86eccacbe24a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3524601418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3524601418 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2891930809 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 9975959856 ps |
| CPU time | 1829.42 seconds |
| Started | Jul 22 08:27:17 PM PDT 24 |
| Finished | Jul 22 08:57:47 PM PDT 24 |
| Peak memory | 618084 kb |
| Host | smart-33857b0c-f796-4d9b-a331-cfb1ec852db7 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2891930809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2891930809 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3499981634 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 6928454440 ps |
| CPU time | 1274.41 seconds |
| Started | Jul 22 08:22:04 PM PDT 24 |
| Finished | Jul 22 08:43:20 PM PDT 24 |
| Peak memory | 611452 kb |
| Host | smart-4b2f7b15-6d0d-4500-bd7e-1988e47253de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349998 1634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.3499981634 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3213599651 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 9262966648 ps |
| CPU time | 2283.62 seconds |
| Started | Jul 22 08:23:43 PM PDT 24 |
| Finished | Jul 22 09:01:48 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-4d163f61-a42a-48bb-988d-e9eb6ddb308d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32135 99651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3213599651 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2991502991 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 12843119490 ps |
| CPU time | 3308.79 seconds |
| Started | Jul 22 08:20:47 PM PDT 24 |
| Finished | Jul 22 09:15:57 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-7012d23f-a8f0-41f5-8114-ede9a66b675c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915 02991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2991502991 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.3007657206 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3201425748 ps |
| CPU time | 182.23 seconds |
| Started | Jul 22 08:20:12 PM PDT 24 |
| Finished | Jul 22 08:23:15 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-fca7f2f3-31c0-44c7-9f9a-16e0f302cc74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007657206 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3007657206 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.1495563312 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3051895100 ps |
| CPU time | 318.29 seconds |
| Started | Jul 22 08:24:26 PM PDT 24 |
| Finished | Jul 22 08:29:48 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-b405e37e-c08b-45b5-bbf9-1a8362fcf9e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495563312 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1495563312 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.2961994807 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3399897314 ps |
| CPU time | 307.12 seconds |
| Started | Jul 22 08:20:16 PM PDT 24 |
| Finished | Jul 22 08:25:24 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-6034fc71-fae5-4c5e-95bd-75e5f12bce86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961994807 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.2961994807 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.349393411 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2940619056 ps |
| CPU time | 198.92 seconds |
| Started | Jul 22 08:24:10 PM PDT 24 |
| Finished | Jul 22 08:27:29 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-92562902-ac36-41d2-b7c3-f525bfcbbaa0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349393411 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.349393411 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1957387866 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 2861517362 ps |
| CPU time | 266.34 seconds |
| Started | Jul 22 08:24:44 PM PDT 24 |
| Finished | Jul 22 08:29:11 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-1cea2f80-f837-4a32-a45b-db7145d33c83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957387866 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1957387866 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.237932560 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3253495215 ps |
| CPU time | 328.91 seconds |
| Started | Jul 22 08:23:21 PM PDT 24 |
| Finished | Jul 22 08:28:50 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-3dc5cec7-579f-4923-b680-8fe23771b719 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237932560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.237932560 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3364776959 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3045021112 ps |
| CPU time | 288.06 seconds |
| Started | Jul 22 08:22:56 PM PDT 24 |
| Finished | Jul 22 08:27:45 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-1aa37157-347d-48c6-9949-6e1dfde93600 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33647769 59 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3364776959 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.1231292047 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 3177868020 ps |
| CPU time | 313.21 seconds |
| Started | Jul 22 08:27:17 PM PDT 24 |
| Finished | Jul 22 08:32:32 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-da079559-25d3-45e7-a0f4-fefb58981240 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231292047 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.1231292047 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4173115319 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 3239447482 ps |
| CPU time | 287.98 seconds |
| Started | Jul 22 08:17:26 PM PDT 24 |
| Finished | Jul 22 08:22:14 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-3ffe999c-2232-49da-9c6f-214febc228be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173115319 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.4173115319 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.766334089 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4724775392 ps |
| CPU time | 426.73 seconds |
| Started | Jul 22 08:21:19 PM PDT 24 |
| Finished | Jul 22 08:28:27 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-5dd8292d-e2ea-4466-8607-1e51d31e75bc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=766334089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.766334089 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.951641588 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 6210838476 ps |
| CPU time | 487.96 seconds |
| Started | Jul 22 08:30:16 PM PDT 24 |
| Finished | Jul 22 08:38:25 PM PDT 24 |
| Peak memory | 622948 kb |
| Host | smart-bf6f96ab-5194-4d4d-b068-3d63b1156529 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951641588 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.951641588 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.19872625 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1946119995 ps |
| CPU time | 114.15 seconds |
| Started | Jul 22 08:22:22 PM PDT 24 |
| Finished | Jul 22 08:24:17 PM PDT 24 |
| Peak memory | 617460 kb |
| Host | smart-f130cc78-a2d2-4a47-aaa7-b04e48e46411 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=19872625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.19872625 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1005432179 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 2379856438 ps |
| CPU time | 103.89 seconds |
| Started | Jul 22 08:18:57 PM PDT 24 |
| Finished | Jul 22 08:20:42 PM PDT 24 |
| Peak memory | 617268 kb |
| Host | smart-0f7b3681-f30c-4cae-8634-906a6860edcb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005432179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1005432179 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1132782576 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 50126570744 ps |
| CPU time | 6139.35 seconds |
| Started | Jul 22 08:18:20 PM PDT 24 |
| Finished | Jul 22 10:00:41 PM PDT 24 |
| Peak memory | 621084 kb |
| Host | smart-6c917288-0433-4824-a035-217356dae5da |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132782576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1132782576 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3641405108 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 10627971378 ps |
| CPU time | 964.92 seconds |
| Started | Jul 22 08:19:13 PM PDT 24 |
| Finished | Jul 22 08:35:20 PM PDT 24 |
| Peak memory | 620376 kb |
| Host | smart-b19ca1c5-f3ae-4c97-9b6c-faafe25ee1da |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641405108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3641405108 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1537654545 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 46627060119 ps |
| CPU time | 5078.73 seconds |
| Started | Jul 22 08:16:48 PM PDT 24 |
| Finished | Jul 22 09:41:27 PM PDT 24 |
| Peak memory | 620784 kb |
| Host | smart-24b8b22a-9110-4fc7-b7f2-f3923291ad3c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537654545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1537654545 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.59785567 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 25772494173 ps |
| CPU time | 1949.31 seconds |
| Started | Jul 22 08:30:25 PM PDT 24 |
| Finished | Jul 22 09:02:57 PM PDT 24 |
| Peak memory | 620304 kb |
| Host | smart-bee58179-e82e-473c-a7aa-5206850eb3b8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=59785567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.59785567 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4245311637 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 16999401330 ps |
| CPU time | 3818.23 seconds |
| Started | Jul 22 08:18:55 PM PDT 24 |
| Finished | Jul 22 09:22:35 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-4541a771-1af3-48f0-b341-a39fa4887823 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4245311637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.4245311637 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.458338213 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 18874350100 ps |
| CPU time | 3427.46 seconds |
| Started | Jul 22 08:18:40 PM PDT 24 |
| Finished | Jul 22 09:15:49 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-d9937417-9d03-46b8-8fc0-b55e7d88f3ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=458338213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.458338213 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3622404925 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 24775213095 ps |
| CPU time | 3630.9 seconds |
| Started | Jul 22 08:25:58 PM PDT 24 |
| Finished | Jul 22 09:26:30 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-7f3980fb-b6ba-4d10-a1cb-460207b10182 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622404925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3622404925 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3641069053 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3676606600 ps |
| CPU time | 642.19 seconds |
| Started | Jul 22 08:18:36 PM PDT 24 |
| Finished | Jul 22 08:29:19 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-922acb12-c429-4d97-9b60-01a5f881c31c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641069053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3641069053 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.693258493 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5850190474 ps |
| CPU time | 933.49 seconds |
| Started | Jul 22 08:25:27 PM PDT 24 |
| Finished | Jul 22 08:41:02 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-20404ce5-3aef-4fa0-aed4-5a96b4adc68c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=693258493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.693258493 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.3117750397 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 9575243102 ps |
| CPU time | 2691.35 seconds |
| Started | Jul 22 08:26:06 PM PDT 24 |
| Finished | Jul 22 09:10:59 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-0c3e4da1-bf4f-45e6-a391-ba12aa691ede |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117750397 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.3117750397 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3790872046 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2569601838 ps |
| CPU time | 258.28 seconds |
| Started | Jul 22 08:30:35 PM PDT 24 |
| Finished | Jul 22 08:34:55 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-ee2d7d50-c4bd-49af-981a-4cfeeaad8663 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790872046 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3790872046 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3266455361 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 7202514984 ps |
| CPU time | 1396.94 seconds |
| Started | Jul 22 08:15:57 PM PDT 24 |
| Finished | Jul 22 08:39:15 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-856ce577-7142-4ccb-9e0a-749b557fa06f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3266455361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3266455361 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3952958481 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9640073992 ps |
| CPU time | 1438.14 seconds |
| Started | Jul 22 08:21:49 PM PDT 24 |
| Finished | Jul 22 08:45:48 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-833bcb91-704c-4fcf-809d-9441fa133c6a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3952958481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3952958481 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.613264950 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 7856101080 ps |
| CPU time | 1341.29 seconds |
| Started | Jul 22 08:18:46 PM PDT 24 |
| Finished | Jul 22 08:41:09 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-dda0589f-5d94-426a-a76b-214d3bbd1e36 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=613264950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.613264950 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.211738055 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 4315160580 ps |
| CPU time | 822.81 seconds |
| Started | Jul 22 08:17:30 PM PDT 24 |
| Finished | Jul 22 08:31:13 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-c5519851-ae7d-4388-97e7-95c3378ba79d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=211738055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.211738055 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2941844942 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2504635944 ps |
| CPU time | 270 seconds |
| Started | Jul 22 08:26:11 PM PDT 24 |
| Finished | Jul 22 08:30:41 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-5cc702f4-007b-4768-bd4d-2559c345ebe5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941844942 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2941844942 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2463608071 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2835243912 ps |
| CPU time | 264.73 seconds |
| Started | Jul 22 08:18:13 PM PDT 24 |
| Finished | Jul 22 08:22:39 PM PDT 24 |
| Peak memory | 611840 kb |
| Host | smart-967131c4-e7f1-478b-944e-3ce874a0b142 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463608071 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2463608071 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.853400250 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3298969614 ps |
| CPU time | 319.39 seconds |
| Started | Jul 22 08:22:21 PM PDT 24 |
| Finished | Jul 22 08:27:41 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-14e5b958-2105-4443-a5d3-db2e7052c182 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853400250 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_plic_sw_irq.853400250 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.1937692969 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 4471237160 ps |
| CPU time | 785.65 seconds |
| Started | Jul 22 08:25:19 PM PDT 24 |
| Finished | Jul 22 08:38:26 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-b8582011-fdc7-4fae-a0ba-62ec119ba688 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937692969 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1937692969 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.506797514 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4719353174 ps |
| CPU time | 489.08 seconds |
| Started | Jul 22 08:24:23 PM PDT 24 |
| Finished | Jul 22 08:32:33 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-334e2b63-dca4-4d61-b81b-90c7fb1b74cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506797514 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.506797514 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3464828952 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 13289512292 ps |
| CPU time | 1595.54 seconds |
| Started | Jul 22 08:16:13 PM PDT 24 |
| Finished | Jul 22 08:42:50 PM PDT 24 |
| Peak memory | 611832 kb |
| Host | smart-b4d1ae26-217a-4602-8ed7-3c2721090d31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464 828952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3464828952 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2657242987 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 20966200600 ps |
| CPU time | 1960.55 seconds |
| Started | Jul 22 08:20:49 PM PDT 24 |
| Finished | Jul 22 08:53:31 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-c3f5a231-3f8a-482e-8424-e6ab69ca038e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265 7242987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.2657242987 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1309280504 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 13955599638 ps |
| CPU time | 1857.89 seconds |
| Started | Jul 22 08:17:02 PM PDT 24 |
| Finished | Jul 22 08:48:00 PM PDT 24 |
| Peak memory | 611860 kb |
| Host | smart-9de6e70d-4ed8-4239-a187-a8d13f72ebcc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1309280504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1309280504 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1947471122 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 25940774872 ps |
| CPU time | 1683.22 seconds |
| Started | Jul 22 08:22:28 PM PDT 24 |
| Finished | Jul 22 08:50:32 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-f065d415-3dd6-45a1-8eef-f3f6dc7feae2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1947471122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1947471122 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.653220196 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 7102217340 ps |
| CPU time | 731.18 seconds |
| Started | Jul 22 08:17:42 PM PDT 24 |
| Finished | Jul 22 08:29:54 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-50b4aee9-5789-44d8-bf46-c7dd7906430e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653220196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.653220196 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2654208359 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 6239153996 ps |
| CPU time | 479.71 seconds |
| Started | Jul 22 08:20:55 PM PDT 24 |
| Finished | Jul 22 08:28:56 PM PDT 24 |
| Peak memory | 617416 kb |
| Host | smart-9307ef7f-4cc9-4ee6-ac2c-5e6eb4910178 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2654208359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2654208359 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3409045998 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 6312935730 ps |
| CPU time | 501.31 seconds |
| Started | Jul 22 08:23:12 PM PDT 24 |
| Finished | Jul 22 08:31:34 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-5f597497-3401-48a3-b8dd-bf70469476a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409045998 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3409045998 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3984095165 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3826840120 ps |
| CPU time | 535.72 seconds |
| Started | Jul 22 08:23:50 PM PDT 24 |
| Finished | Jul 22 08:32:47 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-7a1bbe89-9a90-442a-b7f0-b36b4b869c8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984095165 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3984095165 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.154987551 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4334308104 ps |
| CPU time | 421.17 seconds |
| Started | Jul 22 08:17:03 PM PDT 24 |
| Finished | Jul 22 08:24:05 PM PDT 24 |
| Peak memory | 617924 kb |
| Host | smart-5bda76bd-3ca5-4b01-9524-97ed0cebb18d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=154987551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.154987551 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3215498654 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 10761371082 ps |
| CPU time | 1502.47 seconds |
| Started | Jul 22 08:18:43 PM PDT 24 |
| Finished | Jul 22 08:43:47 PM PDT 24 |
| Peak memory | 611920 kb |
| Host | smart-c1fe8ae8-2c6c-4ff0-8af1-4aaf04b2a3d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215498654 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3215498654 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.742448043 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 8058812632 ps |
| CPU time | 591.06 seconds |
| Started | Jul 22 08:31:43 PM PDT 24 |
| Finished | Jul 22 08:41:35 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-0b106f1b-41c6-4143-9b97-078d3d93862d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742448043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.742448043 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.388349455 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 5994109053 ps |
| CPU time | 543.91 seconds |
| Started | Jul 22 08:17:55 PM PDT 24 |
| Finished | Jul 22 08:26:59 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-09679735-0714-4b27-9b44-10f3de5b044a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388349455 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.388349455 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4056437064 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 19626332185 ps |
| CPU time | 2091.09 seconds |
| Started | Jul 22 08:23:43 PM PDT 24 |
| Finished | Jul 22 08:58:35 PM PDT 24 |
| Peak memory | 611656 kb |
| Host | smart-4090cceb-d656-4dd1-9186-7eca7653d1f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4056437064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4056437064 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3855753375 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 21483977592 ps |
| CPU time | 1244.36 seconds |
| Started | Jul 22 08:23:45 PM PDT 24 |
| Finished | Jul 22 08:44:30 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-b259dde3-abc1-4e4c-8392-234b955a480f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3855753375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3855753375 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.141582152 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 30935089950 ps |
| CPU time | 2959.86 seconds |
| Started | Jul 22 08:18:08 PM PDT 24 |
| Finished | Jul 22 09:07:28 PM PDT 24 |
| Peak memory | 612000 kb |
| Host | smart-914f5ae3-00fb-4ca2-ac23-514c51d86554 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141582152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.141582152 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1844890292 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 6121173668 ps |
| CPU time | 522.51 seconds |
| Started | Jul 22 08:25:32 PM PDT 24 |
| Finished | Jul 22 08:34:17 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-ef38a022-89e7-40ec-8622-383fb77d09d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1844890292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1844890292 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3167316230 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2437465496 ps |
| CPU time | 231.62 seconds |
| Started | Jul 22 08:22:41 PM PDT 24 |
| Finished | Jul 22 08:26:35 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-db9ffb25-84a4-4a7d-9927-c4ba62a01f20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167316230 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3167316230 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3546842020 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 5459429894 ps |
| CPU time | 477.44 seconds |
| Started | Jul 22 08:21:26 PM PDT 24 |
| Finished | Jul 22 08:29:24 PM PDT 24 |
| Peak memory | 617056 kb |
| Host | smart-4c241770-b6e8-44b6-9d05-d85454c465dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3546842020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3546842020 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1110154939 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5993463944 ps |
| CPU time | 437.33 seconds |
| Started | Jul 22 08:24:55 PM PDT 24 |
| Finished | Jul 22 08:32:14 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-237c3081-4b0a-4cf7-b831-ece041c07367 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101549 39 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1110154939 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2303254286 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 6382869528 ps |
| CPU time | 601.9 seconds |
| Started | Jul 22 08:22:14 PM PDT 24 |
| Finished | Jul 22 08:32:16 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-d8a56c1c-9bf4-4244-b250-0bb23a77917a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2303254286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2303254286 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3947619607 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 5900537122 ps |
| CPU time | 310.34 seconds |
| Started | Jul 22 08:27:46 PM PDT 24 |
| Finished | Jul 22 08:32:57 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-deef1d7d-cc77-4a27-8814-f936713508ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947619607 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.3947619607 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3189863194 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 6296268360 ps |
| CPU time | 1143.44 seconds |
| Started | Jul 22 08:23:24 PM PDT 24 |
| Finished | Jul 22 08:42:28 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-2896c8ba-4712-4b59-8d2d-6e90392c1b52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189863194 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3189863194 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2973382192 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 3791601400 ps |
| CPU time | 489.17 seconds |
| Started | Jul 22 08:20:08 PM PDT 24 |
| Finished | Jul 22 08:28:19 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-846b886b-aecc-4a36-bb65-fedb416adf8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973382192 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2973382192 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3216573560 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 6718962052 ps |
| CPU time | 465.79 seconds |
| Started | Jul 22 08:41:54 PM PDT 24 |
| Finished | Jul 22 08:49:41 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-3a964461-b915-4108-b676-5f22eab6de20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216573560 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3216573560 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1444387060 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 4962674328 ps |
| CPU time | 571.11 seconds |
| Started | Jul 22 08:22:47 PM PDT 24 |
| Finished | Jul 22 08:32:20 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-5f9da56d-4720-4f82-87d9-f0fb0be9d42e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144 4387060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1444387060 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.299542534 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 9126391625 ps |
| CPU time | 449.51 seconds |
| Started | Jul 22 08:24:14 PM PDT 24 |
| Finished | Jul 22 08:31:45 PM PDT 24 |
| Peak memory | 624240 kb |
| Host | smart-6af87829-6598-4888-9d67-b88057b863b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299542534 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.299542534 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.960198585 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4799443480 ps |
| CPU time | 520.72 seconds |
| Started | Jul 22 08:16:41 PM PDT 24 |
| Finished | Jul 22 08:25:23 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-ef6beb25-f3e1-487e-8db6-3d93ff4ce7f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960198585 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.960198585 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.68297089 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4897047008 ps |
| CPU time | 749.84 seconds |
| Started | Jul 22 08:20:25 PM PDT 24 |
| Finished | Jul 22 08:32:57 PM PDT 24 |
| Peak memory | 642008 kb |
| Host | smart-dc3691c6-d572-4bc3-b11c-6fb03618777c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 68297089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.68297089 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1041626349 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 2361102696 ps |
| CPU time | 257.77 seconds |
| Started | Jul 22 08:25:35 PM PDT 24 |
| Finished | Jul 22 08:29:54 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-7ce972dd-4067-4323-b65c-4519b6ad2a3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041626349 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1041626349 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3270994359 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 4529141432 ps |
| CPU time | 325.27 seconds |
| Started | Jul 22 08:30:30 PM PDT 24 |
| Finished | Jul 22 08:35:57 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-796ffc04-66da-4b8d-910d-7709837f5966 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270994359 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3270994359 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.401542820 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2526579408 ps |
| CPU time | 226.74 seconds |
| Started | Jul 22 08:33:06 PM PDT 24 |
| Finished | Jul 22 08:36:53 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-6fc3b015-7db9-498a-9685-389a7a88cdf8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401542820 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.401542820 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1768582707 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2613657510 ps |
| CPU time | 351.67 seconds |
| Started | Jul 22 08:23:00 PM PDT 24 |
| Finished | Jul 22 08:28:52 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-19ab7f67-1f36-4b78-bdd9-daa341feff7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1768582707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1768582707 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1863886449 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2821266372 ps |
| CPU time | 302.27 seconds |
| Started | Jul 22 08:35:58 PM PDT 24 |
| Finished | Jul 22 08:41:02 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-ff83d3c1-0a7a-4753-bf4c-eb4bf4d55c9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863886449 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1863886449 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.954173930 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 5010662044 ps |
| CPU time | 786.78 seconds |
| Started | Jul 22 08:29:54 PM PDT 24 |
| Finished | Jul 22 08:43:02 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-7a12d524-61e7-4af8-8efe-680a0ff88973 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95417 3930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.954173930 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.546640985 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 4954498968 ps |
| CPU time | 953.25 seconds |
| Started | Jul 22 08:32:38 PM PDT 24 |
| Finished | Jul 22 08:48:33 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-fc6b5d9b-3b67-4db1-8e98-08b5a0d8a365 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=546640985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.546640985 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3436711782 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4455883424 ps |
| CPU time | 533.92 seconds |
| Started | Jul 22 08:22:17 PM PDT 24 |
| Finished | Jul 22 08:31:12 PM PDT 24 |
| Peak memory | 621888 kb |
| Host | smart-6a8e7753-8c47-49be-8646-eb303fdb6288 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436711782 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3436711782 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1806079046 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 6780549386 ps |
| CPU time | 509.84 seconds |
| Started | Jul 22 08:23:07 PM PDT 24 |
| Finished | Jul 22 08:31:38 PM PDT 24 |
| Peak memory | 620864 kb |
| Host | smart-c0b6aebb-b811-4d10-b8fd-a9387630054c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806079046 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.1806079046 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1533434107 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5036940756 ps |
| CPU time | 419.81 seconds |
| Started | Jul 22 08:24:33 PM PDT 24 |
| Finished | Jul 22 08:31:33 PM PDT 24 |
| Peak memory | 620896 kb |
| Host | smart-4f3227f9-35fe-4706-a1a4-ff39b5140fed |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153343 4107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1533434107 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1710917726 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 2295351314 ps |
| CPU time | 192.83 seconds |
| Started | Jul 22 08:25:09 PM PDT 24 |
| Finished | Jul 22 08:28:23 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-a2347430-e637-4a80-9981-1d84330774b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710917726 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.1710917726 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.145412806 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2499810760 ps |
| CPU time | 252.29 seconds |
| Started | Jul 22 08:22:34 PM PDT 24 |
| Finished | Jul 22 08:26:47 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-9658274a-8510-49d5-847d-2d7d4cf70872 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145412806 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_irq.145412806 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3985510373 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 3022053496 ps |
| CPU time | 287.38 seconds |
| Started | Jul 22 08:25:57 PM PDT 24 |
| Finished | Jul 22 08:30:46 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-5c26aff4-8930-46bc-93f0-a99b200b198c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985510373 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.3985510373 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3531043024 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2782184390 ps |
| CPU time | 246.8 seconds |
| Started | Jul 22 08:20:10 PM PDT 24 |
| Finished | Jul 22 08:24:19 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-f899b10c-d4e0-4cf1-9fd6-b23157d2a161 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531043 024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3531043024 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3317060546 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3182791064 ps |
| CPU time | 327.38 seconds |
| Started | Jul 22 08:18:15 PM PDT 24 |
| Finished | Jul 22 08:23:43 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-431662be-785a-4e25-89b6-436baeaef915 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317060546 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3317060546 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1500405070 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 7630568760 ps |
| CPU time | 1265.29 seconds |
| Started | Jul 22 08:17:14 PM PDT 24 |
| Finished | Jul 22 08:38:21 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-db6a9c3c-6576-4f17-aaa2-7a12ded95362 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500405070 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1500405070 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.439537025 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 7987601372 ps |
| CPU time | 899.93 seconds |
| Started | Jul 22 08:29:28 PM PDT 24 |
| Finished | Jul 22 08:44:29 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-3b45190b-fe0c-413e-a356-ffa85e907f1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439537025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.439537025 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2672538475 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 7422056568 ps |
| CPU time | 486.06 seconds |
| Started | Jul 22 08:21:48 PM PDT 24 |
| Finished | Jul 22 08:29:55 PM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-de9119f7-3bc1-42be-9dab-42b71ef5e85e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672538475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.2672538475 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3710827336 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5512294752 ps |
| CPU time | 658.46 seconds |
| Started | Jul 22 08:19:43 PM PDT 24 |
| Finished | Jul 22 08:30:44 PM PDT 24 |
| Peak memory | 625336 kb |
| Host | smart-ad60ab7a-1034-4339-9183-6d48811d8934 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710827336 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3710827336 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.2591711534 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3270027725 ps |
| CPU time | 238.42 seconds |
| Started | Jul 22 08:17:03 PM PDT 24 |
| Finished | Jul 22 08:21:02 PM PDT 24 |
| Peak memory | 618696 kb |
| Host | smart-4f373700-7711-40a3-bdea-bfb7b8871dc4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591711534 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.2591711534 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2399781648 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3025902850 ps |
| CPU time | 256.62 seconds |
| Started | Jul 22 08:16:28 PM PDT 24 |
| Finished | Jul 22 08:20:45 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-7d6bf242-a64c-4cad-ba95-751f57bf4c1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399781648 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2399781648 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2803067249 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 4911735874 ps |
| CPU time | 701.76 seconds |
| Started | Jul 22 08:23:18 PM PDT 24 |
| Finished | Jul 22 08:35:01 PM PDT 24 |
| Peak memory | 611488 kb |
| Host | smart-48648cf2-e2f5-4e99-a857-f264a8f38ad6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803067249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2803067249 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.78001824 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 4318518262 ps |
| CPU time | 536.42 seconds |
| Started | Jul 22 08:26:29 PM PDT 24 |
| Finished | Jul 22 08:35:26 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-0837f577-94d6-4bdb-ba92-2e98a8e35be9 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78001824 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.78001824 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3988237832 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3353333280 ps |
| CPU time | 259.59 seconds |
| Started | Jul 22 08:26:08 PM PDT 24 |
| Finished | Jul 22 08:30:29 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-aa8ad83d-0699-40b9-8fca-dba62eb01064 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988237832 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.3988237832 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3245167330 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 20345374807 ps |
| CPU time | 3143.77 seconds |
| Started | Jul 22 08:19:27 PM PDT 24 |
| Finished | Jul 22 09:11:52 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-e690c25d-ae34-4566-815e-bc888b84b9d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245167330 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3245167330 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1563679885 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 4946178521 ps |
| CPU time | 732.03 seconds |
| Started | Jul 22 08:18:16 PM PDT 24 |
| Finished | Jul 22 08:30:31 PM PDT 24 |
| Peak memory | 614396 kb |
| Host | smart-c420b741-be58-4c59-8807-efca9463a6e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563679885 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1563679885 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2193772514 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3274748696 ps |
| CPU time | 344.7 seconds |
| Started | Jul 22 08:22:43 PM PDT 24 |
| Finished | Jul 22 08:28:33 PM PDT 24 |
| Peak memory | 613920 kb |
| Host | smart-d50d3dfd-8c1d-46fa-86b5-c6e36ff818f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193772514 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2193772514 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.808696228 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 3307519924 ps |
| CPU time | 281.73 seconds |
| Started | Jul 22 08:20:19 PM PDT 24 |
| Finished | Jul 22 08:25:01 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-2a7546c5-da31-4852-b4dd-eed0fc245178 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808696228 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.808696228 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4160874571 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6610999860 ps |
| CPU time | 505.95 seconds |
| Started | Jul 22 08:25:59 PM PDT 24 |
| Finished | Jul 22 08:34:27 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-33c6fa3c-3ed7-41b9-ad25-a7d388802ff6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160874571 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4160874571 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.1951568611 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2696684350 ps |
| CPU time | 239.11 seconds |
| Started | Jul 22 08:24:57 PM PDT 24 |
| Finished | Jul 22 08:28:58 PM PDT 24 |
| Peak memory | 616336 kb |
| Host | smart-b5136acb-5936-4170-89ea-28efd8979bab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951568611 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.1951568611 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.3978864186 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 4692870488 ps |
| CPU time | 680.97 seconds |
| Started | Jul 22 08:18:30 PM PDT 24 |
| Finished | Jul 22 08:29:52 PM PDT 24 |
| Peak memory | 625192 kb |
| Host | smart-6d3ad480-f755-4445-ad22-9d75adc0c2f4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978864186 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.3978864186 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.806625297 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 13453346839 ps |
| CPU time | 1616.99 seconds |
| Started | Jul 22 08:28:13 PM PDT 24 |
| Finished | Jul 22 08:55:11 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-2f3c67c8-71a3-4c40-93a7-481bd4556877 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806625297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.806625297 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1272236261 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 77964286790 ps |
| CPU time | 13786 seconds |
| Started | Jul 22 08:16:58 PM PDT 24 |
| Finished | Jul 23 12:06:48 AM PDT 24 |
| Peak memory | 636564 kb |
| Host | smart-45ff06dc-b705-44a3-b706-024f05e71585 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1272236261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1272236261 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.328217953 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4083630174 ps |
| CPU time | 508.77 seconds |
| Started | Jul 22 08:17:28 PM PDT 24 |
| Finished | Jul 22 08:25:58 PM PDT 24 |
| Peak memory | 625104 kb |
| Host | smart-0f9b70e7-bd4d-4588-93d3-728a8f6aa479 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328217953 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.328217953 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1596790959 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 4769006160 ps |
| CPU time | 617.11 seconds |
| Started | Jul 22 08:16:54 PM PDT 24 |
| Finished | Jul 22 08:27:12 PM PDT 24 |
| Peak memory | 625156 kb |
| Host | smart-ecd3b233-f3af-4b37-a98e-3748235440f2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596790959 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1596790959 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.634002788 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 3725002632 ps |
| CPU time | 624.98 seconds |
| Started | Jul 22 08:34:19 PM PDT 24 |
| Finished | Jul 22 08:44:46 PM PDT 24 |
| Peak memory | 625104 kb |
| Host | smart-c125a8ec-0e9d-4172-a5b7-9512ca9ce503 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634002788 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.634002788 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3884620805 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 6983712811 ps |
| CPU time | 657.91 seconds |
| Started | Jul 22 08:22:31 PM PDT 24 |
| Finished | Jul 22 08:33:30 PM PDT 24 |
| Peak memory | 621400 kb |
| Host | smart-af580978-7193-4f63-a163-064c9ab2b98a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3884620805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3884620805 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1392121814 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 7978392737 ps |
| CPU time | 952.11 seconds |
| Started | Jul 22 08:22:34 PM PDT 24 |
| Finished | Jul 22 08:38:27 PM PDT 24 |
| Peak memory | 622780 kb |
| Host | smart-cf14aa8d-62cf-47de-9dd6-af7e7717526e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392121814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1392121814 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.816208654 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 15350715138 ps |
| CPU time | 3911.69 seconds |
| Started | Jul 22 08:41:21 PM PDT 24 |
| Finished | Jul 22 09:46:35 PM PDT 24 |
| Peak memory | 611780 kb |
| Host | smart-7c34b86b-4e2e-421f-805e-24d73394fffa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816208654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.816208654 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.2235150851 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 15253760709 ps |
| CPU time | 3802.47 seconds |
| Started | Jul 22 08:30:28 PM PDT 24 |
| Finished | Jul 22 09:33:54 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-397cda87-8c05-4c3a-8fca-6cdcf807a541 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235150851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2235150851 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2319245848 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 15464996254 ps |
| CPU time | 4044.59 seconds |
| Started | Jul 22 08:29:56 PM PDT 24 |
| Finished | Jul 22 09:37:22 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-9da7038f-85b7-4e38-a6b4-5cc7e4d96668 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319245848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.2319245848 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.944382538 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 15103297028 ps |
| CPU time | 4247.05 seconds |
| Started | Jul 22 08:27:51 PM PDT 24 |
| Finished | Jul 22 09:38:39 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-442830f0-c6e3-47aa-90a4-427e7f99bac7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944382538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_rma.944382538 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.50076006 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 10752613413 ps |
| CPU time | 2743.79 seconds |
| Started | Jul 22 08:28:38 PM PDT 24 |
| Finished | Jul 22 09:14:24 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-2b42966b-02ab-4e10-a4b6-9dfeeb6225e7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50076006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.rom_e2e_asm_init_test_unlocked0.50076006 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2493334671 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 15394122924 ps |
| CPU time | 3218.66 seconds |
| Started | Jul 22 08:27:23 PM PDT 24 |
| Finished | Jul 22 09:21:03 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-ab52883c-feb0-4a2e-9453-1230bc6e7b6b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493334671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2493334671 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3479173923 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 15284714154 ps |
| CPU time | 3148.08 seconds |
| Started | Jul 22 08:31:18 PM PDT 24 |
| Finished | Jul 22 09:23:47 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-f850777d-a1c8-4e64-bb22-5693445a31da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479173923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.3479173923 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.803588445 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 14925885276 ps |
| CPU time | 3374.72 seconds |
| Started | Jul 22 08:30:26 PM PDT 24 |
| Finished | Jul 22 09:26:42 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-af2ab325-1e6e-4f7d-b6d0-8b30fb209ff3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803588445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.803588445 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.355060246 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 25287586152 ps |
| CPU time | 5814.35 seconds |
| Started | Jul 22 08:41:32 PM PDT 24 |
| Finished | Jul 22 10:18:28 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-efc27c8c-34f2-4b64-8b9d-6c21a4a220ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355060246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.355060246 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2561721215 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14823928049 ps |
| CPU time | 3399.16 seconds |
| Started | Jul 22 08:30:38 PM PDT 24 |
| Finished | Jul 22 09:27:19 PM PDT 24 |
| Peak memory | 611804 kb |
| Host | smart-789fdec9-11b2-4732-a9c6-5ddce7dd6d62 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561721215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2561721215 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1224788601 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 25533551950 ps |
| CPU time | 4078.28 seconds |
| Started | Jul 22 08:27:28 PM PDT 24 |
| Finished | Jul 22 09:35:27 PM PDT 24 |
| Peak memory | 611836 kb |
| Host | smart-e0ed5c72-49b1-4f19-85b7-5d1b4c7724db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224788601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1224788601 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3739099634 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 16790103586 ps |
| CPU time | 4124.66 seconds |
| Started | Jul 22 08:31:04 PM PDT 24 |
| Finished | Jul 22 09:39:49 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-72bc160d-9b7f-4a59-ac14-d6022a76547b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739099634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3739099634 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2026350013 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 4249380600 ps |
| CPU time | 547.95 seconds |
| Started | Jul 22 08:25:20 PM PDT 24 |
| Finished | Jul 22 08:34:29 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-04ae1494-d1ed-4d3e-8da3-b9cd546e2860 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026350013 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2026350013 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.558466132 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5615076992 ps |
| CPU time | 275.84 seconds |
| Started | Jul 22 08:27:47 PM PDT 24 |
| Finished | Jul 22 08:32:24 PM PDT 24 |
| Peak memory | 624124 kb |
| Host | smart-fd850c2b-0f6b-4806-9c52-5dd0f73c23d3 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=558466132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.558466132 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.3871193605 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2769143311 ps |
| CPU time | 107.41 seconds |
| Started | Jul 22 08:31:22 PM PDT 24 |
| Finished | Jul 22 08:33:10 PM PDT 24 |
| Peak memory | 617752 kb |
| Host | smart-2b53e283-7bfa-4130-af16-3642cd6c0dc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871193605 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3871193605 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.221287328 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 4757988988 ps |
| CPU time | 624 seconds |
| Started | Jul 22 08:37:30 PM PDT 24 |
| Finished | Jul 22 08:47:56 PM PDT 24 |
| Peak memory | 619456 kb |
| Host | smart-d7109faf-24d6-4e5b-93ae-d9df8d802245 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=221287328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.221287328 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.157906152 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 4582506204 ps |
| CPU time | 559.68 seconds |
| Started | Jul 22 08:38:11 PM PDT 24 |
| Finished | Jul 22 08:47:31 PM PDT 24 |
| Peak memory | 650320 kb |
| Host | smart-9de49299-6994-44b0-8ce9-86e46dc053af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 157906152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.157906152 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1729701035 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 11226547099 ps |
| CPU time | 1148.55 seconds |
| Started | Jul 22 08:38:20 PM PDT 24 |
| Finished | Jul 22 08:57:30 PM PDT 24 |
| Peak memory | 624616 kb |
| Host | smart-45757d2c-108b-456d-a5ed-8aa267b24610 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729701035 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1729701035 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.211995656 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 13212215946 ps |
| CPU time | 2146.2 seconds |
| Started | Jul 22 08:38:37 PM PDT 24 |
| Finished | Jul 22 09:14:25 PM PDT 24 |
| Peak memory | 618044 kb |
| Host | smart-421e35ea-4c5f-4663-a754-f0adbe365ed0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=211995656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.211995656 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.150067064 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4102821662 ps |
| CPU time | 318.48 seconds |
| Started | Jul 22 08:40:07 PM PDT 24 |
| Finished | Jul 22 08:45:26 PM PDT 24 |
| Peak memory | 649248 kb |
| Host | smart-3ffb4156-f938-4acd-9b62-aefc937b9ca4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150067064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_s w_alert_handler_lpg_sleep_mode_alerts.150067064 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3029687742 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 14287512893 ps |
| CPU time | 1118.08 seconds |
| Started | Jul 22 08:42:43 PM PDT 24 |
| Finished | Jul 22 09:01:22 PM PDT 24 |
| Peak memory | 622816 kb |
| Host | smart-9f410a2b-b761-428f-b69d-01ec62d55ff8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029687742 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.3029687742 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4031720778 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 4178102004 ps |
| CPU time | 598.6 seconds |
| Started | Jul 22 08:39:15 PM PDT 24 |
| Finished | Jul 22 08:49:15 PM PDT 24 |
| Peak memory | 618820 kb |
| Host | smart-304e2941-73e4-42b7-b2ff-03609c4a1c0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4031720778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.4031720778 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.961515084 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 10215705848 ps |
| CPU time | 692.61 seconds |
| Started | Jul 22 08:41:10 PM PDT 24 |
| Finished | Jul 22 08:52:44 PM PDT 24 |
| Peak memory | 624592 kb |
| Host | smart-e2f07d08-1caa-437b-a218-3b445c15712a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961515084 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.961515084 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.244871509 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5021636676 ps |
| CPU time | 846.03 seconds |
| Started | Jul 22 08:39:52 PM PDT 24 |
| Finished | Jul 22 08:54:00 PM PDT 24 |
| Peak memory | 619472 kb |
| Host | smart-151bbbb0-1b53-4691-885f-e1d106c03a97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=244871509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.244871509 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1623776888 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 5295664508 ps |
| CPU time | 580.44 seconds |
| Started | Jul 22 08:38:24 PM PDT 24 |
| Finished | Jul 22 08:48:05 PM PDT 24 |
| Peak memory | 622888 kb |
| Host | smart-ca66d6ff-67f9-48c6-8fa8-fe54ce65dcbc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623776888 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1623776888 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3203740177 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 12674680828 ps |
| CPU time | 2167.21 seconds |
| Started | Jul 22 08:39:08 PM PDT 24 |
| Finished | Jul 22 09:15:16 PM PDT 24 |
| Peak memory | 619256 kb |
| Host | smart-871ca34f-ec8c-422a-81cb-c5247e106e46 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3203740177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3203740177 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.122431637 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 8385722584 ps |
| CPU time | 1792.13 seconds |
| Started | Jul 22 08:39:43 PM PDT 24 |
| Finished | Jul 22 09:09:36 PM PDT 24 |
| Peak memory | 619600 kb |
| Host | smart-b62fed5f-fcbc-435e-a6f8-982fe22cf790 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=122431637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.122431637 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2695793662 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4000951720 ps |
| CPU time | 461.17 seconds |
| Started | Jul 22 08:39:56 PM PDT 24 |
| Finished | Jul 22 08:47:39 PM PDT 24 |
| Peak memory | 648960 kb |
| Host | smart-24f71ca1-64eb-4942-a37e-ec584b80ba74 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695793662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2695793662 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3959843549 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 6051072328 ps |
| CPU time | 649.63 seconds |
| Started | Jul 22 08:39:46 PM PDT 24 |
| Finished | Jul 22 08:50:36 PM PDT 24 |
| Peak memory | 620188 kb |
| Host | smart-c9e40a22-5a2a-483c-9413-d5abb4726f7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3959843549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3959843549 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.531105396 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 8394705968 ps |
| CPU time | 1521.5 seconds |
| Started | Jul 22 08:38:59 PM PDT 24 |
| Finished | Jul 22 09:04:21 PM PDT 24 |
| Peak memory | 619264 kb |
| Host | smart-e61fd1cb-306a-43cb-a84e-1cf6ac806bcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=531105396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.531105396 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2008515091 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 4960232558 ps |
| CPU time | 633.09 seconds |
| Started | Jul 22 08:40:28 PM PDT 24 |
| Finished | Jul 22 08:51:05 PM PDT 24 |
| Peak memory | 619528 kb |
| Host | smart-1e843f59-80b7-4ee2-9c68-40c8fa9a4756 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2008515091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2008515091 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.461938399 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 8458099260 ps |
| CPU time | 1725.08 seconds |
| Started | Jul 22 08:39:00 PM PDT 24 |
| Finished | Jul 22 09:07:46 PM PDT 24 |
| Peak memory | 619016 kb |
| Host | smart-a5670e96-46a6-4871-8c05-1241d20abcff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=461938399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.461938399 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.995820026 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4183405952 ps |
| CPU time | 383.37 seconds |
| Started | Jul 22 08:39:45 PM PDT 24 |
| Finished | Jul 22 08:46:09 PM PDT 24 |
| Peak memory | 649464 kb |
| Host | smart-9b54d5fa-6627-47dc-8490-13c2bdb72102 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995820026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_s w_alert_handler_lpg_sleep_mode_alerts.995820026 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.84630994 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 13801330988 ps |
| CPU time | 2393.98 seconds |
| Started | Jul 22 08:40:02 PM PDT 24 |
| Finished | Jul 22 09:19:58 PM PDT 24 |
| Peak memory | 619620 kb |
| Host | smart-08d17341-69d5-48bf-820b-2f4bc5011b00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=84630994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.84630994 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1906529968 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 13860173628 ps |
| CPU time | 1458.44 seconds |
| Started | Jul 22 08:24:55 PM PDT 24 |
| Finished | Jul 22 08:49:15 PM PDT 24 |
| Peak memory | 604140 kb |
| Host | smart-0fe77054-62fc-41bb-8eaf-7444b47739b9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906529968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 906529968 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1932917530 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4149091880 ps |
| CPU time | 281.57 seconds |
| Started | Jul 22 08:33:05 PM PDT 24 |
| Finished | Jul 22 08:37:47 PM PDT 24 |
| Peak memory | 621244 kb |
| Host | smart-fdf7df6b-d682-4477-983c-87674f65ff9b |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 932917530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.1932917530 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.50529215 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3439952560 ps |
| CPU time | 378.22 seconds |
| Started | Jul 22 08:26:22 PM PDT 24 |
| Finished | Jul 22 08:32:41 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-b17239c7-12ec-41ee-a567-ea09a203e87f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=50529215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.50529215 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1518890633 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 19304034524 ps |
| CPU time | 549.12 seconds |
| Started | Jul 22 08:28:37 PM PDT 24 |
| Finished | Jul 22 08:37:48 PM PDT 24 |
| Peak memory | 619736 kb |
| Host | smart-991eae16-3841-4c49-bdf5-c4f294971616 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1518890633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1518890633 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.3599638837 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2892560014 ps |
| CPU time | 328.44 seconds |
| Started | Jul 22 08:30:14 PM PDT 24 |
| Finished | Jul 22 08:35:43 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-5b5ef23c-0fc7-4d20-a08e-573f7b897317 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599638837 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3599638837 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3908819723 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3211443674 ps |
| CPU time | 401.15 seconds |
| Started | Jul 22 08:32:33 PM PDT 24 |
| Finished | Jul 22 08:39:15 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-85ec7da1-aa9e-431e-b77e-5550b92d7a8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908 819723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3908819723 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.463494854 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3387766493 ps |
| CPU time | 364.05 seconds |
| Started | Jul 22 08:33:45 PM PDT 24 |
| Finished | Jul 22 08:39:50 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-c76737d9-edf1-491d-ab2e-2a86a860125a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463494854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.463494854 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.14901429 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 2317780968 ps |
| CPU time | 247.71 seconds |
| Started | Jul 22 08:30:59 PM PDT 24 |
| Finished | Jul 22 08:35:07 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-5405c774-5935-4a43-a97f-ea79d2448b09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14901429 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.14901429 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.823090009 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 2292780120 ps |
| CPU time | 246.53 seconds |
| Started | Jul 22 08:29:57 PM PDT 24 |
| Finished | Jul 22 08:34:05 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-6a819863-bcef-46af-aa35-1ab808c27a5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823090009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.823090009 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.3009425337 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 2733810855 ps |
| CPU time | 262.56 seconds |
| Started | Jul 22 08:31:49 PM PDT 24 |
| Finished | Jul 22 08:36:12 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-4918a6df-283d-4b56-92e2-6c45544b8be3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009425337 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3009425337 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.158017280 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3133615830 ps |
| CPU time | 309.09 seconds |
| Started | Jul 22 08:34:13 PM PDT 24 |
| Finished | Jul 22 08:39:24 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-9f62c21f-4163-4c5f-b810-8e74dcfb544b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158017280 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.158017280 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3469653741 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3769424003 ps |
| CPU time | 267.31 seconds |
| Started | Jul 22 08:32:59 PM PDT 24 |
| Finished | Jul 22 08:37:28 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-b39f2aed-8a55-4ea1-9217-13ea94f68af9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3469653741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3469653741 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.113227254 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 4733124472 ps |
| CPU time | 454.82 seconds |
| Started | Jul 22 08:31:45 PM PDT 24 |
| Finished | Jul 22 08:39:20 PM PDT 24 |
| Peak memory | 620020 kb |
| Host | smart-45228c26-95aa-45b6-9ee6-317f5f1ffb0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=113227254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.113227254 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1992483571 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 6221942006 ps |
| CPU time | 1090.74 seconds |
| Started | Jul 22 08:42:04 PM PDT 24 |
| Finished | Jul 22 09:00:16 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-fc6e73d1-d442-4122-966f-53ab29f98486 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1992483571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1992483571 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3541891914 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7433476216 ps |
| CPU time | 1551.25 seconds |
| Started | Jul 22 08:28:56 PM PDT 24 |
| Finished | Jul 22 08:54:48 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-b9282b51-a158-4ec4-89de-d27c09bb69f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541891914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.3541891914 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2101994825 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 10659489540 ps |
| CPU time | 1349.56 seconds |
| Started | Jul 22 08:31:45 PM PDT 24 |
| Finished | Jul 22 08:54:15 PM PDT 24 |
| Peak memory | 612068 kb |
| Host | smart-bd23f85b-b111-4c75-b73b-825582d1d59e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101994825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.2101994825 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3283429878 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 8099997106 ps |
| CPU time | 1305.72 seconds |
| Started | Jul 22 08:29:51 PM PDT 24 |
| Finished | Jul 22 08:51:38 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-f36fe0c5-e6ea-446c-bd9a-2d9aada297a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3283429878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3283429878 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4064930449 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5540206328 ps |
| CPU time | 784.5 seconds |
| Started | Jul 22 08:30:08 PM PDT 24 |
| Finished | Jul 22 08:43:13 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-d0e94d59-fedd-4425-9063-072829db4588 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4064930449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.4064930449 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2374282067 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 254861507016 ps |
| CPU time | 10978.3 seconds |
| Started | Jul 22 08:31:37 PM PDT 24 |
| Finished | Jul 22 11:34:37 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-ae72ba83-7585-4dd5-beb2-98397a2af81b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374282067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2374282067 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2647105242 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2585377832 ps |
| CPU time | 254.34 seconds |
| Started | Jul 22 08:29:16 PM PDT 24 |
| Finished | Jul 22 08:33:32 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-5ae5e36c-80b1-42cc-93b7-a8bf0dbd6c1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647105242 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2647105242 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1321022999 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 6129201564 ps |
| CPU time | 618.14 seconds |
| Started | Jul 22 08:41:35 PM PDT 24 |
| Finished | Jul 22 08:51:54 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-20e2ca6a-f4d1-4562-9d71-520aca2e3591 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1321022999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1321022999 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3921108530 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4204470356 ps |
| CPU time | 459.71 seconds |
| Started | Jul 22 08:28:36 PM PDT 24 |
| Finished | Jul 22 08:36:17 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-57134eb5-e745-4196-bd33-6e9ad51f5941 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921108530 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3921108530 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.600984884 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 7419831366 ps |
| CPU time | 423.53 seconds |
| Started | Jul 22 08:28:31 PM PDT 24 |
| Finished | Jul 22 08:35:36 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-145cac44-ff12-4f9e-8a39-8e962958e5d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=600984884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.600984884 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3383512569 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 3439936392 ps |
| CPU time | 353.59 seconds |
| Started | Jul 22 08:34:44 PM PDT 24 |
| Finished | Jul 22 08:40:39 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-3b0aff36-298e-4b04-a2bb-a9321526d5a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383512569 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3383512569 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4146622993 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 10443467556 ps |
| CPU time | 906.25 seconds |
| Started | Jul 22 08:41:04 PM PDT 24 |
| Finished | Jul 22 08:56:12 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-66e29005-bfca-4866-bc94-40dafee4c0a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4146622993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.4146622993 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1473239441 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5847560380 ps |
| CPU time | 728.62 seconds |
| Started | Jul 22 08:29:31 PM PDT 24 |
| Finished | Jul 22 08:41:41 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-f063cc39-f6ad-4271-ae2b-e8622ffb2fb0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1473239441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1473239441 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2675817069 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 7074240818 ps |
| CPU time | 1086.95 seconds |
| Started | Jul 22 08:32:25 PM PDT 24 |
| Finished | Jul 22 08:50:32 PM PDT 24 |
| Peak memory | 617424 kb |
| Host | smart-b2e15b37-c14a-40a6-9c34-d9c4337b5d7e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675817069 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2675817069 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1758783994 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 28937038810 ps |
| CPU time | 3574.15 seconds |
| Started | Jul 22 08:33:51 PM PDT 24 |
| Finished | Jul 22 09:33:27 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-e7c768a5-cd28-49c1-8ea8-c49cb8419322 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758783994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1758783994 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2469977318 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 5232881204 ps |
| CPU time | 440.99 seconds |
| Started | Jul 22 08:34:57 PM PDT 24 |
| Finished | Jul 22 08:42:19 PM PDT 24 |
| Peak memory | 625268 kb |
| Host | smart-1b1ae267-6ed4-4e11-9bfe-36edb32dd9db |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2469977318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2469977318 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2438525374 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 4329189206 ps |
| CPU time | 698.6 seconds |
| Started | Jul 22 08:33:06 PM PDT 24 |
| Finished | Jul 22 08:44:45 PM PDT 24 |
| Peak memory | 613448 kb |
| Host | smart-36b9bf75-a99a-4f85-9711-e0c5139549b7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438525374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2438525374 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1988843121 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3932163564 ps |
| CPU time | 616.52 seconds |
| Started | Jul 22 08:35:11 PM PDT 24 |
| Finished | Jul 22 08:45:29 PM PDT 24 |
| Peak memory | 613440 kb |
| Host | smart-beb9b509-e394-4b5d-969c-9ab47b39384e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988843121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1988843121 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4013586525 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 3611288030 ps |
| CPU time | 742.68 seconds |
| Started | Jul 22 08:32:28 PM PDT 24 |
| Finished | Jul 22 08:44:52 PM PDT 24 |
| Peak memory | 613424 kb |
| Host | smart-a38cda16-e9dd-432d-a084-e34f13b1e24a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013586525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4013586525 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1712259295 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4275465160 ps |
| CPU time | 585.14 seconds |
| Started | Jul 22 08:33:30 PM PDT 24 |
| Finished | Jul 22 08:43:19 PM PDT 24 |
| Peak memory | 613136 kb |
| Host | smart-b85cb828-4319-411e-b58b-adf6448384cf |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712259295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1712259295 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3630687126 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4762006708 ps |
| CPU time | 657.81 seconds |
| Started | Jul 22 08:32:20 PM PDT 24 |
| Finished | Jul 22 08:43:20 PM PDT 24 |
| Peak memory | 613228 kb |
| Host | smart-c7668221-adaf-4bd8-81b3-bd8d277414d3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630687126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3630687126 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.186797752 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4597782528 ps |
| CPU time | 687.07 seconds |
| Started | Jul 22 08:35:16 PM PDT 24 |
| Finished | Jul 22 08:46:45 PM PDT 24 |
| Peak memory | 613424 kb |
| Host | smart-81f1f473-a9f7-458d-a5fa-7e5a986e2e39 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186797752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.186797752 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2566109783 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2874325094 ps |
| CPU time | 218.05 seconds |
| Started | Jul 22 08:35:23 PM PDT 24 |
| Finished | Jul 22 08:39:02 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-362168a2-53eb-4e0a-a312-98dc542b9071 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566109783 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2566109783 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.142020982 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 2696257536 ps |
| CPU time | 345.77 seconds |
| Started | Jul 22 08:31:54 PM PDT 24 |
| Finished | Jul 22 08:37:41 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-d1cccdbe-5b3a-4349-b19d-7a21c14b5744 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142020982 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.142020982 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2024772226 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2097466131 ps |
| CPU time | 214.88 seconds |
| Started | Jul 22 08:34:03 PM PDT 24 |
| Finished | Jul 22 08:37:39 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-2d303d56-eeb7-4800-8d2a-d63f999b09f2 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024772226 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2024772226 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2969345342 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4314110080 ps |
| CPU time | 556.32 seconds |
| Started | Jul 22 08:32:50 PM PDT 24 |
| Finished | Jul 22 08:42:07 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-e4a9db5b-8ac3-48cc-97df-93751c6cfcb4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969345342 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2969345342 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4213469755 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 5514481646 ps |
| CPU time | 520.98 seconds |
| Started | Jul 22 08:33:00 PM PDT 24 |
| Finished | Jul 22 08:41:42 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-fcf6639f-e8be-44e7-b796-1a30e5807e72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213469755 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.4213469755 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3696304335 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5311134680 ps |
| CPU time | 431.87 seconds |
| Started | Jul 22 08:31:37 PM PDT 24 |
| Finished | Jul 22 08:38:50 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-1e1f9201-fad2-46b2-933f-351ab3c859de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696304335 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3696304335 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3716510643 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 11681296232 ps |
| CPU time | 1021.33 seconds |
| Started | Jul 22 08:33:38 PM PDT 24 |
| Finished | Jul 22 08:50:42 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-ad96c6da-3250-4dfe-b105-fbdea7dd015d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716510643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3716510643 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2125589301 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 3879361890 ps |
| CPU time | 510.04 seconds |
| Started | Jul 22 08:31:43 PM PDT 24 |
| Finished | Jul 22 08:40:14 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-51d7eed9-d9f6-4159-a20f-c24314c69070 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125589301 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2125589301 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3136558291 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4527578380 ps |
| CPU time | 612.85 seconds |
| Started | Jul 22 08:35:50 PM PDT 24 |
| Finished | Jul 22 08:46:04 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-b57ca32a-9543-4b46-9006-1f20f5e384c8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136558291 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3136558291 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1443749779 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 2752997370 ps |
| CPU time | 210.23 seconds |
| Started | Jul 22 08:34:31 PM PDT 24 |
| Finished | Jul 22 08:38:02 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-8157dc66-bc03-44e1-bb5d-703e5bd87b0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443749779 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.1443749779 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.231352704 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 16412053100 ps |
| CPU time | 3586.39 seconds |
| Started | Jul 22 08:31:03 PM PDT 24 |
| Finished | Jul 22 09:30:51 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-1530abbb-f618-4976-ab0c-de03a7f6818a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231352704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.231352704 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.54114062 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 28771157550 ps |
| CPU time | 4093.91 seconds |
| Started | Jul 22 08:35:05 PM PDT 24 |
| Finished | Jul 22 09:43:19 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-fb499029-68e3-4345-8ce9-0a1371b07e7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=54114062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.54114062 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2956022401 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4586991010 ps |
| CPU time | 563.67 seconds |
| Started | Jul 22 08:30:41 PM PDT 24 |
| Finished | Jul 22 08:40:06 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-f790c558-28c6-41fa-817f-a3fb0d979dbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560 22401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2956022401 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.2940460376 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2538137222 ps |
| CPU time | 320.42 seconds |
| Started | Jul 22 08:30:56 PM PDT 24 |
| Finished | Jul 22 08:36:17 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-d38a49d2-1804-4b13-b8da-985868c9e534 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940460376 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.2940460376 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1848098986 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 6004379945 ps |
| CPU time | 608.32 seconds |
| Started | Jul 22 08:30:32 PM PDT 24 |
| Finished | Jul 22 08:40:42 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-01d8f13b-0394-46bc-8094-6c596f41f706 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848098986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1848098986 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2443695242 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 3204119760 ps |
| CPU time | 262.54 seconds |
| Started | Jul 22 08:36:27 PM PDT 24 |
| Finished | Jul 22 08:40:50 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-1099d206-c65a-4d77-b6e5-fd35c934d0a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443695242 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2443695242 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1033157786 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5218003400 ps |
| CPU time | 794.91 seconds |
| Started | Jul 22 08:26:39 PM PDT 24 |
| Finished | Jul 22 08:39:55 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-88f22e6d-03e0-424a-a7c8-208007a9f2de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1033157786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1033157786 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.354613714 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 7167312424 ps |
| CPU time | 1732.43 seconds |
| Started | Jul 22 08:30:15 PM PDT 24 |
| Finished | Jul 22 08:59:08 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-c7955f8d-e2eb-4a7b-9def-fdf8ecc485b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354613714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a uto_mode.354613714 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2153980017 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3249078648 ps |
| CPU time | 697.48 seconds |
| Started | Jul 22 08:30:53 PM PDT 24 |
| Finished | Jul 22 08:42:31 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-74fce38d-6fa7-4292-8859-1d43322dccbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153980017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2153980017 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2380752547 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 7764630080 ps |
| CPU time | 1353.6 seconds |
| Started | Jul 22 08:32:18 PM PDT 24 |
| Finished | Jul 22 08:54:53 PM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-68c2559b-3484-4319-95a5-b7dbccd65b2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2380752547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2380752547 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2158146540 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 7618925724 ps |
| CPU time | 1649.56 seconds |
| Started | Jul 22 08:31:39 PM PDT 24 |
| Finished | Jul 22 08:59:09 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-f1959dd6-0495-418c-b835-490beec7710d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158146540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2158146540 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3497169329 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3345380088 ps |
| CPU time | 537.01 seconds |
| Started | Jul 22 08:32:12 PM PDT 24 |
| Finished | Jul 22 08:41:09 PM PDT 24 |
| Peak memory | 616796 kb |
| Host | smart-7365f68c-405d-4b0d-bac2-3f704f18fa4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497169329 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3497169329 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2151987157 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 5858942550 ps |
| CPU time | 1311.7 seconds |
| Started | Jul 22 08:31:49 PM PDT 24 |
| Finished | Jul 22 08:53:42 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-97daec79-6523-47e3-9687-07e378a41798 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151987157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2151987157 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3793079813 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 3084882400 ps |
| CPU time | 316.47 seconds |
| Started | Jul 22 08:32:24 PM PDT 24 |
| Finished | Jul 22 08:37:41 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-a0524bc3-ffcd-4e15-9e3c-a85ff1004d1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37 93079813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3793079813 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1279790289 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7351735660 ps |
| CPU time | 1450.67 seconds |
| Started | Jul 22 08:32:27 PM PDT 24 |
| Finished | Jul 22 08:56:38 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-d93955a1-5c0f-48eb-99c6-b4b453343673 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1279790289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1279790289 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3833413505 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 1986126252 ps |
| CPU time | 177.6 seconds |
| Started | Jul 22 08:31:20 PM PDT 24 |
| Finished | Jul 22 08:34:18 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-7108d9eb-9d29-4bb1-821b-435740680981 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833413505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3833413505 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3177687665 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3628874170 ps |
| CPU time | 492.41 seconds |
| Started | Jul 22 08:38:33 PM PDT 24 |
| Finished | Jul 22 08:46:47 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-c26503df-f3f9-4b4f-81e1-ee477ebc75c5 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3177687665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.3177687665 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2495577792 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 2819024136 ps |
| CPU time | 221.63 seconds |
| Started | Jul 22 08:24:36 PM PDT 24 |
| Finished | Jul 22 08:28:19 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-fe1cdbdc-d85f-4d07-8860-5092fe0f5b08 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495577792 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2495577792 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.78205973 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 2996354466 ps |
| CPU time | 202.6 seconds |
| Started | Jul 22 08:26:07 PM PDT 24 |
| Finished | Jul 22 08:29:30 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-f0b86b7f-8438-40b8-bcbe-b6c8f2e4cd7c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78205973 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_flash.78205973 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.4141382249 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 2692907064 ps |
| CPU time | 251.62 seconds |
| Started | Jul 22 08:26:39 PM PDT 24 |
| Finished | Jul 22 08:30:51 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-6cd6cf4e-5653-4f93-97f7-e095e0773ddd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141382249 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.4141382249 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.3542189421 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2802208456 ps |
| CPU time | 125.95 seconds |
| Started | Jul 22 08:24:55 PM PDT 24 |
| Finished | Jul 22 08:27:02 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-4084bc0e-6c5d-4c70-8406-72f84fe705ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542189421 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.3542189421 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.474236698 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 59237099810 ps |
| CPU time | 9705.87 seconds |
| Started | Jul 22 08:29:59 PM PDT 24 |
| Finished | Jul 22 11:11:48 PM PDT 24 |
| Peak memory | 625220 kb |
| Host | smart-d3e051ed-3160-4a8f-b56f-879894aceca5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=474236698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.474236698 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.1752974333 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 5604830244 ps |
| CPU time | 772.81 seconds |
| Started | Jul 22 08:35:35 PM PDT 24 |
| Finished | Jul 22 08:48:30 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-dcfb74ea-d034-454e-90e2-7ed144d3b9da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1752974333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1752974333 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3079320978 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 5962622120 ps |
| CPU time | 1171.31 seconds |
| Started | Jul 22 08:25:52 PM PDT 24 |
| Finished | Jul 22 08:45:24 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-4425d0e9-82a9-4a94-8a8a-569ed856ee01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079320978 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3079320978 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2350268064 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 6132053110 ps |
| CPU time | 1108.56 seconds |
| Started | Jul 22 08:29:11 PM PDT 24 |
| Finished | Jul 22 08:47:41 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-fe0faf54-8977-40a2-8114-281af483a03b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350268064 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2350268064 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.969423579 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 7583198102 ps |
| CPU time | 1292.76 seconds |
| Started | Jul 22 08:33:20 PM PDT 24 |
| Finished | Jul 22 08:54:53 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-bbe0a387-a0a9-42f8-9896-24ce4ccc5834 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969423579 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.969423579 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2824471741 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5898695867 ps |
| CPU time | 1207.22 seconds |
| Started | Jul 22 08:31:32 PM PDT 24 |
| Finished | Jul 22 08:51:41 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-89a56954-967c-449c-8f91-9b8c132cadd2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824471741 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2824471741 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2418154933 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4165572716 ps |
| CPU time | 518.64 seconds |
| Started | Jul 22 08:29:27 PM PDT 24 |
| Finished | Jul 22 08:38:07 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-57e5a56d-17b9-49e5-9cb1-f9546dfe889d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418154933 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2418154933 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1840430935 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6120793542 ps |
| CPU time | 1252.75 seconds |
| Started | Jul 22 08:33:53 PM PDT 24 |
| Finished | Jul 22 08:54:47 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-f567e3d7-de95-4711-96d8-b7f6e8c17436 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840430935 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1840430935 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2653226456 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4303005511 ps |
| CPU time | 797.64 seconds |
| Started | Jul 22 08:32:46 PM PDT 24 |
| Finished | Jul 22 08:46:05 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-a21c6f0e-8891-4003-94d9-ee4362dfd92a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2653226456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2653226456 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2554458467 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3120591600 ps |
| CPU time | 346.44 seconds |
| Started | Jul 22 08:32:31 PM PDT 24 |
| Finished | Jul 22 08:38:18 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-68bb8985-e2bd-4198-89d8-cb8ecc7b809d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554458 467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2554458467 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1624929427 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 23154430744 ps |
| CPU time | 2225.79 seconds |
| Started | Jul 22 08:25:39 PM PDT 24 |
| Finished | Jul 22 09:02:46 PM PDT 24 |
| Peak memory | 613972 kb |
| Host | smart-d26b199d-1876-484f-8e3e-d73ed5a2442d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624929427 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1624929427 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1998975600 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3122213026 ps |
| CPU time | 306.57 seconds |
| Started | Jul 22 08:40:31 PM PDT 24 |
| Finished | Jul 22 08:45:41 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-fea03801-9879-461c-8544-78c1effcdc93 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1998975600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1998975600 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.945049533 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 2777796655 ps |
| CPU time | 320.35 seconds |
| Started | Jul 22 08:38:32 PM PDT 24 |
| Finished | Jul 22 08:43:54 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-f2b0de4d-b6dc-4f4c-b039-9a8359812457 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945049533 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_gpio_smoketest.945049533 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.802497532 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2749480518 ps |
| CPU time | 273.99 seconds |
| Started | Jul 22 08:31:03 PM PDT 24 |
| Finished | Jul 22 08:35:38 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-194681dc-a73e-4c8d-a15c-7f332ab04fd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802497532 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.802497532 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1675676845 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 3467733180 ps |
| CPU time | 330.47 seconds |
| Started | Jul 22 08:30:24 PM PDT 24 |
| Finished | Jul 22 08:35:55 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-4f52b38e-0446-45c1-a1f8-d6a3f4d75ac5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675676845 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.1675676845 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1345368254 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2553236072 ps |
| CPU time | 273.22 seconds |
| Started | Jul 22 08:33:36 PM PDT 24 |
| Finished | Jul 22 08:38:13 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-2a882fc5-327e-47e8-b3d4-ecad2575aefb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345368254 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1345368254 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.692717790 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3782199840 ps |
| CPU time | 297.95 seconds |
| Started | Jul 22 08:35:10 PM PDT 24 |
| Finished | Jul 22 08:40:10 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-21d92f70-f918-4dc7-bad0-60f216a5aba4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692717790 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.692717790 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1456323340 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 7658306600 ps |
| CPU time | 1563.36 seconds |
| Started | Jul 22 08:35:02 PM PDT 24 |
| Finished | Jul 22 09:01:07 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-2d326e28-7928-4baf-85af-d63cc6138d41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456323340 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1456323340 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.4002340889 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 2817381412 ps |
| CPU time | 293.19 seconds |
| Started | Jul 22 08:31:09 PM PDT 24 |
| Finished | Jul 22 08:36:02 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-b4727497-9b1c-49e8-af3d-ab10e6593c1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002340889 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.4002340889 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1428713668 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3168669816 ps |
| CPU time | 363.54 seconds |
| Started | Jul 22 08:34:58 PM PDT 24 |
| Finished | Jul 22 08:41:02 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-c968cdcd-f9ad-43de-9c89-bab892116acc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428713668 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1428713668 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1191095957 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4161243492 ps |
| CPU time | 542.91 seconds |
| Started | Jul 22 08:28:39 PM PDT 24 |
| Finished | Jul 22 08:37:43 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-e6c03e43-2599-4ccd-aab0-e04b7f51253d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191095957 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1191095957 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.319874619 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5924437496 ps |
| CPU time | 983.5 seconds |
| Started | Jul 22 08:28:54 PM PDT 24 |
| Finished | Jul 22 08:45:19 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-691cdc38-2055-42e2-8011-2fea79af8968 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319874619 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.319874619 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1232534426 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 5145466746 ps |
| CPU time | 885.65 seconds |
| Started | Jul 22 08:27:05 PM PDT 24 |
| Finished | Jul 22 08:41:51 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-8ff32609-23f0-4675-951c-bbf55c8cfee3 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232534426 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.1232534426 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1731733861 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 63762574981 ps |
| CPU time | 10949.3 seconds |
| Started | Jul 22 08:28:22 PM PDT 24 |
| Finished | Jul 22 11:30:54 PM PDT 24 |
| Peak memory | 625184 kb |
| Host | smart-12efd9ba-cccb-4e20-b013-cdcb8fc8e5db |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1731733861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1731733861 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3591593782 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 7298542866 ps |
| CPU time | 1020.24 seconds |
| Started | Jul 22 08:35:00 PM PDT 24 |
| Finished | Jul 22 08:52:01 PM PDT 24 |
| Peak memory | 617012 kb |
| Host | smart-545a309a-9831-49f7-ae66-0f82e01e2f61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591 593782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.3591593782 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4190782383 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 9912028880 ps |
| CPU time | 1938.69 seconds |
| Started | Jul 22 08:32:01 PM PDT 24 |
| Finished | Jul 22 09:04:21 PM PDT 24 |
| Peak memory | 617064 kb |
| Host | smart-1feb3463-bacd-4ee0-8a32-ad2301e9c358 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4190782383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.4190782383 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3126705481 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 8136608966 ps |
| CPU time | 1039.77 seconds |
| Started | Jul 22 08:32:41 PM PDT 24 |
| Finished | Jul 22 08:50:02 PM PDT 24 |
| Peak memory | 616772 kb |
| Host | smart-be8a360d-bb9d-4a68-a4ab-6106bc5c81eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3126705481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3126705481 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2018281268 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 8817821172 ps |
| CPU time | 1601.92 seconds |
| Started | Jul 22 08:31:43 PM PDT 24 |
| Finished | Jul 22 08:58:26 PM PDT 24 |
| Peak memory | 617144 kb |
| Host | smart-a6388897-7037-4eed-ba2e-8ca3da3e16b9 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2018281268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2018281268 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2767922569 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 10225461260 ps |
| CPU time | 1598.49 seconds |
| Started | Jul 22 08:32:05 PM PDT 24 |
| Finished | Jul 22 08:58:45 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-72279da9-079a-4670-abbf-21250a73ea08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276792 2569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2767922569 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2460566247 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 9448368664 ps |
| CPU time | 1495.63 seconds |
| Started | Jul 22 08:30:26 PM PDT 24 |
| Finished | Jul 22 08:55:23 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-b2173089-57ae-49ee-8f00-0310274f68bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605 66247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.2460566247 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.4195162206 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 3061578060 ps |
| CPU time | 276.66 seconds |
| Started | Jul 22 08:30:39 PM PDT 24 |
| Finished | Jul 22 08:35:17 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-801abc5b-6fd7-4995-a2c8-b4b67a29af15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195162206 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.4195162206 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3308083324 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 3617598856 ps |
| CPU time | 364.53 seconds |
| Started | Jul 22 08:26:27 PM PDT 24 |
| Finished | Jul 22 08:32:33 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-1c47b332-6af1-40a8-a0b2-bc01d342f59b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308083324 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3308083324 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1505269453 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3005790100 ps |
| CPU time | 220.88 seconds |
| Started | Jul 22 08:31:25 PM PDT 24 |
| Finished | Jul 22 08:35:07 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-5daa2194-2dbb-4e8d-88ac-6baae42ad586 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505269453 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1505269453 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.888843575 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3136319150 ps |
| CPU time | 302.99 seconds |
| Started | Jul 22 08:31:43 PM PDT 24 |
| Finished | Jul 22 08:36:47 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-6e625687-146d-4d8c-96e1-be8631b88f97 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888843575 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.888843575 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.370529293 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3558431316 ps |
| CPU time | 330.16 seconds |
| Started | Jul 22 08:33:27 PM PDT 24 |
| Finished | Jul 22 08:39:00 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-bc9d7db7-5f15-4250-a089-002d2bb19401 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370529293 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_kmac_mode_kmac.370529293 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3359340092 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2885597102 ps |
| CPU time | 334.46 seconds |
| Started | Jul 22 08:31:43 PM PDT 24 |
| Finished | Jul 22 08:37:19 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-ab1c7cad-fef7-446d-8b6e-5a611b753af2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359340092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3359340092 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1652030974 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3384534097 ps |
| CPU time | 370.62 seconds |
| Started | Jul 22 08:33:28 PM PDT 24 |
| Finished | Jul 22 08:39:42 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-b2bb4c4a-3d5a-4fef-a7db-ed85aedd957f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520309 74 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1652030974 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.1690642465 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 2940593628 ps |
| CPU time | 451.41 seconds |
| Started | Jul 22 08:34:36 PM PDT 24 |
| Finished | Jul 22 08:42:09 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-51d30aa4-fedd-4287-9e30-eb6d32705705 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690642465 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1690642465 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3538225689 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3242248052 ps |
| CPU time | 336.19 seconds |
| Started | Jul 22 08:26:29 PM PDT 24 |
| Finished | Jul 22 08:32:06 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-7058bc68-ccaa-446f-b833-06457217c7cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538225689 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3538225689 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3109459026 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3892454540 ps |
| CPU time | 426.91 seconds |
| Started | Jul 22 08:36:09 PM PDT 24 |
| Finished | Jul 22 08:43:17 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-7c066c8a-bf10-424b-8184-14e73efee95e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3109459026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.3109459026 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2908489117 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3495230204 ps |
| CPU time | 251.04 seconds |
| Started | Jul 22 08:28:54 PM PDT 24 |
| Finished | Jul 22 08:33:06 PM PDT 24 |
| Peak memory | 622088 kb |
| Host | smart-fe870118-3686-49d1-a33e-e949f69ca8ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084891 17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2908489117 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.69093342 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 7287227845 ps |
| CPU time | 496.93 seconds |
| Started | Jul 22 08:27:56 PM PDT 24 |
| Finished | Jul 22 08:36:15 PM PDT 24 |
| Peak memory | 620824 kb |
| Host | smart-9ef473f3-1d92-4bba-acce-786df60a6203 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69093342 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.69093342 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1268851216 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2938399017 ps |
| CPU time | 109.57 seconds |
| Started | Jul 22 08:28:39 PM PDT 24 |
| Finished | Jul 22 08:30:30 PM PDT 24 |
| Peak memory | 617340 kb |
| Host | smart-d3908fee-3b30-49d9-b643-053818917b11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1268851216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1268851216 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1117606806 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2482607093 ps |
| CPU time | 111.61 seconds |
| Started | Jul 22 08:27:38 PM PDT 24 |
| Finished | Jul 22 08:29:31 PM PDT 24 |
| Peak memory | 623420 kb |
| Host | smart-b7cd7fa4-22a5-4bae-bb5d-d01a6bee9451 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117606806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1117606806 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1308232253 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 47980463090 ps |
| CPU time | 5603.35 seconds |
| Started | Jul 22 08:27:11 PM PDT 24 |
| Finished | Jul 22 10:00:36 PM PDT 24 |
| Peak memory | 619808 kb |
| Host | smart-da3b4f8e-add2-4660-8f75-fdc90c23c65b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308232253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.1308232253 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.684460837 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 49881173681 ps |
| CPU time | 5611.27 seconds |
| Started | Jul 22 08:27:42 PM PDT 24 |
| Finished | Jul 22 10:01:14 PM PDT 24 |
| Peak memory | 619856 kb |
| Host | smart-2726ed4a-9d26-4521-839c-b0912bc4a1e7 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684460837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.684460837 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.481477347 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 9537296024 ps |
| CPU time | 1059.5 seconds |
| Started | Jul 22 08:27:53 PM PDT 24 |
| Finished | Jul 22 08:45:34 PM PDT 24 |
| Peak memory | 620196 kb |
| Host | smart-7653aa26-6d03-43c7-950e-b077f82f2b72 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=481477347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.481477347 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1104593927 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 47653647394 ps |
| CPU time | 4483.41 seconds |
| Started | Jul 22 08:31:28 PM PDT 24 |
| Finished | Jul 22 09:46:13 PM PDT 24 |
| Peak memory | 620500 kb |
| Host | smart-ab12403a-17f3-4cc8-85f1-6d14d4dc86d0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104593927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1104593927 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.100403381 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 27829854377 ps |
| CPU time | 2151.1 seconds |
| Started | Jul 22 08:27:11 PM PDT 24 |
| Finished | Jul 22 09:03:04 PM PDT 24 |
| Peak memory | 620776 kb |
| Host | smart-94f4b3c3-f021-488a-a408-8cdf15ffc523 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=100403381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.100403381 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1308153879 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 17272018364 ps |
| CPU time | 3610.01 seconds |
| Started | Jul 22 08:31:47 PM PDT 24 |
| Finished | Jul 22 09:31:58 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-29e8625b-f3f2-4606-bb71-dc0c52b8d551 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1308153879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1308153879 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2724086563 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 18189133560 ps |
| CPU time | 3389.59 seconds |
| Started | Jul 22 08:29:05 PM PDT 24 |
| Finished | Jul 22 09:25:36 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-a1b76b7a-230f-405e-9ca8-28ab775b053f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2724086563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2724086563 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3484029381 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 24363172212 ps |
| CPU time | 3337.33 seconds |
| Started | Jul 22 08:33:21 PM PDT 24 |
| Finished | Jul 22 09:29:00 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-4dea8cb0-7a91-4c3f-bff6-a03113d0c93b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484029381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3484029381 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2887646576 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3335312350 ps |
| CPU time | 549.24 seconds |
| Started | Jul 22 08:30:16 PM PDT 24 |
| Finished | Jul 22 08:39:27 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-3fff600d-a976-41e5-a047-5c92c1417dd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887646576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.2887646576 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1447437250 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5966345272 ps |
| CPU time | 1137.88 seconds |
| Started | Jul 22 08:28:35 PM PDT 24 |
| Finished | Jul 22 08:47:34 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-e8828818-c732-48b3-8804-75038222c5b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1447437250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1447437250 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.577883973 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 9063610968 ps |
| CPU time | 1793.82 seconds |
| Started | Jul 22 08:36:58 PM PDT 24 |
| Finished | Jul 22 09:06:55 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-0a61c692-5b5d-4aff-8f10-58ab3842d221 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577883973 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.577883973 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2500213146 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3262474413 ps |
| CPU time | 275.07 seconds |
| Started | Jul 22 08:28:34 PM PDT 24 |
| Finished | Jul 22 08:33:10 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-964f4360-d020-454c-9434-acc4ba535fad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500213146 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.2500213146 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3517776445 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 7524029480 ps |
| CPU time | 1135.77 seconds |
| Started | Jul 22 08:29:03 PM PDT 24 |
| Finished | Jul 22 08:47:59 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-b1bef317-3264-43f3-91ba-e66fdc52888a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3517776445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3517776445 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1583316370 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 8539049300 ps |
| CPU time | 1418.37 seconds |
| Started | Jul 22 08:32:09 PM PDT 24 |
| Finished | Jul 22 08:55:48 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-cc699318-f45c-4653-8a06-51281c524d96 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1583316370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1583316370 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3723640849 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 8212128436 ps |
| CPU time | 1300.15 seconds |
| Started | Jul 22 08:29:31 PM PDT 24 |
| Finished | Jul 22 08:51:13 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-a92a96df-b541-4e45-b15a-06bea21732c7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3723640849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.3723640849 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1235221585 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 4276986960 ps |
| CPU time | 659.89 seconds |
| Started | Jul 22 08:32:03 PM PDT 24 |
| Finished | Jul 22 08:43:04 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-e2c50cf6-d2b8-476c-a53a-432bf724b689 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1235221585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1235221585 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.636544169 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 2799357824 ps |
| CPU time | 306.62 seconds |
| Started | Jul 22 08:34:00 PM PDT 24 |
| Finished | Jul 22 08:39:07 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-7b6c9a71-6f31-45a0-af3f-b4826c099f7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636544169 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.636544169 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.296956564 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2522953720 ps |
| CPU time | 176.97 seconds |
| Started | Jul 22 08:24:46 PM PDT 24 |
| Finished | Jul 22 08:27:44 PM PDT 24 |
| Peak memory | 613500 kb |
| Host | smart-4d6d806a-348a-4596-b513-9cd1078647c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296956564 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.296956564 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1551137529 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2658271600 ps |
| CPU time | 250.35 seconds |
| Started | Jul 22 08:34:18 PM PDT 24 |
| Finished | Jul 22 08:38:30 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-f049489d-9693-4cd1-8ff2-933bf69877a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551137529 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1551137529 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.538718065 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 4647188616 ps |
| CPU time | 672.55 seconds |
| Started | Jul 22 08:35:07 PM PDT 24 |
| Finished | Jul 22 08:46:21 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-f601101e-beb6-40ad-a1e2-68a5fcd15c62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538718065 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.538718065 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.1597990165 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 9485124108 ps |
| CPU time | 607.29 seconds |
| Started | Jul 22 08:36:02 PM PDT 24 |
| Finished | Jul 22 08:46:11 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-76887c3f-62cb-4cd0-ad48-f9626280af74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597990165 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1597990165 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2377382214 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 12141411009 ps |
| CPU time | 1470.44 seconds |
| Started | Jul 22 08:30:32 PM PDT 24 |
| Finished | Jul 22 08:55:04 PM PDT 24 |
| Peak memory | 611668 kb |
| Host | smart-10e22a24-9521-41ca-a103-ffc71f20465a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377 382214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2377382214 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2793142342 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 28793968425 ps |
| CPU time | 1869.57 seconds |
| Started | Jul 22 08:30:42 PM PDT 24 |
| Finished | Jul 22 09:01:53 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-fbd739e7-d631-458e-a595-af1026eec737 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279 3142342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2793142342 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.43327276 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 15456402432 ps |
| CPU time | 1100.54 seconds |
| Started | Jul 22 08:39:03 PM PDT 24 |
| Finished | Jul 22 08:57:24 PM PDT 24 |
| Peak memory | 611868 kb |
| Host | smart-4254c1a5-3e3b-41a4-b88f-d23919a3f94a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=43327276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.43327276 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1062824943 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 25554262312 ps |
| CPU time | 1759.65 seconds |
| Started | Jul 22 08:33:40 PM PDT 24 |
| Finished | Jul 22 09:03:01 PM PDT 24 |
| Peak memory | 611284 kb |
| Host | smart-752f7dd5-559c-400a-bd13-730a6bfa597a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1062824943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1062824943 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3484335183 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8789193296 ps |
| CPU time | 909.12 seconds |
| Started | Jul 22 08:28:57 PM PDT 24 |
| Finished | Jul 22 08:44:07 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-ae62300b-8ac8-4c78-b44b-e3b35f18a699 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484335183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3484335183 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2114163770 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 6968557128 ps |
| CPU time | 446.35 seconds |
| Started | Jul 22 08:27:13 PM PDT 24 |
| Finished | Jul 22 08:34:40 PM PDT 24 |
| Peak memory | 617756 kb |
| Host | smart-985ce9ea-124f-48e8-9178-7ac85d0e0f96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2114163770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2114163770 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2022349429 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 7030506050 ps |
| CPU time | 530.96 seconds |
| Started | Jul 22 08:30:17 PM PDT 24 |
| Finished | Jul 22 08:39:09 PM PDT 24 |
| Peak memory | 611404 kb |
| Host | smart-4ba5f21d-30a5-464e-b448-8b2d556a34f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022349429 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2022349429 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.60433085 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3613509332 ps |
| CPU time | 461.55 seconds |
| Started | Jul 22 08:36:18 PM PDT 24 |
| Finished | Jul 22 08:44:00 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-e7dc1f67-9d01-4b83-823e-7a387a8f1297 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60433085 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.60433085 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1406992637 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 5155468894 ps |
| CPU time | 568.71 seconds |
| Started | Jul 22 08:30:15 PM PDT 24 |
| Finished | Jul 22 08:39:45 PM PDT 24 |
| Peak memory | 617164 kb |
| Host | smart-c5cf2dbe-e24e-4a6d-a3dd-ecb90ba2d9b6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1406992637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1406992637 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2478408517 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 11269387961 ps |
| CPU time | 1389.59 seconds |
| Started | Jul 22 08:30:46 PM PDT 24 |
| Finished | Jul 22 08:53:56 PM PDT 24 |
| Peak memory | 612016 kb |
| Host | smart-f5366058-269a-43c0-933a-a45a1d12a369 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478408517 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2478408517 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3097789952 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 7087238028 ps |
| CPU time | 520.24 seconds |
| Started | Jul 22 08:33:28 PM PDT 24 |
| Finished | Jul 22 08:42:11 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-7fa7641b-440e-4567-9193-fc04bbd5a58a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097789952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3097789952 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3649207585 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 6166055785 ps |
| CPU time | 538.28 seconds |
| Started | Jul 22 08:41:28 PM PDT 24 |
| Finished | Jul 22 08:50:28 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-96500fc3-01f5-4037-8bc5-cfe069a3fe03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649207585 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3649207585 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2150560683 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 23584897311 ps |
| CPU time | 2615.22 seconds |
| Started | Jul 22 08:28:45 PM PDT 24 |
| Finished | Jul 22 09:12:22 PM PDT 24 |
| Peak memory | 611856 kb |
| Host | smart-6ea04c56-9387-49e5-9075-ad2d8507beb0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2150560683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2150560683 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4201483195 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 24840919548 ps |
| CPU time | 2039.67 seconds |
| Started | Jul 22 08:31:53 PM PDT 24 |
| Finished | Jul 22 09:05:54 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-c7bad1e6-5f5d-4b3c-aca1-a6ab6fe09524 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4201483195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4201483195 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2144570616 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 23114737400 ps |
| CPU time | 2468.16 seconds |
| Started | Jul 22 08:28:08 PM PDT 24 |
| Finished | Jul 22 09:09:17 PM PDT 24 |
| Peak memory | 611904 kb |
| Host | smart-639548d4-0b19-4779-84db-f12adf8b442b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144570616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2144570616 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1275132822 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5228300534 ps |
| CPU time | 460.4 seconds |
| Started | Jul 22 08:37:07 PM PDT 24 |
| Finished | Jul 22 08:44:49 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-3c4ce17b-a6cc-4e8d-baee-cc8dc7dabcd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1275132822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1275132822 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3330213323 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3500026764 ps |
| CPU time | 221.98 seconds |
| Started | Jul 22 08:28:39 PM PDT 24 |
| Finished | Jul 22 08:32:22 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-d24c52d0-5b52-4707-b19b-311d9a1ed06e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330213323 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.3330213323 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.288590587 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 5630658888 ps |
| CPU time | 615.87 seconds |
| Started | Jul 22 08:29:32 PM PDT 24 |
| Finished | Jul 22 08:39:48 PM PDT 24 |
| Peak memory | 617920 kb |
| Host | smart-0b715dd2-ef7c-40d9-a78d-7353af0e69db |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=288590587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.288590587 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2299581009 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4686664708 ps |
| CPU time | 420.36 seconds |
| Started | Jul 22 08:31:01 PM PDT 24 |
| Finished | Jul 22 08:38:02 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-bbeb8bc8-f13c-47c0-ab7a-38e62ea27ea1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22995810 09 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2299581009 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3407553481 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 6499074788 ps |
| CPU time | 658.37 seconds |
| Started | Jul 22 08:32:00 PM PDT 24 |
| Finished | Jul 22 08:43:00 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-2aadaf0f-aaf2-4d0f-83d0-3941a0354480 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3407553481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3407553481 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2484196790 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 5623176740 ps |
| CPU time | 586.79 seconds |
| Started | Jul 22 08:35:28 PM PDT 24 |
| Finished | Jul 22 08:45:15 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-c9ad06bc-6774-4526-83b6-42152581dfa7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484196790 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2484196790 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.167251513 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 8591537920 ps |
| CPU time | 1258.88 seconds |
| Started | Jul 22 08:28:50 PM PDT 24 |
| Finished | Jul 22 08:49:50 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-d6da98dc-52c8-46f6-b8b1-426fe5c277c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167251513 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.167251513 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3580226858 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 5304198200 ps |
| CPU time | 643.12 seconds |
| Started | Jul 22 08:28:45 PM PDT 24 |
| Finished | Jul 22 08:39:29 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-f80d59e1-07a7-4c18-a683-ad02d3a1b6ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580226858 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3580226858 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2263172060 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4998337680 ps |
| CPU time | 400.42 seconds |
| Started | Jul 22 08:36:12 PM PDT 24 |
| Finished | Jul 22 08:42:53 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-fd77283c-f6aa-4f3d-8b45-38c191cb1f15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263172060 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.2263172060 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3402952033 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 5582623076 ps |
| CPU time | 530.75 seconds |
| Started | Jul 22 08:29:33 PM PDT 24 |
| Finished | Jul 22 08:38:25 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-aa17a332-6640-419c-a771-f5326ae01484 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340 2952033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3402952033 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4203667136 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 8204691301 ps |
| CPU time | 543.39 seconds |
| Started | Jul 22 08:30:54 PM PDT 24 |
| Finished | Jul 22 08:39:58 PM PDT 24 |
| Peak memory | 624308 kb |
| Host | smart-ab78effa-5606-4e9e-8a3d-2b07fc7bbafd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203667136 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.4203667136 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1607022995 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5111429800 ps |
| CPU time | 497.96 seconds |
| Started | Jul 22 08:28:43 PM PDT 24 |
| Finished | Jul 22 08:37:02 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-2b4df2c7-2909-43da-ab31-4fbdc21b66dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607022995 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1607022995 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4213040738 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5024561620 ps |
| CPU time | 644.79 seconds |
| Started | Jul 22 08:26:16 PM PDT 24 |
| Finished | Jul 22 08:37:01 PM PDT 24 |
| Peak memory | 642004 kb |
| Host | smart-c3b36ab0-a5d5-4e8d-b9aa-d610a2858add |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4213040738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.4213040738 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2253603076 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2351066180 ps |
| CPU time | 241.93 seconds |
| Started | Jul 22 08:37:13 PM PDT 24 |
| Finished | Jul 22 08:41:16 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-8c8acfd3-cc85-43ef-b429-2a29e782bc2d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253603076 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2253603076 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3988072644 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4337174220 ps |
| CPU time | 374.51 seconds |
| Started | Jul 22 08:28:20 PM PDT 24 |
| Finished | Jul 22 08:34:36 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-f9e1c374-9201-4e3d-be9c-a19e6ce7ddef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988072644 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.3988072644 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3057376203 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2935551576 ps |
| CPU time | 372.35 seconds |
| Started | Jul 22 08:28:26 PM PDT 24 |
| Finished | Jul 22 08:34:39 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-b1daa489-ef37-4b0a-9ffd-5b65a8007fe2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057376203 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3057376203 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1542273012 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3102942760 ps |
| CPU time | 353.66 seconds |
| Started | Jul 22 08:32:02 PM PDT 24 |
| Finished | Jul 22 08:37:57 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-9c3bf8d6-5bb3-4c82-9909-e2c432ac37ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1542273012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1542273012 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.409389028 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2676854215 ps |
| CPU time | 207.93 seconds |
| Started | Jul 22 08:32:37 PM PDT 24 |
| Finished | Jul 22 08:36:05 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-f17558ac-31a1-4321-be5d-f1023e224f05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409389028 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.409389028 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2928933278 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4986059944 ps |
| CPU time | 894.05 seconds |
| Started | Jul 22 08:29:52 PM PDT 24 |
| Finished | Jul 22 08:44:48 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-bfd4f66e-f18d-4a5d-a3d1-4855aee33592 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29289 33278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2928933278 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2316156935 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 5386589240 ps |
| CPU time | 939.23 seconds |
| Started | Jul 22 08:31:53 PM PDT 24 |
| Finished | Jul 22 08:47:33 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-739c959e-befa-4192-97ba-dde74f1e9c32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2316156935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2316156935 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.461892789 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4826836521 ps |
| CPU time | 548.8 seconds |
| Started | Jul 22 08:37:13 PM PDT 24 |
| Finished | Jul 22 08:46:23 PM PDT 24 |
| Peak memory | 624240 kb |
| Host | smart-80e140ca-4fb4-4270-846c-bfc4434aa8c5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461892789 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.461892789 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1799741353 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6483731128 ps |
| CPU time | 663.31 seconds |
| Started | Jul 22 08:33:22 PM PDT 24 |
| Finished | Jul 22 08:44:27 PM PDT 24 |
| Peak memory | 624364 kb |
| Host | smart-fe0c8fd6-9966-454b-924d-73a1303d9b5f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799741353 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.1799741353 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.811229684 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 4932614056 ps |
| CPU time | 547.02 seconds |
| Started | Jul 22 08:33:34 PM PDT 24 |
| Finished | Jul 22 08:42:44 PM PDT 24 |
| Peak memory | 619696 kb |
| Host | smart-b072afe3-54a9-4b89-867f-4ea9cb01e94a |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811229 684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.811229684 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1482990867 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3118462280 ps |
| CPU time | 219.94 seconds |
| Started | Jul 22 08:37:09 PM PDT 24 |
| Finished | Jul 22 08:40:51 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-cd5518ec-497a-4d1d-a2dc-795857a4f1a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482990867 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1482990867 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.368205985 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 2450394256 ps |
| CPU time | 237.75 seconds |
| Started | Jul 22 08:28:48 PM PDT 24 |
| Finished | Jul 22 08:32:46 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-b1d5436e-ab2c-476c-8011-79cc4625cb0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368205985 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.368205985 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.97546309 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2180101236 ps |
| CPU time | 225.38 seconds |
| Started | Jul 22 08:36:58 PM PDT 24 |
| Finished | Jul 22 08:40:46 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-e880b852-e8d5-4802-be40-7e559381abef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97546309 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_timer_smoketest.97546309 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3318243889 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6391808120 ps |
| CPU time | 835.86 seconds |
| Started | Jul 22 08:31:57 PM PDT 24 |
| Finished | Jul 22 08:45:56 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-b136a0dc-574c-44f6-b2ee-48ad4f84be7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33182438 89 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3318243889 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3943077818 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 2760509981 ps |
| CPU time | 282.12 seconds |
| Started | Jul 22 08:33:25 PM PDT 24 |
| Finished | Jul 22 08:38:09 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-59336e73-1c87-4c3f-b11a-f4622577c61e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943077 818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3943077818 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.875831876 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3711085194 ps |
| CPU time | 371.29 seconds |
| Started | Jul 22 08:26:40 PM PDT 24 |
| Finished | Jul 22 08:32:52 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-08a9c06f-a1c7-4220-95e0-b224074ae9a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875831876 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.875831876 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.262684932 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 6604952656 ps |
| CPU time | 491.88 seconds |
| Started | Jul 22 08:27:39 PM PDT 24 |
| Finished | Jul 22 08:35:53 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-a308e261-4489-4f36-958d-24bc896137ef |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262684932 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.262684932 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.786180048 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 8761844180 ps |
| CPU time | 1397.34 seconds |
| Started | Jul 22 08:26:33 PM PDT 24 |
| Finished | Jul 22 08:49:51 PM PDT 24 |
| Peak memory | 611240 kb |
| Host | smart-d5b0dd9f-a785-44e2-ad9d-18c49e0fe440 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786180048 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.786180048 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3350392080 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 8672537152 ps |
| CPU time | 672.98 seconds |
| Started | Jul 22 08:31:25 PM PDT 24 |
| Finished | Jul 22 08:42:39 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-c7e02ae4-5c00-4a1e-bc97-827da9789b83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350392080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3350392080 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2874379305 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 7555099608 ps |
| CPU time | 847.04 seconds |
| Started | Jul 22 08:34:17 PM PDT 24 |
| Finished | Jul 22 08:48:25 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-cdae1716-d00c-4f62-948a-b42425c69ccf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874379305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2874379305 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1461816962 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6337712342 ps |
| CPU time | 605.28 seconds |
| Started | Jul 22 08:28:22 PM PDT 24 |
| Finished | Jul 22 08:38:28 PM PDT 24 |
| Peak memory | 625376 kb |
| Host | smart-93d3b4c7-2b5f-43fd-8470-fea5ca066a7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461816962 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1461816962 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1029524408 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4765727770 ps |
| CPU time | 597.79 seconds |
| Started | Jul 22 08:29:09 PM PDT 24 |
| Finished | Jul 22 08:39:07 PM PDT 24 |
| Peak memory | 625420 kb |
| Host | smart-b26b0db5-c080-4789-930b-1e534afcf616 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029524408 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1029524408 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2257574676 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3739583002 ps |
| CPU time | 340.99 seconds |
| Started | Jul 22 08:26:54 PM PDT 24 |
| Finished | Jul 22 08:32:36 PM PDT 24 |
| Peak memory | 618516 kb |
| Host | smart-35a5a516-76d6-4212-8a16-d48bd1268d2d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257574676 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2257574676 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.995765619 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3091685911 ps |
| CPU time | 403.79 seconds |
| Started | Jul 22 08:26:11 PM PDT 24 |
| Finished | Jul 22 08:32:56 PM PDT 24 |
| Peak memory | 618724 kb |
| Host | smart-45e17f34-aa33-4198-a9a0-0a53762988e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995765619 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.995765619 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1647952735 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3010819880 ps |
| CPU time | 281.98 seconds |
| Started | Jul 22 08:27:56 PM PDT 24 |
| Finished | Jul 22 08:32:41 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-468449e0-ed05-47f5-aff4-cbc77c6ec432 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647952735 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1647952735 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3525516300 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 9674779399 ps |
| CPU time | 1015.35 seconds |
| Started | Jul 22 08:31:59 PM PDT 24 |
| Finished | Jul 22 08:48:56 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-23acbe2a-a57d-4f18-aad4-e9e650816aa7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525516300 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3525516300 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.213938911 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3640970040 ps |
| CPU time | 451.19 seconds |
| Started | Jul 22 08:32:02 PM PDT 24 |
| Finished | Jul 22 08:39:34 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-1b8c91a5-d0ab-49a7-aedd-fb486dd6c975 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213938911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.213938911 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1020461968 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5881799685 ps |
| CPU time | 863.74 seconds |
| Started | Jul 22 08:31:36 PM PDT 24 |
| Finished | Jul 22 08:46:01 PM PDT 24 |
| Peak memory | 611580 kb |
| Host | smart-be65d17a-89cb-435b-8709-88457558c9de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020461968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1020461968 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.478937818 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4527771915 ps |
| CPU time | 785.67 seconds |
| Started | Jul 22 08:33:45 PM PDT 24 |
| Finished | Jul 22 08:46:52 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-046483d3-05ec-40d0-ba19-f7b20a235cf1 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478937818 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.478937818 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3292824973 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2904440742 ps |
| CPU time | 241.72 seconds |
| Started | Jul 22 08:35:17 PM PDT 24 |
| Finished | Jul 22 08:39:21 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-e780143b-66e1-4460-8383-8e6337474793 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292824973 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3292824973 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.428507514 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 20059960596 ps |
| CPU time | 3085.46 seconds |
| Started | Jul 22 08:29:25 PM PDT 24 |
| Finished | Jul 22 09:20:52 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-dd231678-4af3-4b8d-9fa5-e5bc9e50b5a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428507514 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.428507514 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3834526049 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 5206478220 ps |
| CPU time | 794.18 seconds |
| Started | Jul 22 08:28:47 PM PDT 24 |
| Finished | Jul 22 08:42:03 PM PDT 24 |
| Peak memory | 614332 kb |
| Host | smart-bdeb56ae-2cf9-44ec-a182-2873f7ec505c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834526049 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3834526049 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.268517556 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3246898129 ps |
| CPU time | 366.85 seconds |
| Started | Jul 22 08:30:54 PM PDT 24 |
| Finished | Jul 22 08:37:03 PM PDT 24 |
| Peak memory | 614008 kb |
| Host | smart-7ab71819-50b8-49a7-add5-bf348da63273 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268517556 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.268517556 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3050532242 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3245204758 ps |
| CPU time | 402.47 seconds |
| Started | Jul 22 08:41:52 PM PDT 24 |
| Finished | Jul 22 08:48:36 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-f738573d-bbd8-44df-bb99-dc4a1f340be6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050532242 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3050532242 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3805493343 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 25477440316 ps |
| CPU time | 1633.18 seconds |
| Started | Jul 22 08:31:23 PM PDT 24 |
| Finished | Jul 22 08:58:38 PM PDT 24 |
| Peak memory | 615360 kb |
| Host | smart-7d4e07ef-1aeb-4bb7-bced-a3a8f0fb40a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38054933 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.3805493343 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1405112307 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6302946550 ps |
| CPU time | 560.45 seconds |
| Started | Jul 22 08:28:01 PM PDT 24 |
| Finished | Jul 22 08:37:22 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-f3bed6ac-7b2e-453b-b5e8-8e01977e12bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405112307 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1405112307 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1961187989 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3994425640 ps |
| CPU time | 566.8 seconds |
| Started | Jul 22 08:30:06 PM PDT 24 |
| Finished | Jul 22 08:39:33 PM PDT 24 |
| Peak memory | 619212 kb |
| Host | smart-3163feaa-bc21-4b13-96b3-a9845973c691 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1961187989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1961187989 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.2652561705 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2919098900 ps |
| CPU time | 203.32 seconds |
| Started | Jul 22 08:40:03 PM PDT 24 |
| Finished | Jul 22 08:43:27 PM PDT 24 |
| Peak memory | 617544 kb |
| Host | smart-60608386-87df-4db6-a6c7-537c42b6e6d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652561705 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2652561705 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.3886361524 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 4423970028 ps |
| CPU time | 728.81 seconds |
| Started | Jul 22 08:25:50 PM PDT 24 |
| Finished | Jul 22 08:38:01 PM PDT 24 |
| Peak memory | 625140 kb |
| Host | smart-12ddbea3-4331-4f06-849e-e46994edd8a0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886361524 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3886361524 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3742737114 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 8384343242 ps |
| CPU time | 1908.46 seconds |
| Started | Jul 22 08:26:48 PM PDT 24 |
| Finished | Jul 22 08:58:38 PM PDT 24 |
| Peak memory | 625136 kb |
| Host | smart-e504e8b8-d1c2-445f-8052-67b12be1c872 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742737114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3742737114 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.475327158 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 78538965802 ps |
| CPU time | 13853.3 seconds |
| Started | Jul 22 08:28:27 PM PDT 24 |
| Finished | Jul 23 12:19:23 AM PDT 24 |
| Peak memory | 634480 kb |
| Host | smart-1c09c082-7c58-485f-a322-b73d4ecc2eef |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=475327158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.475327158 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3993798206 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 4461528536 ps |
| CPU time | 684.54 seconds |
| Started | Jul 22 08:26:14 PM PDT 24 |
| Finished | Jul 22 08:37:39 PM PDT 24 |
| Peak memory | 625136 kb |
| Host | smart-52da0a4b-62e9-4ca1-b732-6885641319ea |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993798206 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.3993798206 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1887834687 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3852820720 ps |
| CPU time | 685.48 seconds |
| Started | Jul 22 08:26:17 PM PDT 24 |
| Finished | Jul 22 08:37:44 PM PDT 24 |
| Peak memory | 625252 kb |
| Host | smart-66de02b8-484e-480a-af1a-53b35fd659ee |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887834687 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1887834687 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1270638630 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4231732400 ps |
| CPU time | 664.93 seconds |
| Started | Jul 22 08:28:26 PM PDT 24 |
| Finished | Jul 22 08:39:32 PM PDT 24 |
| Peak memory | 625152 kb |
| Host | smart-f47c6a77-536a-4e70-9da4-3b50a43ce525 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270638630 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1270638630 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.3948752948 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 12148042263 ps |
| CPU time | 1107.3 seconds |
| Started | Jul 22 08:36:16 PM PDT 24 |
| Finished | Jul 22 08:54:44 PM PDT 24 |
| Peak memory | 621400 kb |
| Host | smart-f2b93985-2024-4c5c-a4f0-d46e2c4886b2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3948752948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3948752948 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.1981920481 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 3179162073 ps |
| CPU time | 153.12 seconds |
| Started | Jul 22 08:31:54 PM PDT 24 |
| Finished | Jul 22 08:34:29 PM PDT 24 |
| Peak memory | 621796 kb |
| Host | smart-2cb55eb5-14fa-4754-adff-9ddb80cc1e11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981920481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1981920481 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.753952068 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 7107029698 ps |
| CPU time | 512.41 seconds |
| Started | Jul 22 08:30:38 PM PDT 24 |
| Finished | Jul 22 08:39:11 PM PDT 24 |
| Peak memory | 622432 kb |
| Host | smart-4bab9aef-b5a8-4928-91b8-aca6da554099 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=753952068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.753952068 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1612276526 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 15613676784 ps |
| CPU time | 3574.95 seconds |
| Started | Jul 22 08:38:23 PM PDT 24 |
| Finished | Jul 22 09:37:59 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-e278c005-86ef-4141-95b0-b50ff5ceeee5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612276526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1612276526 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2878201876 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 16202700584 ps |
| CPU time | 3610.51 seconds |
| Started | Jul 22 08:39:01 PM PDT 24 |
| Finished | Jul 22 09:39:13 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-180d0413-c531-4fc7-ad90-16a73d696fc9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878201876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2878201876 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.516185213 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 15877510100 ps |
| CPU time | 3202.89 seconds |
| Started | Jul 22 08:38:42 PM PDT 24 |
| Finished | Jul 22 09:32:10 PM PDT 24 |
| Peak memory | 611844 kb |
| Host | smart-c1d8c33c-9e07-4700-8ae4-5db6b5c186b6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516185213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.rom_e2e_asm_init_prod_end.516185213 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.417331831 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 14153130673 ps |
| CPU time | 3119.46 seconds |
| Started | Jul 22 08:39:39 PM PDT 24 |
| Finished | Jul 22 09:31:40 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-ff9030ec-8723-46dd-b911-4625e2cf4468 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417331831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.417331831 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2581805813 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 11229559706 ps |
| CPU time | 2430 seconds |
| Started | Jul 22 08:37:49 PM PDT 24 |
| Finished | Jul 22 09:18:20 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-b67c67c3-17c0-47e3-9d6b-5c0935d40abd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581805813 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2581805813 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1181054806 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 14696563128 ps |
| CPU time | 3342.41 seconds |
| Started | Jul 22 08:37:36 PM PDT 24 |
| Finished | Jul 22 09:33:20 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-f8716ec2-7b6b-46df-86ef-b95ff033bd40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181054806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1181054806 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3201724035 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 15557520904 ps |
| CPU time | 3791.34 seconds |
| Started | Jul 22 08:40:08 PM PDT 24 |
| Finished | Jul 22 09:43:21 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-f005023c-68ea-4b69-9817-b3239a18645b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201724035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3201724035 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1087936621 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 14931329420 ps |
| CPU time | 3816.72 seconds |
| Started | Jul 22 08:40:24 PM PDT 24 |
| Finished | Jul 22 09:44:02 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-047e03c4-ebb2-4a19-8758-a23621b5f580 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087936621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1087936621 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.3976374565 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 25733766080 ps |
| CPU time | 4932.28 seconds |
| Started | Jul 22 08:40:20 PM PDT 24 |
| Finished | Jul 22 10:02:33 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-6fe7cb9a-526c-4216-bad7-07c01127863c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976374565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3976374565 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3202157352 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 15002968924 ps |
| CPU time | 3074.94 seconds |
| Started | Jul 22 08:40:47 PM PDT 24 |
| Finished | Jul 22 09:32:04 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-d0a2d59f-daa1-4a35-9bae-b42096312e4c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202157352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.3202157352 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.3637768731 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 25674851842 ps |
| CPU time | 3461.51 seconds |
| Started | Jul 22 08:40:54 PM PDT 24 |
| Finished | Jul 22 09:38:38 PM PDT 24 |
| Peak memory | 612172 kb |
| Host | smart-e426b570-b2d9-4788-91a5-c1285608d42d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637768731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3637768731 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.3120927026 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 14537636120 ps |
| CPU time | 3147.71 seconds |
| Started | Jul 22 08:38:51 PM PDT 24 |
| Finished | Jul 22 09:31:20 PM PDT 24 |
| Peak memory | 611832 kb |
| Host | smart-e8e9f0c1-562e-463f-badd-a307d6d74afa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3120927026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3120927026 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.3502798771 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 17055594872 ps |
| CPU time | 4061.52 seconds |
| Started | Jul 22 08:40:22 PM PDT 24 |
| Finished | Jul 22 09:48:05 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-0ea392db-49e6-47e9-b7da-eee3ada2fca2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502798771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3502798771 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3987987147 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 3958540968 ps |
| CPU time | 625.73 seconds |
| Started | Jul 22 08:35:39 PM PDT 24 |
| Finished | Jul 22 08:46:06 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-8f9fd5e5-cace-451d-900f-c479ad116961 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987987147 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3987987147 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.1188824861 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 4399538155 ps |
| CPU time | 233.84 seconds |
| Started | Jul 22 08:35:45 PM PDT 24 |
| Finished | Jul 22 08:39:41 PM PDT 24 |
| Peak memory | 619652 kb |
| Host | smart-f3abc189-cbea-44c1-bc0e-a093a18864af |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1188824861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1188824861 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.1941499699 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1880829468 ps |
| CPU time | 109.71 seconds |
| Started | Jul 22 08:33:55 PM PDT 24 |
| Finished | Jul 22 08:35:46 PM PDT 24 |
| Peak memory | 623352 kb |
| Host | smart-00ca4cd4-3a5e-4ccb-88d5-ac0d4d7d5398 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941499699 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1941499699 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.626341560 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 4151418808 ps |
| CPU time | 458.71 seconds |
| Started | Jul 22 08:41:15 PM PDT 24 |
| Finished | Jul 22 08:48:57 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-9f58ff26-5a97-48a1-acfc-e50c8cd1793f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 626341560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.626341560 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388633946 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3025733320 ps |
| CPU time | 419.44 seconds |
| Started | Jul 22 08:42:16 PM PDT 24 |
| Finished | Jul 22 08:49:16 PM PDT 24 |
| Peak memory | 649152 kb |
| Host | smart-ac6a9801-4b85-4570-b4cd-f74a23d49427 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388633946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3388633946 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1746076753 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5102963000 ps |
| CPU time | 577.09 seconds |
| Started | Jul 22 08:42:12 PM PDT 24 |
| Finished | Jul 22 08:51:50 PM PDT 24 |
| Peak memory | 620068 kb |
| Host | smart-7527e639-90a9-403f-931d-f0837b137930 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1746076753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1746076753 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.580766623 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 5201659880 ps |
| CPU time | 502.14 seconds |
| Started | Jul 22 08:41:41 PM PDT 24 |
| Finished | Jul 22 08:50:04 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-02830959-6eaa-49a0-9e3f-a599c45b5dcb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 580766623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.580766623 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.3705384966 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5411936260 ps |
| CPU time | 617.61 seconds |
| Started | Jul 22 08:41:31 PM PDT 24 |
| Finished | Jul 22 08:51:50 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-e27f713d-02c4-4b1f-97b0-11ff64c25cee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3705384966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3705384966 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.487987314 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4453354096 ps |
| CPU time | 587.42 seconds |
| Started | Jul 22 08:41:57 PM PDT 24 |
| Finished | Jul 22 08:51:46 PM PDT 24 |
| Peak memory | 650392 kb |
| Host | smart-5489254a-48f5-4cfe-a348-62a00b4df4a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 487987314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.487987314 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239380962 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 3567313720 ps |
| CPU time | 373.17 seconds |
| Started | Jul 22 08:40:33 PM PDT 24 |
| Finished | Jul 22 08:46:48 PM PDT 24 |
| Peak memory | 649212 kb |
| Host | smart-e3787d39-587b-44f2-8510-73ead1f43488 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239380962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2239380962 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.4028392195 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3877915672 ps |
| CPU time | 643.55 seconds |
| Started | Jul 22 08:40:16 PM PDT 24 |
| Finished | Jul 22 08:51:00 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-126ddda3-2d21-467f-882d-7c60a75a63b8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4028392195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.4028392195 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294185603 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4275986970 ps |
| CPU time | 435.61 seconds |
| Started | Jul 22 08:41:32 PM PDT 24 |
| Finished | Jul 22 08:48:48 PM PDT 24 |
| Peak memory | 649160 kb |
| Host | smart-489c9d30-16c2-43d0-b7d5-536a8727b269 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294185603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3294185603 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.620576956 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 7084197462 ps |
| CPU time | 360.07 seconds |
| Started | Jul 22 08:36:41 PM PDT 24 |
| Finished | Jul 22 08:42:42 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-29d2f2dd-3c61-4fd7-a24b-c3a5465230e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=620576956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.620576956 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2833207613 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 11341545126 ps |
| CPU time | 2649.37 seconds |
| Started | Jul 22 08:37:41 PM PDT 24 |
| Finished | Jul 22 09:21:51 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-8ddc3a6c-8dbf-48bb-a444-7f94e1fc77aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833207613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2833207613 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.118500539 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 6042715744 ps |
| CPU time | 552.35 seconds |
| Started | Jul 22 08:37:44 PM PDT 24 |
| Finished | Jul 22 08:46:57 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-c9fbc8cd-4c59-437c-8655-013f73fe9d64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=118500539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.118500539 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.823326917 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 13435759005 ps |
| CPU time | 968.57 seconds |
| Started | Jul 22 08:38:10 PM PDT 24 |
| Finished | Jul 22 08:54:20 PM PDT 24 |
| Peak memory | 624056 kb |
| Host | smart-96be69fa-7fda-4aae-9d96-cf9b7ed3fc29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823326917 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.823326917 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2560770603 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 4002911840 ps |
| CPU time | 581.57 seconds |
| Started | Jul 22 08:37:08 PM PDT 24 |
| Finished | Jul 22 08:46:52 PM PDT 24 |
| Peak memory | 619528 kb |
| Host | smart-a22f5e89-862a-4598-b8b5-5e95ede47979 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2560770603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.2560770603 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.3398089830 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 4375801162 ps |
| CPU time | 665.62 seconds |
| Started | Jul 22 08:35:53 PM PDT 24 |
| Finished | Jul 22 08:47:00 PM PDT 24 |
| Peak memory | 623072 kb |
| Host | smart-49ef266d-efdf-4585-b082-1c063738be71 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398089830 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3398089830 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.314051444 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 4499889003 ps |
| CPU time | 596.57 seconds |
| Started | Jul 22 08:35:38 PM PDT 24 |
| Finished | Jul 22 08:45:37 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-90b6a298-d505-4135-acb7-eb782d71989c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314051444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq.314051444 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1861414810 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3980616217 ps |
| CPU time | 462.65 seconds |
| Started | Jul 22 08:38:11 PM PDT 24 |
| Finished | Jul 22 08:45:56 PM PDT 24 |
| Peak memory | 625172 kb |
| Host | smart-6e4a446f-e57c-4076-9079-d121bb623ce8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861414810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1861414810 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.657777749 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4344282912 ps |
| CPU time | 664.72 seconds |
| Started | Jul 22 08:35:27 PM PDT 24 |
| Finished | Jul 22 08:46:32 PM PDT 24 |
| Peak memory | 625148 kb |
| Host | smart-910055fc-33cc-42a0-a427-ef23a697cf80 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657777749 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.657777749 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3249434224 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4519837450 ps |
| CPU time | 577.89 seconds |
| Started | Jul 22 08:36:46 PM PDT 24 |
| Finished | Jul 22 08:46:26 PM PDT 24 |
| Peak memory | 625180 kb |
| Host | smart-a2e5c651-5135-455a-8b1c-ee49cf4f0f2d |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249434224 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3249434224 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2335743947 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 4066799528 ps |
| CPU time | 788.03 seconds |
| Started | Jul 22 08:35:21 PM PDT 24 |
| Finished | Jul 22 08:48:30 PM PDT 24 |
| Peak memory | 622884 kb |
| Host | smart-1c7268d9-d574-47ec-b12e-696ef409c779 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335743947 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2335743947 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.122827320 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 7898851965 ps |
| CPU time | 859.5 seconds |
| Started | Jul 22 08:36:13 PM PDT 24 |
| Finished | Jul 22 08:50:33 PM PDT 24 |
| Peak memory | 621568 kb |
| Host | smart-0e898027-e614-4999-8ad0-38be4761ab74 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=122827320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.122827320 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.2757025157 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 2694255454 ps |
| CPU time | 147.62 seconds |
| Started | Jul 22 08:35:42 PM PDT 24 |
| Finished | Jul 22 08:38:11 PM PDT 24 |
| Peak memory | 620476 kb |
| Host | smart-253d44c1-f337-4087-933b-27352f0f4122 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757025157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2757025157 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.3674079162 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 2784397320 ps |
| CPU time | 181.5 seconds |
| Started | Jul 22 08:35:39 PM PDT 24 |
| Finished | Jul 22 08:38:42 PM PDT 24 |
| Peak memory | 622056 kb |
| Host | smart-3a4d770e-bb21-461b-8e90-66b22741f98f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674079162 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.3674079162 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.1699486679 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 4750466870 ps |
| CPU time | 588.56 seconds |
| Started | Jul 22 08:40:37 PM PDT 24 |
| Finished | Jul 22 08:50:26 PM PDT 24 |
| Peak memory | 650664 kb |
| Host | smart-77d8771c-7b2b-480b-b5a4-a41eada2df2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1699486679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1699486679 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.161529752 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4176842656 ps |
| CPU time | 336.38 seconds |
| Started | Jul 22 08:41:24 PM PDT 24 |
| Finished | Jul 22 08:47:01 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-9d4e5e25-7ac6-4226-b808-58023ea84865 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161529752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s w_alert_handler_lpg_sleep_mode_alerts.161529752 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.1358749823 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 5283959404 ps |
| CPU time | 590.56 seconds |
| Started | Jul 22 08:41:34 PM PDT 24 |
| Finished | Jul 22 08:51:26 PM PDT 24 |
| Peak memory | 650096 kb |
| Host | smart-017c56a7-f8dc-4b6c-8e32-dd038358c2ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1358749823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.1358749823 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725898983 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3367436006 ps |
| CPU time | 362.42 seconds |
| Started | Jul 22 08:41:35 PM PDT 24 |
| Finished | Jul 22 08:47:38 PM PDT 24 |
| Peak memory | 649284 kb |
| Host | smart-3f866818-b1fa-43d2-a3b2-eb6297ab43e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725898983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3725898983 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.508061720 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5267340212 ps |
| CPU time | 528.46 seconds |
| Started | Jul 22 08:41:30 PM PDT 24 |
| Finished | Jul 22 08:50:20 PM PDT 24 |
| Peak memory | 650812 kb |
| Host | smart-0872ac90-31a8-49a7-8ab2-5db4e836eab9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 508061720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.508061720 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2859649123 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4027480876 ps |
| CPU time | 401.47 seconds |
| Started | Jul 22 08:40:54 PM PDT 24 |
| Finished | Jul 22 08:47:37 PM PDT 24 |
| Peak memory | 649268 kb |
| Host | smart-220eac68-9e41-4ebf-8884-6b01d159a012 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859649123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2859649123 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.595068465 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6070666898 ps |
| CPU time | 881.85 seconds |
| Started | Jul 22 08:41:08 PM PDT 24 |
| Finished | Jul 22 08:55:52 PM PDT 24 |
| Peak memory | 621196 kb |
| Host | smart-2c8f1ae7-2342-4014-873e-d2b2a7f51e66 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 595068465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.595068465 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3081955853 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3553586884 ps |
| CPU time | 386.39 seconds |
| Started | Jul 22 08:41:09 PM PDT 24 |
| Finished | Jul 22 08:47:37 PM PDT 24 |
| Peak memory | 649220 kb |
| Host | smart-435f2508-0c7f-42cb-ad06-9ea75af666b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081955853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3081955853 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1785714643 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3250526278 ps |
| CPU time | 314.04 seconds |
| Started | Jul 22 08:43:54 PM PDT 24 |
| Finished | Jul 22 08:49:11 PM PDT 24 |
| Peak memory | 648956 kb |
| Host | smart-79e513dc-c3f8-45ad-bcd8-32b9b5149651 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785714643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1785714643 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3533102476 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4901127504 ps |
| CPU time | 469.5 seconds |
| Started | Jul 22 08:41:50 PM PDT 24 |
| Finished | Jul 22 08:49:40 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-9d60d893-0c18-4a80-bd73-94b26965f6be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3533102476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3533102476 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1191365626 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3886666248 ps |
| CPU time | 340.94 seconds |
| Started | Jul 22 08:41:36 PM PDT 24 |
| Finished | Jul 22 08:47:18 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-84254ff9-d0be-4a5f-aa95-b0d49f1015c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191365626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1191365626 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.2942612382 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4734096248 ps |
| CPU time | 523.09 seconds |
| Started | Jul 22 08:43:47 PM PDT 24 |
| Finished | Jul 22 08:52:31 PM PDT 24 |
| Peak memory | 650408 kb |
| Host | smart-c4671f57-45c1-4bac-b55c-1f4475acc9d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2942612382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2942612382 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.473366911 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 5098270770 ps |
| CPU time | 751.17 seconds |
| Started | Jul 22 08:37:52 PM PDT 24 |
| Finished | Jul 22 08:50:25 PM PDT 24 |
| Peak memory | 650532 kb |
| Host | smart-dd3bb225-d9aa-4dcc-a92b-d41109738cdb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 473366911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.473366911 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1684324882 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 7022021076 ps |
| CPU time | 407.78 seconds |
| Started | Jul 22 08:37:31 PM PDT 24 |
| Finished | Jul 22 08:44:20 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-f25ea462-2043-4571-9141-c2978d21fe26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1684324882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1684324882 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1966749959 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 14609338688 ps |
| CPU time | 3514.74 seconds |
| Started | Jul 22 08:36:26 PM PDT 24 |
| Finished | Jul 22 09:35:02 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-4ca8cd0a-30a6-4e89-91c8-6be3a51af399 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966749959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.1966749959 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2096795136 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4488490908 ps |
| CPU time | 696.93 seconds |
| Started | Jul 22 08:38:38 PM PDT 24 |
| Finished | Jul 22 08:50:18 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-cc8a7f6e-b1c7-4c21-993a-fc392c61d525 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2096795136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2096795136 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3554098330 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 12657009200 ps |
| CPU time | 1288.72 seconds |
| Started | Jul 22 08:35:53 PM PDT 24 |
| Finished | Jul 22 08:57:23 PM PDT 24 |
| Peak memory | 625244 kb |
| Host | smart-d6f3a644-4f97-4a4a-b309-95122504680f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554098330 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3554098330 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4169335370 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6914656480 ps |
| CPU time | 983.36 seconds |
| Started | Jul 22 08:38:08 PM PDT 24 |
| Finished | Jul 22 08:54:33 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-7915378a-ecd0-4579-94c2-b2cee02f7dc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693353 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4169335370 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2573434865 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 4483300488 ps |
| CPU time | 589.13 seconds |
| Started | Jul 22 08:36:18 PM PDT 24 |
| Finished | Jul 22 08:46:08 PM PDT 24 |
| Peak memory | 619484 kb |
| Host | smart-6915f93c-b2b3-4415-9127-ae2cd5594659 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2573434865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2573434865 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.4092496222 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4182878070 ps |
| CPU time | 603.25 seconds |
| Started | Jul 22 08:36:41 PM PDT 24 |
| Finished | Jul 22 08:46:46 PM PDT 24 |
| Peak memory | 625104 kb |
| Host | smart-483544c8-f0db-489d-a704-b365f70e15a0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092496222 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.4092496222 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.265928348 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 4102001026 ps |
| CPU time | 603.37 seconds |
| Started | Jul 22 08:36:55 PM PDT 24 |
| Finished | Jul 22 08:47:00 PM PDT 24 |
| Peak memory | 625100 kb |
| Host | smart-03eb23a0-5574-4131-a068-b7bd9d5ff89b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265928348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq.265928348 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1982464068 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 5068983618 ps |
| CPU time | 503.91 seconds |
| Started | Jul 22 08:36:49 PM PDT 24 |
| Finished | Jul 22 08:45:15 PM PDT 24 |
| Peak memory | 625204 kb |
| Host | smart-05111309-b8e8-4cbb-be5e-bf34c7d30a78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982464068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1982464068 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3811725283 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 3888180638 ps |
| CPU time | 620.42 seconds |
| Started | Jul 22 08:36:17 PM PDT 24 |
| Finished | Jul 22 08:46:38 PM PDT 24 |
| Peak memory | 625256 kb |
| Host | smart-bc8a0fa9-1abc-4145-b8b9-8382f3a90e29 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811725283 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3811725283 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2636385372 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 4562953064 ps |
| CPU time | 715.28 seconds |
| Started | Jul 22 08:37:29 PM PDT 24 |
| Finished | Jul 22 08:49:25 PM PDT 24 |
| Peak memory | 625192 kb |
| Host | smart-33ce8150-acd5-4411-9d46-751aa1ecfd30 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636385372 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2636385372 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4224448379 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4799514010 ps |
| CPU time | 632.07 seconds |
| Started | Jul 22 08:38:42 PM PDT 24 |
| Finished | Jul 22 08:49:18 PM PDT 24 |
| Peak memory | 625132 kb |
| Host | smart-366a735b-c68a-44c8-a6cb-94c50cac13b0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224448379 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.4224448379 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.2716353949 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 13365698221 ps |
| CPU time | 1190.93 seconds |
| Started | Jul 22 08:36:33 PM PDT 24 |
| Finished | Jul 22 08:56:25 PM PDT 24 |
| Peak memory | 621436 kb |
| Host | smart-1aa62b4e-0608-451c-9c42-5f3f83868ec0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716353949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2716353949 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.2819268642 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4345883050 ps |
| CPU time | 278.7 seconds |
| Started | Jul 22 08:36:25 PM PDT 24 |
| Finished | Jul 22 08:41:05 PM PDT 24 |
| Peak memory | 621444 kb |
| Host | smart-cfd5231c-175f-41fd-b17f-0027e8771091 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819268642 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2819268642 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133461303 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3219767900 ps |
| CPU time | 383.97 seconds |
| Started | Jul 22 08:44:16 PM PDT 24 |
| Finished | Jul 22 08:50:41 PM PDT 24 |
| Peak memory | 649280 kb |
| Host | smart-eff9a127-2a03-4f4a-8e08-face0db60291 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133461303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3133461303 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.2763582437 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5943329076 ps |
| CPU time | 534.29 seconds |
| Started | Jul 22 08:41:29 PM PDT 24 |
| Finished | Jul 22 08:50:25 PM PDT 24 |
| Peak memory | 650392 kb |
| Host | smart-1723b735-c567-457d-bab0-bfaca879866e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2763582437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.2763582437 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872876370 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3262709240 ps |
| CPU time | 365.48 seconds |
| Started | Jul 22 08:43:13 PM PDT 24 |
| Finished | Jul 22 08:49:20 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-c3cdbace-093a-4204-ab7e-04a27da94ec2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872876370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1872876370 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330070047 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3504148840 ps |
| CPU time | 416.34 seconds |
| Started | Jul 22 08:44:16 PM PDT 24 |
| Finished | Jul 22 08:51:13 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-26db76d2-ae33-449d-b3cb-977daa0becfe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330070047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1330070047 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.482362044 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4693387976 ps |
| CPU time | 547.11 seconds |
| Started | Jul 22 08:43:12 PM PDT 24 |
| Finished | Jul 22 08:52:20 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-9ddffd90-83bb-4e2f-ad3b-53998483b8bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 482362044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.482362044 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.429181648 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 4144523016 ps |
| CPU time | 364.19 seconds |
| Started | Jul 22 08:42:38 PM PDT 24 |
| Finished | Jul 22 08:48:43 PM PDT 24 |
| Peak memory | 619276 kb |
| Host | smart-80300a66-74aa-48f6-90bf-e25dd286e213 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429181648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.429181648 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3172671204 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4518050112 ps |
| CPU time | 562.75 seconds |
| Started | Jul 22 08:40:29 PM PDT 24 |
| Finished | Jul 22 08:49:55 PM PDT 24 |
| Peak memory | 650880 kb |
| Host | smart-59e6d2c1-a640-4f9b-a70b-bf11f3cec97d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3172671204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3172671204 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.1700264322 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5595837208 ps |
| CPU time | 716.12 seconds |
| Started | Jul 22 08:41:07 PM PDT 24 |
| Finished | Jul 22 08:53:04 PM PDT 24 |
| Peak memory | 650708 kb |
| Host | smart-f423a148-2436-4512-8c0a-6f000999b991 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1700264322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1700264322 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545375256 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3335279322 ps |
| CPU time | 362.03 seconds |
| Started | Jul 22 08:38:43 PM PDT 24 |
| Finished | Jul 22 08:44:50 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-4f20de57-f806-4f1d-a3fb-49cb4255cb0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545375256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.1545375256 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.1510101985 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4817093768 ps |
| CPU time | 691.24 seconds |
| Started | Jul 22 08:40:00 PM PDT 24 |
| Finished | Jul 22 08:51:34 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-ce0a04fc-aa53-4b55-a829-758113f84362 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1510101985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1510101985 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1067392742 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 17983993478 ps |
| CPU time | 3328.99 seconds |
| Started | Jul 22 08:41:18 PM PDT 24 |
| Finished | Jul 22 09:36:50 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-86bf04d4-5eec-4489-ae4e-a6a3357e7ef5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067392742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1067392742 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4291291381 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5250869384 ps |
| CPU time | 793.86 seconds |
| Started | Jul 22 08:37:02 PM PDT 24 |
| Finished | Jul 22 08:50:20 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-e68c3c88-b9de-4c21-8504-55e6a9b9db8b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4291291381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.4291291381 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2197361140 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 7429399412 ps |
| CPU time | 611.95 seconds |
| Started | Jul 22 08:39:32 PM PDT 24 |
| Finished | Jul 22 08:49:45 PM PDT 24 |
| Peak memory | 620932 kb |
| Host | smart-db0fd4c3-de73-4a1b-abbc-f12a7c930bc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197361140 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2197361140 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1820280365 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 8238926040 ps |
| CPU time | 1338.48 seconds |
| Started | Jul 22 08:38:04 PM PDT 24 |
| Finished | Jul 22 09:00:25 PM PDT 24 |
| Peak memory | 619528 kb |
| Host | smart-932c848c-0a49-4798-8d71-472d3cce22f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1820280365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.1820280365 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.1806730461 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5755593402 ps |
| CPU time | 545.33 seconds |
| Started | Jul 22 08:42:28 PM PDT 24 |
| Finished | Jul 22 08:51:35 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-81cfa283-110b-41ca-bff9-fdbaece8f66c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1806730461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1806730461 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.1999123610 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4843640160 ps |
| CPU time | 595.48 seconds |
| Started | Jul 22 08:42:06 PM PDT 24 |
| Finished | Jul 22 08:52:03 PM PDT 24 |
| Peak memory | 650404 kb |
| Host | smart-7dfc5c6e-6463-4ecb-8545-5a0e55a0cae2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1999123610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1999123610 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2276595944 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3277877550 ps |
| CPU time | 422.35 seconds |
| Started | Jul 22 08:45:25 PM PDT 24 |
| Finished | Jul 22 08:52:28 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-b09893be-8ace-4efe-a92f-28b5ee7d716a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276595944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2276595944 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.904391936 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5257853300 ps |
| CPU time | 514.53 seconds |
| Started | Jul 22 08:44:46 PM PDT 24 |
| Finished | Jul 22 08:53:21 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-397a493d-37b5-4dbf-9918-20f7ace749a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 904391936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.904391936 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.808806856 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3873527660 ps |
| CPU time | 448.44 seconds |
| Started | Jul 22 08:43:29 PM PDT 24 |
| Finished | Jul 22 08:50:58 PM PDT 24 |
| Peak memory | 649172 kb |
| Host | smart-ad13de0e-8e66-47f6-98fd-9cb022ccf4e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808806856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s w_alert_handler_lpg_sleep_mode_alerts.808806856 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1084369322 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 6366750946 ps |
| CPU time | 657.12 seconds |
| Started | Jul 22 08:42:18 PM PDT 24 |
| Finished | Jul 22 08:53:16 PM PDT 24 |
| Peak memory | 650188 kb |
| Host | smart-cb9be920-bc35-47f6-a748-c88563cf2358 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1084369322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1084369322 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025351569 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3894668392 ps |
| CPU time | 400.16 seconds |
| Started | Jul 22 08:42:50 PM PDT 24 |
| Finished | Jul 22 08:49:31 PM PDT 24 |
| Peak memory | 648872 kb |
| Host | smart-f483b457-d507-4064-92a6-7505e37d1fca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025351569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3025351569 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.1945768372 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5100323344 ps |
| CPU time | 530.92 seconds |
| Started | Jul 22 08:45:26 PM PDT 24 |
| Finished | Jul 22 08:54:19 PM PDT 24 |
| Peak memory | 650328 kb |
| Host | smart-2585e67b-c5ad-43fa-9383-adc66d573179 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1945768372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.1945768372 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3503258711 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3997236820 ps |
| CPU time | 410.95 seconds |
| Started | Jul 22 08:45:35 PM PDT 24 |
| Finished | Jul 22 08:52:27 PM PDT 24 |
| Peak memory | 649136 kb |
| Host | smart-98cfeada-4f07-4477-8254-6027b56165b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503258711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3503258711 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.1719336583 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 5505958906 ps |
| CPU time | 676.88 seconds |
| Started | Jul 22 08:42:27 PM PDT 24 |
| Finished | Jul 22 08:53:45 PM PDT 24 |
| Peak memory | 650104 kb |
| Host | smart-3b6e2e12-d465-42ee-aec3-0f68748a80a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1719336583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1719336583 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1000088505 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 4847840818 ps |
| CPU time | 725.43 seconds |
| Started | Jul 22 08:44:41 PM PDT 24 |
| Finished | Jul 22 08:56:48 PM PDT 24 |
| Peak memory | 620184 kb |
| Host | smart-ec46da3a-d38c-44f5-802c-7e3e760bda6c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1000088505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1000088505 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.914023180 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3911729544 ps |
| CPU time | 522.42 seconds |
| Started | Jul 22 08:43:52 PM PDT 24 |
| Finished | Jul 22 08:52:37 PM PDT 24 |
| Peak memory | 647056 kb |
| Host | smart-16a2fcdb-466a-4a46-b106-e54da2954453 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914023180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_s w_alert_handler_lpg_sleep_mode_alerts.914023180 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1992869096 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 5590502960 ps |
| CPU time | 534.59 seconds |
| Started | Jul 22 08:42:21 PM PDT 24 |
| Finished | Jul 22 08:51:17 PM PDT 24 |
| Peak memory | 650136 kb |
| Host | smart-fa47165a-f29b-4fd3-9f2e-415e0df3b6d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1992869096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1992869096 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.1104285707 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5380428816 ps |
| CPU time | 530.09 seconds |
| Started | Jul 22 08:42:58 PM PDT 24 |
| Finished | Jul 22 08:51:49 PM PDT 24 |
| Peak memory | 650364 kb |
| Host | smart-2818e217-51a0-48c5-bc0b-7ea1303a222d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1104285707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1104285707 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211904193 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4029531536 ps |
| CPU time | 444.19 seconds |
| Started | Jul 22 08:38:07 PM PDT 24 |
| Finished | Jul 22 08:45:34 PM PDT 24 |
| Peak memory | 648936 kb |
| Host | smart-ca841969-e083-46b1-b897-df67a7b9d351 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211904193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3211904193 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.960528538 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 26512182160 ps |
| CPU time | 5644.13 seconds |
| Started | Jul 22 08:39:51 PM PDT 24 |
| Finished | Jul 22 10:13:58 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-351d3142-67c7-4b04-ac83-b53c97e89c68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960528538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.960528538 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1777418000 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 6912167477 ps |
| CPU time | 551.97 seconds |
| Started | Jul 22 08:37:36 PM PDT 24 |
| Finished | Jul 22 08:46:50 PM PDT 24 |
| Peak memory | 620868 kb |
| Host | smart-a62fa6bc-5a5e-4edf-9ff7-ce8f9f8e0dca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777418000 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.1777418000 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.985843443 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 8434809000 ps |
| CPU time | 1347.22 seconds |
| Started | Jul 22 08:39:40 PM PDT 24 |
| Finished | Jul 22 09:02:10 PM PDT 24 |
| Peak memory | 619264 kb |
| Host | smart-7f02b9f1-f218-479c-9c29-41e8d2e9573f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=985843443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.985843443 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3206645330 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4256422650 ps |
| CPU time | 361.52 seconds |
| Started | Jul 22 08:44:28 PM PDT 24 |
| Finished | Jul 22 08:50:31 PM PDT 24 |
| Peak memory | 649292 kb |
| Host | smart-a1624737-48b1-421c-a2a5-1daedecde37e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206645330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3206645330 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.4056858663 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 4383027412 ps |
| CPU time | 493.07 seconds |
| Started | Jul 22 08:43:55 PM PDT 24 |
| Finished | Jul 22 08:52:11 PM PDT 24 |
| Peak memory | 650360 kb |
| Host | smart-b8570756-a5b9-43e4-8ae2-a08ab028cdd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4056858663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.4056858663 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2003892316 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 3957860764 ps |
| CPU time | 501.57 seconds |
| Started | Jul 22 08:43:25 PM PDT 24 |
| Finished | Jul 22 08:51:48 PM PDT 24 |
| Peak memory | 619372 kb |
| Host | smart-f24804fe-960c-44c3-8a90-81cabc20e5ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003892316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2003892316 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.3173060565 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 4694382848 ps |
| CPU time | 667.25 seconds |
| Started | Jul 22 08:43:23 PM PDT 24 |
| Finished | Jul 22 08:54:31 PM PDT 24 |
| Peak memory | 650444 kb |
| Host | smart-83229353-e325-4b59-bec8-bfd75fdae9c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3173060565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3173060565 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2446426530 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3130041902 ps |
| CPU time | 318.23 seconds |
| Started | Jul 22 08:44:12 PM PDT 24 |
| Finished | Jul 22 08:49:32 PM PDT 24 |
| Peak memory | 649008 kb |
| Host | smart-532ea41d-68f3-41c8-9c6f-4866f7345ab5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446426530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2446426530 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.1013309438 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 4639324500 ps |
| CPU time | 582.55 seconds |
| Started | Jul 22 08:43:49 PM PDT 24 |
| Finished | Jul 22 08:53:34 PM PDT 24 |
| Peak memory | 650712 kb |
| Host | smart-269a6b70-944c-4eed-ad28-4a771992f612 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1013309438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1013309438 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.341036653 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3916619632 ps |
| CPU time | 328.38 seconds |
| Started | Jul 22 08:44:37 PM PDT 24 |
| Finished | Jul 22 08:50:07 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-7b846de2-c8e2-4fb7-a296-c18c7c2ddeed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341036653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.341036653 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3300102447 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6030955472 ps |
| CPU time | 616.54 seconds |
| Started | Jul 22 08:46:43 PM PDT 24 |
| Finished | Jul 22 08:57:00 PM PDT 24 |
| Peak memory | 650424 kb |
| Host | smart-dc9604ec-bbcc-4a3c-934d-d6462400c313 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3300102447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3300102447 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1792008540 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4321499844 ps |
| CPU time | 378.95 seconds |
| Started | Jul 22 08:45:44 PM PDT 24 |
| Finished | Jul 22 08:52:03 PM PDT 24 |
| Peak memory | 649632 kb |
| Host | smart-ebda8499-ff69-437a-8b55-e076028f910c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792008540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1792008540 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.343162972 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3582307588 ps |
| CPU time | 348.6 seconds |
| Started | Jul 22 08:44:24 PM PDT 24 |
| Finished | Jul 22 08:50:13 PM PDT 24 |
| Peak memory | 649004 kb |
| Host | smart-3feec395-d002-41a6-b4b5-98e7dab0c1e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343162972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.343162972 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.4271105248 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 5290960836 ps |
| CPU time | 534.54 seconds |
| Started | Jul 22 08:42:58 PM PDT 24 |
| Finished | Jul 22 08:51:53 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-13c4e2af-dd78-48c7-b259-7ed40837ce7b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4271105248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.4271105248 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.602160957 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5757381574 ps |
| CPU time | 899.19 seconds |
| Started | Jul 22 08:44:28 PM PDT 24 |
| Finished | Jul 22 08:59:28 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-7df5ecef-3132-4afd-85f3-bb178db90cb1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 602160957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.602160957 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.587428405 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4054957994 ps |
| CPU time | 349.1 seconds |
| Started | Jul 22 08:47:09 PM PDT 24 |
| Finished | Jul 22 08:52:59 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-f6b4e69e-cfe1-4d4f-81d4-6b5c50564b10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587428405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.587428405 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.926379866 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5725185136 ps |
| CPU time | 543.78 seconds |
| Started | Jul 22 08:43:36 PM PDT 24 |
| Finished | Jul 22 08:52:40 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-b6c2f537-bdfb-4e12-8374-d0a9ab23dd22 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 926379866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.926379866 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3127714923 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4978213850 ps |
| CPU time | 592.18 seconds |
| Started | Jul 22 08:47:10 PM PDT 24 |
| Finished | Jul 22 08:57:03 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-f7d7cb6a-e1f5-4bf3-9c94-7476be138124 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3127714923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3127714923 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.180443734 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3811908448 ps |
| CPU time | 436.8 seconds |
| Started | Jul 22 08:44:11 PM PDT 24 |
| Finished | Jul 22 08:51:30 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-b0a02b48-1476-4233-a61c-281fb4ae25fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180443734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s w_alert_handler_lpg_sleep_mode_alerts.180443734 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.4250075327 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4481119208 ps |
| CPU time | 526.19 seconds |
| Started | Jul 22 08:47:14 PM PDT 24 |
| Finished | Jul 22 08:56:00 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-89bdf967-b357-4833-85c9-b69dd8c9f591 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4250075327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.4250075327 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3691870636 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4077886174 ps |
| CPU time | 447.59 seconds |
| Started | Jul 22 08:37:32 PM PDT 24 |
| Finished | Jul 22 08:45:01 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-eea5e96e-5896-4838-a878-91d5cb0a1687 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691870636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3691870636 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1191107823 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 6942599846 ps |
| CPU time | 525.59 seconds |
| Started | Jul 22 08:37:34 PM PDT 24 |
| Finished | Jul 22 08:46:21 PM PDT 24 |
| Peak memory | 620780 kb |
| Host | smart-f42331b1-5deb-4ba1-8608-ffd2483c26e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191107823 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.1191107823 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2711749540 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8249569008 ps |
| CPU time | 1339.98 seconds |
| Started | Jul 22 08:39:01 PM PDT 24 |
| Finished | Jul 22 09:01:23 PM PDT 24 |
| Peak memory | 619468 kb |
| Host | smart-ab5ed497-7971-403a-8504-a29504c85cf8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2711749540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2711749540 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.3666165841 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 6188855662 ps |
| CPU time | 500.39 seconds |
| Started | Jul 22 08:44:23 PM PDT 24 |
| Finished | Jul 22 08:52:44 PM PDT 24 |
| Peak memory | 650952 kb |
| Host | smart-607ae154-d254-4c88-a1ab-f38eee18be1b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3666165841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3666165841 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.529920723 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 5231525024 ps |
| CPU time | 595.98 seconds |
| Started | Jul 22 08:44:21 PM PDT 24 |
| Finished | Jul 22 08:54:18 PM PDT 24 |
| Peak memory | 650812 kb |
| Host | smart-0a97d05d-6ace-4fa9-8d25-05c4d15960e4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 529920723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.529920723 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.19885365 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4090845380 ps |
| CPU time | 437.37 seconds |
| Started | Jul 22 08:44:48 PM PDT 24 |
| Finished | Jul 22 08:52:06 PM PDT 24 |
| Peak memory | 649308 kb |
| Host | smart-60b780b7-3428-4760-b034-fea88d7f8963 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw _alert_handler_lpg_sleep_mode_alerts.19885365 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.1066503982 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 6803411356 ps |
| CPU time | 758.48 seconds |
| Started | Jul 22 08:43:54 PM PDT 24 |
| Finished | Jul 22 08:56:36 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-5177956b-5272-45dd-8741-efdb9f5c41be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1066503982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1066503982 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828507248 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4030296076 ps |
| CPU time | 451.82 seconds |
| Started | Jul 22 08:43:36 PM PDT 24 |
| Finished | Jul 22 08:51:09 PM PDT 24 |
| Peak memory | 649284 kb |
| Host | smart-cffe6cdf-61d2-488a-9d31-7a07f8e018f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828507248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2828507248 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.4099369287 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5452511230 ps |
| CPU time | 659.42 seconds |
| Started | Jul 22 08:44:13 PM PDT 24 |
| Finished | Jul 22 08:55:14 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-0fb0127a-769a-4e8e-b61d-bc837785a3e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4099369287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.4099369287 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1084779721 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3709142168 ps |
| CPU time | 410.07 seconds |
| Started | Jul 22 08:43:47 PM PDT 24 |
| Finished | Jul 22 08:50:39 PM PDT 24 |
| Peak memory | 619248 kb |
| Host | smart-f60bb083-e97c-44b5-b997-dd40c67cd032 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084779721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1084779721 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2378928842 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5292666572 ps |
| CPU time | 516.4 seconds |
| Started | Jul 22 08:45:33 PM PDT 24 |
| Finished | Jul 22 08:54:11 PM PDT 24 |
| Peak memory | 650364 kb |
| Host | smart-5fb2383b-5f6e-4971-83c2-b03b3d1c02de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2378928842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2378928842 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668918685 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4339499556 ps |
| CPU time | 447.63 seconds |
| Started | Jul 22 08:43:42 PM PDT 24 |
| Finished | Jul 22 08:51:10 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-827d983b-9469-490d-94e9-fee530ac5185 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668918685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3668918685 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.4060871175 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4863371208 ps |
| CPU time | 606.38 seconds |
| Started | Jul 22 08:44:57 PM PDT 24 |
| Finished | Jul 22 08:55:04 PM PDT 24 |
| Peak memory | 650268 kb |
| Host | smart-5bd23f0d-13b1-4763-80be-71f08e33f5f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4060871175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.4060871175 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2015590456 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3555324550 ps |
| CPU time | 353.13 seconds |
| Started | Jul 22 08:45:00 PM PDT 24 |
| Finished | Jul 22 08:50:54 PM PDT 24 |
| Peak memory | 649484 kb |
| Host | smart-ae40c3d5-fc85-4cd7-9c69-279f1202ab95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015590456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2015590456 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.3520342848 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 5457524562 ps |
| CPU time | 532.87 seconds |
| Started | Jul 22 08:44:31 PM PDT 24 |
| Finished | Jul 22 08:53:25 PM PDT 24 |
| Peak memory | 650120 kb |
| Host | smart-2bebc488-4367-4390-b030-49980d60b48e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3520342848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3520342848 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3902599466 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3598595732 ps |
| CPU time | 365.12 seconds |
| Started | Jul 22 08:44:59 PM PDT 24 |
| Finished | Jul 22 08:51:05 PM PDT 24 |
| Peak memory | 649068 kb |
| Host | smart-45d46b62-8041-425c-baa7-8819f2bbc0af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902599466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3902599466 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1292590172 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 5640076264 ps |
| CPU time | 511.66 seconds |
| Started | Jul 22 08:43:35 PM PDT 24 |
| Finished | Jul 22 08:52:08 PM PDT 24 |
| Peak memory | 650428 kb |
| Host | smart-c5217f95-14bf-42c2-937f-23bb3956693a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1292590172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1292590172 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565284078 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4272761792 ps |
| CPU time | 434.42 seconds |
| Started | Jul 22 08:44:58 PM PDT 24 |
| Finished | Jul 22 08:52:13 PM PDT 24 |
| Peak memory | 649128 kb |
| Host | smart-954c10f2-69a9-4577-ae61-d9d8bc5340c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565284078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1565284078 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551042667 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3227591828 ps |
| CPU time | 324.36 seconds |
| Started | Jul 22 08:39:01 PM PDT 24 |
| Finished | Jul 22 08:44:27 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-5f2ac61a-f7f6-4f18-9ad1-b744169626c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551042667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.1551042667 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3050983631 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 15770810590 ps |
| CPU time | 3008.83 seconds |
| Started | Jul 22 08:41:15 PM PDT 24 |
| Finished | Jul 22 09:31:27 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-d2f7f941-9205-4347-91a0-8c4d796c5134 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050983631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.3050983631 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3338783905 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 7484458923 ps |
| CPU time | 522.85 seconds |
| Started | Jul 22 08:40:32 PM PDT 24 |
| Finished | Jul 22 08:49:19 PM PDT 24 |
| Peak memory | 625200 kb |
| Host | smart-e5da0a2c-fb65-4b1b-a6a1-55947c0a2312 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338783905 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3338783905 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2517153068 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 13129418200 ps |
| CPU time | 2547.79 seconds |
| Started | Jul 22 08:38:22 PM PDT 24 |
| Finished | Jul 22 09:20:51 PM PDT 24 |
| Peak memory | 619336 kb |
| Host | smart-7cbf613f-1767-4b33-9b5e-71b8a3668efb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2517153068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2517153068 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.2802831602 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4703674840 ps |
| CPU time | 528.06 seconds |
| Started | Jul 22 08:47:06 PM PDT 24 |
| Finished | Jul 22 08:55:54 PM PDT 24 |
| Peak memory | 650396 kb |
| Host | smart-3bcd3551-1f0a-49e2-9c0e-d3f692748ef4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2802831602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2802831602 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.4047909458 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5112522814 ps |
| CPU time | 666.3 seconds |
| Started | Jul 22 08:45:58 PM PDT 24 |
| Finished | Jul 22 08:57:05 PM PDT 24 |
| Peak memory | 650460 kb |
| Host | smart-fd3a665d-96f2-4139-9b3e-9ef8e64fff77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4047909458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.4047909458 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377428613 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4664870344 ps |
| CPU time | 452.54 seconds |
| Started | Jul 22 08:45:59 PM PDT 24 |
| Finished | Jul 22 08:53:32 PM PDT 24 |
| Peak memory | 649472 kb |
| Host | smart-24a957a3-8de9-4b9d-9670-5e4e83090a19 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377428613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1377428613 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.747395413 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 3790553208 ps |
| CPU time | 361.9 seconds |
| Started | Jul 22 08:45:28 PM PDT 24 |
| Finished | Jul 22 08:51:31 PM PDT 24 |
| Peak memory | 649312 kb |
| Host | smart-650417ab-b3ba-4ca6-9c8f-a2eed4acb99a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747395413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_s w_alert_handler_lpg_sleep_mode_alerts.747395413 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.1227046389 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4318477208 ps |
| CPU time | 502.31 seconds |
| Started | Jul 22 08:45:57 PM PDT 24 |
| Finished | Jul 22 08:54:21 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-17f707e8-0020-4cac-ad1b-ed200d033c25 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1227046389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.1227046389 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2837661579 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3285131404 ps |
| CPU time | 306.6 seconds |
| Started | Jul 22 08:48:09 PM PDT 24 |
| Finished | Jul 22 08:53:16 PM PDT 24 |
| Peak memory | 649308 kb |
| Host | smart-c171a439-a0ca-47b9-8c93-e6420b740c91 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837661579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2837661579 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1971320543 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3899467848 ps |
| CPU time | 356.44 seconds |
| Started | Jul 22 08:45:55 PM PDT 24 |
| Finished | Jul 22 08:51:52 PM PDT 24 |
| Peak memory | 648900 kb |
| Host | smart-e2b15017-9df4-42af-b637-8a21bde929a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971320543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1971320543 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869998641 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 3843778440 ps |
| CPU time | 401.9 seconds |
| Started | Jul 22 08:46:42 PM PDT 24 |
| Finished | Jul 22 08:53:25 PM PDT 24 |
| Peak memory | 649256 kb |
| Host | smart-046b6e13-2244-4130-81e7-0b41e7777be5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869998641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3869998641 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.2218412568 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5680201292 ps |
| CPU time | 655.27 seconds |
| Started | Jul 22 08:46:04 PM PDT 24 |
| Finished | Jul 22 08:57:00 PM PDT 24 |
| Peak memory | 650052 kb |
| Host | smart-d256af46-7e6b-4698-9729-2d793761762f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2218412568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.2218412568 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131261685 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 4142261000 ps |
| CPU time | 391.32 seconds |
| Started | Jul 22 08:45:53 PM PDT 24 |
| Finished | Jul 22 08:52:26 PM PDT 24 |
| Peak memory | 618988 kb |
| Host | smart-0856fe53-cb71-4ab2-becc-63ca3ffea0e9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131261685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4131261685 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.578997897 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 5895031950 ps |
| CPU time | 569.82 seconds |
| Started | Jul 22 08:46:04 PM PDT 24 |
| Finished | Jul 22 08:55:35 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-e11a1a90-970e-4333-8905-2eaaf78e20c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 578997897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.578997897 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064429236 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3308106224 ps |
| CPU time | 297.53 seconds |
| Started | Jul 22 08:46:37 PM PDT 24 |
| Finished | Jul 22 08:51:36 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-31d891da-d16b-434c-81ad-19c69912a04d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064429236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1064429236 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1241672548 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 4717742344 ps |
| CPU time | 509.22 seconds |
| Started | Jul 22 08:46:52 PM PDT 24 |
| Finished | Jul 22 08:55:22 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-35599f85-0fd7-4dc6-9121-d14f3bc8535d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1241672548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1241672548 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.616608536 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3396994952 ps |
| CPU time | 354.38 seconds |
| Started | Jul 22 08:40:42 PM PDT 24 |
| Finished | Jul 22 08:46:38 PM PDT 24 |
| Peak memory | 648936 kb |
| Host | smart-66e8b52b-9daf-4c10-8f0c-a6904e5e5d5b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616608536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw _alert_handler_lpg_sleep_mode_alerts.616608536 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1305051129 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4911048084 ps |
| CPU time | 682.32 seconds |
| Started | Jul 22 08:38:55 PM PDT 24 |
| Finished | Jul 22 08:50:18 PM PDT 24 |
| Peak memory | 650700 kb |
| Host | smart-ded2dfbe-e52b-4626-b7bd-84bb5b125256 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1305051129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1305051129 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3983458711 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 16440816326 ps |
| CPU time | 3002.25 seconds |
| Started | Jul 22 08:40:27 PM PDT 24 |
| Finished | Jul 22 09:30:31 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-57a6527e-4aff-4df9-8b1c-9646f7445205 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983458711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.3983458711 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.533679469 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 7224562792 ps |
| CPU time | 625.89 seconds |
| Started | Jul 22 08:40:30 PM PDT 24 |
| Finished | Jul 22 08:50:59 PM PDT 24 |
| Peak memory | 622948 kb |
| Host | smart-d6cfef46-b4c8-424d-b320-ac68fab8c2a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533679469 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.533679469 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1664918839 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 7712940384 ps |
| CPU time | 1248.33 seconds |
| Started | Jul 22 08:39:41 PM PDT 24 |
| Finished | Jul 22 09:00:31 PM PDT 24 |
| Peak memory | 619220 kb |
| Host | smart-f41093ea-968b-4d41-87fb-95b90a84671f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1664918839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1664918839 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.1998117844 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 6218828840 ps |
| CPU time | 641.93 seconds |
| Started | Jul 22 08:46:58 PM PDT 24 |
| Finished | Jul 22 08:57:41 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-57131302-4122-463e-bbc0-1657dad0b0a0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1998117844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.1998117844 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3891096264 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5335930880 ps |
| CPU time | 556.63 seconds |
| Started | Jul 22 08:46:15 PM PDT 24 |
| Finished | Jul 22 08:55:32 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-14362d46-6598-40f1-b083-d86311a82a89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3891096264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3891096264 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1727418529 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5831537710 ps |
| CPU time | 603.3 seconds |
| Started | Jul 22 08:46:06 PM PDT 24 |
| Finished | Jul 22 08:56:10 PM PDT 24 |
| Peak memory | 620184 kb |
| Host | smart-358b750a-0885-4443-945f-bcd1a213577e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1727418529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1727418529 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.458492490 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 6716068918 ps |
| CPU time | 683.03 seconds |
| Started | Jul 22 08:46:33 PM PDT 24 |
| Finished | Jul 22 08:57:56 PM PDT 24 |
| Peak memory | 651008 kb |
| Host | smart-08b826c8-5e93-4bcb-9eab-3046a530c18e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 458492490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.458492490 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1826805181 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 5933205870 ps |
| CPU time | 525.5 seconds |
| Started | Jul 22 08:46:07 PM PDT 24 |
| Finished | Jul 22 08:54:53 PM PDT 24 |
| Peak memory | 650228 kb |
| Host | smart-296f3552-1413-4b6e-b41e-0bc7123073a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1826805181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1826805181 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2998272040 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 5313278248 ps |
| CPU time | 599.5 seconds |
| Started | Jul 22 08:47:12 PM PDT 24 |
| Finished | Jul 22 08:57:12 PM PDT 24 |
| Peak memory | 650424 kb |
| Host | smart-8e75f478-64b7-4e11-ac40-1233273f3e69 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2998272040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2998272040 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.198913484 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4517117136 ps |
| CPU time | 529.38 seconds |
| Started | Jul 22 08:46:11 PM PDT 24 |
| Finished | Jul 22 08:55:01 PM PDT 24 |
| Peak memory | 650444 kb |
| Host | smart-d3f39e79-f66f-405f-8baf-9c554d05bfe3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 198913484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.198913484 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.3120771101 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4451344008 ps |
| CPU time | 533.8 seconds |
| Started | Jul 22 08:47:01 PM PDT 24 |
| Finished | Jul 22 08:55:55 PM PDT 24 |
| Peak memory | 650556 kb |
| Host | smart-8214978f-48e3-4b03-a189-097357d4f512 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3120771101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.3120771101 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.1453536998 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5925776132 ps |
| CPU time | 533.49 seconds |
| Started | Jul 22 08:47:01 PM PDT 24 |
| Finished | Jul 22 08:55:55 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-a60a7919-db14-4a2d-935f-663916c7da6d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1453536998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1453536998 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2720544883 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4766406150 ps |
| CPU time | 508.76 seconds |
| Started | Jul 22 08:46:35 PM PDT 24 |
| Finished | Jul 22 08:55:05 PM PDT 24 |
| Peak memory | 650312 kb |
| Host | smart-8d6d3642-77e5-4fd9-b465-458d53b1d70f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2720544883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2720544883 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1133993371 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5776238886 ps |
| CPU time | 455.29 seconds |
| Started | Jul 22 08:39:31 PM PDT 24 |
| Finished | Jul 22 08:47:08 PM PDT 24 |
| Peak memory | 650744 kb |
| Host | smart-2824f0f7-3bb6-46dd-9a4f-356c724728d5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133993371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1133993371 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1668305774 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4216293048 ps |
| CPU time | 305.42 seconds |
| Started | Jul 22 08:39:38 PM PDT 24 |
| Finished | Jul 22 08:44:44 PM PDT 24 |
| Peak memory | 641236 kb |
| Host | smart-8c9e3fcd-7924-424d-9bce-3132bf31f82e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668305774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1668305774 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2220812521 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4875014833 ps |
| CPU time | 306.99 seconds |
| Started | Jul 22 08:39:34 PM PDT 24 |
| Finished | Jul 22 08:44:42 PM PDT 24 |
| Peak memory | 657704 kb |
| Host | smart-042326a8-544c-4f84-b43f-7334b4a28bab |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220812521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.2220812521 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.649717117 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5087106328 ps |
| CPU time | 352.99 seconds |
| Started | Jul 22 08:39:35 PM PDT 24 |
| Finished | Jul 22 08:45:29 PM PDT 24 |
| Peak memory | 657776 kb |
| Host | smart-4e119c3c-74ae-43ee-8eec-55a0247af11a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649717117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.649717117 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3973954894 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5552195120 ps |
| CPU time | 311.41 seconds |
| Started | Jul 22 08:39:31 PM PDT 24 |
| Finished | Jul 22 08:44:44 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-89836b1f-af05-4212-9cc2-725744b50114 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973954894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3973954894 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1397018843 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4331846792 ps |
| CPU time | 274.2 seconds |
| Started | Jul 22 08:39:55 PM PDT 24 |
| Finished | Jul 22 08:44:31 PM PDT 24 |
| Peak memory | 649484 kb |
| Host | smart-9357d4f0-98f6-49f9-a23d-8673b29f68d0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397018843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1397018843 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1937994191 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4126376098 ps |
| CPU time | 278.38 seconds |
| Started | Jul 22 08:40:37 PM PDT 24 |
| Finished | Jul 22 08:45:16 PM PDT 24 |
| Peak memory | 641348 kb |
| Host | smart-b03a50a6-427a-43eb-9dc0-ffc560186d55 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937994191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1937994191 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2868984450 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4957612164 ps |
| CPU time | 261.2 seconds |
| Started | Jul 22 08:39:33 PM PDT 24 |
| Finished | Jul 22 08:43:56 PM PDT 24 |
| Peak memory | 651868 kb |
| Host | smart-73a6a3e0-15b5-4b5d-ba8d-b3f84888441c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868984450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2868984450 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1318469087 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4227644838 ps |
| CPU time | 320.94 seconds |
| Started | Jul 22 08:40:21 PM PDT 24 |
| Finished | Jul 22 08:45:44 PM PDT 24 |
| Peak memory | 641364 kb |
| Host | smart-34fe0ccd-8d50-47af-9c3c-ca630da1e2a0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318469087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1318469087 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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