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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.12 95.44 93.98 95.35 94.84 97.53 99.57


Total test records in report: 2931
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T1031 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1373597096 Jul 22 08:24:01 PM PDT 24 Jul 22 08:42:41 PM PDT 24 5775786572 ps
T1032 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1979021365 Jul 22 08:19:26 PM PDT 24 Jul 22 08:29:43 PM PDT 24 4098672378 ps
T1033 /workspace/coverage/default/1.chip_sw_example_rom.612258742 Jul 22 08:14:01 PM PDT 24 Jul 22 08:15:50 PM PDT 24 2060595032 ps
T749 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1084779721 Jul 22 08:43:47 PM PDT 24 Jul 22 08:50:39 PM PDT 24 3709142168 ps
T292 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.478937818 Jul 22 08:33:45 PM PDT 24 Jul 22 08:46:52 PM PDT 24 4527771915 ps
T1034 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.288590587 Jul 22 08:29:32 PM PDT 24 Jul 22 08:39:48 PM PDT 24 5630658888 ps
T1035 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3177687665 Jul 22 08:38:33 PM PDT 24 Jul 22 08:46:47 PM PDT 24 3628874170 ps
T1036 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3753662598 Jul 22 08:13:18 PM PDT 24 Jul 22 08:20:05 PM PDT 24 3379692120 ps
T1037 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2627325810 Jul 22 08:21:55 PM PDT 24 Jul 22 08:28:45 PM PDT 24 5635945123 ps
T692 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4138542786 Jul 22 08:12:12 PM PDT 24 Jul 22 08:14:51 PM PDT 24 2757006690 ps
T764 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1792008540 Jul 22 08:45:44 PM PDT 24 Jul 22 08:52:03 PM PDT 24 4321499844 ps
T1038 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.475327158 Jul 22 08:28:27 PM PDT 24 Jul 23 12:19:23 AM PDT 24 78538965802 ps
T1039 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.747395413 Jul 22 08:45:28 PM PDT 24 Jul 22 08:51:31 PM PDT 24 3790553208 ps
T750 /workspace/coverage/default/73.chip_sw_all_escalation_resets.4099369287 Jul 22 08:44:13 PM PDT 24 Jul 22 08:55:14 PM PDT 24 5452511230 ps
T315 /workspace/coverage/default/43.chip_sw_all_escalation_resets.4063287308 Jul 22 08:42:44 PM PDT 24 Jul 22 08:54:36 PM PDT 24 5634983780 ps
T1040 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.231352704 Jul 22 08:31:03 PM PDT 24 Jul 22 09:30:51 PM PDT 24 16412053100 ps
T1041 /workspace/coverage/default/0.chip_sw_hmac_enc.3418779821 Jul 22 08:14:29 PM PDT 24 Jul 22 08:18:12 PM PDT 24 2374289418 ps
T355 /workspace/coverage/default/1.chip_sival_flash_info_access.1124149620 Jul 22 08:17:16 PM PDT 24 Jul 22 08:22:05 PM PDT 24 2556498026 ps
T248 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1607022995 Jul 22 08:28:43 PM PDT 24 Jul 22 08:37:02 PM PDT 24 5111429800 ps
T1042 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2144570616 Jul 22 08:28:08 PM PDT 24 Jul 22 09:09:17 PM PDT 24 23114737400 ps
T1043 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2921408192 Jul 22 08:11:30 PM PDT 24 Jul 22 08:23:33 PM PDT 24 4687222510 ps
T1044 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3973466538 Jul 22 08:13:35 PM PDT 24 Jul 22 08:58:59 PM PDT 24 25944115456 ps
T240 /workspace/coverage/default/0.chip_sw_flash_init.3304970836 Jul 22 08:10:50 PM PDT 24 Jul 22 08:47:42 PM PDT 24 22378918520 ps
T457 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3184863681 Jul 22 08:37:59 PM PDT 24 Jul 22 08:50:57 PM PDT 24 4669823700 ps
T714 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3167316230 Jul 22 08:22:41 PM PDT 24 Jul 22 08:26:35 PM PDT 24 2437465496 ps
T1045 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3364776959 Jul 22 08:22:56 PM PDT 24 Jul 22 08:27:45 PM PDT 24 3045021112 ps
T459 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1992483571 Jul 22 08:42:04 PM PDT 24 Jul 22 09:00:16 PM PDT 24 6221942006 ps
T1046 /workspace/coverage/default/1.chip_tap_straps_prod.1392121814 Jul 22 08:22:34 PM PDT 24 Jul 22 08:38:27 PM PDT 24 7978392737 ps
T1047 /workspace/coverage/default/1.rom_e2e_shutdown_output.1224788601 Jul 22 08:27:28 PM PDT 24 Jul 22 09:35:27 PM PDT 24 25533551950 ps
T1048 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2937157701 Jul 22 08:18:46 PM PDT 24 Jul 22 08:45:30 PM PDT 24 6974886954 ps
T368 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2276595944 Jul 22 08:45:25 PM PDT 24 Jul 22 08:52:28 PM PDT 24 3277877550 ps
T778 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639365398 Jul 22 08:47:45 PM PDT 24 Jul 22 08:53:30 PM PDT 24 3515968176 ps
T1049 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3869416128 Jul 22 08:15:20 PM PDT 24 Jul 22 08:21:12 PM PDT 24 3124822576 ps
T1050 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1482990867 Jul 22 08:37:09 PM PDT 24 Jul 22 08:40:51 PM PDT 24 3118462280 ps
T1051 /workspace/coverage/default/1.rom_e2e_asm_init_dev.816208654 Jul 22 08:41:21 PM PDT 24 Jul 22 09:46:35 PM PDT 24 15350715138 ps
T242 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2567608086 Jul 22 08:11:37 PM PDT 24 Jul 22 08:22:30 PM PDT 24 4795791929 ps
T369 /workspace/coverage/default/18.chip_sw_all_escalation_resets.46267746 Jul 22 08:39:41 PM PDT 24 Jul 22 08:52:23 PM PDT 24 5198535456 ps
T808 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2969633271 Jul 22 08:38:44 PM PDT 24 Jul 22 08:46:29 PM PDT 24 3973094516 ps
T1052 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3136151247 Jul 22 08:21:13 PM PDT 24 Jul 22 08:47:31 PM PDT 24 7138342056 ps
T1053 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2438525374 Jul 22 08:33:06 PM PDT 24 Jul 22 08:44:45 PM PDT 24 4329189206 ps
T348 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.244871509 Jul 22 08:39:52 PM PDT 24 Jul 22 08:54:00 PM PDT 24 5021636676 ps
T1054 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3790872046 Jul 22 08:30:35 PM PDT 24 Jul 22 08:34:55 PM PDT 24 2569601838 ps
T1055 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3609874208 Jul 22 08:12:51 PM PDT 24 Jul 22 09:00:48 PM PDT 24 11450611051 ps
T1056 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2111413833 Jul 22 08:20:13 PM PDT 24 Jul 22 08:45:32 PM PDT 24 7495619026 ps
T809 /workspace/coverage/default/20.chip_sw_all_escalation_resets.626341560 Jul 22 08:41:15 PM PDT 24 Jul 22 08:48:57 PM PDT 24 4151418808 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2716408062 Jul 22 08:12:12 PM PDT 24 Jul 22 08:44:25 PM PDT 24 7700568104 ps
T163 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2101994825 Jul 22 08:31:45 PM PDT 24 Jul 22 08:54:15 PM PDT 24 10659489540 ps
T1057 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1444387060 Jul 22 08:22:47 PM PDT 24 Jul 22 08:32:20 PM PDT 24 4962674328 ps
T1058 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2380752547 Jul 22 08:32:18 PM PDT 24 Jul 22 08:54:53 PM PDT 24 7764630080 ps
T304 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.45610422 Jul 22 08:15:13 PM PDT 24 Jul 22 08:20:18 PM PDT 24 3410113220 ps
T1059 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1241672548 Jul 22 08:46:52 PM PDT 24 Jul 22 08:55:22 PM PDT 24 4717742344 ps
T171 /workspace/coverage/default/35.chip_sw_all_escalation_resets.595068465 Jul 22 08:41:08 PM PDT 24 Jul 22 08:55:52 PM PDT 24 6070666898 ps
T772 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551042667 Jul 22 08:39:01 PM PDT 24 Jul 22 08:44:27 PM PDT 24 3227591828 ps
T72 /workspace/coverage/default/0.chip_sw_usbdev_pullup.598419932 Jul 22 08:12:05 PM PDT 24 Jul 22 08:17:22 PM PDT 24 3680957002 ps
T1060 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1825713735 Jul 22 08:31:16 PM PDT 24 Jul 22 08:34:34 PM PDT 24 2377280991 ps
T769 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2272172054 Jul 22 08:45:30 PM PDT 24 Jul 22 08:50:53 PM PDT 24 3810494456 ps
T1061 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3029687742 Jul 22 08:42:43 PM PDT 24 Jul 22 09:01:22 PM PDT 24 14287512893 ps
T1062 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1664918839 Jul 22 08:39:41 PM PDT 24 Jul 22 09:00:31 PM PDT 24 7712940384 ps
T309 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2878264649 Jul 22 08:16:06 PM PDT 24 Jul 22 08:25:41 PM PDT 24 6656297070 ps
T1063 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1067392742 Jul 22 08:41:18 PM PDT 24 Jul 22 09:36:50 PM PDT 24 17983993478 ps
T730 /workspace/coverage/default/2.rom_raw_unlock.1188824861 Jul 22 08:35:45 PM PDT 24 Jul 22 08:39:41 PM PDT 24 4399538155 ps
T1064 /workspace/coverage/default/0.chip_sw_power_sleep_load.3019377647 Jul 22 08:25:35 PM PDT 24 Jul 22 08:32:18 PM PDT 24 10653048432 ps
T1065 /workspace/coverage/default/1.chip_sw_kmac_idle.2961994807 Jul 22 08:20:16 PM PDT 24 Jul 22 08:25:24 PM PDT 24 3399897314 ps
T282 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.4291291381 Jul 22 08:37:02 PM PDT 24 Jul 22 08:50:20 PM PDT 24 5250869384 ps
T249 /workspace/coverage/default/17.chip_sw_all_escalation_resets.343608977 Jul 22 08:39:29 PM PDT 24 Jul 22 08:47:08 PM PDT 24 5399236696 ps
T1066 /workspace/coverage/default/4.chip_sw_uart_tx_rx.4092496222 Jul 22 08:36:41 PM PDT 24 Jul 22 08:46:46 PM PDT 24 4182878070 ps
T52 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.875831876 Jul 22 08:26:40 PM PDT 24 Jul 22 08:32:52 PM PDT 24 3711085194 ps
T693 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.19872625 Jul 22 08:22:22 PM PDT 24 Jul 22 08:24:17 PM PDT 24 1946119995 ps
T1067 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2617672044 Jul 22 08:19:23 PM PDT 24 Jul 22 08:30:17 PM PDT 24 5294144280 ps
T1068 /workspace/coverage/default/0.rom_e2e_static_critical.2991654277 Jul 22 08:21:25 PM PDT 24 Jul 22 09:19:37 PM PDT 24 17297818776 ps
T811 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1185114754 Jul 22 08:42:29 PM PDT 24 Jul 22 08:54:40 PM PDT 24 5190550680 ps
T753 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1538149424 Jul 22 08:37:59 PM PDT 24 Jul 22 08:47:10 PM PDT 24 5170386888 ps
T1069 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.808806856 Jul 22 08:43:29 PM PDT 24 Jul 22 08:50:58 PM PDT 24 3873527660 ps
T1070 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3231085957 Jul 22 08:21:47 PM PDT 24 Jul 22 09:16:59 PM PDT 24 10800848458 ps
T1071 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1887834687 Jul 22 08:26:17 PM PDT 24 Jul 22 08:37:44 PM PDT 24 3852820720 ps
T752 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.68297089 Jul 22 08:20:25 PM PDT 24 Jul 22 08:32:57 PM PDT 24 4897047008 ps
T331 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2675312294 Jul 22 08:12:49 PM PDT 24 Jul 22 08:27:10 PM PDT 24 5256086520 ps
T1072 /workspace/coverage/default/0.chip_sw_usbdev_vbus.2358603354 Jul 22 08:10:52 PM PDT 24 Jul 22 08:15:56 PM PDT 24 2870603520 ps
T1073 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.969423579 Jul 22 08:33:20 PM PDT 24 Jul 22 08:54:53 PM PDT 24 7583198102 ps
T1074 /workspace/coverage/default/1.chip_sw_example_flash.745621253 Jul 22 08:17:36 PM PDT 24 Jul 22 08:20:11 PM PDT 24 2130543424 ps
T1075 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1697633206 Jul 22 08:21:16 PM PDT 24 Jul 22 09:40:13 PM PDT 24 15033932484 ps
T1076 /workspace/coverage/default/2.rom_e2e_self_hash.3976374565 Jul 22 08:40:20 PM PDT 24 Jul 22 10:02:33 PM PDT 24 25733766080 ps
T90 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3666165841 Jul 22 08:44:23 PM PDT 24 Jul 22 08:52:44 PM PDT 24 6188855662 ps
T1077 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2038580974 Jul 22 08:15:48 PM PDT 24 Jul 22 08:37:53 PM PDT 24 8002145964 ps
T806 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1816054021 Jul 22 08:38:13 PM PDT 24 Jul 22 08:45:49 PM PDT 24 4386383000 ps
T1078 /workspace/coverage/default/3.chip_tap_straps_prod.2757025157 Jul 22 08:35:42 PM PDT 24 Jul 22 08:38:11 PM PDT 24 2694255454 ps
T790 /workspace/coverage/default/81.chip_sw_all_escalation_resets.4047909458 Jul 22 08:45:58 PM PDT 24 Jul 22 08:57:05 PM PDT 24 5112522814 ps
T795 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2998272040 Jul 22 08:47:12 PM PDT 24 Jul 22 08:57:12 PM PDT 24 5313278248 ps
T535 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.954173930 Jul 22 08:29:54 PM PDT 24 Jul 22 08:43:02 PM PDT 24 5010662044 ps
T229 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3499981634 Jul 22 08:22:04 PM PDT 24 Jul 22 08:43:20 PM PDT 24 6928454440 ps
T1079 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2926758941 Jul 22 08:14:16 PM PDT 24 Jul 22 08:57:16 PM PDT 24 13551738878 ps
T1080 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2940460376 Jul 22 08:30:56 PM PDT 24 Jul 22 08:36:17 PM PDT 24 2538137222 ps
T1081 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2956022401 Jul 22 08:30:41 PM PDT 24 Jul 22 08:40:06 PM PDT 24 4586991010 ps
T800 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3891096264 Jul 22 08:46:15 PM PDT 24 Jul 22 08:55:32 PM PDT 24 5335930880 ps
T1082 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.429181648 Jul 22 08:42:38 PM PDT 24 Jul 22 08:48:43 PM PDT 24 4144523016 ps
T53 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2257574676 Jul 22 08:26:54 PM PDT 24 Jul 22 08:32:36 PM PDT 24 3739583002 ps
T1083 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.97546309 Jul 22 08:36:58 PM PDT 24 Jul 22 08:40:46 PM PDT 24 2180101236 ps
T448 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.595603321 Jul 22 08:17:27 PM PDT 24 Jul 22 09:02:11 PM PDT 24 34406026313 ps
T1084 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.684460837 Jul 22 08:27:42 PM PDT 24 Jul 22 10:01:14 PM PDT 24 49881173681 ps
T1085 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1697873183 Jul 22 08:21:27 PM PDT 24 Jul 22 09:14:11 PM PDT 24 11612920114 ps
T1086 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1806079046 Jul 22 08:23:07 PM PDT 24 Jul 22 08:31:38 PM PDT 24 6780549386 ps
T1087 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.439537025 Jul 22 08:29:28 PM PDT 24 Jul 22 08:44:29 PM PDT 24 7987601372 ps
T1088 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.122431637 Jul 22 08:39:43 PM PDT 24 Jul 22 09:09:36 PM PDT 24 8385722584 ps
T1089 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2636385372 Jul 22 08:37:29 PM PDT 24 Jul 22 08:49:25 PM PDT 24 4562953064 ps
T1090 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4076895641 Jul 22 08:16:36 PM PDT 24 Jul 22 08:37:35 PM PDT 24 5489204760 ps
T1091 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1000088505 Jul 22 08:44:41 PM PDT 24 Jul 22 08:56:48 PM PDT 24 4847840818 ps
T1092 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3696304335 Jul 22 08:31:37 PM PDT 24 Jul 22 08:38:50 PM PDT 24 5311134680 ps
T817 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2837661579 Jul 22 08:48:09 PM PDT 24 Jul 22 08:53:16 PM PDT 24 3285131404 ps
T738 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1430209838 Jul 22 08:15:06 PM PDT 24 Jul 22 08:24:14 PM PDT 24 4701693540 ps
T1093 /workspace/coverage/default/2.chip_sival_flash_info_access.50529215 Jul 22 08:26:22 PM PDT 24 Jul 22 08:32:41 PM PDT 24 3439952560 ps
T1094 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1675676845 Jul 22 08:30:24 PM PDT 24 Jul 22 08:35:55 PM PDT 24 3467733180 ps
T1095 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.43327276 Jul 22 08:39:03 PM PDT 24 Jul 22 08:57:24 PM PDT 24 15456402432 ps
T1096 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.634002788 Jul 22 08:34:19 PM PDT 24 Jul 22 08:44:46 PM PDT 24 3725002632 ps
T1097 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1820280365 Jul 22 08:38:04 PM PDT 24 Jul 22 09:00:25 PM PDT 24 8238926040 ps
T102 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1683316343 Jul 22 08:16:58 PM PDT 24 Jul 22 08:22:05 PM PDT 24 2650772640 ps
T1098 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.100403381 Jul 22 08:27:11 PM PDT 24 Jul 22 09:03:04 PM PDT 24 27829854377 ps
T54 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1734665164 Jul 22 08:12:59 PM PDT 24 Jul 22 08:17:40 PM PDT 24 3576938563 ps
T1099 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.406171318 Jul 22 08:28:28 PM PDT 24 Jul 22 08:38:36 PM PDT 24 5410246430 ps
T1100 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.636544169 Jul 22 08:34:00 PM PDT 24 Jul 22 08:39:07 PM PDT 24 2799357824 ps
T1101 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3255250126 Jul 22 08:21:12 PM PDT 24 Jul 22 10:02:56 PM PDT 24 23383612480 ps
T339 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.735956827 Jul 22 08:14:56 PM PDT 24 Jul 22 08:21:27 PM PDT 24 3804341592 ps
T370 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2720544883 Jul 22 08:46:35 PM PDT 24 Jul 22 08:55:05 PM PDT 24 4766406150 ps
T746 /workspace/coverage/default/29.chip_sw_all_escalation_resets.215307297 Jul 22 08:42:06 PM PDT 24 Jul 22 08:50:27 PM PDT 24 4336666000 ps
T1102 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3655531952 Jul 22 08:20:00 PM PDT 24 Jul 22 09:43:17 PM PDT 24 17487657300 ps
T211 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.268517556 Jul 22 08:30:54 PM PDT 24 Jul 22 08:37:03 PM PDT 24 3246898129 ps
T818 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1326460568 Jul 22 08:36:54 PM PDT 24 Jul 22 08:43:37 PM PDT 24 3388727800 ps
T741 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1191365626 Jul 22 08:41:36 PM PDT 24 Jul 22 08:47:18 PM PDT 24 3886666248 ps
T80 /workspace/coverage/default/1.chip_jtag_mem_access.6847598 Jul 22 08:14:23 PM PDT 24 Jul 22 08:46:25 PM PDT 24 13423946911 ps
T823 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1704913605 Jul 22 08:29:55 PM PDT 24 Jul 22 08:37:26 PM PDT 24 3274385104 ps
T1103 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4173115319 Jul 22 08:17:26 PM PDT 24 Jul 22 08:22:14 PM PDT 24 3239447482 ps
T319 /workspace/coverage/default/2.chip_plic_all_irqs_0.245994700 Jul 22 08:30:58 PM PDT 24 Jul 22 08:51:54 PM PDT 24 6127207888 ps
T791 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2691163991 Jul 22 08:41:18 PM PDT 24 Jul 22 08:51:03 PM PDT 24 5120538344 ps
T1104 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1113522995 Jul 22 08:18:17 PM PDT 24 Jul 22 08:36:02 PM PDT 24 5322172680 ps
T201 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1029524408 Jul 22 08:29:09 PM PDT 24 Jul 22 08:39:07 PM PDT 24 4765727770 ps
T1105 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4011256068 Jul 22 08:11:07 PM PDT 24 Jul 22 08:58:31 PM PDT 24 19838578667 ps
T416 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4198409369 Jul 22 08:15:01 PM PDT 24 Jul 22 08:21:36 PM PDT 24 7603810680 ps
T1106 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2560770603 Jul 22 08:37:08 PM PDT 24 Jul 22 08:46:52 PM PDT 24 4002911840 ps
T1107 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2253603076 Jul 22 08:37:13 PM PDT 24 Jul 22 08:41:16 PM PDT 24 2351066180 ps
T115 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1109255504 Jul 22 08:13:00 PM PDT 24 Jul 22 11:03:39 PM PDT 24 72986656196 ps
T29 /workspace/coverage/default/1.chip_sw_gpio.2942296738 Jul 22 08:23:33 PM PDT 24 Jul 22 08:31:39 PM PDT 24 3959782200 ps
T1108 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1076790653 Jul 22 08:23:55 PM PDT 24 Jul 22 08:29:52 PM PDT 24 7926917120 ps
T1109 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.367376077 Jul 22 08:15:55 PM PDT 24 Jul 22 08:27:25 PM PDT 24 4786321976 ps
T1110 /workspace/coverage/default/1.chip_sw_gpio_smoketest.2368933812 Jul 22 08:26:17 PM PDT 24 Jul 22 08:30:51 PM PDT 24 3232933983 ps
T1111 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1500405070 Jul 22 08:17:14 PM PDT 24 Jul 22 08:38:21 PM PDT 24 7630568760 ps
T1112 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3201724035 Jul 22 08:40:08 PM PDT 24 Jul 22 09:43:21 PM PDT 24 15557520904 ps
T345 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1229619737 Jul 22 08:19:26 PM PDT 24 Jul 22 08:32:30 PM PDT 24 4102274216 ps
T1113 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3189863194 Jul 22 08:23:24 PM PDT 24 Jul 22 08:42:28 PM PDT 24 6296268360 ps
T1114 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4278995972 Jul 22 08:14:37 PM PDT 24 Jul 22 11:24:23 PM PDT 24 63640547817 ps
T805 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1104285707 Jul 22 08:42:58 PM PDT 24 Jul 22 08:51:49 PM PDT 24 5380428816 ps
T436 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1062824943 Jul 22 08:33:40 PM PDT 24 Jul 22 09:03:01 PM PDT 24 25554262312 ps
T1115 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3751055462 Jul 22 08:22:08 PM PDT 24 Jul 22 09:19:29 PM PDT 24 14648289684 ps
T1116 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2165689284 Jul 22 08:21:50 PM PDT 24 Jul 22 09:21:06 PM PDT 24 15216340360 ps
T293 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2468231714 Jul 22 08:15:09 PM PDT 24 Jul 22 08:26:02 PM PDT 24 5156291184 ps
T1117 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3579151127 Jul 22 08:16:31 PM PDT 24 Jul 22 08:32:44 PM PDT 24 7294853332 ps
T364 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3890147519 Jul 22 08:23:50 PM PDT 24 Jul 22 08:29:28 PM PDT 24 3575946363 ps
T1118 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2151987157 Jul 22 08:31:49 PM PDT 24 Jul 22 08:53:42 PM PDT 24 5858942550 ps
T1119 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1491831150 Jul 22 08:18:50 PM PDT 24 Jul 22 08:24:08 PM PDT 24 6934934906 ps
T1120 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4248947395 Jul 22 08:13:54 PM PDT 24 Jul 22 08:48:36 PM PDT 24 8718493652 ps
T266 /workspace/coverage/default/34.chip_sw_all_escalation_resets.508061720 Jul 22 08:41:30 PM PDT 24 Jul 22 08:50:20 PM PDT 24 5267340212 ps
T264 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3176368776 Jul 22 08:14:37 PM PDT 24 Jul 22 08:50:54 PM PDT 24 11992054391 ps
T1121 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4031720778 Jul 22 08:39:15 PM PDT 24 Jul 22 08:49:15 PM PDT 24 4178102004 ps
T1122 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3517776445 Jul 22 08:29:03 PM PDT 24 Jul 22 08:47:59 PM PDT 24 7524029480 ps
T787 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1072194116 Jul 22 08:39:27 PM PDT 24 Jul 22 08:45:24 PM PDT 24 3895750368 ps
T1123 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3136558291 Jul 22 08:35:50 PM PDT 24 Jul 22 08:46:04 PM PDT 24 4527578380 ps
T1124 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1349110185 Jul 22 08:11:37 PM PDT 24 Jul 22 08:35:27 PM PDT 24 7507658648 ps
T449 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3201463086 Jul 22 08:15:57 PM PDT 24 Jul 22 08:56:30 PM PDT 24 26546897239 ps
T73 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.828715575 Jul 22 08:24:59 PM PDT 24 Jul 22 10:18:35 PM PDT 24 31627487464 ps
T1125 /workspace/coverage/default/1.chip_sw_hmac_enc.1262677877 Jul 22 08:20:22 PM PDT 24 Jul 22 08:25:30 PM PDT 24 2573565992 ps
T1126 /workspace/coverage/default/0.rom_e2e_smoke.3157610395 Jul 22 08:29:28 PM PDT 24 Jul 22 09:41:50 PM PDT 24 15123476360 ps
T257 /workspace/coverage/default/0.chip_jtag_mem_access.3311250739 Jul 22 08:05:14 PM PDT 24 Jul 22 08:33:25 PM PDT 24 13422017800 ps
T1127 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1087936621 Jul 22 08:40:24 PM PDT 24 Jul 22 09:44:02 PM PDT 24 14931329420 ps
T322 /workspace/coverage/default/1.chip_plic_all_irqs_20.2603857093 Jul 22 08:26:14 PM PDT 24 Jul 22 08:41:58 PM PDT 24 4455157228 ps
T1128 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.380043192 Jul 22 08:16:53 PM PDT 24 Jul 22 08:20:07 PM PDT 24 2156962368 ps
T826 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3503258711 Jul 22 08:45:35 PM PDT 24 Jul 22 08:52:27 PM PDT 24 3997236820 ps
T1129 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2855179991 Jul 22 08:18:52 PM PDT 24 Jul 22 08:32:26 PM PDT 24 7710669580 ps
T91 /workspace/coverage/default/93.chip_sw_all_escalation_resets.458492490 Jul 22 08:46:33 PM PDT 24 Jul 22 08:57:56 PM PDT 24 6716068918 ps
T1130 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3459262370 Jul 22 08:12:27 PM PDT 24 Jul 22 09:49:02 PM PDT 24 27624395224 ps
T777 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.263933683 Jul 22 08:39:46 PM PDT 24 Jul 22 08:48:34 PM PDT 24 3912943212 ps
T1131 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2600144509 Jul 22 08:23:33 PM PDT 24 Jul 22 08:30:44 PM PDT 24 4114518688 ps
T371 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3294185603 Jul 22 08:41:32 PM PDT 24 Jul 22 08:48:48 PM PDT 24 4275986970 ps
T694 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1268851216 Jul 22 08:28:39 PM PDT 24 Jul 22 08:30:30 PM PDT 24 2938399017 ps
T773 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2365213859 Jul 22 08:10:05 PM PDT 24 Jul 22 08:21:47 PM PDT 24 5318795830 ps
T1132 /workspace/coverage/default/2.chip_sw_example_flash.78205973 Jul 22 08:26:07 PM PDT 24 Jul 22 08:29:30 PM PDT 24 2996354466 ps
T1133 /workspace/coverage/default/30.chip_sw_all_escalation_resets.1699486679 Jul 22 08:40:37 PM PDT 24 Jul 22 08:50:26 PM PDT 24 4750466870 ps
T1134 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.141582152 Jul 22 08:18:08 PM PDT 24 Jul 22 09:07:28 PM PDT 24 30935089950 ps
T346 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2822848314 Jul 22 08:21:01 PM PDT 24 Jul 22 08:32:32 PM PDT 24 4318019661 ps
T1135 /workspace/coverage/default/1.chip_sw_kmac_smoketest.1231292047 Jul 22 08:27:17 PM PDT 24 Jul 22 08:32:32 PM PDT 24 3177868020 ps
T1136 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3270994359 Jul 22 08:30:30 PM PDT 24 Jul 22 08:35:57 PM PDT 24 4529141432 ps
T390 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2722767637 Jul 22 08:24:53 PM PDT 24 Jul 22 10:01:04 PM PDT 24 24172067960 ps
T1137 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1530934474 Jul 22 08:24:55 PM PDT 24 Jul 22 09:25:30 PM PDT 24 15458108330 ps
T1138 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1775152815 Jul 22 08:14:49 PM PDT 24 Jul 22 08:25:49 PM PDT 24 4112053992 ps
T1139 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2469977318 Jul 22 08:34:57 PM PDT 24 Jul 22 08:42:19 PM PDT 24 5232881204 ps
T1140 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2003892316 Jul 22 08:43:25 PM PDT 24 Jul 22 08:51:48 PM PDT 24 3957860764 ps
T1141 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1277159814 Jul 22 08:21:26 PM PDT 24 Jul 22 09:21:21 PM PDT 24 14559644052 ps
T1142 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2581805813 Jul 22 08:37:49 PM PDT 24 Jul 22 09:18:20 PM PDT 24 11229559706 ps
T224 /workspace/coverage/default/0.chip_jtag_csr_rw.2089761611 Jul 22 08:05:18 PM PDT 24 Jul 22 08:30:50 PM PDT 24 12666520646 ps
T1143 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.936232828 Jul 22 08:19:15 PM PDT 24 Jul 22 08:25:24 PM PDT 24 3295246616 ps
T1144 /workspace/coverage/default/0.chip_sw_otbn_randomness.2062000494 Jul 22 08:13:13 PM PDT 24 Jul 22 08:28:08 PM PDT 24 6717449110 ps
T784 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3133461303 Jul 22 08:44:16 PM PDT 24 Jul 22 08:50:41 PM PDT 24 3219767900 ps
T1145 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2008515091 Jul 22 08:40:28 PM PDT 24 Jul 22 08:51:05 PM PDT 24 4960232558 ps
T1146 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3407553481 Jul 22 08:32:00 PM PDT 24 Jul 22 08:43:00 PM PDT 24 6499074788 ps
T1147 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.401542820 Jul 22 08:33:06 PM PDT 24 Jul 22 08:36:53 PM PDT 24 2526579408 ps
T812 /workspace/coverage/default/40.chip_sw_all_escalation_resets.2763582437 Jul 22 08:41:29 PM PDT 24 Jul 22 08:50:25 PM PDT 24 5943329076 ps
T1148 /workspace/coverage/default/2.rom_keymgr_functest.3987987147 Jul 22 08:35:39 PM PDT 24 Jul 22 08:46:06 PM PDT 24 3958540968 ps
T1149 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2316156935 Jul 22 08:31:53 PM PDT 24 Jul 22 08:47:33 PM PDT 24 5386589240 ps
T234 /workspace/coverage/default/1.chip_sw_flash_init.1002981140 Jul 22 08:13:45 PM PDT 24 Jul 22 08:49:34 PM PDT 24 22258896423 ps
T1150 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1308232253 Jul 22 08:27:11 PM PDT 24 Jul 22 10:00:36 PM PDT 24 47980463090 ps
T757 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441375946 Jul 22 08:47:18 PM PDT 24 Jul 22 08:54:44 PM PDT 24 4077895452 ps
T1151 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3715613053 Jul 22 08:11:04 PM PDT 24 Jul 22 08:23:44 PM PDT 24 5088235696 ps
T1152 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2024772226 Jul 22 08:34:03 PM PDT 24 Jul 22 08:37:39 PM PDT 24 2097466131 ps
T1153 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1967718608 Jul 22 08:17:12 PM PDT 24 Jul 22 11:25:50 PM PDT 24 63326333137 ps
T1154 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3400007631 Jul 22 08:33:07 PM PDT 24 Jul 22 08:41:22 PM PDT 24 4620546754 ps
T829 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724990215 Jul 22 08:41:59 PM PDT 24 Jul 22 08:48:56 PM PDT 24 3682984942 ps
T732 /workspace/coverage/default/1.chip_sw_pattgen_ios.2463608071 Jul 22 08:18:13 PM PDT 24 Jul 22 08:22:39 PM PDT 24 2835243912 ps
T834 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1066503982 Jul 22 08:43:54 PM PDT 24 Jul 22 08:56:36 PM PDT 24 6803411356 ps
T65 /workspace/coverage/default/2.chip_tap_straps_testunlock0.753952068 Jul 22 08:30:38 PM PDT 24 Jul 22 08:39:11 PM PDT 24 7107029698 ps
T1155 /workspace/coverage/default/2.chip_sw_aes_idle.823090009 Jul 22 08:29:57 PM PDT 24 Jul 22 08:34:05 PM PDT 24 2292780120 ps
T243 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1132782576 Jul 22 08:18:20 PM PDT 24 Jul 22 10:00:41 PM PDT 24 50126570744 ps
T1156 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2702804036 Jul 22 08:18:04 PM PDT 24 Jul 22 08:23:06 PM PDT 24 3202219991 ps
T36 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1647952735 Jul 22 08:27:56 PM PDT 24 Jul 22 08:32:41 PM PDT 24 3010819880 ps
T1157 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2763081869 Jul 22 08:32:12 PM PDT 24 Jul 22 09:53:02 PM PDT 24 14753405712 ps
T835 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.504719785 Jul 22 08:44:01 PM PDT 24 Jul 22 08:50:45 PM PDT 24 4311725190 ps
T754 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1806730461 Jul 22 08:42:28 PM PDT 24 Jul 22 08:51:35 PM PDT 24 5755593402 ps
T47 /workspace/coverage/default/2.chip_sw_alert_test.2647105242 Jul 22 08:29:16 PM PDT 24 Jul 22 08:33:32 PM PDT 24 2585377832 ps
T1158 /workspace/coverage/default/0.chip_tap_straps_prod.860109684 Jul 22 08:13:03 PM PDT 24 Jul 22 08:28:10 PM PDT 24 8262409008 ps
T361 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2656609679 Jul 22 08:13:58 PM PDT 24 Jul 22 08:24:14 PM PDT 24 4786192366 ps
T1159 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.980034148 Jul 22 08:16:46 PM PDT 24 Jul 22 08:35:55 PM PDT 24 6302821500 ps
T747 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1221790081 Jul 22 08:45:49 PM PDT 24 Jul 22 08:52:53 PM PDT 24 3631526262 ps
T320 /workspace/coverage/default/1.chip_plic_all_irqs_0.2293776444 Jul 22 08:22:03 PM PDT 24 Jul 22 08:47:16 PM PDT 24 6315671460 ps
T1160 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.44169525 Jul 22 08:22:19 PM PDT 24 Jul 22 10:32:44 PM PDT 24 24683485582 ps
T1161 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3108634919 Jul 22 08:21:35 PM PDT 24 Jul 22 08:43:14 PM PDT 24 5390675572 ps
T1162 /workspace/coverage/default/0.rom_keymgr_functest.1583607615 Jul 22 08:17:53 PM PDT 24 Jul 22 08:29:47 PM PDT 24 4571296324 ps
T451 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3469653741 Jul 22 08:32:59 PM PDT 24 Jul 22 08:37:28 PM PDT 24 3769424003 ps
T1163 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.640964305 Jul 22 08:30:25 PM PDT 24 Jul 22 08:33:21 PM PDT 24 2574057108 ps
T1164 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3338783905 Jul 22 08:40:32 PM PDT 24 Jul 22 08:49:19 PM PDT 24 7484458923 ps
T1165 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1014447080 Jul 22 08:13:26 PM PDT 24 Jul 22 08:46:40 PM PDT 24 8606491208 ps
T1166 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3309427324 Jul 22 08:12:16 PM PDT 24 Jul 22 08:22:33 PM PDT 24 6337333332 ps
T1167 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2928462066 Jul 22 08:23:00 PM PDT 24 Jul 22 08:35:29 PM PDT 24 4090423468 ps
T813 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725898983 Jul 22 08:41:35 PM PDT 24 Jul 22 08:47:38 PM PDT 24 3367436006 ps
T1168 /workspace/coverage/default/23.chip_sw_all_escalation_resets.580766623 Jul 22 08:41:41 PM PDT 24 Jul 22 08:50:04 PM PDT 24 5201659880 ps
T294 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.213938911 Jul 22 08:32:02 PM PDT 24 Jul 22 08:39:34 PM PDT 24 3640970040 ps
T1169 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.142020982 Jul 22 08:31:54 PM PDT 24 Jul 22 08:37:41 PM PDT 24 2696257536 ps
T437 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.742448043 Jul 22 08:31:43 PM PDT 24 Jul 22 08:41:35 PM PDT 24 8058812632 ps
T1170 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.221287328 Jul 22 08:37:30 PM PDT 24 Jul 22 08:47:56 PM PDT 24 4757988988 ps
T1171 /workspace/coverage/default/2.chip_sw_aes_entropy.14901429 Jul 22 08:30:59 PM PDT 24 Jul 22 08:35:07 PM PDT 24 2317780968 ps
T1172 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3264721203 Jul 22 08:16:45 PM PDT 24 Jul 22 08:21:45 PM PDT 24 2589049528 ps
T830 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1992869096 Jul 22 08:42:21 PM PDT 24 Jul 22 08:51:17 PM PDT 24 5590502960 ps
T1173 /workspace/coverage/default/2.chip_sw_example_rom.3542189421 Jul 22 08:24:55 PM PDT 24 Jul 22 08:27:02 PM PDT 24 2802208456 ps
T1174 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.458338213 Jul 22 08:18:40 PM PDT 24 Jul 22 09:15:49 PM PDT 24 18874350100 ps
T212 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3834526049 Jul 22 08:28:47 PM PDT 24 Jul 22 08:42:03 PM PDT 24 5206478220 ps
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