| T1175 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1785860167 |
|
|
Jul 22 08:24:05 PM PDT 24 |
Jul 22 08:48:37 PM PDT 24 |
7299288589 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2962727879 |
|
|
Jul 22 08:16:10 PM PDT 24 |
Jul 22 09:03:56 PM PDT 24 |
21049762818 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1056756245 |
|
|
Jul 22 08:12:02 PM PDT 24 |
Jul 22 08:19:45 PM PDT 24 |
5516547976 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_aes_enc.2535498384 |
|
|
Jul 22 08:19:47 PM PDT 24 |
Jul 22 08:23:52 PM PDT 24 |
2609709800 ps |
| T1178 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.78001824 |
|
|
Jul 22 08:26:29 PM PDT 24 |
Jul 22 08:35:26 PM PDT 24 |
4318518262 ps |
| T1179 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2682010211 |
|
|
Jul 22 08:14:12 PM PDT 24 |
Jul 22 08:21:56 PM PDT 24 |
4957372988 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3591593782 |
|
|
Jul 22 08:35:00 PM PDT 24 |
Jul 22 08:52:01 PM PDT 24 |
7298542866 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1848098986 |
|
|
Jul 22 08:30:32 PM PDT 24 |
Jul 22 08:40:42 PM PDT 24 |
6004379945 ps |
| T1182 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.113227254 |
|
|
Jul 22 08:31:45 PM PDT 24 |
Jul 22 08:39:20 PM PDT 24 |
4733124472 ps |
| T1183 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.461938399 |
|
|
Jul 22 08:39:00 PM PDT 24 |
Jul 22 09:07:46 PM PDT 24 |
8458099260 ps |
| T742 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1436124775 |
|
|
Jul 22 08:42:00 PM PDT 24 |
Jul 22 08:47:43 PM PDT 24 |
3415583424 ps |
| T372 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2942612382 |
|
|
Jul 22 08:43:47 PM PDT 24 |
Jul 22 08:52:31 PM PDT 24 |
4734096248 ps |
| T414 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.299542534 |
|
|
Jul 22 08:24:14 PM PDT 24 |
Jul 22 08:31:45 PM PDT 24 |
9126391625 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3886361524 |
|
|
Jul 22 08:25:50 PM PDT 24 |
Jul 22 08:38:01 PM PDT 24 |
4423970028 ps |
| T819 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2446426530 |
|
|
Jul 22 08:44:12 PM PDT 24 |
Jul 22 08:49:32 PM PDT 24 |
3130041902 ps |
| T1185 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.2878201876 |
|
|
Jul 22 08:39:01 PM PDT 24 |
Jul 22 09:39:13 PM PDT 24 |
16202700584 ps |
| T1186 |
/workspace/coverage/default/1.rom_e2e_static_critical.3739099634 |
|
|
Jul 22 08:31:04 PM PDT 24 |
Jul 22 09:39:49 PM PDT 24 |
16790103586 ps |
| T797 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146842878 |
|
|
Jul 22 08:45:29 PM PDT 24 |
Jul 22 08:52:56 PM PDT 24 |
4386603966 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2150560683 |
|
|
Jul 22 08:28:45 PM PDT 24 |
Jul 22 09:12:22 PM PDT 24 |
23584897311 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2077869759 |
|
|
Jul 22 08:14:00 PM PDT 24 |
Jul 22 09:17:21 PM PDT 24 |
17091509130 ps |
| T1189 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2197361140 |
|
|
Jul 22 08:39:32 PM PDT 24 |
Jul 22 08:49:45 PM PDT 24 |
7429399412 ps |
| T310 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3525516300 |
|
|
Jul 22 08:31:59 PM PDT 24 |
Jul 22 08:48:56 PM PDT 24 |
9674779399 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3699856290 |
|
|
Jul 22 08:11:56 PM PDT 24 |
Jul 22 08:28:59 PM PDT 24 |
5759153620 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3793079813 |
|
|
Jul 22 08:32:24 PM PDT 24 |
Jul 22 08:37:41 PM PDT 24 |
3084882400 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3984095165 |
|
|
Jul 22 08:23:50 PM PDT 24 |
Jul 22 08:32:47 PM PDT 24 |
3826840120 ps |
| T167 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.873865676 |
|
|
Jul 22 08:12:35 PM PDT 24 |
Jul 22 08:14:30 PM PDT 24 |
2748376747 ps |
| T48 |
/workspace/coverage/default/1.chip_sw_alert_test.1855675277 |
|
|
Jul 22 08:23:18 PM PDT 24 |
Jul 22 08:28:55 PM PDT 24 |
2695509240 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.472330807 |
|
|
Jul 22 08:20:14 PM PDT 24 |
Jul 22 08:25:56 PM PDT 24 |
3819790873 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2804439411 |
|
|
Jul 22 08:11:14 PM PDT 24 |
Jul 22 08:16:48 PM PDT 24 |
3440298765 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2890214385 |
|
|
Jul 22 08:19:14 PM PDT 24 |
Jul 22 08:58:30 PM PDT 24 |
10147723755 ps |
| T1194 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3951131040 |
|
|
Jul 22 08:13:25 PM PDT 24 |
Jul 22 08:41:22 PM PDT 24 |
8571342360 ps |
| T316 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4267778292 |
|
|
Jul 22 08:38:45 PM PDT 24 |
Jul 22 08:46:13 PM PDT 24 |
3640421760 ps |
| T1195 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.157906152 |
|
|
Jul 22 08:38:11 PM PDT 24 |
Jul 22 08:47:31 PM PDT 24 |
4582506204 ps |
| T1196 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.211995656 |
|
|
Jul 22 08:38:37 PM PDT 24 |
Jul 22 09:14:25 PM PDT 24 |
13212215946 ps |
| T810 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872876370 |
|
|
Jul 22 08:43:13 PM PDT 24 |
Jul 22 08:49:20 PM PDT 24 |
3262709240 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_alert_test.3176166196 |
|
|
Jul 22 08:13:16 PM PDT 24 |
Jul 22 08:18:23 PM PDT 24 |
2786287520 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1905387980 |
|
|
Jul 22 08:14:31 PM PDT 24 |
Jul 22 08:24:45 PM PDT 24 |
9400599604 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2672538475 |
|
|
Jul 22 08:21:48 PM PDT 24 |
Jul 22 08:29:55 PM PDT 24 |
7422056568 ps |
| T1199 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.827868008 |
|
|
Jul 22 08:19:08 PM PDT 24 |
Jul 22 09:27:24 PM PDT 24 |
15214414776 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1937692969 |
|
|
Jul 22 08:25:19 PM PDT 24 |
Jul 22 08:38:26 PM PDT 24 |
4471237160 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3126705481 |
|
|
Jul 22 08:32:41 PM PDT 24 |
Jul 22 08:50:02 PM PDT 24 |
8136608966 ps |
| T1202 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4203667136 |
|
|
Jul 22 08:30:54 PM PDT 24 |
Jul 22 08:39:58 PM PDT 24 |
8204691301 ps |
| T92 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3044361181 |
|
|
Jul 22 08:44:23 PM PDT 24 |
Jul 22 08:56:57 PM PDT 24 |
4747124468 ps |
| T824 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3127714923 |
|
|
Jul 22 08:47:10 PM PDT 24 |
Jul 22 08:57:03 PM PDT 24 |
4978213850 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.954803598 |
|
|
Jul 22 08:11:58 PM PDT 24 |
Jul 22 08:22:44 PM PDT 24 |
4307172760 ps |
| T1204 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1472226152 |
|
|
Jul 22 08:19:41 PM PDT 24 |
Jul 22 09:08:46 PM PDT 24 |
11076135288 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.245636327 |
|
|
Jul 22 08:14:57 PM PDT 24 |
Jul 22 08:25:54 PM PDT 24 |
7485938248 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2451181250 |
|
|
Jul 22 08:13:29 PM PDT 24 |
Jul 22 08:39:26 PM PDT 24 |
8788991048 ps |
| T1206 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3768645484 |
|
|
Jul 22 08:26:27 PM PDT 24 |
Jul 22 08:47:50 PM PDT 24 |
9494952486 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.1177162829 |
|
|
Jul 22 08:12:51 PM PDT 24 |
Jul 22 08:19:47 PM PDT 24 |
3358661718 ps |
| T770 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.52869925 |
|
|
Jul 22 08:40:04 PM PDT 24 |
Jul 22 08:46:40 PM PDT 24 |
3589538820 ps |
| T1208 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.69093342 |
|
|
Jul 22 08:27:56 PM PDT 24 |
Jul 22 08:36:15 PM PDT 24 |
7287227845 ps |
| T366 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3429836627 |
|
|
Jul 22 08:13:40 PM PDT 24 |
Jul 22 08:25:30 PM PDT 24 |
5985182800 ps |
| T69 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2804274889 |
|
|
Jul 22 08:36:25 PM PDT 24 |
Jul 22 08:47:29 PM PDT 24 |
6303792858 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2519329807 |
|
|
Jul 22 08:14:17 PM PDT 24 |
Jul 22 08:22:43 PM PDT 24 |
4725781684 ps |
| T150 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1171460072 |
|
|
Jul 22 08:18:31 PM PDT 24 |
Jul 22 08:41:13 PM PDT 24 |
12302964696 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2286759170 |
|
|
Jul 22 08:23:57 PM PDT 24 |
Jul 22 09:03:06 PM PDT 24 |
13336770946 ps |
| T1210 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2034355555 |
|
|
Jul 22 08:12:12 PM PDT 24 |
Jul 22 08:21:53 PM PDT 24 |
4855978232 ps |
| T1211 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3276309755 |
|
|
Jul 22 08:19:26 PM PDT 24 |
Jul 22 08:21:22 PM PDT 24 |
2855495174 ps |
| T1212 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.531105396 |
|
|
Jul 22 08:38:59 PM PDT 24 |
Jul 22 09:04:21 PM PDT 24 |
8394705968 ps |
| T1213 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.786236756 |
|
|
Jul 22 08:22:22 PM PDT 24 |
Jul 22 09:28:14 PM PDT 24 |
14934200973 ps |
| T387 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.303996432 |
|
|
Jul 22 08:11:55 PM PDT 24 |
Jul 22 08:26:42 PM PDT 24 |
5054233172 ps |
| T1214 |
/workspace/coverage/default/0.chip_sival_flash_info_access.3681126806 |
|
|
Jul 22 08:20:05 PM PDT 24 |
Jul 22 08:24:38 PM PDT 24 |
3464366230 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2222092078 |
|
|
Jul 22 08:12:09 PM PDT 24 |
Jul 22 08:20:57 PM PDT 24 |
3558105852 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1827902917 |
|
|
Jul 22 08:12:31 PM PDT 24 |
Jul 22 08:16:36 PM PDT 24 |
3543923460 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3467123868 |
|
|
Jul 22 08:14:48 PM PDT 24 |
Jul 22 08:33:54 PM PDT 24 |
4874106304 ps |
| T1218 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1013309438 |
|
|
Jul 22 08:43:49 PM PDT 24 |
Jul 22 08:53:34 PM PDT 24 |
4639324500 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1951568611 |
|
|
Jul 22 08:24:57 PM PDT 24 |
Jul 22 08:28:58 PM PDT 24 |
2696684350 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4156137773 |
|
|
Jul 22 08:13:14 PM PDT 24 |
Jul 22 09:09:02 PM PDT 24 |
26548467014 ps |
| T1221 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.803588445 |
|
|
Jul 22 08:30:26 PM PDT 24 |
Jul 22 09:26:42 PM PDT 24 |
14925885276 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1405112307 |
|
|
Jul 22 08:28:01 PM PDT 24 |
Jul 22 08:37:22 PM PDT 24 |
6302946550 ps |
| T832 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2859649123 |
|
|
Jul 22 08:40:54 PM PDT 24 |
Jul 22 08:47:37 PM PDT 24 |
4027480876 ps |
| T1222 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.4271105248 |
|
|
Jul 22 08:42:58 PM PDT 24 |
Jul 22 08:51:53 PM PDT 24 |
5290960836 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2238987222 |
|
|
Jul 22 08:14:07 PM PDT 24 |
Jul 22 08:30:58 PM PDT 24 |
5666712184 ps |
| T798 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3206645330 |
|
|
Jul 22 08:44:28 PM PDT 24 |
Jul 22 08:50:31 PM PDT 24 |
4256422650 ps |
| T267 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.482362044 |
|
|
Jul 22 08:43:12 PM PDT 24 |
Jul 22 08:52:20 PM PDT 24 |
4693387976 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.172065427 |
|
|
Jul 22 08:20:48 PM PDT 24 |
Jul 22 11:47:50 PM PDT 24 |
254631301096 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.3009425337 |
|
|
Jul 22 08:31:49 PM PDT 24 |
Jul 22 08:36:12 PM PDT 24 |
2733810855 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.4220762075 |
|
|
Jul 22 08:13:34 PM PDT 24 |
Jul 22 08:18:42 PM PDT 24 |
2894516512 ps |
| T1227 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1002714851 |
|
|
Jul 22 08:12:45 PM PDT 24 |
Jul 22 08:22:54 PM PDT 24 |
8927728142 ps |
| T438 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1947471122 |
|
|
Jul 22 08:22:28 PM PDT 24 |
Jul 22 08:50:32 PM PDT 24 |
25940774872 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3484029381 |
|
|
Jul 22 08:33:21 PM PDT 24 |
Jul 22 09:29:00 PM PDT 24 |
24363172212 ps |
| T1229 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4049201106 |
|
|
Jul 22 08:22:39 PM PDT 24 |
Jul 22 10:19:55 PM PDT 24 |
24438811670 ps |
| T1230 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.893652504 |
|
|
Jul 22 08:21:10 PM PDT 24 |
Jul 22 09:48:20 PM PDT 24 |
21603805148 ps |
| T253 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1367448199 |
|
|
Jul 22 08:45:34 PM PDT 24 |
Jul 22 08:51:24 PM PDT 24 |
3248002500 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.766334089 |
|
|
Jul 22 08:21:19 PM PDT 24 |
Jul 22 08:28:27 PM PDT 24 |
4724775392 ps |
| T807 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1979741461 |
|
|
Jul 22 08:41:53 PM PDT 24 |
Jul 22 08:48:15 PM PDT 24 |
3224159062 ps |
| T801 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.788593483 |
|
|
Jul 22 08:41:20 PM PDT 24 |
Jul 22 08:50:22 PM PDT 24 |
5660556452 ps |
| T728 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2928933278 |
|
|
Jul 22 08:29:52 PM PDT 24 |
Jul 22 08:44:48 PM PDT 24 |
4986059944 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3292824973 |
|
|
Jul 22 08:35:17 PM PDT 24 |
Jul 22 08:39:21 PM PDT 24 |
2904440742 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1957387866 |
|
|
Jul 22 08:24:44 PM PDT 24 |
Jul 22 08:29:11 PM PDT 24 |
2861517362 ps |
| T792 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.343162972 |
|
|
Jul 22 08:44:24 PM PDT 24 |
Jul 22 08:50:13 PM PDT 24 |
3582307588 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1406992637 |
|
|
Jul 22 08:30:15 PM PDT 24 |
Jul 22 08:39:45 PM PDT 24 |
5155468894 ps |
| T1234 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2517153068 |
|
|
Jul 22 08:38:22 PM PDT 24 |
Jul 22 09:20:51 PM PDT 24 |
13129418200 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1585279616 |
|
|
Jul 22 08:12:56 PM PDT 24 |
Jul 22 09:55:27 PM PDT 24 |
46528340464 ps |
| T785 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452928213 |
|
|
Jul 22 08:39:38 PM PDT 24 |
Jul 22 08:47:10 PM PDT 24 |
4173722444 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2018281268 |
|
|
Jul 22 08:31:43 PM PDT 24 |
Jul 22 08:58:26 PM PDT 24 |
8817821172 ps |
| T1237 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3231659995 |
|
|
Jul 22 08:21:40 PM PDT 24 |
Jul 22 08:32:58 PM PDT 24 |
3388983164 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.806625297 |
|
|
Jul 22 08:28:13 PM PDT 24 |
Jul 22 08:55:11 PM PDT 24 |
13453346839 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3580226858 |
|
|
Jul 22 08:28:45 PM PDT 24 |
Jul 22 08:39:29 PM PDT 24 |
5304198200 ps |
| T1240 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3350392080 |
|
|
Jul 22 08:31:25 PM PDT 24 |
Jul 22 08:42:39 PM PDT 24 |
8672537152 ps |
| T1241 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1690642465 |
|
|
Jul 22 08:34:36 PM PDT 24 |
Jul 22 08:42:09 PM PDT 24 |
2940593628 ps |
| T1242 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.554216606 |
|
|
Jul 22 08:17:51 PM PDT 24 |
Jul 22 09:15:02 PM PDT 24 |
15293258982 ps |
| T1243 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2891930809 |
|
|
Jul 22 08:27:17 PM PDT 24 |
Jul 22 08:57:47 PM PDT 24 |
9975959856 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1533434107 |
|
|
Jul 22 08:24:33 PM PDT 24 |
Jul 22 08:31:33 PM PDT 24 |
5036940756 ps |
| T831 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3598350101 |
|
|
Jul 22 08:46:17 PM PDT 24 |
Jul 22 08:54:40 PM PDT 24 |
5616610720 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2843733327 |
|
|
Jul 22 08:13:05 PM PDT 24 |
Jul 22 08:29:07 PM PDT 24 |
6398105480 ps |
| T1244 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1777418000 |
|
|
Jul 22 08:37:36 PM PDT 24 |
Jul 22 08:46:50 PM PDT 24 |
6912167477 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1005432179 |
|
|
Jul 22 08:18:57 PM PDT 24 |
Jul 22 08:20:42 PM PDT 24 |
2379856438 ps |
| T191 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3606172093 |
|
|
Jul 22 08:30:24 PM PDT 24 |
Jul 22 09:46:36 PM PDT 24 |
43808537012 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2886967130 |
|
|
Jul 22 08:20:18 PM PDT 24 |
Jul 22 08:24:46 PM PDT 24 |
2917296884 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.729020110 |
|
|
Jul 22 08:15:02 PM PDT 24 |
Jul 22 08:21:45 PM PDT 24 |
3675447160 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2761534099 |
|
|
Jul 22 08:22:09 PM PDT 24 |
Jul 22 08:32:57 PM PDT 24 |
3858367948 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1564927222 |
|
|
Jul 22 08:11:03 PM PDT 24 |
Jul 22 08:30:19 PM PDT 24 |
10413682050 ps |
| T1250 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3402952033 |
|
|
Jul 22 08:29:33 PM PDT 24 |
Jul 22 08:38:25 PM PDT 24 |
5582623076 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2429812235 |
|
|
Jul 22 08:12:07 PM PDT 24 |
Jul 22 08:14:47 PM PDT 24 |
3208516008 ps |
| T373 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4250075327 |
|
|
Jul 22 08:47:14 PM PDT 24 |
Jul 22 08:56:00 PM PDT 24 |
4481119208 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3245167330 |
|
|
Jul 22 08:19:27 PM PDT 24 |
Jul 22 09:11:52 PM PDT 24 |
20345374807 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2158146540 |
|
|
Jul 22 08:31:39 PM PDT 24 |
Jul 22 08:59:09 PM PDT 24 |
7618925724 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1014974534 |
|
|
Jul 22 08:14:44 PM PDT 24 |
Jul 22 08:19:47 PM PDT 24 |
2884515314 ps |
| T788 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1097773694 |
|
|
Jul 22 08:37:40 PM PDT 24 |
Jul 22 08:44:52 PM PDT 24 |
3356607486 ps |
| T1255 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.473366911 |
|
|
Jul 22 08:37:52 PM PDT 24 |
Jul 22 08:50:25 PM PDT 24 |
5098270770 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.339257727 |
|
|
Jul 22 08:25:48 PM PDT 24 |
Jul 22 08:38:36 PM PDT 24 |
5897972628 ps |
| T1257 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3219187552 |
|
|
Jul 22 08:23:53 PM PDT 24 |
Jul 22 08:34:52 PM PDT 24 |
6130658878 ps |
| T1258 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.20198690 |
|
|
Jul 22 08:15:21 PM PDT 24 |
Jul 22 08:20:43 PM PDT 24 |
3575449256 ps |
| T1259 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4213469755 |
|
|
Jul 22 08:33:00 PM PDT 24 |
Jul 22 08:41:42 PM PDT 24 |
5514481646 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4013586525 |
|
|
Jul 22 08:32:28 PM PDT 24 |
Jul 22 08:44:52 PM PDT 24 |
3611288030 ps |
| T305 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1768582707 |
|
|
Jul 22 08:23:00 PM PDT 24 |
Jul 22 08:28:52 PM PDT 24 |
2613657510 ps |
| T1261 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4060871175 |
|
|
Jul 22 08:44:57 PM PDT 24 |
Jul 22 08:55:04 PM PDT 24 |
4863371208 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4071423071 |
|
|
Jul 22 08:13:38 PM PDT 24 |
Jul 22 08:40:33 PM PDT 24 |
16180559293 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.775149031 |
|
|
Jul 22 08:13:52 PM PDT 24 |
Jul 22 08:24:45 PM PDT 24 |
4482927080 ps |
| T1264 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.533679469 |
|
|
Jul 22 08:40:30 PM PDT 24 |
Jul 22 08:50:59 PM PDT 24 |
7224562792 ps |
| T833 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.225278617 |
|
|
Jul 22 08:39:58 PM PDT 24 |
Jul 22 08:53:27 PM PDT 24 |
5842414756 ps |
| T1265 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.601446531 |
|
|
Jul 22 08:13:31 PM PDT 24 |
Jul 22 08:19:24 PM PDT 24 |
3194116208 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1041626349 |
|
|
Jul 22 08:25:35 PM PDT 24 |
Jul 22 08:29:54 PM PDT 24 |
2361102696 ps |
| T1267 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2973382192 |
|
|
Jul 22 08:20:08 PM PDT 24 |
Jul 22 08:28:19 PM PDT 24 |
3791601400 ps |
| T1268 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3811725283 |
|
|
Jul 22 08:36:17 PM PDT 24 |
Jul 22 08:46:38 PM PDT 24 |
3888180638 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2586792470 |
|
|
Jul 22 08:13:13 PM PDT 24 |
Jul 22 09:21:23 PM PDT 24 |
19161540880 ps |
| T1270 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1966749959 |
|
|
Jul 22 08:36:26 PM PDT 24 |
Jul 22 09:35:02 PM PDT 24 |
14609338688 ps |
| T1271 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3398089830 |
|
|
Jul 22 08:35:53 PM PDT 24 |
Jul 22 08:47:00 PM PDT 24 |
4375801162 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3774010328 |
|
|
Jul 22 08:17:36 PM PDT 24 |
Jul 22 08:28:38 PM PDT 24 |
5518378390 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4170785014 |
|
|
Jul 22 08:12:55 PM PDT 24 |
Jul 22 08:23:23 PM PDT 24 |
4073068032 ps |
| T1274 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.1394420740 |
|
|
Jul 22 08:39:38 PM PDT 24 |
Jul 22 08:48:50 PM PDT 24 |
5082485048 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3641069053 |
|
|
Jul 22 08:18:36 PM PDT 24 |
Jul 22 08:29:19 PM PDT 24 |
3676606600 ps |
| T1276 |
/workspace/coverage/default/0.chip_tap_straps_dev.3284257293 |
|
|
Jul 22 08:15:21 PM PDT 24 |
Jul 22 08:17:52 PM PDT 24 |
2687276801 ps |
| T306 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2394899854 |
|
|
Jul 22 08:13:11 PM PDT 24 |
Jul 22 08:17:57 PM PDT 24 |
2837373308 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2399781648 |
|
|
Jul 22 08:16:28 PM PDT 24 |
Jul 22 08:20:45 PM PDT 24 |
3025902850 ps |
| T149 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3784584245 |
|
|
Jul 22 08:10:52 PM PDT 24 |
Jul 22 08:16:44 PM PDT 24 |
7303535334 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_aes_entropy.4291116109 |
|
|
Jul 22 08:19:53 PM PDT 24 |
Jul 22 08:24:48 PM PDT 24 |
2403059380 ps |
| T336 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2116866899 |
|
|
Jul 22 08:21:13 PM PDT 24 |
Jul 22 08:30:00 PM PDT 24 |
4057755196 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1878861520 |
|
|
Jul 22 08:16:20 PM PDT 24 |
Jul 22 08:27:37 PM PDT 24 |
8050420584 ps |
| T1279 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1623776888 |
|
|
Jul 22 08:38:24 PM PDT 24 |
Jul 22 08:48:05 PM PDT 24 |
5295664508 ps |
| T1280 |
/workspace/coverage/default/1.chip_tap_straps_dev.3884620805 |
|
|
Jul 22 08:22:31 PM PDT 24 |
Jul 22 08:33:30 PM PDT 24 |
6983712811 ps |
| T1281 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3612541395 |
|
|
Jul 22 08:22:35 PM PDT 24 |
Jul 22 08:27:42 PM PDT 24 |
2657093944 ps |
| T202 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3710827336 |
|
|
Jul 22 08:19:43 PM PDT 24 |
Jul 22 08:30:44 PM PDT 24 |
5512294752 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3850346292 |
|
|
Jul 22 08:22:09 PM PDT 24 |
Jul 22 08:53:26 PM PDT 24 |
23849666831 ps |
| T1283 |
/workspace/coverage/default/2.chip_tap_straps_prod.1981920481 |
|
|
Jul 22 08:31:54 PM PDT 24 |
Jul 22 08:34:29 PM PDT 24 |
3179162073 ps |
| T1284 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.91989723 |
|
|
Jul 22 08:12:46 PM PDT 24 |
Jul 22 08:19:14 PM PDT 24 |
3460402936 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_aes_entropy.1737954526 |
|
|
Jul 22 08:12:30 PM PDT 24 |
Jul 22 08:17:23 PM PDT 24 |
2764085490 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.64798986 |
|
|
Jul 22 08:11:22 PM PDT 24 |
Jul 22 08:32:07 PM PDT 24 |
5854883600 ps |
| T1287 |
/workspace/coverage/default/2.rom_e2e_static_critical.3502798771 |
|
|
Jul 22 08:40:22 PM PDT 24 |
Jul 22 09:48:05 PM PDT 24 |
17055594872 ps |
| T776 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.872068628 |
|
|
Jul 22 08:41:32 PM PDT 24 |
Jul 22 08:51:10 PM PDT 24 |
3830354660 ps |
| T112 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1786772298 |
|
|
Jul 22 08:24:16 PM PDT 24 |
Jul 22 08:33:13 PM PDT 24 |
4443766088 ps |
| T1288 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2022349429 |
|
|
Jul 22 08:30:17 PM PDT 24 |
Jul 22 08:39:09 PM PDT 24 |
7030506050 ps |
| T1289 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3173060565 |
|
|
Jul 22 08:43:23 PM PDT 24 |
Jul 22 08:54:31 PM PDT 24 |
4694382848 ps |
| T715 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3607669068 |
|
|
Jul 22 08:13:07 PM PDT 24 |
Jul 22 08:18:05 PM PDT 24 |
3246439192 ps |
| T1290 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3538225689 |
|
|
Jul 22 08:26:29 PM PDT 24 |
Jul 22 08:32:06 PM PDT 24 |
3242248052 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.618805138 |
|
|
Jul 22 08:21:28 PM PDT 24 |
Jul 22 08:24:59 PM PDT 24 |
2467304728 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.463494854 |
|
|
Jul 22 08:33:45 PM PDT 24 |
Jul 22 08:39:50 PM PDT 24 |
3387766493 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.613264950 |
|
|
Jul 22 08:18:46 PM PDT 24 |
Jul 22 08:41:09 PM PDT 24 |
7856101080 ps |
| T1294 |
/workspace/coverage/default/0.chip_sw_aes_idle.2125754030 |
|
|
Jul 22 08:11:56 PM PDT 24 |
Jul 22 08:15:05 PM PDT 24 |
1905171892 ps |
| T1295 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3300102447 |
|
|
Jul 22 08:46:43 PM PDT 24 |
Jul 22 08:57:00 PM PDT 24 |
6030955472 ps |
| T1296 |
/workspace/coverage/default/3.chip_tap_straps_rma.3674079162 |
|
|
Jul 22 08:35:39 PM PDT 24 |
Jul 22 08:38:42 PM PDT 24 |
2784397320 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2561870511 |
|
|
Jul 22 08:34:07 PM PDT 24 |
Jul 22 08:42:59 PM PDT 24 |
3785589977 ps |
| T1298 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.546640985 |
|
|
Jul 22 08:32:38 PM PDT 24 |
Jul 22 08:48:33 PM PDT 24 |
4954498968 ps |
| T1299 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3050983631 |
|
|
Jul 22 08:41:15 PM PDT 24 |
Jul 22 09:31:27 PM PDT 24 |
15770810590 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4030786329 |
|
|
Jul 22 08:25:33 PM PDT 24 |
Jul 22 08:35:47 PM PDT 24 |
5232492824 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1712259295 |
|
|
Jul 22 08:33:30 PM PDT 24 |
Jul 22 08:43:19 PM PDT 24 |
4275465160 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1749522988 |
|
|
Jul 22 08:20:01 PM PDT 24 |
Jul 22 09:43:17 PM PDT 24 |
50055379615 ps |
| T782 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.198913484 |
|
|
Jul 22 08:46:11 PM PDT 24 |
Jul 22 08:55:01 PM PDT 24 |
4517117136 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_edn_kat.1430980508 |
|
|
Jul 22 08:18:14 PM PDT 24 |
Jul 22 08:27:35 PM PDT 24 |
3253891180 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.1752974333 |
|
|
Jul 22 08:35:35 PM PDT 24 |
Jul 22 08:48:30 PM PDT 24 |
5604830244 ps |
| T1305 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.985843443 |
|
|
Jul 22 08:39:40 PM PDT 24 |
Jul 22 09:02:10 PM PDT 24 |
8434809000 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3318243889 |
|
|
Jul 22 08:31:57 PM PDT 24 |
Jul 22 08:45:56 PM PDT 24 |
6391808120 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3943077818 |
|
|
Jul 22 08:33:25 PM PDT 24 |
Jul 22 08:38:09 PM PDT 24 |
2760509981 ps |
| T1307 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1043773348 |
|
|
Jul 22 08:13:50 PM PDT 24 |
Jul 22 08:22:43 PM PDT 24 |
5274000842 ps |
| T1308 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2498432030 |
|
|
Jul 22 08:13:28 PM PDT 24 |
Jul 22 09:11:17 PM PDT 24 |
21189069830 ps |
| T1309 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.3959843549 |
|
|
Jul 22 08:39:46 PM PDT 24 |
Jul 22 08:50:36 PM PDT 24 |
6051072328 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3387126490 |
|
|
Jul 22 08:17:43 PM PDT 24 |
Jul 22 08:22:03 PM PDT 24 |
3586493557 ps |
| T142 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1040548237 |
|
|
Jul 22 08:26:16 PM PDT 24 |
Jul 22 08:41:56 PM PDT 24 |
6357385800 ps |
| T1311 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1309280504 |
|
|
Jul 22 08:17:02 PM PDT 24 |
Jul 22 08:48:00 PM PDT 24 |
13955599638 ps |
| T1312 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2114163770 |
|
|
Jul 22 08:27:13 PM PDT 24 |
Jul 22 08:34:40 PM PDT 24 |
6968557128 ps |
| T802 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1719336583 |
|
|
Jul 22 08:42:27 PM PDT 24 |
Jul 22 08:53:45 PM PDT 24 |
5505958906 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.481477347 |
|
|
Jul 22 08:27:53 PM PDT 24 |
Jul 22 08:45:34 PM PDT 24 |
9537296024 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.484499542 |
|
|
Jul 22 08:15:33 PM PDT 24 |
Jul 22 08:19:47 PM PDT 24 |
3269086759 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2991502991 |
|
|
Jul 22 08:20:47 PM PDT 24 |
Jul 22 09:15:57 PM PDT 24 |
12843119490 ps |
| T1315 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.4195162206 |
|
|
Jul 22 08:30:39 PM PDT 24 |
Jul 22 08:35:17 PM PDT 24 |
3061578060 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2019259888 |
|
|
Jul 22 08:26:30 PM PDT 24 |
Jul 22 08:36:02 PM PDT 24 |
4444174460 ps |
| T1316 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2484196790 |
|
|
Jul 22 08:35:28 PM PDT 24 |
Jul 22 08:45:15 PM PDT 24 |
5623176740 ps |
| T327 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.2504852580 |
|
|
Jul 22 08:19:06 PM PDT 24 |
Jul 22 08:40:11 PM PDT 24 |
5458439564 ps |
| T1317 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239380962 |
|
|
Jul 22 08:40:33 PM PDT 24 |
Jul 22 08:46:48 PM PDT 24 |
3567313720 ps |
| T440 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1932917530 |
|
|
Jul 22 08:33:05 PM PDT 24 |
Jul 22 08:37:47 PM PDT 24 |
4149091880 ps |
| T775 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1910047049 |
|
|
Jul 22 08:45:01 PM PDT 24 |
Jul 22 08:51:13 PM PDT 24 |
4057503270 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2377155595 |
|
|
Jul 22 08:20:51 PM PDT 24 |
Jul 22 08:49:20 PM PDT 24 |
7349077848 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2653226456 |
|
|
Jul 22 08:32:46 PM PDT 24 |
Jul 22 08:46:05 PM PDT 24 |
4303005511 ps |
| T1318 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2144033968 |
|
|
Jul 22 08:12:28 PM PDT 24 |
Jul 22 08:23:17 PM PDT 24 |
7444496730 ps |
| T1319 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2319245848 |
|
|
Jul 22 08:29:56 PM PDT 24 |
Jul 22 09:37:22 PM PDT 24 |
15464996254 ps |
| T736 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.266832134 |
|
|
Jul 22 08:44:13 PM PDT 24 |
Jul 22 08:51:30 PM PDT 24 |
3787353036 ps |
| T56 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.262684932 |
|
|
Jul 22 08:27:39 PM PDT 24 |
Jul 22 08:35:53 PM PDT 24 |
6604952656 ps |
| T1320 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.1106858161 |
|
|
Jul 22 08:27:37 PM PDT 24 |
Jul 22 08:33:59 PM PDT 24 |
3648659904 ps |
| T1321 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2573434865 |
|
|
Jul 22 08:36:18 PM PDT 24 |
Jul 22 08:46:08 PM PDT 24 |
4483300488 ps |
| T1322 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.3871193605 |
|
|
Jul 22 08:31:22 PM PDT 24 |
Jul 22 08:33:10 PM PDT 24 |
2769143311 ps |
| T1323 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2303254286 |
|
|
Jul 22 08:22:14 PM PDT 24 |
Jul 22 08:32:16 PM PDT 24 |
6382869528 ps |
| T1324 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.84630994 |
|
|
Jul 22 08:40:02 PM PDT 24 |
Jul 22 09:19:58 PM PDT 24 |
13801330988 ps |
| T743 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3902599466 |
|
|
Jul 22 08:44:59 PM PDT 24 |
Jul 22 08:51:05 PM PDT 24 |
3598595732 ps |
| T689 |
/workspace/coverage/default/4.chip_tap_straps_dev.3435545050 |
|
|
Jul 22 08:37:39 PM PDT 24 |
Jul 22 08:51:51 PM PDT 24 |
8557664974 ps |
| T1325 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2803067249 |
|
|
Jul 22 08:23:18 PM PDT 24 |
Jul 22 08:35:01 PM PDT 24 |
4911735874 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1447437250 |
|
|
Jul 22 08:28:35 PM PDT 24 |
Jul 22 08:47:34 PM PDT 24 |
5966345272 ps |
| T1327 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1525719595 |
|
|
Jul 22 08:13:11 PM PDT 24 |
Jul 22 08:16:30 PM PDT 24 |
3251408792 ps |
| T1328 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.4024789588 |
|
|
Jul 22 08:13:13 PM PDT 24 |
Jul 22 08:51:43 PM PDT 24 |
8431713000 ps |
| T1329 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2664788097 |
|
|
Jul 22 08:20:34 PM PDT 24 |
Jul 22 08:32:30 PM PDT 24 |
4288197344 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2495577792 |
|
|
Jul 22 08:24:36 PM PDT 24 |
Jul 22 08:28:19 PM PDT 24 |
2819024136 ps |
| T1331 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1205342556 |
|
|
Jul 22 08:18:55 PM PDT 24 |
Jul 22 09:16:04 PM PDT 24 |
14189241334 ps |
| T1332 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3671692246 |
|
|
Jul 22 08:20:49 PM PDT 24 |
Jul 22 08:31:29 PM PDT 24 |
4876984828 ps |
| T727 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3348643210 |
|
|
Jul 22 08:21:02 PM PDT 24 |
Jul 22 08:47:41 PM PDT 24 |
22267548864 ps |
| T1333 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3117933265 |
|
|
Jul 22 08:20:50 PM PDT 24 |
Jul 22 08:31:49 PM PDT 24 |
5095582070 ps |
| T1334 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1843423046 |
|
|
Jul 22 08:28:32 PM PDT 24 |
Jul 22 08:56:29 PM PDT 24 |
13379864560 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2931427576 |
|
|
Jul 22 08:19:24 PM PDT 24 |
Jul 22 08:29:30 PM PDT 24 |
4399595567 ps |
| T1335 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1554893626 |
|
|
Jul 22 08:21:50 PM PDT 24 |
Jul 22 09:22:50 PM PDT 24 |
14988197616 ps |
| T1336 |
/workspace/coverage/default/2.chip_tap_straps_dev.3948752948 |
|
|
Jul 22 08:36:16 PM PDT 24 |
Jul 22 08:54:44 PM PDT 24 |
12148042263 ps |
| T740 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.616608536 |
|
|
Jul 22 08:40:42 PM PDT 24 |
Jul 22 08:46:38 PM PDT 24 |
3396994952 ps |
| T1337 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1131213553 |
|
|
Jul 22 08:18:50 PM PDT 24 |
Jul 22 08:56:14 PM PDT 24 |
11361739370 ps |
| T1338 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.945049533 |
|
|
Jul 22 08:38:32 PM PDT 24 |
Jul 22 08:43:54 PM PDT 24 |
2777796655 ps |
| T1339 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1443749779 |
|
|
Jul 22 08:34:31 PM PDT 24 |
Jul 22 08:38:02 PM PDT 24 |
2752997370 ps |
| T1340 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3760233761 |
|
|
Jul 22 08:11:30 PM PDT 24 |
Jul 22 08:33:17 PM PDT 24 |
6270273951 ps |
| T1341 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3851013968 |
|
|
Jul 22 08:15:07 PM PDT 24 |
Jul 22 08:21:51 PM PDT 24 |
3102560896 ps |
| T1342 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3549479583 |
|
|
Jul 22 08:18:47 PM PDT 24 |
Jul 22 09:19:15 PM PDT 24 |
14714356871 ps |
| T1343 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1563679885 |
|
|
Jul 22 08:18:16 PM PDT 24 |
Jul 22 08:30:31 PM PDT 24 |
4946178521 ps |
| T1344 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3544720346 |
|
|
Jul 22 08:10:37 PM PDT 24 |
Jul 22 08:21:44 PM PDT 24 |
3775610472 ps |
| T768 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2687852536 |
|
|
Jul 22 08:40:55 PM PDT 24 |
Jul 22 08:48:05 PM PDT 24 |
3588522880 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1758783994 |
|
|
Jul 22 08:33:51 PM PDT 24 |
Jul 22 09:33:27 PM PDT 24 |
28937038810 ps |
| T1345 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2337701808 |
|
|
Jul 22 08:14:35 PM PDT 24 |
Jul 22 08:16:12 PM PDT 24 |
2545571161 ps |
| T1346 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1400383861 |
|
|
Jul 22 08:13:46 PM PDT 24 |
Jul 22 08:21:47 PM PDT 24 |
5448534430 ps |
| T1347 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.577883973 |
|
|
Jul 22 08:36:58 PM PDT 24 |
Jul 22 09:06:55 PM PDT 24 |
9063610968 ps |
| T783 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2595640541 |
|
|
Jul 22 08:46:09 PM PDT 24 |
Jul 22 08:55:44 PM PDT 24 |
4364580696 ps |
| T1348 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.808696228 |
|
|
Jul 22 08:20:19 PM PDT 24 |
Jul 22 08:25:01 PM PDT 24 |
3307519924 ps |
| T1349 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2865797996 |
|
|
Jul 22 08:19:58 PM PDT 24 |
Jul 22 09:21:01 PM PDT 24 |
15136691374 ps |
| T1350 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1358749823 |
|
|
Jul 22 08:41:34 PM PDT 24 |
Jul 22 08:51:26 PM PDT 24 |
5283959404 ps |
| T1351 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1299852493 |
|
|
Jul 22 08:14:30 PM PDT 24 |
Jul 22 08:18:45 PM PDT 24 |
2127259754 ps |
| T1352 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2374282067 |
|
|
Jul 22 08:31:37 PM PDT 24 |
Jul 22 11:34:37 PM PDT 24 |
254861507016 ps |