| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.01 | 95.45 | 93.70 | 95.43 | 94.40 | 97.53 | 99.55 |
| T2763 | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2074161647 | Jul 25 07:28:11 PM PDT 24 | Jul 25 07:33:51 PM PDT 24 | 4198388474 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/0.xbar_error_random.2078191705 | Jul 25 07:25:33 PM PDT 24 | Jul 25 07:26:19 PM PDT 24 | 516872791 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.1697644306 | Jul 25 07:38:09 PM PDT 24 | Jul 25 07:39:18 PM PDT 24 | 1134915588 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/36.xbar_smoke.2958832700 | Jul 25 07:38:37 PM PDT 24 | Jul 25 07:38:46 PM PDT 24 | 255113257 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/98.xbar_smoke.1130242426 | Jul 25 07:51:36 PM PDT 24 | Jul 25 07:51:42 PM PDT 24 | 52850788 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.2803278267 | Jul 25 07:48:05 PM PDT 24 | Jul 25 08:23:45 PM PDT 24 | 117378907949 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/16.xbar_smoke.3091292095 | Jul 25 07:32:45 PM PDT 24 | Jul 25 07:32:54 PM PDT 24 | 215731285 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1239969317 | Jul 25 07:47:20 PM PDT 24 | Jul 25 07:47:26 PM PDT 24 | 52573333 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/39.xbar_smoke.2194595330 | Jul 25 07:39:14 PM PDT 24 | Jul 25 07:39:22 PM PDT 24 | 174174204 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2261080652 | Jul 25 07:28:53 PM PDT 24 | Jul 25 07:44:03 PM PDT 24 | 56897162840 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.31579956 | Jul 25 07:41:16 PM PDT 24 | Jul 25 07:41:44 PM PDT 24 | 591861144 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.981518689 | Jul 25 07:30:36 PM PDT 24 | Jul 25 07:48:50 PM PDT 24 | 64323420314 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/52.xbar_error_random.4262431463 | Jul 25 07:42:19 PM PDT 24 | Jul 25 07:42:30 PM PDT 24 | 197201391 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3640769323 | Jul 25 07:50:54 PM PDT 24 | Jul 25 07:52:04 PM PDT 24 | 4504332248 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.822723594 | Jul 25 07:50:47 PM PDT 24 | Jul 25 08:01:21 PM PDT 24 | 57566965248 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3396953010 | Jul 25 07:50:02 PM PDT 24 | Jul 25 07:52:42 PM PDT 24 | 4433323392 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3414048076 | Jul 25 07:38:59 PM PDT 24 | Jul 25 07:48:56 PM PDT 24 | 7076843894 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3346128605 | Jul 25 07:47:26 PM PDT 24 | Jul 25 07:48:07 PM PDT 24 | 527217428 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1897154775 | Jul 25 07:36:33 PM PDT 24 | Jul 25 07:38:50 PM PDT 24 | 3295236181 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/56.xbar_smoke.4003852629 | Jul 25 07:43:23 PM PDT 24 | Jul 25 07:43:31 PM PDT 24 | 193969785 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2081326283 | Jul 25 07:39:34 PM PDT 24 | Jul 25 07:39:41 PM PDT 24 | 47917168 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.291583025 | Jul 25 07:40:54 PM PDT 24 | Jul 25 07:46:02 PM PDT 24 | 4540983257 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1602431109 | Jul 25 07:34:42 PM PDT 24 | Jul 25 07:34:48 PM PDT 24 | 38043240 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1004500043 | Jul 25 07:38:27 PM PDT 24 | Jul 25 08:06:51 PM PDT 24 | 96966970342 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3603595475 | Jul 25 07:51:14 PM PDT 24 | Jul 25 07:52:36 PM PDT 24 | 150838307 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.166917004 | Jul 25 07:35:14 PM PDT 24 | Jul 25 07:42:43 PM PDT 24 | 7825950533 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.316352142 | Jul 25 07:40:11 PM PDT 24 | Jul 25 07:41:32 PM PDT 24 | 7566746052 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3943040055 | Jul 25 07:50:39 PM PDT 24 | Jul 25 07:52:12 PM PDT 24 | 5327475168 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.727088209 | Jul 25 07:49:38 PM PDT 24 | Jul 25 07:56:26 PM PDT 24 | 38412802923 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3440514364 | Jul 25 07:48:16 PM PDT 24 | Jul 25 08:00:28 PM PDT 24 | 44016313576 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3767245157 | Jul 25 07:47:25 PM PDT 24 | Jul 25 07:48:10 PM PDT 24 | 967537651 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/18.xbar_random.2845662369 | Jul 25 07:34:32 PM PDT 24 | Jul 25 07:34:51 PM PDT 24 | 177679705 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/70.xbar_error_random.564135444 | Jul 25 07:47:43 PM PDT 24 | Jul 25 07:48:18 PM PDT 24 | 1078572286 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/25.chip_tl_errors.4192483830 | Jul 25 07:35:52 PM PDT 24 | Jul 25 07:44:32 PM PDT 24 | 6379846639 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4111924401 | Jul 25 07:31:10 PM PDT 24 | Jul 25 07:31:30 PM PDT 24 | 215872857 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1052598988 | Jul 25 07:49:28 PM PDT 24 | Jul 25 07:50:32 PM PDT 24 | 1534893684 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.858580839 | Jul 25 07:43:44 PM PDT 24 | Jul 25 07:44:05 PM PDT 24 | 179697508 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.766035887 | Jul 25 07:36:43 PM PDT 24 | Jul 25 07:46:17 PM PDT 24 | 55217357869 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.2668706657 | Jul 25 07:49:55 PM PDT 24 | Jul 25 07:51:12 PM PDT 24 | 7507455955 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3325264891 | Jul 25 07:50:25 PM PDT 24 | Jul 25 08:07:03 PM PDT 24 | 98169873349 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.905466158 | Jul 25 07:28:40 PM PDT 24 | Jul 25 07:31:21 PM PDT 24 | 535446864 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1211132538 | Jul 25 07:36:19 PM PDT 24 | Jul 25 07:36:26 PM PDT 24 | 51076175 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.157239138 | Jul 25 07:37:32 PM PDT 24 | Jul 25 07:46:36 PM PDT 24 | 30036312820 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.461196452 | Jul 25 07:40:56 PM PDT 24 | Jul 25 07:41:05 PM PDT 24 | 161244402 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3778208219 | Jul 25 07:40:36 PM PDT 24 | Jul 25 07:41:45 PM PDT 24 | 1763444436 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/26.xbar_same_source.1862603364 | Jul 25 07:36:07 PM PDT 24 | Jul 25 07:36:20 PM PDT 24 | 148276708 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/78.xbar_error_random.205395690 | Jul 25 07:48:55 PM PDT 24 | Jul 25 07:49:10 PM PDT 24 | 157886231 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.412216217 | Jul 25 07:38:28 PM PDT 24 | Jul 25 07:38:34 PM PDT 24 | 45205537 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2663317188 | Jul 25 07:28:46 PM PDT 24 | Jul 25 07:28:52 PM PDT 24 | 40340867 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.874782523 | Jul 25 07:41:04 PM PDT 24 | Jul 25 07:42:49 PM PDT 24 | 6265245389 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2342639637 | Jul 25 07:41:29 PM PDT 24 | Jul 25 07:41:35 PM PDT 24 | 47741417 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/45.xbar_smoke.2261564122 | Jul 25 07:40:37 PM PDT 24 | Jul 25 07:40:47 PM PDT 24 | 243020230 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3579667628 | Jul 25 07:48:09 PM PDT 24 | Jul 25 07:49:18 PM PDT 24 | 371197408 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.3512199555 | Jul 25 07:47:17 PM PDT 24 | Jul 25 07:55:38 PM PDT 24 | 30186391749 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2137079105 | Jul 25 07:30:51 PM PDT 24 | Jul 25 07:59:05 PM PDT 24 | 101844879635 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.985655386 | Jul 25 07:40:24 PM PDT 24 | Jul 25 07:40:40 PM PDT 24 | 140122945 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1894571099 | Jul 25 07:38:14 PM PDT 24 | Jul 25 07:38:43 PM PDT 24 | 796013361 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3653074091 | Jul 25 07:48:39 PM PDT 24 | Jul 25 07:48:45 PM PDT 24 | 42708543 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1942885265 | Jul 25 07:48:06 PM PDT 24 | Jul 25 07:48:38 PM PDT 24 | 797499304 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.982734835 | Jul 25 07:25:36 PM PDT 24 | Jul 25 07:33:11 PM PDT 24 | 24646466201 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/65.xbar_stress_all.151352774 | Jul 25 07:47:25 PM PDT 24 | Jul 25 07:55:36 PM PDT 24 | 15037857988 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.777284562 | Jul 25 07:34:44 PM PDT 24 | Jul 25 07:38:54 PM PDT 24 | 3386004122 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/17.xbar_stress_all.2300533212 | Jul 25 07:33:01 PM PDT 24 | Jul 25 07:40:51 PM PDT 24 | 12151931398 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/15.xbar_error_random.703491200 | Jul 25 07:32:23 PM PDT 24 | Jul 25 07:32:50 PM PDT 24 | 793532264 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2098139130 | Jul 25 07:26:16 PM PDT 24 | Jul 25 07:35:59 PM PDT 24 | 34075857311 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1403862456 | Jul 25 07:43:52 PM PDT 24 | Jul 25 07:48:21 PM PDT 24 | 3492759407 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4257498730 | Jul 25 07:50:37 PM PDT 24 | Jul 25 07:52:59 PM PDT 24 | 4117217991 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3561204736 | Jul 25 07:42:21 PM PDT 24 | Jul 25 07:46:12 PM PDT 24 | 7294734772 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2192999529 | Jul 25 07:34:29 PM PDT 24 | Jul 25 07:35:46 PM PDT 24 | 4626043886 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3297446580 | Jul 25 07:41:29 PM PDT 24 | Jul 25 07:41:57 PM PDT 24 | 225602276 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3701789380 | Jul 25 07:38:44 PM PDT 24 | Jul 25 07:42:27 PM PDT 24 | 1198452187 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.190051248 | Jul 25 07:31:14 PM PDT 24 | Jul 25 07:33:10 PM PDT 24 | 11956943413 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3962566680 | Jul 25 07:27:49 PM PDT 24 | Jul 25 07:28:38 PM PDT 24 | 1215391567 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/55.xbar_stress_all.2980506052 | Jul 25 07:43:24 PM PDT 24 | Jul 25 07:50:07 PM PDT 24 | 10438895583 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.893702212 | Jul 25 07:30:26 PM PDT 24 | Jul 25 08:31:39 PM PDT 24 | 29823822890 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.426215678 | Jul 25 07:49:22 PM PDT 24 | Jul 25 07:52:00 PM PDT 24 | 3125429097 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1218770092 | Jul 25 07:47:43 PM PDT 24 | Jul 25 08:05:34 PM PDT 24 | 92739719573 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/96.xbar_random.1917293110 | Jul 25 07:51:14 PM PDT 24 | Jul 25 07:52:19 PM PDT 24 | 1957127852 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.5392315 | Jul 25 07:49:47 PM PDT 24 | Jul 25 07:50:40 PM PDT 24 | 610121076 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/90.xbar_same_source.2437669820 | Jul 25 07:50:18 PM PDT 24 | Jul 25 07:50:56 PM PDT 24 | 571738598 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.653920454 | Jul 25 07:28:00 PM PDT 24 | Jul 25 07:29:33 PM PDT 24 | 5449253057 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1403103779 | Jul 25 07:48:38 PM PDT 24 | Jul 25 08:07:53 PM PDT 24 | 108504193877 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2113531386 | Jul 25 07:50:28 PM PDT 24 | Jul 25 08:03:17 PM PDT 24 | 45446921631 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/16.chip_csr_rw.141193499 | Jul 25 07:32:46 PM PDT 24 | Jul 25 07:42:38 PM PDT 24 | 5808832160 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.355957484 | Jul 25 07:50:51 PM PDT 24 | Jul 25 07:51:28 PM PDT 24 | 812808837 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3857927958 | Jul 25 07:47:23 PM PDT 24 | Jul 25 07:51:33 PM PDT 24 | 1533544565 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.121290413 | Jul 25 07:25:54 PM PDT 24 | Jul 25 07:33:16 PM PDT 24 | 9142121061 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2362193233 | Jul 25 07:43:52 PM PDT 24 | Jul 25 07:45:11 PM PDT 24 | 7729989476 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/46.xbar_error_random.748985445 | Jul 25 07:41:05 PM PDT 24 | Jul 25 07:41:37 PM PDT 24 | 911504212 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.257650256 | Jul 25 07:34:32 PM PDT 24 | Jul 25 07:39:46 PM PDT 24 | 1188695704 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.848658670 | Jul 25 07:47:24 PM PDT 24 | Jul 25 07:48:53 PM PDT 24 | 2620190005 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.3782642181 | Jul 25 07:36:21 PM PDT 24 | Jul 25 07:49:28 PM PDT 24 | 49945260825 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3358272489 | Jul 25 07:34:31 PM PDT 24 | Jul 25 07:34:37 PM PDT 24 | 45747474 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/34.xbar_error_random.2558195746 | Jul 25 07:38:29 PM PDT 24 | Jul 25 07:38:58 PM PDT 24 | 1004944963 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/33.xbar_random.3507300959 | Jul 25 07:38:11 PM PDT 24 | Jul 25 07:38:18 PM PDT 24 | 106939911 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/29.xbar_same_source.4052118404 | Jul 25 07:36:58 PM PDT 24 | Jul 25 07:38:11 PM PDT 24 | 2371060085 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/26.xbar_error_random.104803840 | Jul 25 07:36:07 PM PDT 24 | Jul 25 07:37:44 PM PDT 24 | 2572381471 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/44.xbar_smoke.455936 | Jul 25 07:40:24 PM PDT 24 | Jul 25 07:40:33 PM PDT 24 | 205203737 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2877238376 | Jul 25 07:29:10 PM PDT 24 | Jul 25 07:33:47 PM PDT 24 | 623946454 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1227164646 | Jul 25 07:31:33 PM PDT 24 | Jul 25 07:33:46 PM PDT 24 | 321842135 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3156791815 | Jul 25 07:48:58 PM PDT 24 | Jul 25 07:54:54 PM PDT 24 | 21573052718 ps | ||
| T665 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2123833178 | Jul 25 07:42:59 PM PDT 24 | Jul 25 07:45:39 PM PDT 24 | 3914956978 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1821742356 | Jul 25 07:48:56 PM PDT 24 | Jul 25 07:51:26 PM PDT 24 | 4359514173 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/10.xbar_error_random.1579953921 | Jul 25 07:30:16 PM PDT 24 | Jul 25 07:30:29 PM PDT 24 | 143692213 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.708683307 | Jul 25 07:25:53 PM PDT 24 | Jul 25 07:38:21 PM PDT 24 | 73766470575 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/59.xbar_error_random.2634414648 | Jul 25 07:43:51 PM PDT 24 | Jul 25 07:44:00 PM PDT 24 | 82122328 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3965306492 | Jul 25 07:43:30 PM PDT 24 | Jul 25 08:04:07 PM PDT 24 | 67553594017 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/90.xbar_smoke.907199653 | Jul 25 07:50:16 PM PDT 24 | Jul 25 07:50:25 PM PDT 24 | 221227229 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2236497979 | Jul 25 07:49:34 PM PDT 24 | Jul 25 07:53:10 PM PDT 24 | 2782062533 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/41.xbar_same_source.1483645320 | Jul 25 07:40:01 PM PDT 24 | Jul 25 07:40:15 PM PDT 24 | 159970801 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.51251458 | Jul 25 07:47:55 PM PDT 24 | Jul 25 08:02:19 PM PDT 24 | 48888628175 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.128826817 | Jul 25 07:50:06 PM PDT 24 | Jul 25 07:56:09 PM PDT 24 | 22113164137 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/50.xbar_same_source.2473966627 | Jul 25 07:41:43 PM PDT 24 | Jul 25 07:43:01 PM PDT 24 | 2723654730 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/64.xbar_error_random.4234231074 | Jul 25 07:47:13 PM PDT 24 | Jul 25 07:48:46 PM PDT 24 | 2480015986 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.620318637 | Jul 25 07:43:33 PM PDT 24 | Jul 25 07:44:53 PM PDT 24 | 7995017706 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3878448959 | Jul 25 07:48:43 PM PDT 24 | Jul 25 07:52:48 PM PDT 24 | 14866066830 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3097039259 | Jul 25 07:32:22 PM PDT 24 | Jul 25 07:34:04 PM PDT 24 | 5790663826 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.263029540 | Jul 25 07:35:36 PM PDT 24 | Jul 25 07:36:35 PM PDT 24 | 214030227 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/1.xbar_smoke.3572920766 | Jul 25 07:25:53 PM PDT 24 | Jul 25 07:25:59 PM PDT 24 | 39868897 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3173863874 | Jul 25 07:47:16 PM PDT 24 | Jul 25 07:59:40 PM PDT 24 | 44106341341 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3324918868 | Jul 25 07:41:08 PM PDT 24 | Jul 25 07:42:35 PM PDT 24 | 8662950482 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2568500986 | Jul 25 07:49:14 PM PDT 24 | Jul 25 07:49:45 PM PDT 24 | 395840153 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2105257943 | Jul 25 07:43:31 PM PDT 24 | Jul 25 07:44:56 PM PDT 24 | 1320407204 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2955407299 | Jul 25 07:38:13 PM PDT 24 | Jul 25 07:38:44 PM PDT 24 | 732591661 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3017219184 | Jul 25 07:31:46 PM PDT 24 | Jul 25 07:31:54 PM PDT 24 | 55846474 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3552954855 | Jul 25 07:50:48 PM PDT 24 | Jul 25 08:01:31 PM PDT 24 | 34321352630 ps | ||
| T437 | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.188773967 | Jul 25 07:29:53 PM PDT 24 | Jul 25 07:46:25 PM PDT 24 | 12681492280 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/40.xbar_same_source.3783967195 | Jul 25 07:39:48 PM PDT 24 | Jul 25 07:40:07 PM PDT 24 | 230632089 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1313243136 | Jul 25 07:39:36 PM PDT 24 | Jul 25 08:04:17 PM PDT 24 | 88724155554 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/40.xbar_stress_all.826716152 | Jul 25 07:39:47 PM PDT 24 | Jul 25 07:46:20 PM PDT 24 | 4918500397 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.494956209 | Jul 25 07:43:45 PM PDT 24 | Jul 25 07:51:24 PM PDT 24 | 9998529538 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/71.xbar_same_source.29266896 | Jul 25 07:47:49 PM PDT 24 | Jul 25 07:49:05 PM PDT 24 | 2447476522 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2994188764 | Jul 25 07:25:34 PM PDT 24 | Jul 25 07:27:15 PM PDT 24 | 2677281784 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.78983573 | Jul 25 07:34:33 PM PDT 24 | Jul 25 07:35:46 PM PDT 24 | 7664893030 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1909624530 | Jul 25 07:47:43 PM PDT 24 | Jul 25 08:10:16 PM PDT 24 | 74695533230 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2246275039 | Jul 25 07:49:33 PM PDT 24 | Jul 25 07:49:39 PM PDT 24 | 42184271 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3076665469 | Jul 25 07:49:22 PM PDT 24 | Jul 25 08:06:40 PM PDT 24 | 60588264346 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2860330113 | Jul 25 07:40:23 PM PDT 24 | Jul 25 07:40:27 PM PDT 24 | 6604990 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2957686545 | Jul 25 07:49:21 PM PDT 24 | Jul 25 08:07:05 PM PDT 24 | 100902372140 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2651276208 | Jul 25 07:37:08 PM PDT 24 | Jul 25 07:38:53 PM PDT 24 | 1304446498 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3836790880 | Jul 25 07:47:42 PM PDT 24 | Jul 25 07:47:48 PM PDT 24 | 42276739 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.4067901345 | Jul 25 07:32:53 PM PDT 24 | Jul 25 07:39:00 PM PDT 24 | 7077209864 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4251679345 | Jul 25 07:30:07 PM PDT 24 | Jul 25 07:30:48 PM PDT 24 | 491761093 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3783629332 | Jul 25 07:51:45 PM PDT 24 | Jul 25 08:10:51 PM PDT 24 | 107206241493 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/50.xbar_random.1644404176 | Jul 25 07:41:41 PM PDT 24 | Jul 25 07:42:57 PM PDT 24 | 2115166613 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/7.chip_csr_rw.834203491 | Jul 25 07:29:10 PM PDT 24 | Jul 25 07:39:06 PM PDT 24 | 5699794396 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1243959762 | Jul 25 07:47:49 PM PDT 24 | Jul 25 07:48:23 PM PDT 24 | 303379561 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2255953238 | Jul 25 07:38:31 PM PDT 24 | Jul 25 07:39:00 PM PDT 24 | 376610330 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2195114433 | Jul 25 07:38:34 PM PDT 24 | Jul 25 07:38:43 PM PDT 24 | 175186835 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.340858144 | Jul 25 07:48:15 PM PDT 24 | Jul 25 07:48:55 PM PDT 24 | 1076653725 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.430544712 | Jul 25 07:50:49 PM PDT 24 | Jul 25 07:50:55 PM PDT 24 | 37770025 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3375104542 | Jul 25 07:47:35 PM PDT 24 | Jul 25 07:47:48 PM PDT 24 | 98852192 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/4.xbar_error_random.2049176987 | Jul 25 07:27:51 PM PDT 24 | Jul 25 07:28:20 PM PDT 24 | 861555632 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2219943572 | Jul 25 07:49:31 PM PDT 24 | Jul 25 07:49:49 PM PDT 24 | 190975343 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.61539480 | Jul 25 07:29:27 PM PDT 24 | Jul 25 08:00:23 PM PDT 24 | 108285554612 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1093041461 | Jul 25 07:30:14 PM PDT 24 | Jul 25 07:32:50 PM PDT 24 | 4549981771 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2616848989 | Jul 25 07:43:00 PM PDT 24 | Jul 25 07:45:04 PM PDT 24 | 11920495377 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3187601719 | Jul 25 07:47:31 PM PDT 24 | Jul 25 07:49:54 PM PDT 24 | 719462314 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1110076964 | Jul 25 07:28:59 PM PDT 24 | Jul 25 07:29:06 PM PDT 24 | 31343207 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.4162539243 | Jul 25 07:32:54 PM PDT 24 | Jul 25 07:34:44 PM PDT 24 | 3532023363 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1443524655 | Jul 25 07:29:24 PM PDT 24 | Jul 25 07:29:31 PM PDT 24 | 37668548 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2402918331 | Jul 25 07:28:45 PM PDT 24 | Jul 25 07:30:06 PM PDT 24 | 8507668500 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.344784026 | Jul 25 07:50:27 PM PDT 24 | Jul 25 07:50:34 PM PDT 24 | 51208306 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1438982372 | Jul 25 07:40:03 PM PDT 24 | Jul 25 07:51:48 PM PDT 24 | 39980005631 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.613548501 | Jul 25 07:38:49 PM PDT 24 | Jul 25 07:39:25 PM PDT 24 | 721886507 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1666381042 | Jul 25 07:26:08 PM PDT 24 | Jul 25 07:32:42 PM PDT 24 | 7989099412 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/12.xbar_random.2898819310 | Jul 25 07:30:58 PM PDT 24 | Jul 25 07:31:21 PM PDT 24 | 579594147 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3642684950 | Jul 25 07:47:50 PM PDT 24 | Jul 25 07:48:51 PM PDT 24 | 5862147052 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1022333049 | Jul 25 07:42:19 PM PDT 24 | Jul 25 07:43:38 PM PDT 24 | 5267153577 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3147318152 | Jul 25 07:49:53 PM PDT 24 | Jul 25 07:57:24 PM PDT 24 | 13523820733 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2173713499 | Jul 25 07:50:37 PM PDT 24 | Jul 25 07:51:20 PM PDT 24 | 472161121 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/55.xbar_smoke.417196048 | Jul 25 07:43:02 PM PDT 24 | Jul 25 07:43:12 PM PDT 24 | 216364886 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3511905063 | Jul 25 07:47:19 PM PDT 24 | Jul 25 07:49:01 PM PDT 24 | 6266939142 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3175736179 | Jul 25 07:28:52 PM PDT 24 | Jul 25 07:42:11 PM PDT 24 | 45626386906 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1592817440 | Jul 25 07:50:50 PM PDT 24 | Jul 25 08:00:11 PM PDT 24 | 7109115236 ps | ||
| T2936 | /workspace/coverage/cover_reg_top/16.xbar_stress_all.918250295 | Jul 25 07:32:45 PM PDT 24 | Jul 25 07:33:58 PM PDT 24 | 2152553782 ps | ||
| T2937 | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2707195535 | Jul 25 07:41:29 PM PDT 24 | Jul 25 07:57:42 PM PDT 24 | 58532499924 ps | ||
| T30 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2292029652 | Jul 25 08:30:51 PM PDT 24 | Jul 25 08:36:05 PM PDT 24 | 5139336153 ps | ||
| T31 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.791700569 | Jul 25 08:31:15 PM PDT 24 | Jul 25 08:35:49 PM PDT 24 | 5684102042 ps | ||
| T32 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2082634224 | Jul 25 08:31:04 PM PDT 24 | Jul 25 08:36:11 PM PDT 24 | 5202929364 ps | ||
| T36 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3157581783 | Jul 25 08:30:50 PM PDT 24 | Jul 25 08:35:39 PM PDT 24 | 4629728500 ps | ||
| T195 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4115801926 | Jul 25 08:30:47 PM PDT 24 | Jul 25 08:35:46 PM PDT 24 | 4546432004 ps | ||
| T196 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3705948219 | Jul 25 08:31:02 PM PDT 24 | Jul 25 08:35:43 PM PDT 24 | 5873162310 ps | ||
| T197 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.65676072 | Jul 25 08:31:07 PM PDT 24 | Jul 25 08:35:29 PM PDT 24 | 4944049292 ps | ||
| T198 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.242727893 | Jul 25 08:31:13 PM PDT 24 | Jul 25 08:36:31 PM PDT 24 | 6005704998 ps | ||
| T199 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2480218275 | Jul 25 08:31:04 PM PDT 24 | Jul 25 08:36:57 PM PDT 24 | 5945794116 ps | ||
| T200 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1150904826 | Jul 25 08:31:17 PM PDT 24 | Jul 25 08:35:07 PM PDT 24 | 4352824320 ps |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1121556817 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5728234000 ps |
| CPU time | 441.61 seconds |
| Started | Jul 25 08:12:23 PM PDT 24 |
| Finished | Jul 25 08:19:46 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-ae845ef4-752e-468e-8943-07033c292e5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215568 17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1121556817 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.1584985954 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 6264178927 ps |
| CPU time | 500.79 seconds |
| Started | Jul 25 07:31:34 PM PDT 24 |
| Finished | Jul 25 07:39:55 PM PDT 24 |
| Peak memory | 598936 kb |
| Host | smart-ede6f722-d25b-4592-a7b4-7d6a1036e92c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584985954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.1584985954 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.249592091 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4973018556 ps |
| CPU time | 822.89 seconds |
| Started | Jul 25 08:23:21 PM PDT 24 |
| Finished | Jul 25 08:37:04 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-22601b7d-cac5-4a5a-9fd8-061fd693115a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249592091 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.249592091 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1212422026 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 143911583110 ps |
| CPU time | 2422.52 seconds |
| Started | Jul 25 07:49:07 PM PDT 24 |
| Finished | Jul 25 08:29:30 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-b664e2ae-a350-4d84-8266-1495bf0e7450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212422026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1212422026 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.293399025 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 8484460985 ps |
| CPU time | 280.36 seconds |
| Started | Jul 25 07:51:45 PM PDT 24 |
| Finished | Jul 25 07:56:26 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-93386173-0ec7-4354-8aec-934bd8c732e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293399025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.293399025 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2292029652 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5139336153 ps |
| CPU time | 314.35 seconds |
| Started | Jul 25 08:30:51 PM PDT 24 |
| Finished | Jul 25 08:36:05 PM PDT 24 |
| Peak memory | 649696 kb |
| Host | smart-ef836cb2-a5d1-454e-9b81-81d0ddbecdd8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292029652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.2292029652 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3030930585 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 121964287465 ps |
| CPU time | 1988.8 seconds |
| Started | Jul 25 07:47:41 PM PDT 24 |
| Finished | Jul 25 08:20:50 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-285244f3-407d-40c5-a7ed-de411ab42456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030930585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3030930585 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.861736336 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 7438833096 ps |
| CPU time | 1154.08 seconds |
| Started | Jul 25 08:17:24 PM PDT 24 |
| Finished | Jul 25 08:36:39 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-c518d995-f45d-400c-89eb-5d15d9b05f76 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=861736336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.861736336 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4128405893 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 81898132996 ps |
| CPU time | 1401.31 seconds |
| Started | Jul 25 07:30:15 PM PDT 24 |
| Finished | Jul 25 07:53:37 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-d7cdff8a-0ad0-40fe-9293-7eb837aa17d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128405893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.4128405893 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3485695556 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15318957915 ps |
| CPU time | 4289.85 seconds |
| Started | Jul 25 08:22:07 PM PDT 24 |
| Finished | Jul 25 09:33:38 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-eed1b4c9-04ac-456e-a5df-afe938a57922 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485695556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3485695556 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1289784231 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6157984666 ps |
| CPU time | 1071.7 seconds |
| Started | Jul 25 08:24:55 PM PDT 24 |
| Finished | Jul 25 08:42:48 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-80022a16-c804-4695-a18a-3d20264e5031 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289784231 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1289784231 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.5601527 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2919605044 ps |
| CPU time | 358.81 seconds |
| Started | Jul 25 08:04:21 PM PDT 24 |
| Finished | Jul 25 08:10:20 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-0a8cb5c5-156f-43c3-863e-7cbeaecdce74 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5601 527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.5601527 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2296012906 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 22605568435 ps |
| CPU time | 2133.63 seconds |
| Started | Jul 25 07:59:25 PM PDT 24 |
| Finished | Jul 25 08:34:59 PM PDT 24 |
| Peak memory | 621620 kb |
| Host | smart-ced1209e-f5fa-4b82-b396-ec3a86192835 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2296012906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.2296012906 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2906438561 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 50589208538 ps |
| CPU time | 918.11 seconds |
| Started | Jul 25 07:49:39 PM PDT 24 |
| Finished | Jul 25 08:04:58 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f55d20cb-965a-4b39-8c7e-640e5601456f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906438561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2906438561 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1972946965 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3478225444 ps |
| CPU time | 306.74 seconds |
| Started | Jul 25 08:25:41 PM PDT 24 |
| Finished | Jul 25 08:30:48 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-eb9340e8-c1a9-45b0-b788-69dc6e2ad7ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1972946965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1972946965 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3281506668 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 12067990348 ps |
| CPU time | 1793.98 seconds |
| Started | Jul 25 08:02:37 PM PDT 24 |
| Finished | Jul 25 08:32:32 PM PDT 24 |
| Peak memory | 611568 kb |
| Host | smart-e6a85ff8-2e62-4204-85aa-88755929aaf6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281506668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3281506668 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2187636385 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 93205946720 ps |
| CPU time | 1636.28 seconds |
| Started | Jul 25 07:41:50 PM PDT 24 |
| Finished | Jul 25 08:09:06 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-e2e2abcd-07ee-4bbc-82c0-77c1d336a5ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187636385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.2187636385 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.484183119 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 6492612852 ps |
| CPU time | 997.23 seconds |
| Started | Jul 25 08:08:31 PM PDT 24 |
| Finished | Jul 25 08:25:09 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-5bb57423-82fc-41cd-8b1c-01009b386e72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48418 3119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.484183119 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.2121545292 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5803400338 ps |
| CPU time | 1335.26 seconds |
| Started | Jul 25 08:20:55 PM PDT 24 |
| Finished | Jul 25 08:43:11 PM PDT 24 |
| Peak memory | 625616 kb |
| Host | smart-28d83c5f-54f2-43fb-b9d0-072666df0b9d |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2121545292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2121545292 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2669509583 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3997045027 ps |
| CPU time | 301.35 seconds |
| Started | Jul 25 08:08:18 PM PDT 24 |
| Finished | Jul 25 08:13:19 PM PDT 24 |
| Peak memory | 619748 kb |
| Host | smart-5b30edec-9fa4-406e-9437-40cefe4e4a81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669509583 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.2669509583 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3188074365 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 9608681501 ps |
| CPU time | 363.33 seconds |
| Started | Jul 25 07:40:16 PM PDT 24 |
| Finished | Jul 25 07:46:20 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-1252b4d7-aece-4b55-bafd-4a28f7b13272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188074365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3188074365 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3618666842 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 162806493005 ps |
| CPU time | 3193.81 seconds |
| Started | Jul 25 07:39:23 PM PDT 24 |
| Finished | Jul 25 08:32:37 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-5d8e5ba8-7ee5-4a33-ae09-3f9046eb91f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618666842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.3618666842 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2499107090 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 17533657324 ps |
| CPU time | 1911.97 seconds |
| Started | Jul 25 08:15:45 PM PDT 24 |
| Finished | Jul 25 08:47:37 PM PDT 24 |
| Peak memory | 604576 kb |
| Host | smart-3ed1accd-b7f0-4d9a-a007-a8094628c934 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499107090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2499107090 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2602843346 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4280129550 ps |
| CPU time | 362.95 seconds |
| Started | Jul 25 07:31:57 PM PDT 24 |
| Finished | Jul 25 07:38:00 PM PDT 24 |
| Peak memory | 603404 kb |
| Host | smart-9c64f0a2-d0d6-4626-a8d8-44cf93020110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602843346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2602843346 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2961812532 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 135858221328 ps |
| CPU time | 18959 seconds |
| Started | Jul 25 08:26:05 PM PDT 24 |
| Finished | Jul 26 01:42:07 AM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-a1037032-8d10-4998-bb59-1afcd800714c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2961812532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2961812532 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.857777163 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 85621415809 ps |
| CPU time | 1548.69 seconds |
| Started | Jul 25 07:49:27 PM PDT 24 |
| Finished | Jul 25 08:15:16 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-f9200112-3bf2-41c0-91ec-95d8e0ac8c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857777163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_d evice_slow_rsp.857777163 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.3142672810 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3283107926 ps |
| CPU time | 577.2 seconds |
| Started | Jul 25 08:22:55 PM PDT 24 |
| Finished | Jul 25 08:32:33 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-829d2e85-ba2d-46f9-aa53-4d91d16dcf83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142672810 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3142672810 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.913740958 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4492603292 ps |
| CPU time | 492.9 seconds |
| Started | Jul 25 08:04:07 PM PDT 24 |
| Finished | Jul 25 08:12:20 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-18837059-6a5b-4ee9-8f24-f4711ee1f5e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913740958 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.913740958 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.660136069 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 72792008885 ps |
| CPU time | 1311.46 seconds |
| Started | Jul 25 07:49:29 PM PDT 24 |
| Finished | Jul 25 08:11:21 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-cc3a2eff-7afb-44b8-9b0d-3d5d0caed5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660136069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.660136069 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2145773357 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 31551462688 ps |
| CPU time | 3911.23 seconds |
| Started | Jul 25 07:31:01 PM PDT 24 |
| Finished | Jul 25 08:36:13 PM PDT 24 |
| Peak memory | 592668 kb |
| Host | smart-c62a8c09-1eac-48ff-9cc5-547bb962c7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145773357 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2145773357 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.802966150 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 20018766839 ps |
| CPU time | 1492.79 seconds |
| Started | Jul 25 08:15:57 PM PDT 24 |
| Finished | Jul 25 08:40:50 PM PDT 24 |
| Peak memory | 617148 kb |
| Host | smart-076cb8c1-ea03-48d4-8deb-2c99b3fbd6cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=802966150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.802966150 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.2472047120 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 485347138 ps |
| CPU time | 46.49 seconds |
| Started | Jul 25 07:41:04 PM PDT 24 |
| Finished | Jul 25 07:41:51 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-3c9f6de0-e5d6-4386-b343-03959055f510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472047120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.2472047120 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1211874005 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4393801416 ps |
| CPU time | 586.9 seconds |
| Started | Jul 25 08:33:28 PM PDT 24 |
| Finished | Jul 25 08:43:15 PM PDT 24 |
| Peak memory | 650688 kb |
| Host | smart-bed1723d-358e-4269-83e8-aefbb51945ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1211874005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1211874005 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3559631883 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 5399157703 ps |
| CPU time | 720.32 seconds |
| Started | Jul 25 07:49:53 PM PDT 24 |
| Finished | Jul 25 08:01:54 PM PDT 24 |
| Peak memory | 577732 kb |
| Host | smart-ec241cca-f2c2-4e2f-9c0a-54a7c8e4283e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559631883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.3559631883 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3701746520 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3495621868 ps |
| CPU time | 345.78 seconds |
| Started | Jul 25 08:01:02 PM PDT 24 |
| Finished | Jul 25 08:06:48 PM PDT 24 |
| Peak memory | 611156 kb |
| Host | smart-c344af22-57c0-4c4f-b661-7e16b97ef67c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701 746520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3701746520 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1287391234 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 44155398959 ps |
| CPU time | 4587.31 seconds |
| Started | Jul 25 08:04:42 PM PDT 24 |
| Finished | Jul 25 09:21:10 PM PDT 24 |
| Peak memory | 621552 kb |
| Host | smart-daedee8d-0dd4-40b7-9ee8-67a3e4cf257c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1287391234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1287391234 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1604168573 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 7855530487 ps |
| CPU time | 76.2 seconds |
| Started | Jul 25 07:47:46 PM PDT 24 |
| Finished | Jul 25 07:49:02 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-5eeceb41-a35b-41ca-8e70-47471e752488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604168573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1604168573 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.882804805 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3997558538 ps |
| CPU time | 557.51 seconds |
| Started | Jul 25 08:03:55 PM PDT 24 |
| Finished | Jul 25 08:13:13 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-0fddf84d-cf79-45ad-b887-997fff9ce6c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882804805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.882804805 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.133588573 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 25313162100 ps |
| CPU time | 1964.52 seconds |
| Started | Jul 25 08:00:10 PM PDT 24 |
| Finished | Jul 25 08:32:55 PM PDT 24 |
| Peak memory | 615936 kb |
| Host | smart-e1cfaacb-3966-4eb9-a726-3aec233a80dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13358857 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.133588573 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.1779895434 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 4441049035 ps |
| CPU time | 323.49 seconds |
| Started | Jul 25 07:32:47 PM PDT 24 |
| Finished | Jul 25 07:38:11 PM PDT 24 |
| Peak memory | 603388 kb |
| Host | smart-6a04e444-43a6-468c-b88a-309dc56572ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779895434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1779895434 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3157581783 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4629728500 ps |
| CPU time | 288.53 seconds |
| Started | Jul 25 08:30:50 PM PDT 24 |
| Finished | Jul 25 08:35:39 PM PDT 24 |
| Peak memory | 656080 kb |
| Host | smart-b420604a-323d-4e34-bd67-d01642d60046 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157581783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.3157581783 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.1657316080 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 6133157760 ps |
| CPU time | 664.22 seconds |
| Started | Jul 25 08:29:15 PM PDT 24 |
| Finished | Jul 25 08:40:20 PM PDT 24 |
| Peak memory | 620272 kb |
| Host | smart-047b911f-112a-472f-bcc4-3741b8b62045 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1657316080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1657316080 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2718956164 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 22288056824 ps |
| CPU time | 1457.14 seconds |
| Started | Jul 25 08:23:49 PM PDT 24 |
| Finished | Jul 25 08:48:06 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-b4ab64c8-a4b6-4330-891d-a322c3c102cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2718956164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2718956164 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.4165115158 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3202619900 ps |
| CPU time | 264.95 seconds |
| Started | Jul 25 08:00:45 PM PDT 24 |
| Finished | Jul 25 08:05:10 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-a622c58a-49bd-4db7-902e-0eca0cd8bf18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165115158 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.4165115158 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3073077650 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 3686243520 ps |
| CPU time | 207.9 seconds |
| Started | Jul 25 07:25:44 PM PDT 24 |
| Finished | Jul 25 07:29:12 PM PDT 24 |
| Peak memory | 663608 kb |
| Host | smart-6eac06e9-da48-4705-ba87-a0c389a61abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073077650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3073077650 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.417293489 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 51588264648 ps |
| CPU time | 5993.21 seconds |
| Started | Jul 25 08:01:41 PM PDT 24 |
| Finished | Jul 25 09:41:36 PM PDT 24 |
| Peak memory | 622144 kb |
| Host | smart-658f7349-ea0b-4b75-94b5-ef2d41ed8194 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417293489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_prod.417293489 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200991385 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4320658136 ps |
| CPU time | 435.21 seconds |
| Started | Jul 25 08:36:45 PM PDT 24 |
| Finished | Jul 25 08:44:01 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-b3c03cdb-8e6b-48f5-a309-41b7a738b23a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200991385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1200991385 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1887016022 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3136629766 ps |
| CPU time | 282.93 seconds |
| Started | Jul 25 08:18:11 PM PDT 24 |
| Finished | Jul 25 08:22:54 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-9401e1c3-7f20-4f16-94f6-630972e1e6a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887 016022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1887016022 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3284231414 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 21691849423 ps |
| CPU time | 1052.73 seconds |
| Started | Jul 25 07:40:55 PM PDT 24 |
| Finished | Jul 25 07:58:28 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-c0ce71c8-5f81-4d3e-8f72-fe6f9b92bf94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284231414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.3284231414 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.774690176 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5574362520 ps |
| CPU time | 539.71 seconds |
| Started | Jul 25 08:34:17 PM PDT 24 |
| Finished | Jul 25 08:43:17 PM PDT 24 |
| Peak memory | 650732 kb |
| Host | smart-f3342c23-edb9-44fb-8d97-de23819a9d46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 774690176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.774690176 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1966703176 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5608762363 ps |
| CPU time | 794.67 seconds |
| Started | Jul 25 08:08:02 PM PDT 24 |
| Finished | Jul 25 08:21:17 PM PDT 24 |
| Peak memory | 611684 kb |
| Host | smart-6218a8b6-15e8-4211-9e63-29881cdec41a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966703176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1966703176 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.4023549801 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 4768700741 ps |
| CPU time | 443.91 seconds |
| Started | Jul 25 07:31:06 PM PDT 24 |
| Finished | Jul 25 07:38:30 PM PDT 24 |
| Peak memory | 603392 kb |
| Host | smart-50f929bf-4cf1-4b07-9354-214ddf436e6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023549801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.4023549801 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.124706426 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3227668344 ps |
| CPU time | 191.75 seconds |
| Started | Jul 25 08:27:12 PM PDT 24 |
| Finished | Jul 25 08:30:24 PM PDT 24 |
| Peak memory | 623096 kb |
| Host | smart-99584a83-e753-43e8-b6ff-8b13aab762b5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124706426 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.124706426 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.756274494 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4823531500 ps |
| CPU time | 648.01 seconds |
| Started | Jul 25 08:29:37 PM PDT 24 |
| Finished | Jul 25 08:40:25 PM PDT 24 |
| Peak memory | 650936 kb |
| Host | smart-ce11755e-2c13-4ca5-9584-dba1a2785009 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 756274494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.756274494 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.1483859076 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4875687600 ps |
| CPU time | 563.78 seconds |
| Started | Jul 25 08:39:23 PM PDT 24 |
| Finished | Jul 25 08:48:47 PM PDT 24 |
| Peak memory | 651232 kb |
| Host | smart-27bf673c-b89f-4098-a86d-8f8d54ee0c92 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1483859076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1483859076 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1984468443 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3231289580 ps |
| CPU time | 350.1 seconds |
| Started | Jul 25 08:30:22 PM PDT 24 |
| Finished | Jul 25 08:36:13 PM PDT 24 |
| Peak memory | 649456 kb |
| Host | smart-0c43581f-407b-4b97-b492-acfcc3802ffa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984468443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1984468443 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2203684057 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3805674067 ps |
| CPU time | 528.7 seconds |
| Started | Jul 25 07:49:03 PM PDT 24 |
| Finished | Jul 25 07:57:52 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9761b0e2-c828-4369-bd90-74573fb52f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203684057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2203684057 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3500067940 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5964164768 ps |
| CPU time | 773.66 seconds |
| Started | Jul 25 08:18:06 PM PDT 24 |
| Finished | Jul 25 08:31:00 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-0c120abf-1fc0-4552-9b2a-d32002f87aeb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3500067940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3500067940 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.1563324193 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 6043741036 ps |
| CPU time | 1108.12 seconds |
| Started | Jul 25 08:20:10 PM PDT 24 |
| Finished | Jul 25 08:38:38 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-85d6a71b-c819-483c-a95a-178cb0be3f82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563324193 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1563324193 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.741044351 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 6082257416 ps |
| CPU time | 902.7 seconds |
| Started | Jul 25 08:02:54 PM PDT 24 |
| Finished | Jul 25 08:17:57 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-18b68114-667f-4a07-b96f-890c6e071d5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74104435 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.741044351 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1478762598 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4536651838 ps |
| CPU time | 378.89 seconds |
| Started | Jul 25 08:02:04 PM PDT 24 |
| Finished | Jul 25 08:08:23 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-12980459-bfce-432e-9e28-c29a58c06e4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478762598 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1478762598 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.894496633 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5465897855 ps |
| CPU time | 634.47 seconds |
| Started | Jul 25 08:07:17 PM PDT 24 |
| Finished | Jul 25 08:17:52 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-9988f836-0eef-4217-ac60-2414fe52c63c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89 4496633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.894496633 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1580839805 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3335517690 ps |
| CPU time | 248.11 seconds |
| Started | Jul 25 07:59:58 PM PDT 24 |
| Finished | Jul 25 08:04:07 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-076d1982-887f-435d-8864-c5fbd5991db4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580839805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1580839805 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.708356785 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 12215414436 ps |
| CPU time | 706.95 seconds |
| Started | Jul 25 07:49:54 PM PDT 24 |
| Finished | Jul 25 08:01:42 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-cec32887-0c9d-449f-a6ea-9f26cb8227cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708356785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_ with_rand_reset.708356785 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1249189519 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 77821773672 ps |
| CPU time | 13482 seconds |
| Started | Jul 25 07:59:49 PM PDT 24 |
| Finished | Jul 25 11:44:33 PM PDT 24 |
| Peak memory | 635788 kb |
| Host | smart-bc30851c-7540-4ad6-afea-0d0179adece9 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1249189519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1249189519 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3815479669 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4785195000 ps |
| CPU time | 488.47 seconds |
| Started | Jul 25 08:17:22 PM PDT 24 |
| Finished | Jul 25 08:25:31 PM PDT 24 |
| Peak memory | 611340 kb |
| Host | smart-576e3b82-db47-454e-9430-438a3d279f78 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815479669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3815479669 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.378138802 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3309564880 ps |
| CPU time | 254.96 seconds |
| Started | Jul 25 08:04:01 PM PDT 24 |
| Finished | Jul 25 08:08:16 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-c7284135-ff48-4792-adfc-d03c2a0bb562 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378138802 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.378138802 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2822578151 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 3314396252 ps |
| CPU time | 192.67 seconds |
| Started | Jul 25 08:00:49 PM PDT 24 |
| Finished | Jul 25 08:04:03 PM PDT 24 |
| Peak memory | 620368 kb |
| Host | smart-3b5d2e87-471a-47c0-be7d-f0e240347291 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28225781 51 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2822578151 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3285843 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4192421470 ps |
| CPU time | 664.14 seconds |
| Started | Jul 25 08:30:01 PM PDT 24 |
| Finished | Jul 25 08:41:06 PM PDT 24 |
| Peak memory | 619532 kb |
| Host | smart-28722c01-5d07-4cf0-aac3-ebba8f0cfe99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3285843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.3285843 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.782048686 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 3249047784 ps |
| CPU time | 235.55 seconds |
| Started | Jul 25 07:36:10 PM PDT 24 |
| Finished | Jul 25 07:40:06 PM PDT 24 |
| Peak memory | 603368 kb |
| Host | smart-f6211338-8bbb-4664-b975-ede9f150f394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782048686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.782048686 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1483882560 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 37148166409 ps |
| CPU time | 3049.55 seconds |
| Started | Jul 25 08:18:52 PM PDT 24 |
| Finished | Jul 25 09:09:42 PM PDT 24 |
| Peak memory | 612808 kb |
| Host | smart-533ba696-94db-4811-b879-cb1d0b68352e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483882560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1483882560 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1347158614 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 8574531081 ps |
| CPU time | 1883.82 seconds |
| Started | Jul 25 07:59:04 PM PDT 24 |
| Finished | Jul 25 08:30:29 PM PDT 24 |
| Peak memory | 625396 kb |
| Host | smart-2361b9fc-6e1c-4cc2-bbee-7d21f64d0cd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347158614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1347158614 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.459507027 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 44857854152 ps |
| CPU time | 5165.26 seconds |
| Started | Jul 25 07:59:00 PM PDT 24 |
| Finished | Jul 25 09:25:07 PM PDT 24 |
| Peak memory | 621464 kb |
| Host | smart-1aa4cca7-f304-446e-a385-a91c561673f6 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=459507027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.459507027 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.413903411 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 31674255352 ps |
| CPU time | 7572.74 seconds |
| Started | Jul 25 07:59:55 PM PDT 24 |
| Finished | Jul 25 10:06:08 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-aa7435cc-29d6-406f-bc7a-1ffe8d89672f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=413903411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.413903411 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.3101182237 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 16860503157 ps |
| CPU time | 761.28 seconds |
| Started | Jul 25 07:49:15 PM PDT 24 |
| Finished | Jul 25 08:01:56 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-265dbe46-2262-4e21-9fe4-c4ffe97426bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101182237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3101182237 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.682432605 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5928809975 ps |
| CPU time | 411.18 seconds |
| Started | Jul 25 07:29:37 PM PDT 24 |
| Finished | Jul 25 07:36:28 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-3f72173c-7e16-4420-b032-2cd0097a6d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682432605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_reset_error.682432605 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1172443692 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14938334323 ps |
| CPU time | 3795.81 seconds |
| Started | Jul 25 08:12:45 PM PDT 24 |
| Finished | Jul 25 09:16:02 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-396901bd-abfe-4a4c-99ec-f68bf5c0a91c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172443692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.1172443692 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.3370210229 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4086323480 ps |
| CPU time | 782.58 seconds |
| Started | Jul 25 08:00:53 PM PDT 24 |
| Finished | Jul 25 08:13:56 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-fdb1bacb-f9f7-4cc1-ad04-abc636b53872 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370210229 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.3370210229 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2669129539 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5764264600 ps |
| CPU time | 1120.53 seconds |
| Started | Jul 25 08:02:46 PM PDT 24 |
| Finished | Jul 25 08:21:27 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-e34f85d6-d0cd-4c5f-86e1-f8bc311fc1c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669129539 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2669129539 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1405353417 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 5256754140 ps |
| CPU time | 464.09 seconds |
| Started | Jul 25 07:31:35 PM PDT 24 |
| Finished | Jul 25 07:39:19 PM PDT 24 |
| Peak memory | 603392 kb |
| Host | smart-dfb6091e-66ee-46ec-b0c6-390b104c5929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405353417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1405353417 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3120249048 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1065179018 ps |
| CPU time | 187.48 seconds |
| Started | Jul 25 07:31:37 PM PDT 24 |
| Finished | Jul 25 07:34:44 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-2aa3e187-e4a6-4ddc-adc1-03f8affa8e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120249048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3120249048 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.770280814 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3282201972 ps |
| CPU time | 496.56 seconds |
| Started | Jul 25 08:17:08 PM PDT 24 |
| Finished | Jul 25 08:25:25 PM PDT 24 |
| Peak memory | 620636 kb |
| Host | smart-0f19677a-30d4-4f7e-a87f-21b524370037 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7 70280814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.770280814 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.784682145 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 44968346034 ps |
| CPU time | 4494.13 seconds |
| Started | Jul 25 08:17:45 PM PDT 24 |
| Finished | Jul 25 09:32:40 PM PDT 24 |
| Peak memory | 621756 kb |
| Host | smart-c07ab9c6-7108-4fc7-816a-1f79e3072280 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=784682145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.784682145 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1113876680 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 7126700280 ps |
| CPU time | 648.02 seconds |
| Started | Jul 25 08:13:07 PM PDT 24 |
| Finished | Jul 25 08:23:55 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-c4b55b1c-0ceb-401f-b21c-d7069795cec4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138766 80 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1113876680 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2872413987 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3170271682 ps |
| CPU time | 270.2 seconds |
| Started | Jul 25 08:00:27 PM PDT 24 |
| Finished | Jul 25 08:04:59 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-34e47418-6128-4c39-9bc7-bf1fc71f9b1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872413987 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2872413987 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.65676252 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 7842851048 ps |
| CPU time | 364.65 seconds |
| Started | Jul 25 07:26:25 PM PDT 24 |
| Finished | Jul 25 07:32:30 PM PDT 24 |
| Peak memory | 661996 kb |
| Host | smart-c879616c-0bc5-4bc9-aa6b-63afd795aab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65676252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_res et.65676252 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1186247268 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2553437090 ps |
| CPU time | 115.96 seconds |
| Started | Jul 25 08:19:53 PM PDT 24 |
| Finished | Jul 25 08:21:49 PM PDT 24 |
| Peak memory | 621380 kb |
| Host | smart-006ed7a2-0b0b-42df-8980-b1fb16aac846 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186247268 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1186247268 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1932151518 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 5460809257 ps |
| CPU time | 208.42 seconds |
| Started | Jul 25 07:49:21 PM PDT 24 |
| Finished | Jul 25 07:52:50 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-31604795-247b-4249-8fcb-bb84a26daf1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932151518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1932151518 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3647272429 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10797132472 ps |
| CPU time | 925.36 seconds |
| Started | Jul 25 08:30:42 PM PDT 24 |
| Finished | Jul 25 08:46:08 PM PDT 24 |
| Peak memory | 621284 kb |
| Host | smart-f0f35403-93fd-4841-9af6-c4e6a7415048 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647272429 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3647272429 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1111853643 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 20937844012 ps |
| CPU time | 883.6 seconds |
| Started | Jul 25 07:38:46 PM PDT 24 |
| Finished | Jul 25 07:53:30 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-b5e81a7b-3fb7-44ca-855b-5a0ec666b043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111853643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1111853643 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3994103619 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 12638142198 ps |
| CPU time | 534.44 seconds |
| Started | Jul 25 07:50:49 PM PDT 24 |
| Finished | Jul 25 07:59:44 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-82931977-a30a-48d4-8488-531a8eb7d077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994103619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3994103619 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.1709843459 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3894891436 ps |
| CPU time | 464.78 seconds |
| Started | Jul 25 08:12:54 PM PDT 24 |
| Finished | Jul 25 08:20:39 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-d669aa22-8283-4e94-99f7-b19575dfdc2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709843459 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.1709843459 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2436098975 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 9526910517 ps |
| CPU time | 490.09 seconds |
| Started | Jul 25 07:35:04 PM PDT 24 |
| Finished | Jul 25 07:43:14 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-564dd2d1-c1fa-4411-aa13-de877a59fbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436098975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2436098975 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.434706563 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 4221716964 ps |
| CPU time | 379.93 seconds |
| Started | Jul 25 07:29:33 PM PDT 24 |
| Finished | Jul 25 07:35:53 PM PDT 24 |
| Peak memory | 603324 kb |
| Host | smart-557ce09e-4aee-4f16-a501-008de27debf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434706563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.434706563 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1502314627 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 4611029209 ps |
| CPU time | 304.33 seconds |
| Started | Jul 25 07:47:17 PM PDT 24 |
| Finished | Jul 25 07:52:21 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-5c6191d5-4e8a-4110-8b0b-086551dfa22c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502314627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.1502314627 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3152239141 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3960661824 ps |
| CPU time | 613.25 seconds |
| Started | Jul 25 08:19:22 PM PDT 24 |
| Finished | Jul 25 08:29:36 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-c0979e4e-f654-4196-817e-93e92bbf02ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3152239141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.3152239141 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1895774033 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 19247572190 ps |
| CPU time | 488.05 seconds |
| Started | Jul 25 08:01:48 PM PDT 24 |
| Finished | Jul 25 08:09:57 PM PDT 24 |
| Peak memory | 620124 kb |
| Host | smart-2dc32bbc-957e-498e-8215-447ed8a9f692 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1895774033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1895774033 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4220707749 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4740680304 ps |
| CPU time | 671.56 seconds |
| Started | Jul 25 08:03:39 PM PDT 24 |
| Finished | Jul 25 08:14:51 PM PDT 24 |
| Peak memory | 612740 kb |
| Host | smart-5b17e2ef-440a-4fda-9694-6c862442501c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220707749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.4220707749 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1931188010 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 8483350640 ps |
| CPU time | 1798.86 seconds |
| Started | Jul 25 08:00:45 PM PDT 24 |
| Finished | Jul 25 08:30:46 PM PDT 24 |
| Peak memory | 619544 kb |
| Host | smart-b0f4d324-d29b-4bcc-ae0e-57add3a02013 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1931188010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1931188010 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.2142111502 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3950784512 ps |
| CPU time | 507.02 seconds |
| Started | Jul 25 08:17:01 PM PDT 24 |
| Finished | Jul 25 08:25:28 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-7e53d172-252e-4756-a87d-6863f6deb4cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142111502 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.2142111502 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2738577470 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 346469186 ps |
| CPU time | 127.56 seconds |
| Started | Jul 25 07:36:08 PM PDT 24 |
| Finished | Jul 25 07:38:15 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-6ba83d50-b3bd-4144-806a-963d92114ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738577470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2738577470 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1580083045 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 9326930107 ps |
| CPU time | 470.26 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:58:53 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-1295ee16-7596-4d47-99ad-a87920b2efc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580083045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.1580083045 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.4240893016 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5337888784 ps |
| CPU time | 764.79 seconds |
| Started | Jul 25 08:22:05 PM PDT 24 |
| Finished | Jul 25 08:34:50 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-44af1907-2fd3-4f21-a97c-ccbba1160dce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240893016 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.4240893016 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.454045070 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2072077539 ps |
| CPU time | 95.01 seconds |
| Started | Jul 25 07:59:38 PM PDT 24 |
| Finished | Jul 25 08:01:15 PM PDT 24 |
| Peak memory | 622608 kb |
| Host | smart-b680b31b-17a0-445d-a7fe-b584a0b15a19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454045070 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.454045070 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.2819236150 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5554430176 ps |
| CPU time | 611.61 seconds |
| Started | Jul 25 08:37:11 PM PDT 24 |
| Finished | Jul 25 08:47:23 PM PDT 24 |
| Peak memory | 650716 kb |
| Host | smart-0415ef0e-69be-4980-a8da-2745691cc523 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2819236150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2819236150 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1611276040 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3876966288 ps |
| CPU time | 492.52 seconds |
| Started | Jul 25 07:59:55 PM PDT 24 |
| Finished | Jul 25 08:08:08 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-197fe8b3-ccb2-48c2-abb2-fe2fa414cbc2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161127 6040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1611276040 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2812416578 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 4872443204 ps |
| CPU time | 504.75 seconds |
| Started | Jul 25 08:09:11 PM PDT 24 |
| Finished | Jul 25 08:17:37 PM PDT 24 |
| Peak memory | 619636 kb |
| Host | smart-2822f990-9bce-4942-b08c-e4a540033407 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281241 6578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2812416578 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.776184038 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4959379826 ps |
| CPU time | 429.59 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:54:35 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-14f9d39d-9f86-4a8c-a23b-79cde920e4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776184038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.776184038 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2499547368 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3500280696 ps |
| CPU time | 400.45 seconds |
| Started | Jul 25 08:05:39 PM PDT 24 |
| Finished | Jul 25 08:12:21 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-225379aa-8a75-4ec6-b0c8-670a935aa0cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499547368 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2499547368 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.844639553 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3269407292 ps |
| CPU time | 225.12 seconds |
| Started | Jul 25 08:02:56 PM PDT 24 |
| Finished | Jul 25 08:06:41 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-702d734f-3634-4391-ac05-2a7283aa0cab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844639553 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.844639553 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.612110371 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2997362990 ps |
| CPU time | 143.16 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:37:07 PM PDT 24 |
| Peak memory | 599252 kb |
| Host | smart-a843bded-6925-49a3-b8d3-0f2619965cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612110371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.612110371 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1129535692 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9892139992 ps |
| CPU time | 1326.38 seconds |
| Started | Jul 25 07:58:58 PM PDT 24 |
| Finished | Jul 25 08:21:05 PM PDT 24 |
| Peak memory | 611564 kb |
| Host | smart-2de37d30-e8ae-4bde-8715-8a03ae7882e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1129535692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1129535692 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2779443974 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 33229393272 ps |
| CPU time | 4752.94 seconds |
| Started | Jul 25 07:32:55 PM PDT 24 |
| Finished | Jul 25 08:52:08 PM PDT 24 |
| Peak memory | 592792 kb |
| Host | smart-9fa51306-f31c-4f24-a68d-e38c66aa53d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779443974 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2779443974 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3253788470 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 422614247 ps |
| CPU time | 19.58 seconds |
| Started | Jul 25 07:36:08 PM PDT 24 |
| Finished | Jul 25 07:36:28 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-6f4071b3-399c-4d5c-985a-794aca868a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253788470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3253788470 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.282190552 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 606224395 ps |
| CPU time | 53.15 seconds |
| Started | Jul 25 07:42:39 PM PDT 24 |
| Finished | Jul 25 07:43:32 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-74ab9697-9eef-4fe8-a997-557d01838cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282190552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.282190552 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1540298000 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4466409068 ps |
| CPU time | 404.29 seconds |
| Started | Jul 25 07:36:10 PM PDT 24 |
| Finished | Jul 25 07:42:54 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f8af42ee-f420-483b-86f1-7600a6f07d79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540298000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.1540298000 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118753591 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3566028318 ps |
| CPU time | 380.93 seconds |
| Started | Jul 25 08:03:35 PM PDT 24 |
| Finished | Jul 25 08:09:56 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-7a7781a1-95d0-4904-8892-a50f10c8c6f2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118753591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2118753591 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.123125300 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 5577856984 ps |
| CPU time | 762.28 seconds |
| Started | Jul 25 07:59:11 PM PDT 24 |
| Finished | Jul 25 08:11:55 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-7a454a68-ccf7-4118-8292-b8cd695c49b6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 123125300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.123125300 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615249026 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3741128074 ps |
| CPU time | 393.38 seconds |
| Started | Jul 25 08:07:57 PM PDT 24 |
| Finished | Jul 25 08:14:30 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-d3c8762d-bfff-4cbd-be6c-4ad09817c0bc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615249026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1615249026 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1341178986 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 5909517890 ps |
| CPU time | 713.29 seconds |
| Started | Jul 25 08:06:36 PM PDT 24 |
| Finished | Jul 25 08:18:30 PM PDT 24 |
| Peak memory | 650604 kb |
| Host | smart-587e771a-5425-431f-8973-b19b6595a6ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1341178986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1341178986 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2244859738 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3365352964 ps |
| CPU time | 376.83 seconds |
| Started | Jul 25 08:31:13 PM PDT 24 |
| Finished | Jul 25 08:37:30 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-f57350da-f14c-4669-9764-e0f8df039ebb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244859738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2244859738 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.2133457990 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 5285564154 ps |
| CPU time | 727.61 seconds |
| Started | Jul 25 08:31:02 PM PDT 24 |
| Finished | Jul 25 08:43:10 PM PDT 24 |
| Peak memory | 650664 kb |
| Host | smart-3408a83f-5f38-4f95-a8cd-e62c8eea34a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2133457990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2133457990 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455791626 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 3835155340 ps |
| CPU time | 422.62 seconds |
| Started | Jul 25 08:29:03 PM PDT 24 |
| Finished | Jul 25 08:36:05 PM PDT 24 |
| Peak memory | 649760 kb |
| Host | smart-e3feac9d-d194-4c51-87c5-a6a0c8a0dd54 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455791626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1455791626 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.350570401 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 6144653944 ps |
| CPU time | 761.46 seconds |
| Started | Jul 25 08:30:34 PM PDT 24 |
| Finished | Jul 25 08:43:16 PM PDT 24 |
| Peak memory | 650908 kb |
| Host | smart-8c42158a-3867-474f-bc16-e58a00b2dbc5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 350570401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.350570401 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134283558 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3763000776 ps |
| CPU time | 405.95 seconds |
| Started | Jul 25 08:29:52 PM PDT 24 |
| Finished | Jul 25 08:36:38 PM PDT 24 |
| Peak memory | 649544 kb |
| Host | smart-b677ed82-489c-4029-b537-b9588cfd5fab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134283558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3134283558 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1010336441 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4998352156 ps |
| CPU time | 767.37 seconds |
| Started | Jul 25 08:30:53 PM PDT 24 |
| Finished | Jul 25 08:43:41 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-d01afe93-6fe6-4980-bb15-6b318346019a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1010336441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1010336441 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303973346 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3750747712 ps |
| CPU time | 339.16 seconds |
| Started | Jul 25 08:30:32 PM PDT 24 |
| Finished | Jul 25 08:36:11 PM PDT 24 |
| Peak memory | 649312 kb |
| Host | smart-33599678-1ca0-4e8a-b23d-e41e5e25ca85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303973346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3303973346 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2575275138 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4217513448 ps |
| CPU time | 406.24 seconds |
| Started | Jul 25 08:31:59 PM PDT 24 |
| Finished | Jul 25 08:38:45 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-620200d8-3d6c-42d1-bccc-173fd49a5a59 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575275138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2575275138 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3591016445 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4758311880 ps |
| CPU time | 694.06 seconds |
| Started | Jul 25 08:31:31 PM PDT 24 |
| Finished | Jul 25 08:43:05 PM PDT 24 |
| Peak memory | 650628 kb |
| Host | smart-549963cf-10a3-4753-95ff-dd543331f026 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3591016445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3591016445 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105619164 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3600305504 ps |
| CPU time | 416.83 seconds |
| Started | Jul 25 08:32:17 PM PDT 24 |
| Finished | Jul 25 08:39:14 PM PDT 24 |
| Peak memory | 649444 kb |
| Host | smart-92c3cf64-096e-45fb-9cb3-b0fbb3f28c3d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105619164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4105619164 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.4115068756 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5490806596 ps |
| CPU time | 608.99 seconds |
| Started | Jul 25 08:29:57 PM PDT 24 |
| Finished | Jul 25 08:40:06 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-c2c6d2ef-4bc1-40d5-aaed-0ba5de312296 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4115068756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.4115068756 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1184074380 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5804848608 ps |
| CPU time | 702.42 seconds |
| Started | Jul 25 08:16:32 PM PDT 24 |
| Finished | Jul 25 08:28:15 PM PDT 24 |
| Peak memory | 650648 kb |
| Host | smart-736485ba-bff9-4e56-9d79-0c4aecc891f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1184074380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1184074380 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.512494466 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4534901100 ps |
| CPU time | 419.69 seconds |
| Started | Jul 25 08:31:16 PM PDT 24 |
| Finished | Jul 25 08:38:15 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-7258fa4f-a4bb-4c14-afed-f5a5fe0b1988 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512494466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_s w_alert_handler_lpg_sleep_mode_alerts.512494466 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.3224366065 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5009951106 ps |
| CPU time | 584.35 seconds |
| Started | Jul 25 08:30:50 PM PDT 24 |
| Finished | Jul 25 08:40:34 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-3365af79-7af9-4a55-a355-82386f4b85b4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3224366065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3224366065 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.3705111992 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 5458549172 ps |
| CPU time | 740.09 seconds |
| Started | Jul 25 08:30:21 PM PDT 24 |
| Finished | Jul 25 08:42:41 PM PDT 24 |
| Peak memory | 650584 kb |
| Host | smart-50917be6-45a7-4d67-bcb7-6baa12595b7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3705111992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3705111992 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.185519794 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3995523700 ps |
| CPU time | 465.85 seconds |
| Started | Jul 25 08:31:32 PM PDT 24 |
| Finished | Jul 25 08:39:18 PM PDT 24 |
| Peak memory | 649292 kb |
| Host | smart-5be71cb5-3f48-4d6b-a2d2-832e9c4c649b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185519794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.185519794 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1823953167 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5118649464 ps |
| CPU time | 611.25 seconds |
| Started | Jul 25 08:31:03 PM PDT 24 |
| Finished | Jul 25 08:41:15 PM PDT 24 |
| Peak memory | 650688 kb |
| Host | smart-708a372d-7d56-44d9-ae27-c5cf70fd03f8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1823953167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1823953167 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151701828 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3932883960 ps |
| CPU time | 385.69 seconds |
| Started | Jul 25 08:32:51 PM PDT 24 |
| Finished | Jul 25 08:39:17 PM PDT 24 |
| Peak memory | 649376 kb |
| Host | smart-34ed11b5-f862-4d0e-9250-d83551aef383 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151701828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1151701828 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.81219010 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3396466640 ps |
| CPU time | 419.89 seconds |
| Started | Jul 25 08:33:56 PM PDT 24 |
| Finished | Jul 25 08:40:57 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-8eb37dc1-7d8b-4bf4-b0f0-e35b27a59c8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81219010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw _alert_handler_lpg_sleep_mode_alerts.81219010 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1261432839 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 6369160324 ps |
| CPU time | 699.97 seconds |
| Started | Jul 25 08:31:53 PM PDT 24 |
| Finished | Jul 25 08:43:33 PM PDT 24 |
| Peak memory | 650624 kb |
| Host | smart-6ace4466-43e7-459b-9b3c-57c6961c362d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1261432839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1261432839 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.578421974 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3841588824 ps |
| CPU time | 422.17 seconds |
| Started | Jul 25 08:33:57 PM PDT 24 |
| Finished | Jul 25 08:40:59 PM PDT 24 |
| Peak memory | 649288 kb |
| Host | smart-049524a3-8c15-4749-96c3-7cd6648d16c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578421974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.578421974 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963341193 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3981526180 ps |
| CPU time | 501.81 seconds |
| Started | Jul 25 08:31:51 PM PDT 24 |
| Finished | Jul 25 08:40:13 PM PDT 24 |
| Peak memory | 649784 kb |
| Host | smart-e69ffbd7-2d0c-4227-9b5b-fd6862658bfc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963341193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3963341193 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.2825464720 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 5990398252 ps |
| CPU time | 538.03 seconds |
| Started | Jul 25 08:32:01 PM PDT 24 |
| Finished | Jul 25 08:40:59 PM PDT 24 |
| Peak memory | 650564 kb |
| Host | smart-dcae0379-c929-4770-b5bd-309f2c3faf32 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2825464720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2825464720 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.4139311586 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4542767780 ps |
| CPU time | 715.23 seconds |
| Started | Jul 25 08:31:24 PM PDT 24 |
| Finished | Jul 25 08:43:20 PM PDT 24 |
| Peak memory | 650552 kb |
| Host | smart-101a2f28-9636-4736-b0ec-3485d9d168c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4139311586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.4139311586 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.985995564 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3852017356 ps |
| CPU time | 465.22 seconds |
| Started | Jul 25 08:32:37 PM PDT 24 |
| Finished | Jul 25 08:40:23 PM PDT 24 |
| Peak memory | 649824 kb |
| Host | smart-5f5c845b-cbdd-4e3e-81e2-1f35737bc5b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985995564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.985995564 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.1358496089 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 6134466792 ps |
| CPU time | 633.39 seconds |
| Started | Jul 25 08:31:26 PM PDT 24 |
| Finished | Jul 25 08:42:00 PM PDT 24 |
| Peak memory | 650616 kb |
| Host | smart-b1eb32fc-c1d7-4d62-bbb3-0012aa2c4899 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1358496089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1358496089 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.571632529 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3830668942 ps |
| CPU time | 442.25 seconds |
| Started | Jul 25 08:31:50 PM PDT 24 |
| Finished | Jul 25 08:39:13 PM PDT 24 |
| Peak memory | 649792 kb |
| Host | smart-b92e8a03-e40d-4bbf-9d15-7e6525f3bcd7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571632529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.571632529 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1113902292 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5277594350 ps |
| CPU time | 643.84 seconds |
| Started | Jul 25 08:31:23 PM PDT 24 |
| Finished | Jul 25 08:42:08 PM PDT 24 |
| Peak memory | 650688 kb |
| Host | smart-41840ab7-9b30-42a0-ab63-8c28a0ddfa21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1113902292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1113902292 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3105652593 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 6079633850 ps |
| CPU time | 642.34 seconds |
| Started | Jul 25 08:34:16 PM PDT 24 |
| Finished | Jul 25 08:44:59 PM PDT 24 |
| Peak memory | 650748 kb |
| Host | smart-e458ac48-2a9c-4aed-a885-90ab75be11e5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3105652593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3105652593 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1267697730 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3743839206 ps |
| CPU time | 462.48 seconds |
| Started | Jul 25 08:33:19 PM PDT 24 |
| Finished | Jul 25 08:41:02 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-5bc25f63-ce8c-44d4-ab64-578ed3fb3b72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267697730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1267697730 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.199425081 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4573034100 ps |
| CPU time | 718.14 seconds |
| Started | Jul 25 08:32:22 PM PDT 24 |
| Finished | Jul 25 08:44:21 PM PDT 24 |
| Peak memory | 650352 kb |
| Host | smart-6da7186f-f796-488d-baa5-a409bb8d7fb0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 199425081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.199425081 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.1367677538 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5000978260 ps |
| CPU time | 618.53 seconds |
| Started | Jul 25 08:26:37 PM PDT 24 |
| Finished | Jul 25 08:36:56 PM PDT 24 |
| Peak memory | 650668 kb |
| Host | smart-98ce5f18-1a56-4280-ba38-2128feb41933 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1367677538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1367677538 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.1365245972 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5107682814 ps |
| CPU time | 577.25 seconds |
| Started | Jul 25 08:33:10 PM PDT 24 |
| Finished | Jul 25 08:42:48 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-fda09c45-1e67-413f-85b2-e66d51a489eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1365245972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1365245972 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.2109403520 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5656928208 ps |
| CPU time | 632.59 seconds |
| Started | Jul 25 08:36:20 PM PDT 24 |
| Finished | Jul 25 08:46:53 PM PDT 24 |
| Peak memory | 650316 kb |
| Host | smart-debc01d3-8fd1-493e-be98-2f716dc34255 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2109403520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.2109403520 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.714288223 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3838445640 ps |
| CPU time | 465.18 seconds |
| Started | Jul 25 08:32:50 PM PDT 24 |
| Finished | Jul 25 08:40:36 PM PDT 24 |
| Peak memory | 649428 kb |
| Host | smart-8751fe0f-9f02-4cc8-870f-e1e0b65d2933 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714288223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.714288223 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.960344260 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3593533898 ps |
| CPU time | 489.25 seconds |
| Started | Jul 25 08:37:05 PM PDT 24 |
| Finished | Jul 25 08:45:15 PM PDT 24 |
| Peak memory | 649484 kb |
| Host | smart-c31fc2e7-d8b0-4dd9-8058-24057507215d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960344260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s w_alert_handler_lpg_sleep_mode_alerts.960344260 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.302313938 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4067174102 ps |
| CPU time | 390.04 seconds |
| Started | Jul 25 08:28:16 PM PDT 24 |
| Finished | Jul 25 08:34:46 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-14778659-a8a6-4672-93d0-5f49a1af9054 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302313938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.302313938 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.704960350 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4837961264 ps |
| CPU time | 574.38 seconds |
| Started | Jul 25 08:33:39 PM PDT 24 |
| Finished | Jul 25 08:43:14 PM PDT 24 |
| Peak memory | 650928 kb |
| Host | smart-bfab6cdc-e695-4edc-bd7c-45cdf7ff9741 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 704960350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.704960350 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1169116061 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 5591654620 ps |
| CPU time | 510.94 seconds |
| Started | Jul 25 08:33:11 PM PDT 24 |
| Finished | Jul 25 08:41:42 PM PDT 24 |
| Peak memory | 650720 kb |
| Host | smart-1c1b8de7-b2f5-4183-9809-a871a79f6131 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1169116061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1169116061 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936784776 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4069480784 ps |
| CPU time | 341.4 seconds |
| Started | Jul 25 08:34:40 PM PDT 24 |
| Finished | Jul 25 08:40:21 PM PDT 24 |
| Peak memory | 649560 kb |
| Host | smart-dbf2e889-5380-4a41-9f41-402bddabee88 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936784776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1936784776 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007996158 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4336395264 ps |
| CPU time | 338.34 seconds |
| Started | Jul 25 08:33:48 PM PDT 24 |
| Finished | Jul 25 08:39:26 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-3b9e0c14-f45a-4bb8-89c2-f7b6c87da9b9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007996158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2007996158 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.237788539 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4072402484 ps |
| CPU time | 412.2 seconds |
| Started | Jul 25 08:33:22 PM PDT 24 |
| Finished | Jul 25 08:40:14 PM PDT 24 |
| Peak memory | 650376 kb |
| Host | smart-8204a56a-197f-485f-a914-e604481ac826 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 237788539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.237788539 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3253035439 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3097092600 ps |
| CPU time | 299.65 seconds |
| Started | Jul 25 08:34:09 PM PDT 24 |
| Finished | Jul 25 08:39:09 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-bb2505b9-7c39-4328-ae7a-16ce9c1c03cf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253035439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3253035439 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3022702284 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3832665020 ps |
| CPU time | 386.9 seconds |
| Started | Jul 25 08:35:11 PM PDT 24 |
| Finished | Jul 25 08:41:39 PM PDT 24 |
| Peak memory | 649548 kb |
| Host | smart-004291b7-285c-48ea-ba89-e8ed1e14c8b2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022702284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3022702284 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1652174255 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3635826308 ps |
| CPU time | 452.94 seconds |
| Started | Jul 25 08:34:25 PM PDT 24 |
| Finished | Jul 25 08:41:58 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-9ab2f6be-b9cd-4c8f-8d91-42335743727c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652174255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1652174255 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.900750089 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 3724011080 ps |
| CPU time | 367.65 seconds |
| Started | Jul 25 08:35:16 PM PDT 24 |
| Finished | Jul 25 08:41:24 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-5062f037-ce09-4517-8f6b-ac8aa98a755f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900750089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.900750089 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.1144727601 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5630095840 ps |
| CPU time | 647.74 seconds |
| Started | Jul 25 08:35:08 PM PDT 24 |
| Finished | Jul 25 08:45:56 PM PDT 24 |
| Peak memory | 650380 kb |
| Host | smart-1f2a6c4f-088e-460c-9da2-10023ee42e38 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1144727601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1144727601 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1027939989 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4125251920 ps |
| CPU time | 397.85 seconds |
| Started | Jul 25 08:36:42 PM PDT 24 |
| Finished | Jul 25 08:43:20 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-de326cf5-3ee2-4b76-b1e9-0607e3eb4775 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027939989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1027939989 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2782209424 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 4561223084 ps |
| CPU time | 377.56 seconds |
| Started | Jul 25 08:34:26 PM PDT 24 |
| Finished | Jul 25 08:40:44 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-8b040328-1c8b-41b9-a6a3-89a9a23b5810 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782209424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2782209424 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.435169833 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3386605038 ps |
| CPU time | 329.09 seconds |
| Started | Jul 25 08:35:01 PM PDT 24 |
| Finished | Jul 25 08:40:30 PM PDT 24 |
| Peak memory | 649344 kb |
| Host | smart-dbe29762-bb05-425b-8866-5b536176e134 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435169833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.435169833 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739453657 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3805142000 ps |
| CPU time | 326.12 seconds |
| Started | Jul 25 08:34:58 PM PDT 24 |
| Finished | Jul 25 08:40:24 PM PDT 24 |
| Peak memory | 649508 kb |
| Host | smart-cb1f9c7f-43c5-41b5-bf5b-8c2b300dbb19 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739453657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1739453657 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.499579144 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3118732360 ps |
| CPU time | 402.03 seconds |
| Started | Jul 25 08:28:38 PM PDT 24 |
| Finished | Jul 25 08:35:21 PM PDT 24 |
| Peak memory | 649152 kb |
| Host | smart-b9f48611-0fa1-4bb6-a1a9-a295b86282e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499579144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw _alert_handler_lpg_sleep_mode_alerts.499579144 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2242849169 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5303953240 ps |
| CPU time | 409.31 seconds |
| Started | Jul 25 08:28:31 PM PDT 24 |
| Finished | Jul 25 08:35:20 PM PDT 24 |
| Peak memory | 650452 kb |
| Host | smart-876757bd-4351-43f9-b16c-e9aa324ab27f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2242849169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2242849169 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1266021928 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5685455820 ps |
| CPU time | 555.8 seconds |
| Started | Jul 25 08:37:34 PM PDT 24 |
| Finished | Jul 25 08:46:50 PM PDT 24 |
| Peak memory | 650912 kb |
| Host | smart-2686e543-11c6-4ede-ae8a-2daddc65b5a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1266021928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1266021928 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.870161801 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5342656240 ps |
| CPU time | 704.97 seconds |
| Started | Jul 25 08:37:59 PM PDT 24 |
| Finished | Jul 25 08:49:45 PM PDT 24 |
| Peak memory | 650928 kb |
| Host | smart-6dd0dd80-3175-4abc-8042-8d160efcf1f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 870161801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.870161801 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3935415481 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4331414296 ps |
| CPU time | 395.88 seconds |
| Started | Jul 25 08:38:26 PM PDT 24 |
| Finished | Jul 25 08:45:02 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-56fbc6b0-8f06-4dbe-b194-a90dc1fce299 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935415481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3935415481 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989440566 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4356953820 ps |
| CPU time | 321.82 seconds |
| Started | Jul 25 08:37:15 PM PDT 24 |
| Finished | Jul 25 08:42:37 PM PDT 24 |
| Peak memory | 649716 kb |
| Host | smart-8ffa1bd9-5ef9-48c6-9a55-0276ecf3f27e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989440566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3989440566 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.3013533306 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 6529623956 ps |
| CPU time | 617.31 seconds |
| Started | Jul 25 08:37:27 PM PDT 24 |
| Finished | Jul 25 08:47:45 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-507da48b-e24c-4541-ac20-edfb6f1e71e1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3013533306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3013533306 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2727958123 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 4586641160 ps |
| CPU time | 617.21 seconds |
| Started | Jul 25 08:37:45 PM PDT 24 |
| Finished | Jul 25 08:48:02 PM PDT 24 |
| Peak memory | 650708 kb |
| Host | smart-1865e704-7e6a-41f6-938b-5a2504aaec6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2727958123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2727958123 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.2031459171 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5341285820 ps |
| CPU time | 601.6 seconds |
| Started | Jul 25 08:39:19 PM PDT 24 |
| Finished | Jul 25 08:49:21 PM PDT 24 |
| Peak memory | 650880 kb |
| Host | smart-d4201582-21c3-48db-8e7a-ee8b821c23a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2031459171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2031459171 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.768822178 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3608908310 ps |
| CPU time | 521.19 seconds |
| Started | Jul 25 08:01:27 PM PDT 24 |
| Finished | Jul 25 08:10:10 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-0f7a8995-0500-4de8-a3ea-07656d99c4ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768822178 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_10.768822178 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2470417850 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4536579686 ps |
| CPU time | 646.06 seconds |
| Started | Jul 25 08:02:52 PM PDT 24 |
| Finished | Jul 25 08:13:38 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-95222d27-afcf-4ddc-8b79-c7907cff9849 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470417850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2470417850 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3496325969 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3894590384 ps |
| CPU time | 529.76 seconds |
| Started | Jul 25 08:02:25 PM PDT 24 |
| Finished | Jul 25 08:11:15 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-b2c2eda7-59e5-4cbb-b2c9-043f43176c36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496325969 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3496325969 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1269879463 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5156703032 ps |
| CPU time | 530.71 seconds |
| Started | Jul 25 08:05:21 PM PDT 24 |
| Finished | Jul 25 08:14:12 PM PDT 24 |
| Peak memory | 611808 kb |
| Host | smart-5e839617-b267-4c4a-8379-4df410a9efc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1269879463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1269879463 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3298944484 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 7466058962 ps |
| CPU time | 489.47 seconds |
| Started | Jul 25 08:00:51 PM PDT 24 |
| Finished | Jul 25 08:09:01 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-8f821bc9-ab9b-4b0a-848f-90d64714d372 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298944484 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3298944484 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1306500999 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5072462720 ps |
| CPU time | 693.7 seconds |
| Started | Jul 25 08:04:15 PM PDT 24 |
| Finished | Jul 25 08:15:49 PM PDT 24 |
| Peak memory | 624944 kb |
| Host | smart-282fda46-6de4-49bf-898b-c24d5b96f814 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306500999 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1306500999 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.3671922154 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 820574872 ps |
| CPU time | 57.49 seconds |
| Started | Jul 25 07:25:54 PM PDT 24 |
| Finished | Jul 25 07:26:51 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-bba2a376-47b3-4c2d-a571-0b26a1645b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671922154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 3671922154 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.1202283779 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 3397593970 ps |
| CPU time | 231.09 seconds |
| Started | Jul 25 07:25:57 PM PDT 24 |
| Finished | Jul 25 07:29:48 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-02736e83-a579-41bb-ab16-4267344efc9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202283779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1202283779 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1491293485 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 7505537659 ps |
| CPU time | 80.45 seconds |
| Started | Jul 25 07:33:03 PM PDT 24 |
| Finished | Jul 25 07:34:24 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-bc0bb63c-ae01-4053-ab1c-a6be3f6aafd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491293485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1491293485 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.3992906625 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3658014228 ps |
| CPU time | 288.98 seconds |
| Started | Jul 25 07:29:11 PM PDT 24 |
| Finished | Jul 25 07:34:01 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-5bf4111f-04f8-4df0-8e0c-86d0297a8f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992906625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3992906625 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1085388467 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4096476247 ps |
| CPU time | 465.69 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:55:49 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-54f2f129-9928-4c30-ab1a-6119571b791e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085388467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1085388467 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2120650996 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6600421714 ps |
| CPU time | 1395.82 seconds |
| Started | Jul 25 08:02:27 PM PDT 24 |
| Finished | Jul 25 08:25:43 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-7f0e9459-6081-4341-8825-cdb0359ef9b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2120650996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2120650996 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1763848773 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2805304840 ps |
| CPU time | 274.82 seconds |
| Started | Jul 25 07:59:11 PM PDT 24 |
| Finished | Jul 25 08:03:47 PM PDT 24 |
| Peak memory | 612136 kb |
| Host | smart-38b03796-7d7a-49f3-823e-5d580bcf66a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763848773 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1763848773 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.833321577 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 19398889190 ps |
| CPU time | 3097.2 seconds |
| Started | Jul 25 08:11:42 PM PDT 24 |
| Finished | Jul 25 09:03:21 PM PDT 24 |
| Peak memory | 611484 kb |
| Host | smart-7561472f-8a96-48eb-981e-46364169df0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833321577 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.833321577 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2450441479 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6986045038 ps |
| CPU time | 655.59 seconds |
| Started | Jul 25 08:04:01 PM PDT 24 |
| Finished | Jul 25 08:14:58 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-544b6e0c-b12a-4731-a7a2-ef45c95f1a23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450441479 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2450441479 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1886661580 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4904164246 ps |
| CPU time | 224.89 seconds |
| Started | Jul 25 07:26:07 PM PDT 24 |
| Finished | Jul 25 07:29:52 PM PDT 24 |
| Peak memory | 660204 kb |
| Host | smart-88fcec1e-1a15-4b5c-81ae-496eb5db591b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886661580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.1886661580 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2074547166 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 23625572114 ps |
| CPU time | 2481.42 seconds |
| Started | Jul 25 08:00:54 PM PDT 24 |
| Finished | Jul 25 08:42:17 PM PDT 24 |
| Peak memory | 614060 kb |
| Host | smart-b1ca025e-8d65-4032-a2fb-7030782f22dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074547166 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2074547166 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1487913506 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3252395485 ps |
| CPU time | 180.39 seconds |
| Started | Jul 25 07:59:31 PM PDT 24 |
| Finished | Jul 25 08:02:31 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-bce67281-7005-447b-a533-405c9f6be5b1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487913506 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1487913506 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1045960950 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 10076602219 ps |
| CPU time | 2351.31 seconds |
| Started | Jul 25 08:02:21 PM PDT 24 |
| Finished | Jul 25 08:41:33 PM PDT 24 |
| Peak memory | 617576 kb |
| Host | smart-d12dd754-ac35-444e-a6a5-3734dae181dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1045960950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.1045960950 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3062154859 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6127726680 ps |
| CPU time | 728.53 seconds |
| Started | Jul 25 08:02:43 PM PDT 24 |
| Finished | Jul 25 08:14:53 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-6da04512-5e5c-44a9-8be8-f201c5366899 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3062154859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.3062154859 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3170814555 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2986432969 ps |
| CPU time | 308.54 seconds |
| Started | Jul 25 08:04:08 PM PDT 24 |
| Finished | Jul 25 08:09:17 PM PDT 24 |
| Peak memory | 623544 kb |
| Host | smart-9618a90b-009e-4933-bbb1-24f24da7d011 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170814555 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3170814555 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3936105082 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 431238419 ps |
| CPU time | 40.75 seconds |
| Started | Jul 25 07:26:10 PM PDT 24 |
| Finished | Jul 25 07:26:51 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-8c4d0129-dbe2-44fa-8569-9331ddb72f6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936105082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3936105082 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2763234382 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 463378522 ps |
| CPU time | 139.78 seconds |
| Started | Jul 25 07:36:09 PM PDT 24 |
| Finished | Jul 25 07:38:29 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-86384765-c143-4fed-8e34-df70f2d0ecb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763234382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2763234382 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3557296705 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 16448324537 ps |
| CPU time | 572.14 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:48:00 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-7e289656-a3ea-461f-a263-4bc4481cffa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557296705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3557296705 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.516160931 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 16176076801 ps |
| CPU time | 529.1 seconds |
| Started | Jul 25 07:38:31 PM PDT 24 |
| Finished | Jul 25 07:47:20 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-47c869e5-cbe5-4592-b7a0-70449016d7e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516160931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.516160931 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2123833178 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3914956978 ps |
| CPU time | 159.59 seconds |
| Started | Jul 25 07:42:59 PM PDT 24 |
| Finished | Jul 25 07:45:39 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-00ff9e85-c3cd-474b-a4d3-509aa0c16350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123833178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.2123833178 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3424474921 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 4141511345 ps |
| CPU time | 292.09 seconds |
| Started | Jul 25 07:50:29 PM PDT 24 |
| Finished | Jul 25 07:55:21 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-6c8f284e-4a7a-429a-a12e-a3ec787f8ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424474921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.3424474921 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.246094972 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3800090242 ps |
| CPU time | 488.12 seconds |
| Started | Jul 25 07:58:36 PM PDT 24 |
| Finished | Jul 25 08:06:45 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-8208f735-e39d-4fb1-93fd-771fa975b2dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246094972 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.246094972 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3579292007 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 4801761582 ps |
| CPU time | 816.1 seconds |
| Started | Jul 25 08:01:41 PM PDT 24 |
| Finished | Jul 25 08:15:17 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-00b34764-225d-49ce-9235-5c72dab50928 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792 92007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3579292007 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.4134440473 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4385341620 ps |
| CPU time | 497.87 seconds |
| Started | Jul 25 08:12:06 PM PDT 24 |
| Finished | Jul 25 08:20:24 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-bdf96392-0991-4459-872f-d9af1978fa72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134440473 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.4134440473 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.3951770502 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7022985508 ps |
| CPU time | 691.93 seconds |
| Started | Jul 25 08:02:36 PM PDT 24 |
| Finished | Jul 25 08:14:09 PM PDT 24 |
| Peak memory | 633088 kb |
| Host | smart-cda83b2c-e1e8-41c9-b249-f3ec3678e9b7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951770502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3951770502 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.917775925 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 10117570076 ps |
| CPU time | 524.87 seconds |
| Started | Jul 25 07:25:24 PM PDT 24 |
| Finished | Jul 25 07:34:09 PM PDT 24 |
| Peak memory | 590996 kb |
| Host | smart-1f62ab18-2c5f-4094-87ac-439e0c7d7a09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917775925 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.917775925 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.271182649 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 8324396936 ps |
| CPU time | 1455.46 seconds |
| Started | Jul 25 08:02:30 PM PDT 24 |
| Finished | Jul 25 08:26:46 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-7332a888-a9b3-40d7-8853-995aea371fbd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=271182649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.271182649 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2688565989 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3431798544 ps |
| CPU time | 545.68 seconds |
| Started | Jul 25 08:00:16 PM PDT 24 |
| Finished | Jul 25 08:09:22 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-c0758f2d-e9ea-49de-8922-ee260b2891e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688565989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.2688565989 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3833582456 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 15704545356 ps |
| CPU time | 4711.8 seconds |
| Started | Jul 25 08:02:20 PM PDT 24 |
| Finished | Jul 25 09:20:52 PM PDT 24 |
| Peak memory | 611544 kb |
| Host | smart-8d116860-ee5f-4355-8a56-2acb8ea61fd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38335 82456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3833582456 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3903724965 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 18646703775 ps |
| CPU time | 3934.11 seconds |
| Started | Jul 25 08:02:47 PM PDT 24 |
| Finished | Jul 25 09:08:22 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-81d9afd1-39ed-4415-a9a4-b02d58b29a99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3903724965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3903724965 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3630130495 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 8002116330 ps |
| CPU time | 1397.93 seconds |
| Started | Jul 25 08:11:18 PM PDT 24 |
| Finished | Jul 25 08:34:36 PM PDT 24 |
| Peak memory | 611404 kb |
| Host | smart-aaab384a-bc9f-4d4a-a33c-87397ea258a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363013 0495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.3630130495 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.726345456 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3985872900 ps |
| CPU time | 440.57 seconds |
| Started | Jul 25 08:02:30 PM PDT 24 |
| Finished | Jul 25 08:09:50 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-8330afab-6a29-437f-a292-ccc921ca0847 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72634 5456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.726345456 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1692465809 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 23790340954 ps |
| CPU time | 6905.02 seconds |
| Started | Jul 25 08:12:26 PM PDT 24 |
| Finished | Jul 25 10:07:33 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-46d0faf3-58e0-4e66-a1ce-aa81d5cab87d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1692465809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1692465809 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.691960435 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 36129117271 ps |
| CPU time | 5511.64 seconds |
| Started | Jul 25 07:25:23 PM PDT 24 |
| Finished | Jul 25 08:57:15 PM PDT 24 |
| Peak memory | 593676 kb |
| Host | smart-0e44fbc5-9244-4954-ac64-518eec733454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691960435 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.chip_csr_aliasing.691960435 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2473227155 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 4134269128 ps |
| CPU time | 241.51 seconds |
| Started | Jul 25 07:25:26 PM PDT 24 |
| Finished | Jul 25 07:29:27 PM PDT 24 |
| Peak memory | 591048 kb |
| Host | smart-2d811e75-0ac2-402f-a83e-76ce25e43d86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473227155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.2473227155 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3345483435 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 12098560683 ps |
| CPU time | 690.91 seconds |
| Started | Jul 25 07:25:45 PM PDT 24 |
| Finished | Jul 25 07:37:16 PM PDT 24 |
| Peak memory | 652864 kb |
| Host | smart-d639a58e-37d7-4ead-be33-afd18d13210e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345483435 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.3345483435 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.984865851 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 5804589640 ps |
| CPU time | 569.66 seconds |
| Started | Jul 25 07:25:46 PM PDT 24 |
| Finished | Jul 25 07:35:16 PM PDT 24 |
| Peak memory | 598420 kb |
| Host | smart-9743244d-0dab-4c2a-8fcd-5ad052941047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984865851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.984865851 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3506017348 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 3596469038 ps |
| CPU time | 135.27 seconds |
| Started | Jul 25 07:25:24 PM PDT 24 |
| Finished | Jul 25 07:27:40 PM PDT 24 |
| Peak memory | 591116 kb |
| Host | smart-2e931b40-b1d0-4790-8728-7a8fae4742e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506017348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.3506017348 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.153249860 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 28512823134 ps |
| CPU time | 4702.34 seconds |
| Started | Jul 25 07:25:26 PM PDT 24 |
| Finished | Jul 25 08:43:49 PM PDT 24 |
| Peak memory | 593152 kb |
| Host | smart-89513f3b-fc3a-4447-9619-f7f266cb9655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153249860 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.153249860 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2163905652 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3816638120 ps |
| CPU time | 243.2 seconds |
| Started | Jul 25 07:25:26 PM PDT 24 |
| Finished | Jul 25 07:29:29 PM PDT 24 |
| Peak memory | 603400 kb |
| Host | smart-57e164b2-1048-4297-b7ae-51b49b7f0989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163905652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2163905652 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2994188764 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 2677281784 ps |
| CPU time | 100.88 seconds |
| Started | Jul 25 07:25:34 PM PDT 24 |
| Finished | Jul 25 07:27:15 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-bc4800e2-ee9f-4a91-8a19-821083c7f672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994188764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2994188764 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.982734835 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 24646466201 ps |
| CPU time | 455.38 seconds |
| Started | Jul 25 07:25:36 PM PDT 24 |
| Finished | Jul 25 07:33:11 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-e9cff74e-4718-428e-937c-fdf1b56969d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982734835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de vice_slow_rsp.982734835 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.543775036 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 1056908140 ps |
| CPU time | 42.43 seconds |
| Started | Jul 25 07:25:44 PM PDT 24 |
| Finished | Jul 25 07:26:26 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-5cdb05b0-386b-48b1-b5d4-82570326afd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543775036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr. 543775036 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2078191705 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 516872791 ps |
| CPU time | 46.14 seconds |
| Started | Jul 25 07:25:33 PM PDT 24 |
| Finished | Jul 25 07:26:19 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-143f2c8e-33b7-4f28-a4a3-7472887cc780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078191705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2078191705 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3141542254 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 529924738 ps |
| CPU time | 46.58 seconds |
| Started | Jul 25 07:25:33 PM PDT 24 |
| Finished | Jul 25 07:26:20 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-8627db83-7ec1-4712-887d-3a0ba78be476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141542254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3141542254 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1900425108 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 79833759525 ps |
| CPU time | 923.39 seconds |
| Started | Jul 25 07:25:33 PM PDT 24 |
| Finished | Jul 25 07:40:57 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-6c6c848d-637f-4fac-aadb-a206af1b1807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900425108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1900425108 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3350107444 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 7270200327 ps |
| CPU time | 123.32 seconds |
| Started | Jul 25 07:25:34 PM PDT 24 |
| Finished | Jul 25 07:27:37 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-c7096552-e777-476e-957d-cb5db80ec6ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350107444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3350107444 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.763523545 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 344572795 ps |
| CPU time | 27.49 seconds |
| Started | Jul 25 07:25:33 PM PDT 24 |
| Finished | Jul 25 07:26:01 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f7836b3c-b424-47a0-8099-8c91c2eeb390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763523545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delay s.763523545 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1086943390 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 498866949 ps |
| CPU time | 35.84 seconds |
| Started | Jul 25 07:25:32 PM PDT 24 |
| Finished | Jul 25 07:26:08 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-bd7481a9-d3fe-43ad-8b5c-b41414ca471e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086943390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1086943390 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.521953000 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 51664762 ps |
| CPU time | 6.89 seconds |
| Started | Jul 25 07:25:23 PM PDT 24 |
| Finished | Jul 25 07:25:30 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-6f3effea-21c3-4bf8-9914-b28d9f37f28e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521953000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.521953000 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.117400124 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 7293912248 ps |
| CPU time | 75.21 seconds |
| Started | Jul 25 07:25:33 PM PDT 24 |
| Finished | Jul 25 07:26:48 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-e48d9399-272b-4bf0-a610-1434fbf86d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117400124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.117400124 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1303819008 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 6005384427 ps |
| CPU time | 101.98 seconds |
| Started | Jul 25 07:25:32 PM PDT 24 |
| Finished | Jul 25 07:27:14 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-9520d99d-5fe7-4be9-b148-13129ae13824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303819008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1303819008 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3102169896 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 49719463 ps |
| CPU time | 6.76 seconds |
| Started | Jul 25 07:25:35 PM PDT 24 |
| Finished | Jul 25 07:25:42 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-2694377a-9bd3-4559-ab72-0ac22928e980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102169896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3102169896 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1063389698 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 1055657732 ps |
| CPU time | 92.55 seconds |
| Started | Jul 25 07:25:47 PM PDT 24 |
| Finished | Jul 25 07:27:20 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-0abd343c-018b-4ba2-8cd4-cc56baa82f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063389698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1063389698 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.4033217153 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 10464899952 ps |
| CPU time | 377.28 seconds |
| Started | Jul 25 07:25:51 PM PDT 24 |
| Finished | Jul 25 07:32:08 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-b09c523d-4a0e-4a87-b4f2-e318f18fe499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033217153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.4033217153 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3701287469 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 185964103 ps |
| CPU time | 51.08 seconds |
| Started | Jul 25 07:25:43 PM PDT 24 |
| Finished | Jul 25 07:26:34 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-09b033f9-f6a9-414b-8759-aa76a7206532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701287469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3701287469 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.413491755 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 5333950783 ps |
| CPU time | 226.21 seconds |
| Started | Jul 25 07:25:43 PM PDT 24 |
| Finished | Jul 25 07:29:29 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-dd95c9af-dee7-403f-b14a-83a11d167b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413491755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_reset_error.413491755 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.713640350 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 271133246 ps |
| CPU time | 13.86 seconds |
| Started | Jul 25 07:25:44 PM PDT 24 |
| Finished | Jul 25 07:25:58 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-dc713bac-cf9f-41a7-96d2-1a7a315b4f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713640350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.713640350 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2141907216 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 4147269578 ps |
| CPU time | 183.07 seconds |
| Started | Jul 25 07:25:44 PM PDT 24 |
| Finished | Jul 25 07:28:48 PM PDT 24 |
| Peak memory | 590108 kb |
| Host | smart-2cc62135-ab19-413b-8099-f1cb0d3c768e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141907216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2141907216 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3461723522 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 10415194457 ps |
| CPU time | 957.87 seconds |
| Started | Jul 25 07:26:04 PM PDT 24 |
| Finished | Jul 25 07:42:02 PM PDT 24 |
| Peak memory | 646532 kb |
| Host | smart-736b8020-7754-493a-a6ee-98ab786f748a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461723522 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3461723522 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1015410179 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 4047084983 ps |
| CPU time | 287.82 seconds |
| Started | Jul 25 07:26:04 PM PDT 24 |
| Finished | Jul 25 07:30:52 PM PDT 24 |
| Peak memory | 596896 kb |
| Host | smart-d3a1704b-2821-4e03-8865-4d4b5ed07433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015410179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1015410179 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1789847642 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 8453539915 ps |
| CPU time | 290.7 seconds |
| Started | Jul 25 07:25:46 PM PDT 24 |
| Finished | Jul 25 07:30:37 PM PDT 24 |
| Peak memory | 589664 kb |
| Host | smart-cd3c5600-08fb-4e3f-b69d-5e6cc4a33c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789847642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1789847642 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.121290413 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 9142121061 ps |
| CPU time | 442.22 seconds |
| Started | Jul 25 07:25:54 PM PDT 24 |
| Finished | Jul 25 07:33:16 PM PDT 24 |
| Peak memory | 590968 kb |
| Host | smart-dc348633-7044-4e95-9d08-710a88cf7e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121290413 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.chip_rv_dm_lc_disabled.121290413 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.137337250 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 18273665494 ps |
| CPU time | 2024.34 seconds |
| Started | Jul 25 07:25:43 PM PDT 24 |
| Finished | Jul 25 07:59:28 PM PDT 24 |
| Peak memory | 592948 kb |
| Host | smart-96193521-71e7-4650-9a99-bc45cb5eea6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137337250 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.chip_same_csr_outstanding.137337250 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3833959134 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2398731328 ps |
| CPU time | 135.07 seconds |
| Started | Jul 25 07:31:24 PM PDT 24 |
| Finished | Jul 25 07:33:39 PM PDT 24 |
| Peak memory | 603388 kb |
| Host | smart-d5d54adc-0e87-4f58-9585-5444965da3bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833959134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3833959134 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2532026159 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 47131783886 ps |
| CPU time | 792.36 seconds |
| Started | Jul 25 07:25:58 PM PDT 24 |
| Finished | Jul 25 07:39:10 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-37722f12-6e2a-4a47-b6a8-138071284807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532026159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2532026159 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1075550308 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 200746290 ps |
| CPU time | 24.9 seconds |
| Started | Jul 25 07:25:53 PM PDT 24 |
| Finished | Jul 25 07:26:18 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-223767ad-76fc-4bb4-a842-447082dc4366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075550308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1075550308 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1826485884 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 558182869 ps |
| CPU time | 48.82 seconds |
| Started | Jul 25 07:25:52 PM PDT 24 |
| Finished | Jul 25 07:26:41 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-aea7730b-447a-4610-9e90-bd7fc4d66cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826485884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1826485884 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1469521411 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 484605615 ps |
| CPU time | 16.82 seconds |
| Started | Jul 25 07:25:52 PM PDT 24 |
| Finished | Jul 25 07:26:09 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d5981eb0-f86b-4264-8c5d-2797503f52f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469521411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1469521411 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.708683307 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 73766470575 ps |
| CPU time | 748.32 seconds |
| Started | Jul 25 07:25:53 PM PDT 24 |
| Finished | Jul 25 07:38:21 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-ee466964-e5df-4618-a247-701dfc5e413f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708683307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.708683307 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3325843790 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 24629595040 ps |
| CPU time | 445.54 seconds |
| Started | Jul 25 07:25:57 PM PDT 24 |
| Finished | Jul 25 07:33:22 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-44f505e8-8293-4671-96b4-9746fd064a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325843790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3325843790 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3340173424 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 191567211 ps |
| CPU time | 17.8 seconds |
| Started | Jul 25 07:25:55 PM PDT 24 |
| Finished | Jul 25 07:26:13 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-1fe28dec-a770-4a96-a233-6754a874c37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340173424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3340173424 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.42915049 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 398463046 ps |
| CPU time | 13.93 seconds |
| Started | Jul 25 07:25:57 PM PDT 24 |
| Finished | Jul 25 07:26:11 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-8985f710-4177-4ed9-b96b-84a4fc5cbc08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42915049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.42915049 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.3572920766 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 39868897 ps |
| CPU time | 6.01 seconds |
| Started | Jul 25 07:25:53 PM PDT 24 |
| Finished | Jul 25 07:25:59 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-de8546fe-2a2b-4bdd-99ae-f8b2b3bb34ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572920766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3572920766 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.591860432 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 8918069616 ps |
| CPU time | 91.3 seconds |
| Started | Jul 25 07:25:55 PM PDT 24 |
| Finished | Jul 25 07:27:26 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-0489bf37-be1c-45d0-9683-ac185c0dde2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591860432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.591860432 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.685874059 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 7089567820 ps |
| CPU time | 128.59 seconds |
| Started | Jul 25 07:25:55 PM PDT 24 |
| Finished | Jul 25 07:28:04 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-416feaca-fe43-4a84-a46f-549f455b29c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685874059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.685874059 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2844281721 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 47831450 ps |
| CPU time | 6.26 seconds |
| Started | Jul 25 07:25:54 PM PDT 24 |
| Finished | Jul 25 07:26:00 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-97ae2703-31f2-4c0c-a969-9c20f2af94c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844281721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .2844281721 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1662742473 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 250457956 ps |
| CPU time | 152.09 seconds |
| Started | Jul 25 07:26:05 PM PDT 24 |
| Finished | Jul 25 07:28:37 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-fd804086-cdd3-495a-8888-83b6f889b2ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662742473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.1662742473 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.58303756 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 589817051 ps |
| CPU time | 242.35 seconds |
| Started | Jul 25 07:26:09 PM PDT 24 |
| Finished | Jul 25 07:30:11 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-7b5dae42-5ed6-4d45-8c50-54bd73270a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58303756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_reset_error.58303756 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2715075948 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 1284688313 ps |
| CPU time | 49.07 seconds |
| Started | Jul 25 07:25:53 PM PDT 24 |
| Finished | Jul 25 07:26:42 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-1ef27199-8e1a-4965-95c9-5a3e66408bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715075948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2715075948 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.256304464 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 10965901793 ps |
| CPU time | 805.18 seconds |
| Started | Jul 25 07:30:28 PM PDT 24 |
| Finished | Jul 25 07:43:53 PM PDT 24 |
| Peak memory | 646568 kb |
| Host | smart-43b9a80a-2f3b-4909-8e3b-09a5216c9bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256304464 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.256304464 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2136514168 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 5900016664 ps |
| CPU time | 710.37 seconds |
| Started | Jul 25 07:30:14 PM PDT 24 |
| Finished | Jul 25 07:42:04 PM PDT 24 |
| Peak memory | 598604 kb |
| Host | smart-9b91c262-2b65-4861-90f5-41970662d262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136514168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2136514168 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.583298665 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 16412330449 ps |
| CPU time | 2021.18 seconds |
| Started | Jul 25 07:29:53 PM PDT 24 |
| Finished | Jul 25 08:03:34 PM PDT 24 |
| Peak memory | 592900 kb |
| Host | smart-9b3c73e4-57dc-4634-86ec-6252f31fc58c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583298665 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.chip_same_csr_outstanding.583298665 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.3577348462 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2964412022 ps |
| CPU time | 143.7 seconds |
| Started | Jul 25 07:30:02 PM PDT 24 |
| Finished | Jul 25 07:32:26 PM PDT 24 |
| Peak memory | 598296 kb |
| Host | smart-6068ef9a-8593-4aea-b443-d16a669e03a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577348462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3577348462 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3725473820 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 3115747788 ps |
| CPU time | 119.46 seconds |
| Started | Jul 25 07:30:13 PM PDT 24 |
| Finished | Jul 25 07:32:13 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-ebbf921d-8288-4205-b5eb-71026a088605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725473820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3725473820 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.224633449 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 1267975503 ps |
| CPU time | 53.51 seconds |
| Started | Jul 25 07:30:13 PM PDT 24 |
| Finished | Jul 25 07:31:07 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-59548cce-5ff2-46ed-8638-f1226b8512a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224633449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .224633449 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.1579953921 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 143692213 ps |
| CPU time | 12.85 seconds |
| Started | Jul 25 07:30:16 PM PDT 24 |
| Finished | Jul 25 07:30:29 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-26f61341-735a-49ff-8e16-c4d5f949f2c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579953921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1579953921 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1349399195 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 1414214118 ps |
| CPU time | 47.35 seconds |
| Started | Jul 25 07:30:03 PM PDT 24 |
| Finished | Jul 25 07:30:51 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-72b3a413-ad2b-4d2b-9133-cb6209e485e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349399195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1349399195 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3247635611 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 36963820065 ps |
| CPU time | 380.89 seconds |
| Started | Jul 25 07:30:03 PM PDT 24 |
| Finished | Jul 25 07:36:24 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-4ea799c5-2aaa-4cff-b965-c8e7bbdd9b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247635611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3247635611 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.604949814 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 3039033963 ps |
| CPU time | 46.51 seconds |
| Started | Jul 25 07:30:04 PM PDT 24 |
| Finished | Jul 25 07:30:50 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ddaffd88-1fa0-4cb5-a7b6-5a727620a7be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604949814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.604949814 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4251679345 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 491761093 ps |
| CPU time | 41.01 seconds |
| Started | Jul 25 07:30:07 PM PDT 24 |
| Finished | Jul 25 07:30:48 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-e703252b-c312-46b2-9415-6c7557951e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251679345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.4251679345 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3625566140 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 581854640 ps |
| CPU time | 42.86 seconds |
| Started | Jul 25 07:30:15 PM PDT 24 |
| Finished | Jul 25 07:30:58 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-e73cc8a9-5472-440e-a3da-9114c31b714a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625566140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3625566140 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.1593558794 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 218664908 ps |
| CPU time | 9.62 seconds |
| Started | Jul 25 07:30:05 PM PDT 24 |
| Finished | Jul 25 07:30:14 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-f371ce81-1017-402f-ac79-d1a02d5f41b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593558794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1593558794 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.378197213 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 8935544413 ps |
| CPU time | 88.8 seconds |
| Started | Jul 25 07:30:02 PM PDT 24 |
| Finished | Jul 25 07:31:31 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-33325a58-e0c4-4d3d-8e92-f281008aeaf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378197213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.378197213 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3465329616 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 3829802793 ps |
| CPU time | 68.02 seconds |
| Started | Jul 25 07:30:07 PM PDT 24 |
| Finished | Jul 25 07:31:15 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-f85e9559-9bd2-47ab-9047-76fb07d261b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465329616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3465329616 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1260398450 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 54459920 ps |
| CPU time | 6.67 seconds |
| Started | Jul 25 07:30:02 PM PDT 24 |
| Finished | Jul 25 07:30:09 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5b744361-c5de-45f7-b305-51cf8218b892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260398450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1260398450 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.3262901293 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 6336105573 ps |
| CPU time | 255.28 seconds |
| Started | Jul 25 07:30:15 PM PDT 24 |
| Finished | Jul 25 07:34:31 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-2762be0d-4cd4-45d6-8b0e-7379fea04f91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262901293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3262901293 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1093041461 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 4549981771 ps |
| CPU time | 155.78 seconds |
| Started | Jul 25 07:30:14 PM PDT 24 |
| Finished | Jul 25 07:32:50 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-518723e6-91a0-4f06-ab55-f179068cfe4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093041461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1093041461 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3301121440 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 5409035238 ps |
| CPU time | 254.64 seconds |
| Started | Jul 25 07:30:13 PM PDT 24 |
| Finished | Jul 25 07:34:28 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-9991d1dc-a503-42f1-8e0f-91b141312910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301121440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.3301121440 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3473730808 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 150947625 ps |
| CPU time | 42.55 seconds |
| Started | Jul 25 07:30:13 PM PDT 24 |
| Finished | Jul 25 07:30:56 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-d9abc4de-7435-4db7-ae10-558d76a8ec11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473730808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.3473730808 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3406477758 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 571939089 ps |
| CPU time | 24.96 seconds |
| Started | Jul 25 07:30:14 PM PDT 24 |
| Finished | Jul 25 07:30:39 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-67d62a04-b484-44dc-931a-a2ed0944c57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406477758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3406477758 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2493947252 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 6710320332 ps |
| CPU time | 525.53 seconds |
| Started | Jul 25 07:31:13 PM PDT 24 |
| Finished | Jul 25 07:39:59 PM PDT 24 |
| Peak memory | 637824 kb |
| Host | smart-9c0ea5b8-5d82-4916-be70-430a1a025939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493947252 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2493947252 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.1320455944 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 5989595325 ps |
| CPU time | 530.89 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:39:40 PM PDT 24 |
| Peak memory | 598484 kb |
| Host | smart-5962eda4-d93d-4e64-a841-d8b205ffbbd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320455944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.1320455944 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.893702212 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 29823822890 ps |
| CPU time | 3672.62 seconds |
| Started | Jul 25 07:30:26 PM PDT 24 |
| Finished | Jul 25 08:31:39 PM PDT 24 |
| Peak memory | 592724 kb |
| Host | smart-ed06b507-a2c8-43e9-b626-46fedc7c479d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893702212 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.893702212 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1308455514 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4814580435 ps |
| CPU time | 371.02 seconds |
| Started | Jul 25 07:30:25 PM PDT 24 |
| Finished | Jul 25 07:36:36 PM PDT 24 |
| Peak memory | 603332 kb |
| Host | smart-bb259010-2566-407a-9650-d86112a1ebcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308455514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1308455514 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.4277670611 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 633238226 ps |
| CPU time | 23.63 seconds |
| Started | Jul 25 07:30:36 PM PDT 24 |
| Finished | Jul 25 07:31:00 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-31e807b3-c0d6-4417-b71a-d2474a8919d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277670611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .4277670611 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.305646259 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 10355765481 ps |
| CPU time | 171.29 seconds |
| Started | Jul 25 07:30:36 PM PDT 24 |
| Finished | Jul 25 07:33:28 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-6aafeb04-3971-4ddf-b044-0737fa82023a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305646259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_d evice_slow_rsp.305646259 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4132364575 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 766206069 ps |
| CPU time | 35.7 seconds |
| Started | Jul 25 07:30:48 PM PDT 24 |
| Finished | Jul 25 07:31:24 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-0de0695c-9dfc-4a93-ab7f-d1b9cad6f0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132364575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.4132364575 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1349260272 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 558203682 ps |
| CPU time | 20.75 seconds |
| Started | Jul 25 07:30:50 PM PDT 24 |
| Finished | Jul 25 07:31:11 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-fde35c75-f528-47d2-a74c-5f1b0386a2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349260272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1349260272 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.940267969 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1521619526 ps |
| CPU time | 51.76 seconds |
| Started | Jul 25 07:30:36 PM PDT 24 |
| Finished | Jul 25 07:31:28 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-0d0e2aa8-2c2c-41b2-9741-995e49fe63ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940267969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.940267969 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3837309203 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 3736969421 ps |
| CPU time | 38.86 seconds |
| Started | Jul 25 07:30:35 PM PDT 24 |
| Finished | Jul 25 07:31:14 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-efb02281-d863-4178-b645-7d2f0036ddf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837309203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3837309203 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.981518689 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 64323420314 ps |
| CPU time | 1093.86 seconds |
| Started | Jul 25 07:30:36 PM PDT 24 |
| Finished | Jul 25 07:48:50 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-3b373e26-c56f-486d-be12-ae238fa8b773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981518689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.981518689 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.112676113 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 151823222 ps |
| CPU time | 17.82 seconds |
| Started | Jul 25 07:30:36 PM PDT 24 |
| Finished | Jul 25 07:30:54 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-f2a1e39b-d17f-4ced-8098-6b8d3a4ee599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112676113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_dela ys.112676113 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.1686196842 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 266585370 ps |
| CPU time | 19.65 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:31:09 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-919bb8f0-eadc-4fd5-a95e-554ed350ad9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686196842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1686196842 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.214597674 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 214052071 ps |
| CPU time | 9.3 seconds |
| Started | Jul 25 07:30:27 PM PDT 24 |
| Finished | Jul 25 07:30:37 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-aabaab1d-b71c-4389-9a10-2889431cde1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214597674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.214597674 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2461370263 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 9146243891 ps |
| CPU time | 87.3 seconds |
| Started | Jul 25 07:30:25 PM PDT 24 |
| Finished | Jul 25 07:31:52 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-dd4efa4e-6bb4-4df5-8682-9d50975e61b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461370263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2461370263 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3738155082 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 4037461847 ps |
| CPU time | 61.55 seconds |
| Started | Jul 25 07:30:25 PM PDT 24 |
| Finished | Jul 25 07:31:27 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-63aa0cc5-a07f-4d43-8a01-d4c89e429d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738155082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3738155082 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3370460992 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 47637307 ps |
| CPU time | 6.8 seconds |
| Started | Jul 25 07:30:24 PM PDT 24 |
| Finished | Jul 25 07:30:31 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-00672e6b-3d55-41fa-bc49-ff3b51126e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370460992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3370460992 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.3063842361 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 1635311363 ps |
| CPU time | 151.74 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:33:21 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-6f69eec0-6627-4fed-8510-cd39b5f20440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063842361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3063842361 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2574925189 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 9377741604 ps |
| CPU time | 368.84 seconds |
| Started | Jul 25 07:30:48 PM PDT 24 |
| Finished | Jul 25 07:36:57 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-7ac654f2-6b82-4943-bebe-f35c97098d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574925189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2574925189 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2152695183 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 460511807 ps |
| CPU time | 157.93 seconds |
| Started | Jul 25 07:30:53 PM PDT 24 |
| Finished | Jul 25 07:33:31 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-7b37812c-ef28-461b-93cb-b1751d78112b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152695183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2152695183 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1987329993 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 294469395 ps |
| CPU time | 126.85 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:32:56 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-dc944f08-4130-4777-b100-7ca6473ce73b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987329993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1987329993 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2846122770 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 74072558 ps |
| CPU time | 11.3 seconds |
| Started | Jul 25 07:30:51 PM PDT 24 |
| Finished | Jul 25 07:31:02 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-21494a67-b0f0-4237-af3b-c34eed6d62a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846122770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2846122770 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1890334421 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 8484472055 ps |
| CPU time | 732.16 seconds |
| Started | Jul 25 07:31:02 PM PDT 24 |
| Finished | Jul 25 07:43:14 PM PDT 24 |
| Peak memory | 652612 kb |
| Host | smart-acecb1ab-555c-483a-84ed-1fea3e5b0422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890334421 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.1890334421 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.316470719 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 5779590703 ps |
| CPU time | 575.8 seconds |
| Started | Jul 25 07:31:00 PM PDT 24 |
| Finished | Jul 25 07:40:36 PM PDT 24 |
| Peak memory | 598984 kb |
| Host | smart-3f394f9b-fa3a-45b8-a796-40ff7340435b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316470719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.316470719 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.4142547840 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 16435182820 ps |
| CPU time | 2375.98 seconds |
| Started | Jul 25 07:30:48 PM PDT 24 |
| Finished | Jul 25 08:10:24 PM PDT 24 |
| Peak memory | 592996 kb |
| Host | smart-c87a0c34-4f62-4a3e-8235-00c50d4ec9bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142547840 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.4142547840 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.1280177622 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 4847424296 ps |
| CPU time | 299.86 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:35:49 PM PDT 24 |
| Peak memory | 603344 kb |
| Host | smart-18e1c24b-4ed0-4f36-b876-67f954847e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280177622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1280177622 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2491053611 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 392747668 ps |
| CPU time | 38.05 seconds |
| Started | Jul 25 07:30:52 PM PDT 24 |
| Finished | Jul 25 07:31:30 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-cf99126d-2080-4c9a-82b3-099bcf26dc21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491053611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2491053611 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2137079105 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 101844879635 ps |
| CPU time | 1693.93 seconds |
| Started | Jul 25 07:30:51 PM PDT 24 |
| Finished | Jul 25 07:59:05 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-09c45966-41cd-48e0-953d-593e898cdb3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137079105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.2137079105 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.579985549 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 1256707121 ps |
| CPU time | 46.12 seconds |
| Started | Jul 25 07:31:03 PM PDT 24 |
| Finished | Jul 25 07:31:50 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-e589e111-3164-41fa-a069-88d640107dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579985549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr .579985549 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.649732640 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 345932577 ps |
| CPU time | 33.23 seconds |
| Started | Jul 25 07:31:01 PM PDT 24 |
| Finished | Jul 25 07:31:34 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-89b271e9-7c32-4577-a37c-abee6942ef4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649732640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.649732640 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.2898819310 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 579594147 ps |
| CPU time | 23.05 seconds |
| Started | Jul 25 07:30:58 PM PDT 24 |
| Finished | Jul 25 07:31:21 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-6489a878-e873-4f36-90d4-7d51a23fcc9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898819310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.2898819310 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.929353880 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 93370232243 ps |
| CPU time | 960.06 seconds |
| Started | Jul 25 07:30:47 PM PDT 24 |
| Finished | Jul 25 07:46:47 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-2503d601-92f0-471b-a375-1cfee374c949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929353880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.929353880 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.124586870 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 34947161058 ps |
| CPU time | 563.11 seconds |
| Started | Jul 25 07:30:58 PM PDT 24 |
| Finished | Jul 25 07:40:21 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-f2124c96-5521-4edc-a2ae-79677501c27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124586870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.124586870 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4219690681 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 353955728 ps |
| CPU time | 31.23 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:31:21 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-5e2250cc-3863-4387-b48a-4f6e0be77000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219690681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.4219690681 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.237683805 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 610512872 ps |
| CPU time | 20.27 seconds |
| Started | Jul 25 07:30:57 PM PDT 24 |
| Finished | Jul 25 07:31:17 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-27bb8aab-e313-4c5c-a4f7-1411bb07b8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237683805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.237683805 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3142872642 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 183179304 ps |
| CPU time | 8.26 seconds |
| Started | Jul 25 07:30:51 PM PDT 24 |
| Finished | Jul 25 07:30:59 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-9040d6a3-681c-4429-83f0-2b383cabd8be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142872642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3142872642 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2229067173 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 7654637082 ps |
| CPU time | 83.48 seconds |
| Started | Jul 25 07:30:48 PM PDT 24 |
| Finished | Jul 25 07:32:12 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-55dcfa6f-55e4-48eb-88a8-f04093b15f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229067173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2229067173 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2778312197 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 5622939413 ps |
| CPU time | 95.55 seconds |
| Started | Jul 25 07:30:51 PM PDT 24 |
| Finished | Jul 25 07:32:27 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-262d007f-7323-48f5-af8f-a909452ecec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778312197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2778312197 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3061479345 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 47518012 ps |
| CPU time | 6.53 seconds |
| Started | Jul 25 07:30:49 PM PDT 24 |
| Finished | Jul 25 07:30:55 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-5f326ba5-22c7-4fa4-98af-dbe014011687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061479345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.3061479345 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2010612585 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 1889701583 ps |
| CPU time | 145.83 seconds |
| Started | Jul 25 07:31:01 PM PDT 24 |
| Finished | Jul 25 07:33:27 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-7e6d6bd8-4c5e-4e31-a8e6-88085bdcd98c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010612585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2010612585 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2372683622 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 1822271007 ps |
| CPU time | 67.35 seconds |
| Started | Jul 25 07:31:01 PM PDT 24 |
| Finished | Jul 25 07:32:09 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-c7dcdcf4-7307-43db-bbba-29c22e8c836b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372683622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2372683622 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3003803524 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 156024935 ps |
| CPU time | 45.14 seconds |
| Started | Jul 25 07:31:03 PM PDT 24 |
| Finished | Jul 25 07:31:48 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-d8cac887-5244-4862-a925-e86cbbaef8cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003803524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.3003803524 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.336817860 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 5423901848 ps |
| CPU time | 228.03 seconds |
| Started | Jul 25 07:31:00 PM PDT 24 |
| Finished | Jul 25 07:34:48 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-f43eedeb-65c7-451e-963c-68fe76b7fe62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336817860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_reset_error.336817860 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.592476293 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 195469072 ps |
| CPU time | 25.14 seconds |
| Started | Jul 25 07:31:01 PM PDT 24 |
| Finished | Jul 25 07:31:27 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-566c8d75-b44b-4aab-8c6c-14c6855a4860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592476293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.592476293 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.4144684853 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 10277863818 ps |
| CPU time | 914.81 seconds |
| Started | Jul 25 07:31:35 PM PDT 24 |
| Finished | Jul 25 07:46:50 PM PDT 24 |
| Peak memory | 652556 kb |
| Host | smart-428c2d58-e437-4b3e-9285-552c0372104d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144684853 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.4144684853 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2354462742 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 288654954 ps |
| CPU time | 29.46 seconds |
| Started | Jul 25 07:31:18 PM PDT 24 |
| Finished | Jul 25 07:31:48 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-0fd41411-9cd0-4b25-929d-5e39a543e0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354462742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2354462742 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1424957018 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 89611274248 ps |
| CPU time | 1571.69 seconds |
| Started | Jul 25 07:31:20 PM PDT 24 |
| Finished | Jul 25 07:57:32 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-007e1ce2-a87e-4401-bc56-baafc3506e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424957018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.1424957018 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1319751116 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 802174547 ps |
| CPU time | 27.69 seconds |
| Started | Jul 25 07:31:25 PM PDT 24 |
| Finished | Jul 25 07:31:53 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-16ead860-7752-41f7-81da-a12c1b98bc9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319751116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.1319751116 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.210770359 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 586015951 ps |
| CPU time | 40.42 seconds |
| Started | Jul 25 07:31:25 PM PDT 24 |
| Finished | Jul 25 07:32:06 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-3f5b0641-8fab-4f0e-9b5c-e922f216d337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210770359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.210770359 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.1029470113 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 292158458 ps |
| CPU time | 25.98 seconds |
| Started | Jul 25 07:31:10 PM PDT 24 |
| Finished | Jul 25 07:31:36 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-75e60be4-d23d-423c-8e0c-d3187b6cdf45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029470113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1029470113 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.190051248 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 11956943413 ps |
| CPU time | 115.56 seconds |
| Started | Jul 25 07:31:14 PM PDT 24 |
| Finished | Jul 25 07:33:10 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-aef5f8f2-bf7e-4c9e-8b37-db6a337b1e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190051248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.190051248 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1484931139 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 52210867399 ps |
| CPU time | 882.66 seconds |
| Started | Jul 25 07:31:11 PM PDT 24 |
| Finished | Jul 25 07:45:54 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-6bfb83c0-0b59-425d-866c-97625e0ecb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484931139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1484931139 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4111924401 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 215872857 ps |
| CPU time | 19.99 seconds |
| Started | Jul 25 07:31:10 PM PDT 24 |
| Finished | Jul 25 07:31:30 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-fb24cd6f-bfa4-4d58-af2f-b1e22056ba45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111924401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.4111924401 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.1351366707 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 1950831625 ps |
| CPU time | 50.35 seconds |
| Started | Jul 25 07:31:25 PM PDT 24 |
| Finished | Jul 25 07:32:16 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e748c444-6c76-4ab9-944a-bf4ed835fed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351366707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1351366707 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.3691653758 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 170321250 ps |
| CPU time | 8.01 seconds |
| Started | Jul 25 07:31:00 PM PDT 24 |
| Finished | Jul 25 07:31:08 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-73645b7b-d54f-4bb8-b935-57ad7aa98073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691653758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3691653758 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2811875124 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 8716154786 ps |
| CPU time | 90.07 seconds |
| Started | Jul 25 07:31:14 PM PDT 24 |
| Finished | Jul 25 07:32:44 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-2cf57f82-1a03-4171-901c-e95e5866d5ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811875124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2811875124 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.671500031 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 5470205099 ps |
| CPU time | 89.51 seconds |
| Started | Jul 25 07:31:11 PM PDT 24 |
| Finished | Jul 25 07:32:41 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-6880e13e-03e5-470f-933c-f9feabc8b199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671500031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.671500031 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.153888573 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 50676991 ps |
| CPU time | 6.85 seconds |
| Started | Jul 25 07:31:11 PM PDT 24 |
| Finished | Jul 25 07:31:18 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-c93f66fd-4a05-4ca1-83d9-e5060f2b1767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153888573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays .153888573 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3772116519 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2222725471 ps |
| CPU time | 172.05 seconds |
| Started | Jul 25 07:31:35 PM PDT 24 |
| Finished | Jul 25 07:34:27 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-d86818e6-83f1-4535-833b-6d427c6ea706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772116519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3772116519 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4197096589 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 10988138027 ps |
| CPU time | 419.99 seconds |
| Started | Jul 25 07:31:35 PM PDT 24 |
| Finished | Jul 25 07:38:35 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-e7943016-5976-4839-bfa9-179485348072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197096589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4197096589 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1227164646 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 321842135 ps |
| CPU time | 133.48 seconds |
| Started | Jul 25 07:31:33 PM PDT 24 |
| Finished | Jul 25 07:33:46 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-942e0417-d14d-4564-824c-5bd725c4380d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227164646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1227164646 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2674159484 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1007629505 ps |
| CPU time | 48.91 seconds |
| Started | Jul 25 07:31:19 PM PDT 24 |
| Finished | Jul 25 07:32:08 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-e9112334-d2e3-4e55-977e-3ed315e31104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674159484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2674159484 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3555617064 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 11423618164 ps |
| CPU time | 869.78 seconds |
| Started | Jul 25 07:31:57 PM PDT 24 |
| Finished | Jul 25 07:46:27 PM PDT 24 |
| Peak memory | 652788 kb |
| Host | smart-91c8910a-3ff9-4cb7-9e81-75202f4dd0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555617064 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.3555617064 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2683090808 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 5325530384 ps |
| CPU time | 740.39 seconds |
| Started | Jul 25 07:31:59 PM PDT 24 |
| Finished | Jul 25 07:44:20 PM PDT 24 |
| Peak memory | 598132 kb |
| Host | smart-e3ac5677-add3-439c-8df9-025b48a2bdc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683090808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2683090808 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3488775428 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 15933897763 ps |
| CPU time | 1836.15 seconds |
| Started | Jul 25 07:31:35 PM PDT 24 |
| Finished | Jul 25 08:02:11 PM PDT 24 |
| Peak memory | 593004 kb |
| Host | smart-5dbbb06c-9db3-41f5-a98c-dba036d59bca |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488775428 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3488775428 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.1586162610 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 710979384 ps |
| CPU time | 46.73 seconds |
| Started | Jul 25 07:31:45 PM PDT 24 |
| Finished | Jul 25 07:32:32 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-7e4d50b0-cbbc-41f9-9771-b4ebcdc1eaa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586162610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .1586162610 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3110311673 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 97792449931 ps |
| CPU time | 1812.18 seconds |
| Started | Jul 25 07:31:44 PM PDT 24 |
| Finished | Jul 25 08:01:56 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-b53f4179-d823-4f5c-b101-a72f63cde723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110311673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3110311673 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2901345758 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 348611953 ps |
| CPU time | 18.13 seconds |
| Started | Jul 25 07:31:59 PM PDT 24 |
| Finished | Jul 25 07:32:17 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-dfd5b6b3-b26b-4b14-937e-5bd8a8852d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901345758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.2901345758 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.4013662299 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 519608299 ps |
| CPU time | 46.54 seconds |
| Started | Jul 25 07:31:46 PM PDT 24 |
| Finished | Jul 25 07:32:32 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-86e79033-ad3f-4580-aba3-a0bd8adcf945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013662299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4013662299 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2492779730 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 35336720 ps |
| CPU time | 6.43 seconds |
| Started | Jul 25 07:31:45 PM PDT 24 |
| Finished | Jul 25 07:31:51 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f10a0afe-98ae-4770-b708-f2b6589deec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492779730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2492779730 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2959906942 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 30653219919 ps |
| CPU time | 344.16 seconds |
| Started | Jul 25 07:31:45 PM PDT 24 |
| Finished | Jul 25 07:37:29 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-6cd93039-68f1-4c13-a6b0-71ef97325bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959906942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2959906942 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1239130159 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 21764338556 ps |
| CPU time | 390.5 seconds |
| Started | Jul 25 07:31:47 PM PDT 24 |
| Finished | Jul 25 07:38:17 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-4400436d-020c-46a0-960b-433070d98ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239130159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1239130159 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2226631111 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 143679427 ps |
| CPU time | 16.1 seconds |
| Started | Jul 25 07:31:46 PM PDT 24 |
| Finished | Jul 25 07:32:02 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-782ed3b0-ba93-4f0c-9a37-0b11b5140eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226631111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.2226631111 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.3591059054 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 1249090526 ps |
| CPU time | 38.27 seconds |
| Started | Jul 25 07:31:47 PM PDT 24 |
| Finished | Jul 25 07:32:26 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-80ca7b2c-0e79-41e4-929a-30895019bbc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591059054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3591059054 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.1842532227 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 170372719 ps |
| CPU time | 9.05 seconds |
| Started | Jul 25 07:31:45 PM PDT 24 |
| Finished | Jul 25 07:31:54 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-0b2c9de5-0dd8-4978-9289-7721300e63bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842532227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1842532227 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4279413405 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 8463500754 ps |
| CPU time | 92.46 seconds |
| Started | Jul 25 07:31:45 PM PDT 24 |
| Finished | Jul 25 07:33:18 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-dd84ff4a-dc92-4e41-89e3-32e036b1af89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279413405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4279413405 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.518945870 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 6795761640 ps |
| CPU time | 120.32 seconds |
| Started | Jul 25 07:31:48 PM PDT 24 |
| Finished | Jul 25 07:33:48 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-b1ad22c4-32dc-43ad-813e-77a9668e32f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518945870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.518945870 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3017219184 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 55846474 ps |
| CPU time | 7.32 seconds |
| Started | Jul 25 07:31:46 PM PDT 24 |
| Finished | Jul 25 07:31:54 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-f4d2e84d-a85a-4b12-9b8a-a2b41f1e454d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017219184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3017219184 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.4110959958 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 1692656935 ps |
| CPU time | 145 seconds |
| Started | Jul 25 07:31:58 PM PDT 24 |
| Finished | Jul 25 07:34:23 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-e3c79a1d-6b04-4e32-92f3-f0d671a263c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110959958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4110959958 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.492430523 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 16301550253 ps |
| CPU time | 538.09 seconds |
| Started | Jul 25 07:31:59 PM PDT 24 |
| Finished | Jul 25 07:40:58 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-efe2418d-a313-450c-8ad3-ee4a81ce83be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492430523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.492430523 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1705382125 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 104852052 ps |
| CPU time | 50.39 seconds |
| Started | Jul 25 07:31:58 PM PDT 24 |
| Finished | Jul 25 07:32:49 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-12da7720-32a5-4104-b055-2f414da45c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705382125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.1705382125 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3572950985 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 502502127 ps |
| CPU time | 128.29 seconds |
| Started | Jul 25 07:31:59 PM PDT 24 |
| Finished | Jul 25 07:34:07 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-057c5a4f-4523-4a36-a965-e45b20b23499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572950985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3572950985 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.4168149985 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 225929642 ps |
| CPU time | 26.62 seconds |
| Started | Jul 25 07:31:57 PM PDT 24 |
| Finished | Jul 25 07:32:24 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-63953c10-ff2e-46f3-bb48-5134b12d1d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168149985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4168149985 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.4067901345 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 7077209864 ps |
| CPU time | 366.25 seconds |
| Started | Jul 25 07:32:53 PM PDT 24 |
| Finished | Jul 25 07:39:00 PM PDT 24 |
| Peak memory | 643184 kb |
| Host | smart-ef565bfb-b526-4063-8d90-9bf98a30669c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067901345 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.4067901345 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1041556174 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 5671733430 ps |
| CPU time | 538.02 seconds |
| Started | Jul 25 07:32:45 PM PDT 24 |
| Finished | Jul 25 07:41:43 PM PDT 24 |
| Peak memory | 598300 kb |
| Host | smart-63252731-b84e-4f54-857a-8f808adb49d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041556174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1041556174 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.515635185 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 16438349324 ps |
| CPU time | 1926.58 seconds |
| Started | Jul 25 07:31:58 PM PDT 24 |
| Finished | Jul 25 08:04:05 PM PDT 24 |
| Peak memory | 593048 kb |
| Host | smart-3203c559-ff61-41a5-b4a7-a40107509059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515635185 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.chip_same_csr_outstanding.515635185 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1366114540 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 14228417 ps |
| CPU time | 5.7 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:32:29 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-fbd7fd3d-ef8c-40ea-82a7-386351d2b900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366114540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .1366114540 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3097039259 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 5790663826 ps |
| CPU time | 101.95 seconds |
| Started | Jul 25 07:32:22 PM PDT 24 |
| Finished | Jul 25 07:34:04 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-31d022da-de22-4f49-bd48-a2764c1deab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097039259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3097039259 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3878496313 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 1218210245 ps |
| CPU time | 43.1 seconds |
| Started | Jul 25 07:32:25 PM PDT 24 |
| Finished | Jul 25 07:33:08 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-59f57512-5731-40d1-a5f9-c04346abd235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878496313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3878496313 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.703491200 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 793532264 ps |
| CPU time | 26.95 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:32:50 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-139cc53e-9ca6-4e93-a876-eb5649e753d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703491200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.703491200 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.2478179815 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 407748980 ps |
| CPU time | 17.31 seconds |
| Started | Jul 25 07:32:21 PM PDT 24 |
| Finished | Jul 25 07:32:39 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-023fde5a-62b3-4a60-80d5-76b83966341d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478179815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.2478179815 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.654836311 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 26217698528 ps |
| CPU time | 261.21 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:36:44 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-b90884c6-c179-433f-b7e6-5a406003034e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654836311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.654836311 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.4046574103 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 11888192345 ps |
| CPU time | 203.28 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:35:47 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-db255232-8b7b-45ff-b286-edcb98337699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046574103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4046574103 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3688002607 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 287846264 ps |
| CPU time | 28.01 seconds |
| Started | Jul 25 07:32:22 PM PDT 24 |
| Finished | Jul 25 07:32:50 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5cf1d28f-9cc0-44f5-9067-135494fe0035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688002607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.3688002607 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2427705915 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 2594450804 ps |
| CPU time | 82.06 seconds |
| Started | Jul 25 07:32:24 PM PDT 24 |
| Finished | Jul 25 07:33:46 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-1f033ebf-9874-4e45-8d01-66156b7226d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427705915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2427705915 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.2405432487 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 47341881 ps |
| CPU time | 6.57 seconds |
| Started | Jul 25 07:31:56 PM PDT 24 |
| Finished | Jul 25 07:32:03 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-68640e15-356f-49ef-9f9d-0f4dce9d7e23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405432487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2405432487 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3131311153 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 6765341102 ps |
| CPU time | 69.98 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:33:33 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-2373ba51-9908-4072-bcbf-ff5e9dd76757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131311153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3131311153 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2090414164 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 4665953040 ps |
| CPU time | 74.76 seconds |
| Started | Jul 25 07:32:07 PM PDT 24 |
| Finished | Jul 25 07:33:22 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-d053b22b-abd8-47e6-871e-2d0519b8e533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090414164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2090414164 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3951875736 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 52895908 ps |
| CPU time | 6.88 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:32:30 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-edeb814c-60bf-4026-a0d1-7a796b3694e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951875736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3951875736 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1179944787 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 3546837618 ps |
| CPU time | 327.22 seconds |
| Started | Jul 25 07:32:23 PM PDT 24 |
| Finished | Jul 25 07:37:51 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-3cac6340-8829-4aca-be3d-a351b6ff1e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179944787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1179944787 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.4162539243 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 3532023363 ps |
| CPU time | 109.12 seconds |
| Started | Jul 25 07:32:54 PM PDT 24 |
| Finished | Jul 25 07:34:44 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-d7f66115-240f-4768-9ae5-ead59814dc6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162539243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.4162539243 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.647855577 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 118968356 ps |
| CPU time | 58.78 seconds |
| Started | Jul 25 07:33:17 PM PDT 24 |
| Finished | Jul 25 07:34:16 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-2c13c10e-4eb0-4cb7-9331-28254df9af0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647855577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.647855577 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.4231062269 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 904760110 ps |
| CPU time | 268.9 seconds |
| Started | Jul 25 07:32:45 PM PDT 24 |
| Finished | Jul 25 07:37:14 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-8ff4857c-c48d-47f9-818e-6b93042a407b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231062269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.4231062269 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2504158508 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 327423074 ps |
| CPU time | 16.24 seconds |
| Started | Jul 25 07:32:22 PM PDT 24 |
| Finished | Jul 25 07:32:38 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ce585984-7ce0-4792-bdbb-73e3ca67600e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504158508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2504158508 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.473940114 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 11885527528 ps |
| CPU time | 837.51 seconds |
| Started | Jul 25 07:32:47 PM PDT 24 |
| Finished | Jul 25 07:46:45 PM PDT 24 |
| Peak memory | 646412 kb |
| Host | smart-52cc92c8-7e83-45d6-99a5-b29c71743efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473940114 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.473940114 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.141193499 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 5808832160 ps |
| CPU time | 592.16 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:42:38 PM PDT 24 |
| Peak memory | 599104 kb |
| Host | smart-8f9e3833-1a13-4ecb-b9db-f75fb4dde7c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141193499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.141193499 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2791762580 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2550536772 ps |
| CPU time | 122.56 seconds |
| Started | Jul 25 07:32:48 PM PDT 24 |
| Finished | Jul 25 07:34:50 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-e07b1a4d-2d97-4100-ab13-e07f205d6846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791762580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2791762580 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1930273521 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 81011068544 ps |
| CPU time | 1430.01 seconds |
| Started | Jul 25 07:32:35 PM PDT 24 |
| Finished | Jul 25 07:56:25 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-d41d693a-d8bf-41a8-ae2d-6206c2bf4bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930273521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1930273521 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3693957314 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 1048973863 ps |
| CPU time | 44.29 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:33:30 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-513830fb-2ccc-4450-af33-acc160ea8297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693957314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3693957314 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3472753272 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 466799704 ps |
| CPU time | 35.44 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:33:22 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-b3579553-74ca-44b7-a826-52768048051c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472753272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3472753272 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1431422862 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1111499937 ps |
| CPU time | 37.03 seconds |
| Started | Jul 25 07:32:45 PM PDT 24 |
| Finished | Jul 25 07:33:22 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-9c06df7c-005c-4ae5-a613-a9babd4f8696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431422862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1431422862 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2899709749 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 73663034121 ps |
| CPU time | 746.28 seconds |
| Started | Jul 25 07:32:50 PM PDT 24 |
| Finished | Jul 25 07:45:16 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e8134b1d-5daf-4aae-8a35-b75f61983edc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899709749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2899709749 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2287779910 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 41349488536 ps |
| CPU time | 689.4 seconds |
| Started | Jul 25 07:32:54 PM PDT 24 |
| Finished | Jul 25 07:44:23 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-91cd5b92-d886-4f0a-81d6-c35c16660ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287779910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2287779910 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.16578028 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 542773359 ps |
| CPU time | 53.57 seconds |
| Started | Jul 25 07:32:48 PM PDT 24 |
| Finished | Jul 25 07:33:42 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-8a4c08b4-9984-4374-beb7-26fadec2903e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16578028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delay s.16578028 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2712649505 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 1161269582 ps |
| CPU time | 37.84 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:33:24 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-9e7af5b2-339c-4ff3-915e-6a14147b0065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712649505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2712649505 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3091292095 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 215731285 ps |
| CPU time | 8.94 seconds |
| Started | Jul 25 07:32:45 PM PDT 24 |
| Finished | Jul 25 07:32:54 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-429d2643-f644-4e0a-b6d0-4c3e6714a7e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091292095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3091292095 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1364261305 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 8567080488 ps |
| CPU time | 88.55 seconds |
| Started | Jul 25 07:32:47 PM PDT 24 |
| Finished | Jul 25 07:34:16 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-66b8f96c-5480-4b46-b470-b948b8ea29b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364261305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1364261305 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3234243747 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 6509529132 ps |
| CPU time | 113.56 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:34:40 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-9ac522d6-9064-4824-a0dd-6107c23f1f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234243747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3234243747 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2921825180 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 45385558 ps |
| CPU time | 6.77 seconds |
| Started | Jul 25 07:32:45 PM PDT 24 |
| Finished | Jul 25 07:32:52 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-dec48e2c-4ea2-4ae4-927f-7c30ddf12ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921825180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2921825180 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.918250295 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 2152553782 ps |
| CPU time | 73.03 seconds |
| Started | Jul 25 07:32:45 PM PDT 24 |
| Finished | Jul 25 07:33:58 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-3bb550bd-0dc4-4631-b04c-8a42f75cd031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918250295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.918250295 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.538588465 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 2923339247 ps |
| CPU time | 199.44 seconds |
| Started | Jul 25 07:32:47 PM PDT 24 |
| Finished | Jul 25 07:36:07 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-d33edbcc-4140-49b8-978e-bc40986d0955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538588465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.538588465 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1712817699 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 754305729 ps |
| CPU time | 313.07 seconds |
| Started | Jul 25 07:32:44 PM PDT 24 |
| Finished | Jul 25 07:37:57 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-1972c6a1-998c-412a-975a-a9354377b17f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712817699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.1712817699 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1061429626 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 676916429 ps |
| CPU time | 265.84 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:37:12 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-e42c990b-3e18-49b6-810f-7bb6b7673b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061429626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1061429626 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.64654136 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 881742981 ps |
| CPU time | 36.29 seconds |
| Started | Jul 25 07:32:46 PM PDT 24 |
| Finished | Jul 25 07:33:22 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-59102395-1c55-4fa8-9996-0aeddfeeeb0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64654136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.64654136 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.982255006 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 5238132744 ps |
| CPU time | 508.79 seconds |
| Started | Jul 25 07:34:28 PM PDT 24 |
| Finished | Jul 25 07:42:57 PM PDT 24 |
| Peak memory | 641996 kb |
| Host | smart-95a4f70d-8eb8-4cd4-893a-7e6a954ebc7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982255006 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.982255006 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2168011835 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 4188636128 ps |
| CPU time | 267.47 seconds |
| Started | Jul 25 07:34:30 PM PDT 24 |
| Finished | Jul 25 07:38:57 PM PDT 24 |
| Peak memory | 599028 kb |
| Host | smart-3e365378-98ba-4e52-9ab6-58bbb562a752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168011835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2168011835 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2727074901 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 29000150772 ps |
| CPU time | 3789.41 seconds |
| Started | Jul 25 07:32:47 PM PDT 24 |
| Finished | Jul 25 08:35:57 PM PDT 24 |
| Peak memory | 593024 kb |
| Host | smart-c32254ac-533d-4fb5-9357-69c17ac6cbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727074901 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2727074901 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.3086687975 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 3843076884 ps |
| CPU time | 211.95 seconds |
| Started | Jul 25 07:32:43 PM PDT 24 |
| Finished | Jul 25 07:36:16 PM PDT 24 |
| Peak memory | 598252 kb |
| Host | smart-621f91c1-a989-4617-b75f-a882974f6f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086687975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3086687975 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.580601505 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 881480749 ps |
| CPU time | 73.2 seconds |
| Started | Jul 25 07:33:05 PM PDT 24 |
| Finished | Jul 25 07:34:18 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-0ea2b453-947b-4373-9e04-87782bbef26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580601505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device. 580601505 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1974067454 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 31868351713 ps |
| CPU time | 527.18 seconds |
| Started | Jul 25 07:33:04 PM PDT 24 |
| Finished | Jul 25 07:41:51 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-f202dd61-a969-4b54-98b2-d8064d18ee3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974067454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1974067454 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.71040718 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 268957661 ps |
| CPU time | 13.18 seconds |
| Started | Jul 25 07:33:03 PM PDT 24 |
| Finished | Jul 25 07:33:17 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-a034b47b-faba-4b61-bb93-f68ec9c2b171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71040718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.71040718 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3999079269 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 148750112 ps |
| CPU time | 15.55 seconds |
| Started | Jul 25 07:33:01 PM PDT 24 |
| Finished | Jul 25 07:33:17 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-e244299f-b228-4721-a722-f4337a72d120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999079269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3999079269 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.3016342199 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 893886078 ps |
| CPU time | 28.93 seconds |
| Started | Jul 25 07:33:03 PM PDT 24 |
| Finished | Jul 25 07:33:32 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-7507c952-6d26-4e68-9a3b-45910bccef34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016342199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3016342199 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.962426677 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 17670118659 ps |
| CPU time | 171.66 seconds |
| Started | Jul 25 07:33:05 PM PDT 24 |
| Finished | Jul 25 07:35:56 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-cb1b8074-7ffe-4354-b7b0-e0f961b28fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962426677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.962426677 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.92384812 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 3026767191 ps |
| CPU time | 49.68 seconds |
| Started | Jul 25 07:33:02 PM PDT 24 |
| Finished | Jul 25 07:33:52 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-ea7d9a50-13c4-46ed-929b-b5c82f38cb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92384812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.92384812 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2146177328 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 261811787 ps |
| CPU time | 25.87 seconds |
| Started | Jul 25 07:33:05 PM PDT 24 |
| Finished | Jul 25 07:33:31 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-4d4f95c3-1744-4fed-8ef5-0f1cb74c46b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146177328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.2146177328 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3996451502 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 427071765 ps |
| CPU time | 33.51 seconds |
| Started | Jul 25 07:33:01 PM PDT 24 |
| Finished | Jul 25 07:33:35 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d20f26d3-9b54-4623-9850-c1213856420a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996451502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3996451502 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2667571151 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 203476802 ps |
| CPU time | 8.58 seconds |
| Started | Jul 25 07:33:01 PM PDT 24 |
| Finished | Jul 25 07:33:09 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-ded297b9-92b1-4080-8283-0ea3d9df46d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667571151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2667571151 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2483343444 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 4926394387 ps |
| CPU time | 83.29 seconds |
| Started | Jul 25 07:33:02 PM PDT 24 |
| Finished | Jul 25 07:34:26 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-d4e757ad-83d8-4635-ab1c-f3d12bb98f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483343444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2483343444 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3961099192 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 34717073 ps |
| CPU time | 6.03 seconds |
| Started | Jul 25 07:33:00 PM PDT 24 |
| Finished | Jul 25 07:33:06 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-072bae28-5133-4f89-bd4e-5868160317de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961099192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3961099192 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.2300533212 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 12151931398 ps |
| CPU time | 469.94 seconds |
| Started | Jul 25 07:33:01 PM PDT 24 |
| Finished | Jul 25 07:40:51 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-ee50a9a0-dc7e-4141-9aed-d252917cd2ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300533212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2300533212 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1950807411 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 8931886396 ps |
| CPU time | 304.81 seconds |
| Started | Jul 25 07:34:28 PM PDT 24 |
| Finished | Jul 25 07:39:33 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-63a74f3c-6932-4cdc-953d-6c83faedb883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950807411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1950807411 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.990968379 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 367652958 ps |
| CPU time | 164.37 seconds |
| Started | Jul 25 07:33:05 PM PDT 24 |
| Finished | Jul 25 07:35:49 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-74d00106-9f5a-4e17-ad15-0eff22fd5eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990968379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_ with_rand_reset.990968379 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.694596787 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 34988086 ps |
| CPU time | 24.25 seconds |
| Started | Jul 25 07:34:30 PM PDT 24 |
| Finished | Jul 25 07:34:54 PM PDT 24 |
| Peak memory | 573924 kb |
| Host | smart-4e618cde-5563-4f1c-8919-be29781aa0ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694596787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.694596787 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.385142061 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 1193495978 ps |
| CPU time | 51.7 seconds |
| Started | Jul 25 07:33:02 PM PDT 24 |
| Finished | Jul 25 07:33:54 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-2ca2174c-aa1c-4a63-b396-c89ebeb6c3a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385142061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.385142061 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2015222999 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 7097954666 ps |
| CPU time | 455.84 seconds |
| Started | Jul 25 07:34:34 PM PDT 24 |
| Finished | Jul 25 07:42:10 PM PDT 24 |
| Peak memory | 642288 kb |
| Host | smart-8e0969cb-6e9e-4f1e-92a3-d4b2507b2125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015222999 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.2015222999 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.1200650074 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 3890890253 ps |
| CPU time | 407.42 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:41:17 PM PDT 24 |
| Peak memory | 598428 kb |
| Host | smart-4050e046-cc65-4461-8b70-b9994132a814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200650074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1200650074 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1945298639 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 13639258471 ps |
| CPU time | 1655.24 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 08:02:08 PM PDT 24 |
| Peak memory | 592712 kb |
| Host | smart-37110d78-b845-4a91-b0d9-21fdf6c6fd36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945298639 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1945298639 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.3036740326 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3418762120 ps |
| CPU time | 165.14 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:37:15 PM PDT 24 |
| Peak memory | 603308 kb |
| Host | smart-d3959a2a-edd8-4767-b92e-6c7ab70e8748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036740326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3036740326 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1229747121 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 99472833 ps |
| CPU time | 8.42 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:34:38 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-39daff2c-a029-4770-985e-0a8d4daf62b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229747121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1229747121 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3171090008 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 99294583584 ps |
| CPU time | 1577.28 seconds |
| Started | Jul 25 07:34:28 PM PDT 24 |
| Finished | Jul 25 08:00:46 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-3be6d5ac-2bc8-4e56-8c92-1be67b51a24d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171090008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3171090008 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2337937602 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 262049794 ps |
| CPU time | 31.55 seconds |
| Started | Jul 25 07:34:27 PM PDT 24 |
| Finished | Jul 25 07:34:59 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-08870345-df7f-4491-81d0-cdc96177db1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337937602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2337937602 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.1352851021 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 2031746625 ps |
| CPU time | 65.6 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:35:35 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9ed31039-ff09-4d01-8fa6-6654acc993ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352851021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.1352851021 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.2845662369 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 177679705 ps |
| CPU time | 19.01 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 07:34:51 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-2ad7677f-5a44-43ed-a203-41ae3196ab7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845662369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2845662369 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2356405866 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 88605318863 ps |
| CPU time | 889.03 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:49:18 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-8bc94557-25ee-432a-80bc-85fbbe14036c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356405866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2356405866 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.4268322537 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 9214540489 ps |
| CPU time | 164.94 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:37:14 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-5c95c655-c5ad-4947-a82b-dc024c304903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268322537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4268322537 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.714535743 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 157108634 ps |
| CPU time | 15.48 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 07:34:48 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-e6d9da33-27e1-42bc-905a-e167dfc8daeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714535743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_dela ys.714535743 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.1389338036 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 598573090 ps |
| CPU time | 21.68 seconds |
| Started | Jul 25 07:34:28 PM PDT 24 |
| Finished | Jul 25 07:34:50 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-147a9ff0-d477-4e84-927d-38531f1b348f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389338036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1389338036 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3368605109 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 150792542 ps |
| CPU time | 6.87 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:34:39 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-7cd79a9f-ff8d-4fba-957b-e452853c6624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368605109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3368605109 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.78983573 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 7664893030 ps |
| CPU time | 73.74 seconds |
| Started | Jul 25 07:34:33 PM PDT 24 |
| Finished | Jul 25 07:35:46 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-c02e8d4f-14e5-4114-b15c-7b5b4a69a62f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78983573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.78983573 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2192999529 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 4626043886 ps |
| CPU time | 76.1 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:35:46 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-05823483-f34b-437a-994f-bb7ca14a6d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192999529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2192999529 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3358272489 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 45747474 ps |
| CPU time | 6.44 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:34:37 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-66cef2b5-7710-43b5-be5d-d9839f66d06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358272489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.3358272489 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.239602979 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 16659104646 ps |
| CPU time | 625.31 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:44:54 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-2e7495a5-6f1b-4e66-aadc-af2e54b3c025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239602979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.239602979 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.4036233304 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 5468951280 ps |
| CPU time | 220.19 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:38:12 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-01bbc99d-9bdd-4862-93fe-6bd92e22a65a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036233304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.4036233304 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3975966125 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 9179412716 ps |
| CPU time | 585.07 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:44:14 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-6c499774-dba5-4d40-a86c-27f1f560c10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975966125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.3975966125 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1730690923 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 287614151 ps |
| CPU time | 85.85 seconds |
| Started | Jul 25 07:34:30 PM PDT 24 |
| Finished | Jul 25 07:35:56 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-c66212c5-4376-4dfe-a01b-c36a8742d229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730690923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1730690923 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2279380074 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 1068031557 ps |
| CPU time | 47.69 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 07:35:20 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-8e665b24-d11a-4b88-977a-ab9af0a0e57b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279380074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2279380074 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3398659660 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 9906377484 ps |
| CPU time | 878.69 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:49:24 PM PDT 24 |
| Peak memory | 652528 kb |
| Host | smart-7641f7b3-6b81-491c-8373-4c35111f9782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398659660 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.3398659660 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.760175542 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 4581758476 ps |
| CPU time | 420.89 seconds |
| Started | Jul 25 07:34:41 PM PDT 24 |
| Finished | Jul 25 07:41:42 PM PDT 24 |
| Peak memory | 597400 kb |
| Host | smart-88ac0d81-5fef-49ec-8476-c4a3a07b7136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760175542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.760175542 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1148930064 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 16119080585 ps |
| CPU time | 2139.72 seconds |
| Started | Jul 25 07:34:30 PM PDT 24 |
| Finished | Jul 25 08:10:10 PM PDT 24 |
| Peak memory | 592696 kb |
| Host | smart-89221d56-1100-406c-92a9-fbc8269d12ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148930064 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1148930064 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.348079578 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3839799135 ps |
| CPU time | 251.16 seconds |
| Started | Jul 25 07:34:29 PM PDT 24 |
| Finished | Jul 25 07:38:40 PM PDT 24 |
| Peak memory | 599200 kb |
| Host | smart-ea24aa83-3a15-4592-80c6-6add686394ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348079578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.348079578 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1948903763 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 720899672 ps |
| CPU time | 61.86 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 07:35:34 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-5af1137b-8f6e-441a-a797-a6a57823c3a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948903763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .1948903763 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2061457894 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 141892738982 ps |
| CPU time | 2427.7 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 08:15:00 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-ee897663-8b92-45cf-9d9a-136cf2cd61ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061457894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2061457894 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2108975029 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 803697842 ps |
| CPU time | 33.46 seconds |
| Started | Jul 25 07:34:34 PM PDT 24 |
| Finished | Jul 25 07:35:07 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-b5250c8c-8904-45bd-8757-2cfddf448673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108975029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2108975029 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.1110596595 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 782128611 ps |
| CPU time | 26.43 seconds |
| Started | Jul 25 07:34:34 PM PDT 24 |
| Finished | Jul 25 07:35:01 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-52ba1c09-de5e-4ff7-96ff-81c7c5a84c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110596595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1110596595 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.407405322 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 521781167 ps |
| CPU time | 21.95 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:34:54 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-76e1b0bb-98fa-4370-97f3-d3ae845f2940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407405322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.407405322 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1170388394 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 65982365270 ps |
| CPU time | 652.05 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 07:45:24 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-82228914-cdfe-4f39-badc-dd6d54abb8a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170388394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1170388394 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2294900463 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 57875613440 ps |
| CPU time | 890.98 seconds |
| Started | Jul 25 07:34:30 PM PDT 24 |
| Finished | Jul 25 07:49:21 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-cf63a858-a912-43bc-99c9-8f7cb0fba393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294900463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2294900463 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2718074747 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 284332678 ps |
| CPU time | 26.96 seconds |
| Started | Jul 25 07:34:30 PM PDT 24 |
| Finished | Jul 25 07:34:57 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-4ecb1d1a-2308-49ca-8343-bfdac01753b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718074747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2718074747 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.1786989449 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 564296537 ps |
| CPU time | 19.25 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:34:51 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-5b751318-6988-4e6e-a710-599e35cc0197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786989449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1786989449 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.224661254 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 245024061 ps |
| CPU time | 9.69 seconds |
| Started | Jul 25 07:34:28 PM PDT 24 |
| Finished | Jul 25 07:34:38 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-ff4fba7a-142d-4959-92b0-971015b20a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224661254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.224661254 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1131646741 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 8074762510 ps |
| CPU time | 82.56 seconds |
| Started | Jul 25 07:34:33 PM PDT 24 |
| Finished | Jul 25 07:35:56 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-95b58115-6b34-4faa-8152-7f424138db95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131646741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1131646741 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2901750892 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 4131458437 ps |
| CPU time | 67.03 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:35:39 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-13bed833-0734-477b-8a71-bf4ef3c2d5a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901750892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2901750892 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3486489185 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 49563005 ps |
| CPU time | 6.35 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:34:38 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-38c39c72-fbce-487a-89d9-62cdcd0e6f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486489185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3486489185 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2147930849 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 3822073397 ps |
| CPU time | 129.66 seconds |
| Started | Jul 25 07:34:31 PM PDT 24 |
| Finished | Jul 25 07:36:41 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-1209cb24-e611-46ea-a610-d46332af3fb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147930849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2147930849 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.757707467 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 1134876483 ps |
| CPU time | 76.58 seconds |
| Started | Jul 25 07:34:41 PM PDT 24 |
| Finished | Jul 25 07:35:58 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d5f4a7e6-c407-44cb-87a9-1f88bf3d4d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757707467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.757707467 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.257650256 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1188695704 ps |
| CPU time | 313.64 seconds |
| Started | Jul 25 07:34:32 PM PDT 24 |
| Finished | Jul 25 07:39:46 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-0de4910b-4f0b-4ec9-9625-da30799c3cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257650256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.257650256 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2975273220 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 2124412847 ps |
| CPU time | 157.97 seconds |
| Started | Jul 25 07:34:41 PM PDT 24 |
| Finished | Jul 25 07:37:19 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-9f147852-15e8-4fe0-8c4b-dad0421aaf53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975273220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2975273220 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2924344775 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 72862634 ps |
| CPU time | 10.72 seconds |
| Started | Jul 25 07:34:33 PM PDT 24 |
| Finished | Jul 25 07:34:44 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-7666e17b-f15c-4ab4-9720-56f469edbbcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924344775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2924344775 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2587561235 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 16057095764 ps |
| CPU time | 1946.82 seconds |
| Started | Jul 25 07:26:05 PM PDT 24 |
| Finished | Jul 25 07:58:33 PM PDT 24 |
| Peak memory | 592536 kb |
| Host | smart-f9773309-3309-4a92-b89e-276305e9f75c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587561235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.2587561235 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.264038638 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 6952763783 ps |
| CPU time | 496.75 seconds |
| Started | Jul 25 07:26:33 PM PDT 24 |
| Finished | Jul 25 07:34:50 PM PDT 24 |
| Peak memory | 641260 kb |
| Host | smart-a80799df-aa0c-4e02-a78e-300f64d1b53a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264038638 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.264038638 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.1650828890 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4932851992 ps |
| CPU time | 454.1 seconds |
| Started | Jul 25 07:26:32 PM PDT 24 |
| Finished | Jul 25 07:34:07 PM PDT 24 |
| Peak memory | 596316 kb |
| Host | smart-8b4b56c0-e959-4b48-ac67-91f15c6da364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650828890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.1650828890 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1450240310 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 5392901827 ps |
| CPU time | 260.81 seconds |
| Started | Jul 25 07:26:10 PM PDT 24 |
| Finished | Jul 25 07:30:31 PM PDT 24 |
| Peak memory | 591128 kb |
| Host | smart-15aa85a3-4138-4011-bdb5-09294971974a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450240310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.1450240310 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1666381042 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 7989099412 ps |
| CPU time | 393.94 seconds |
| Started | Jul 25 07:26:08 PM PDT 24 |
| Finished | Jul 25 07:32:42 PM PDT 24 |
| Peak memory | 599200 kb |
| Host | smart-ab991973-60c4-467c-84fe-d387b86afb7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666381042 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1666381042 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3933943025 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 16169222360 ps |
| CPU time | 1928.35 seconds |
| Started | Jul 25 07:26:06 PM PDT 24 |
| Finished | Jul 25 07:58:15 PM PDT 24 |
| Peak memory | 592596 kb |
| Host | smart-0ef9a1a5-ea0d-49d0-bee1-39b5d5b70983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933943025 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3933943025 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2200619854 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3592925322 ps |
| CPU time | 301.22 seconds |
| Started | Jul 25 07:26:08 PM PDT 24 |
| Finished | Jul 25 07:31:09 PM PDT 24 |
| Peak memory | 603380 kb |
| Host | smart-c96d6fdf-eb9a-4d4b-9496-93fc22aaa82e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200619854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2200619854 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.221253133 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 562562834 ps |
| CPU time | 40.41 seconds |
| Started | Jul 25 07:26:19 PM PDT 24 |
| Finished | Jul 25 07:26:59 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-26f4da3d-8f86-4a46-a858-b60db29fb0ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221253133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.221253133 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2098139130 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 34075857311 ps |
| CPU time | 582.31 seconds |
| Started | Jul 25 07:26:16 PM PDT 24 |
| Finished | Jul 25 07:35:59 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-e45fbd8c-820f-49de-841e-952b0ae2e9bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098139130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2098139130 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3309338404 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 255148131 ps |
| CPU time | 25.04 seconds |
| Started | Jul 25 07:26:15 PM PDT 24 |
| Finished | Jul 25 07:26:41 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-d7ab6ff5-7719-4835-9e9d-57193c6db073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309338404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .3309338404 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3512324471 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 993358446 ps |
| CPU time | 33.36 seconds |
| Started | Jul 25 07:26:15 PM PDT 24 |
| Finished | Jul 25 07:26:48 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-f536a5ba-75d3-42c8-b486-ce98b4a03b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512324471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3512324471 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.2927042276 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 160268158 ps |
| CPU time | 8.41 seconds |
| Started | Jul 25 07:26:17 PM PDT 24 |
| Finished | Jul 25 07:26:26 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-7482f0a2-9f49-43ce-b805-3bf4f256465e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927042276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2927042276 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1188856078 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 86190633667 ps |
| CPU time | 900.28 seconds |
| Started | Jul 25 07:26:17 PM PDT 24 |
| Finished | Jul 25 07:41:17 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-52c8d3bf-9efc-46d1-9132-6bbb4685aedd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188856078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1188856078 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2054473768 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 59154979910 ps |
| CPU time | 1091.96 seconds |
| Started | Jul 25 07:26:15 PM PDT 24 |
| Finished | Jul 25 07:44:27 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-fe8d5003-6482-4c54-91b0-5b282d4114cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054473768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2054473768 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1240488509 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 346759361 ps |
| CPU time | 30.6 seconds |
| Started | Jul 25 07:26:16 PM PDT 24 |
| Finished | Jul 25 07:26:46 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-897641c2-6a2d-47f3-9a6a-fba528b7ca78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240488509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1240488509 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3266708469 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 49918105 ps |
| CPU time | 6.85 seconds |
| Started | Jul 25 07:26:16 PM PDT 24 |
| Finished | Jul 25 07:26:23 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-a3475e2e-e1ae-4264-8bae-3dea4eb3a358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266708469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3266708469 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.468743959 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 176796279 ps |
| CPU time | 8.31 seconds |
| Started | Jul 25 07:26:08 PM PDT 24 |
| Finished | Jul 25 07:26:16 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c703e32c-db75-416b-91a8-384bea37daae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468743959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.468743959 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3648501117 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 8502610858 ps |
| CPU time | 88.89 seconds |
| Started | Jul 25 07:26:17 PM PDT 24 |
| Finished | Jul 25 07:27:46 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-14661b60-448e-4584-bb65-083bc13abb48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648501117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3648501117 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.493388726 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 5181910328 ps |
| CPU time | 78.67 seconds |
| Started | Jul 25 07:26:19 PM PDT 24 |
| Finished | Jul 25 07:27:38 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-56b111c2-9d14-4843-92e5-2e631f7b241f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493388726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.493388726 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3020946627 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 46896148 ps |
| CPU time | 6.49 seconds |
| Started | Jul 25 07:26:16 PM PDT 24 |
| Finished | Jul 25 07:26:23 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-f7bc4714-0164-4616-aa28-b781c88c9d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020946627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3020946627 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.338819378 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 6704363762 ps |
| CPU time | 271.3 seconds |
| Started | Jul 25 07:26:29 PM PDT 24 |
| Finished | Jul 25 07:31:00 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-0dedb167-4d2d-4894-b063-940bd08f134b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338819378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.338819378 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.333174472 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 2123174917 ps |
| CPU time | 163.26 seconds |
| Started | Jul 25 07:26:28 PM PDT 24 |
| Finished | Jul 25 07:29:11 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-4c667490-d457-4294-838c-a86ccfde734c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333174472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.333174472 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3041406817 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 8161470 ps |
| CPU time | 12.76 seconds |
| Started | Jul 25 07:26:32 PM PDT 24 |
| Finished | Jul 25 07:26:45 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-a2d6ed0a-c45d-4f2e-9fd7-63c535ce90af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041406817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3041406817 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3903513458 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 123426447 ps |
| CPU time | 39.29 seconds |
| Started | Jul 25 07:26:29 PM PDT 24 |
| Finished | Jul 25 07:27:08 PM PDT 24 |
| Peak memory | 576060 kb |
| Host | smart-d576073a-a030-4465-b17a-f8ff56934ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903513458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.3903513458 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1871316964 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 948926772 ps |
| CPU time | 42.21 seconds |
| Started | Jul 25 07:26:14 PM PDT 24 |
| Finished | Jul 25 07:26:56 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-c99d78aa-cf4a-46e8-96ba-9af8e2c111be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871316964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1871316964 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.1537255185 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3774270088 ps |
| CPU time | 285.56 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:39:31 PM PDT 24 |
| Peak memory | 603444 kb |
| Host | smart-9ead0f75-825b-4841-81f8-63fe3d5a7454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537255185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1537255185 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2124676597 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 95580840 ps |
| CPU time | 9.16 seconds |
| Started | Jul 25 07:34:39 PM PDT 24 |
| Finished | Jul 25 07:34:48 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-a89eef95-f8bd-428c-bff3-61440dad9cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124676597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2124676597 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1613428539 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 10260413676 ps |
| CPU time | 169.3 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:37:31 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-ba786e7b-4a64-4d03-9eca-007b913b2d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613428539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.1613428539 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.508453184 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 919869975 ps |
| CPU time | 36.78 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:35:21 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-975c63b6-6b1b-4e8f-9adb-aac35470cfa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508453184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr .508453184 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2365319612 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 36523889 ps |
| CPU time | 5.63 seconds |
| Started | Jul 25 07:34:55 PM PDT 24 |
| Finished | Jul 25 07:35:01 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-a913a5ae-0faf-404a-888d-21ec4747f2c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365319612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2365319612 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.3557025905 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 210029614 ps |
| CPU time | 19.55 seconds |
| Started | Jul 25 07:34:49 PM PDT 24 |
| Finished | Jul 25 07:35:09 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-18e3e118-f2e8-47db-9725-08061d2bd861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557025905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3557025905 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.107303941 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 51919568247 ps |
| CPU time | 495.25 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:43:00 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8d757bc4-b89c-4adc-b57e-2c3466afb1aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107303941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.107303941 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.1493712587 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 29931685320 ps |
| CPU time | 503.58 seconds |
| Started | Jul 25 07:34:47 PM PDT 24 |
| Finished | Jul 25 07:43:11 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-00221ede-c625-41f9-9e1a-935d06026b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493712587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1493712587 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1486049605 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 405374909 ps |
| CPU time | 37.82 seconds |
| Started | Jul 25 07:34:39 PM PDT 24 |
| Finished | Jul 25 07:35:17 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-78bedca6-d634-4dda-9fca-73420ff2f8e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486049605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1486049605 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3234979711 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 404738142 ps |
| CPU time | 30.05 seconds |
| Started | Jul 25 07:34:49 PM PDT 24 |
| Finished | Jul 25 07:35:19 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-55616268-c456-4661-91b1-3e7d7acc51e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234979711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3234979711 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.2106246096 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 146935448 ps |
| CPU time | 7.47 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:34:52 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-8416ab1a-57d0-4fa0-a527-5023dde8900e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106246096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2106246096 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.329686096 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 5242208093 ps |
| CPU time | 52.63 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:35:38 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-80a2b1cc-ceed-4e68-89ed-a45ec806b3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329686096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.329686096 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.1454768076 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 5196825624 ps |
| CPU time | 89.21 seconds |
| Started | Jul 25 07:34:39 PM PDT 24 |
| Finished | Jul 25 07:36:08 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-2e91954d-07ce-4037-a882-dcb35d7c71a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454768076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.1454768076 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.1602431109 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 38043240 ps |
| CPU time | 5.87 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:34:48 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-01dfca85-2674-4b5b-b76a-4f85d8623479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602431109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.1602431109 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.2036416251 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 8058987933 ps |
| CPU time | 287.86 seconds |
| Started | Jul 25 07:34:47 PM PDT 24 |
| Finished | Jul 25 07:39:35 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-615b0e48-edf2-4427-a999-f7b2a402816e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036416251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2036416251 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.3431505378 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 2004885741 ps |
| CPU time | 149.06 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:37:13 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-63588563-2058-4ef2-9663-29634f8a4868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431505378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3431505378 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3541940286 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 1279249650 ps |
| CPU time | 240.57 seconds |
| Started | Jul 25 07:34:46 PM PDT 24 |
| Finished | Jul 25 07:38:47 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-310fb1e1-1c21-4839-9cdc-53c3c8deca61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541940286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.3541940286 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3100038418 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3295443581 ps |
| CPU time | 372.9 seconds |
| Started | Jul 25 07:34:38 PM PDT 24 |
| Finished | Jul 25 07:40:51 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-542e2de7-96ba-4835-ad64-0fcc11c60f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100038418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.3100038418 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.4248469712 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1262746739 ps |
| CPU time | 54.08 seconds |
| Started | Jul 25 07:34:43 PM PDT 24 |
| Finished | Jul 25 07:35:37 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-3f0a7365-e0f5-4926-b50f-db0714068e4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248469712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4248469712 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.297305321 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 739387879 ps |
| CPU time | 73.66 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:35:56 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a62d4992-fd96-48ad-b7c2-31a07e4a1a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297305321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 297305321 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1263744801 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 27400605217 ps |
| CPU time | 432.04 seconds |
| Started | Jul 25 07:34:41 PM PDT 24 |
| Finished | Jul 25 07:41:53 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-8e3aeac1-19a2-4600-85b2-89c3ecbcec17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263744801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1263744801 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1067996102 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 323598983 ps |
| CPU time | 14.98 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:35:00 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-3bf23257-8d74-4d04-a268-db8503e92a3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067996102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1067996102 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.1676139820 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 697892633 ps |
| CPU time | 28.32 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:35:10 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-967f622a-e4fa-4489-aba6-366918bb2366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676139820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1676139820 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.64131506 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 554352406 ps |
| CPU time | 46.58 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:35:30 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-887c5c39-9b84-433f-aab1-388a3f73ad78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64131506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.64131506 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1295159416 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 58393725967 ps |
| CPU time | 611.43 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:44:56 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-c185ab68-8089-4c27-bb98-cf2cce47a9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295159416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1295159416 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.550648807 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 35793246812 ps |
| CPU time | 579.37 seconds |
| Started | Jul 25 07:34:46 PM PDT 24 |
| Finished | Jul 25 07:44:25 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-2e6ea72f-64f5-48e1-bed1-2b111a2d76e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550648807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.550648807 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.507727171 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 276347807 ps |
| CPU time | 23.22 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:35:08 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-9728bcdd-41f2-464a-81dd-cd1c62f351d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507727171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela ys.507727171 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.3843538149 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 1505876892 ps |
| CPU time | 42.26 seconds |
| Started | Jul 25 07:34:46 PM PDT 24 |
| Finished | Jul 25 07:35:28 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-4ac9bd9a-9ff1-41ad-a5c9-3f506544a9d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843538149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3843538149 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.378610291 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 52537202 ps |
| CPU time | 6.67 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:34:52 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-dd3dcccb-8050-473c-9431-630dff2d1fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378610291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.378610291 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.4221842829 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 4759885278 ps |
| CPU time | 47.97 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:35:33 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-73d05d2b-3aa0-4531-8813-c84d8e693fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221842829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.4221842829 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1821814011 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 5154261112 ps |
| CPU time | 87.2 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:36:11 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-0e60b9de-3e89-48b2-a0d1-8ee7b71e69cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821814011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1821814011 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2495096975 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 50118707 ps |
| CPU time | 6.54 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:34:51 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-b3ff8c3d-1e60-4d36-81a6-819ad2b390c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495096975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2495096975 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.3833411899 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 2992200587 ps |
| CPU time | 119.47 seconds |
| Started | Jul 25 07:34:41 PM PDT 24 |
| Finished | Jul 25 07:36:41 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-cbddfd3d-a45a-485c-8256-94264181439e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833411899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3833411899 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.777284562 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 3386004122 ps |
| CPU time | 249.66 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:38:54 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b407fb98-81e5-49e6-a2b0-3ae37ef5c690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777284562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.777284562 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.4173347618 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1346185672 ps |
| CPU time | 309.05 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:39:54 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-a2c6da83-f7d5-4a48-8606-4e7b36673d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173347618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.4173347618 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.748329477 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 62646451 ps |
| CPU time | 35.18 seconds |
| Started | Jul 25 07:34:43 PM PDT 24 |
| Finished | Jul 25 07:35:19 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-b7b2eea6-00b2-46f9-9e09-9a5d026dd8f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748329477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.748329477 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3984250927 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 80249492 ps |
| CPU time | 6.99 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:34:52 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-04d6ae4a-16cb-41b8-896c-0db3f101c3b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984250927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3984250927 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.2877921741 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3176958682 ps |
| CPU time | 144.22 seconds |
| Started | Jul 25 07:34:45 PM PDT 24 |
| Finished | Jul 25 07:37:09 PM PDT 24 |
| Peak memory | 598188 kb |
| Host | smart-805cbe32-2112-4cb7-b99f-b507f834e7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877921741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.2877921741 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.3585671563 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 827692759 ps |
| CPU time | 54.07 seconds |
| Started | Jul 25 07:34:38 PM PDT 24 |
| Finished | Jul 25 07:35:32 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-5155ca27-7cbd-4ee1-89fd-98bd673c660e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585671563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .3585671563 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.887478705 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 151991058928 ps |
| CPU time | 2777.26 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 08:21:02 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d44192bd-ced5-495c-8770-7a6426e85d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887478705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d evice_slow_rsp.887478705 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1152747441 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 549304228 ps |
| CPU time | 25.63 seconds |
| Started | Jul 25 07:34:52 PM PDT 24 |
| Finished | Jul 25 07:35:18 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-a8daac3f-fa6a-4be1-9fd7-cac5ac22ffd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152747441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1152747441 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2596679988 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 388367254 ps |
| CPU time | 29.27 seconds |
| Started | Jul 25 07:34:55 PM PDT 24 |
| Finished | Jul 25 07:35:24 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-00104cda-eb80-4257-a8f2-c3aa6eb33075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596679988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2596679988 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.2876751672 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 57973832 ps |
| CPU time | 8.87 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:34:52 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-e80ab46f-54c3-42c1-9bbb-d341da132c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876751672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2876751672 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1784029156 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 109419927948 ps |
| CPU time | 1140.44 seconds |
| Started | Jul 25 07:34:46 PM PDT 24 |
| Finished | Jul 25 07:53:47 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-8d4375d6-5601-4cd6-9e12-72e267c38fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784029156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1784029156 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.3059068455 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 36141005812 ps |
| CPU time | 587.91 seconds |
| Started | Jul 25 07:34:43 PM PDT 24 |
| Finished | Jul 25 07:44:31 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-49e3aa9a-77af-4df8-ac33-6ff976c5fb19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059068455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3059068455 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1650736545 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 194851842 ps |
| CPU time | 17.74 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:35:00 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-9b1f4257-21b5-4d52-a273-7c12102f1d40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650736545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1650736545 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.3367190015 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 334606757 ps |
| CPU time | 23.98 seconds |
| Started | Jul 25 07:34:55 PM PDT 24 |
| Finished | Jul 25 07:35:19 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-1be6a129-304b-4ccd-a342-290d595b6b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367190015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3367190015 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.3410729220 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 49124576 ps |
| CPU time | 6.39 seconds |
| Started | Jul 25 07:34:44 PM PDT 24 |
| Finished | Jul 25 07:34:51 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-dacd8b49-7e00-4522-b12c-1366b41a3332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410729220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3410729220 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.778467067 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 6129221358 ps |
| CPU time | 65.27 seconds |
| Started | Jul 25 07:34:42 PM PDT 24 |
| Finished | Jul 25 07:35:48 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-475f24f6-5774-4e25-bab2-d97d03f2b1b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778467067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.778467067 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1823672342 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 3653390282 ps |
| CPU time | 58.76 seconds |
| Started | Jul 25 07:34:49 PM PDT 24 |
| Finished | Jul 25 07:35:48 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-3dfacd91-4ada-4c0c-a10a-edca48bda57e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823672342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1823672342 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1316798910 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 51135906 ps |
| CPU time | 6.77 seconds |
| Started | Jul 25 07:34:46 PM PDT 24 |
| Finished | Jul 25 07:34:52 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-730db2c8-a432-4d36-a90b-54ec02f6c977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316798910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1316798910 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.1354763461 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 9795515729 ps |
| CPU time | 394.05 seconds |
| Started | Jul 25 07:34:49 PM PDT 24 |
| Finished | Jul 25 07:41:23 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-6be17815-2a4d-442c-9795-7ca37467424a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354763461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1354763461 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1684742035 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 2381647321 ps |
| CPU time | 183.03 seconds |
| Started | Jul 25 07:35:02 PM PDT 24 |
| Finished | Jul 25 07:38:05 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-4f963f76-815a-4d5b-90ce-273db1d5dfd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684742035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1684742035 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2996499813 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 6783319080 ps |
| CPU time | 294.35 seconds |
| Started | Jul 25 07:34:51 PM PDT 24 |
| Finished | Jul 25 07:39:46 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-621c43f3-3631-4efe-8061-58278f6ee3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996499813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2996499813 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3328877929 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 1216819647 ps |
| CPU time | 52.7 seconds |
| Started | Jul 25 07:34:53 PM PDT 24 |
| Finished | Jul 25 07:35:46 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-36adc1c9-4760-4258-9c85-9bff841710d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328877929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3328877929 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.3685933273 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 4036559940 ps |
| CPU time | 285.66 seconds |
| Started | Jul 25 07:35:02 PM PDT 24 |
| Finished | Jul 25 07:39:48 PM PDT 24 |
| Peak memory | 603368 kb |
| Host | smart-daa81c29-50c3-4be1-abb6-bba8cd5fb13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685933273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3685933273 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.608256193 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 194780742 ps |
| CPU time | 14.08 seconds |
| Started | Jul 25 07:35:20 PM PDT 24 |
| Finished | Jul 25 07:35:34 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-d817bdb3-2667-4df9-b14b-9ce616201512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608256193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 608256193 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.795921488 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 92422048639 ps |
| CPU time | 1684.69 seconds |
| Started | Jul 25 07:35:13 PM PDT 24 |
| Finished | Jul 25 08:03:18 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-75e692d3-c8b8-46c3-a085-39640223858f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795921488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.795921488 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2884212228 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 26684584 ps |
| CPU time | 5.59 seconds |
| Started | Jul 25 07:35:13 PM PDT 24 |
| Finished | Jul 25 07:35:18 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-c2b08881-1ef1-475b-af7e-d9c05cce30c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884212228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.2884212228 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1351692635 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 2082569069 ps |
| CPU time | 71.26 seconds |
| Started | Jul 25 07:35:15 PM PDT 24 |
| Finished | Jul 25 07:36:27 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-b0d4f560-e781-4d04-915e-549670b0c899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351692635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1351692635 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.3674541455 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 716758586 ps |
| CPU time | 26.83 seconds |
| Started | Jul 25 07:35:04 PM PDT 24 |
| Finished | Jul 25 07:35:31 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-306c60fe-e37a-47b7-aabc-3be03e80c8d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674541455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.3674541455 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.1182821593 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 108619440737 ps |
| CPU time | 1140.58 seconds |
| Started | Jul 25 07:35:03 PM PDT 24 |
| Finished | Jul 25 07:54:04 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-cd69cd02-1aff-494f-b3f5-7dfebdcf828a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182821593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1182821593 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.389528897 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 24418454154 ps |
| CPU time | 417.08 seconds |
| Started | Jul 25 07:35:11 PM PDT 24 |
| Finished | Jul 25 07:42:08 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-5782ea1c-f394-4640-b5b0-fde8fe3df991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389528897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.389528897 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1541677962 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 611441090 ps |
| CPU time | 50.94 seconds |
| Started | Jul 25 07:35:05 PM PDT 24 |
| Finished | Jul 25 07:35:56 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-5244f122-cb38-42eb-a57e-366157d78873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541677962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1541677962 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.182942436 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 528336991 ps |
| CPU time | 43.19 seconds |
| Started | Jul 25 07:35:11 PM PDT 24 |
| Finished | Jul 25 07:35:55 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-04e5491a-983c-4985-b8e4-f69963b73a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182942436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.182942436 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.2210831854 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 226925414 ps |
| CPU time | 9.62 seconds |
| Started | Jul 25 07:35:02 PM PDT 24 |
| Finished | Jul 25 07:35:12 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-c66dba6f-b414-4809-9a78-573795f109f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210831854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2210831854 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.531760242 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 7239012659 ps |
| CPU time | 74.87 seconds |
| Started | Jul 25 07:35:03 PM PDT 24 |
| Finished | Jul 25 07:36:18 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-6dd310e3-5784-49f8-80b3-a885c1bfc042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531760242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.531760242 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2490350155 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 4114461161 ps |
| CPU time | 69.82 seconds |
| Started | Jul 25 07:35:03 PM PDT 24 |
| Finished | Jul 25 07:36:13 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-05f9c63a-be46-46f3-9528-026a7c20762a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490350155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2490350155 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3848431 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 51577045 ps |
| CPU time | 6.35 seconds |
| Started | Jul 25 07:35:03 PM PDT 24 |
| Finished | Jul 25 07:35:09 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-5e31ae31-16ed-48f4-9581-90b6ccb97892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3848431 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.166209110 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 7003162248 ps |
| CPU time | 239.53 seconds |
| Started | Jul 25 07:35:15 PM PDT 24 |
| Finished | Jul 25 07:39:15 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-d8db6695-ee43-48b1-9d53-264b3c1f79a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166209110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.166209110 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.135828151 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 17289175715 ps |
| CPU time | 598.23 seconds |
| Started | Jul 25 07:35:14 PM PDT 24 |
| Finished | Jul 25 07:45:13 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-0c6df1c3-6204-472c-b987-7dd3a6454d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135828151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.135828151 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1712681403 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 168954295 ps |
| CPU time | 67.74 seconds |
| Started | Jul 25 07:35:13 PM PDT 24 |
| Finished | Jul 25 07:36:21 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-092826dd-737c-47c0-916f-8152f4411953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712681403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.1712681403 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.166917004 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 7825950533 ps |
| CPU time | 448.73 seconds |
| Started | Jul 25 07:35:14 PM PDT 24 |
| Finished | Jul 25 07:42:43 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-a9238015-fbc6-4ff5-bf59-0269a62907e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166917004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_reset_error.166917004 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2319727073 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 293390466 ps |
| CPU time | 37.74 seconds |
| Started | Jul 25 07:35:13 PM PDT 24 |
| Finished | Jul 25 07:35:51 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-849e2cbc-6762-4ab0-b8c0-bd27dc053567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319727073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2319727073 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3089979395 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4819130198 ps |
| CPU time | 397.02 seconds |
| Started | Jul 25 07:35:12 PM PDT 24 |
| Finished | Jul 25 07:41:49 PM PDT 24 |
| Peak memory | 603412 kb |
| Host | smart-641ea4b3-a7d2-41d5-b6a2-b602aebe907c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089979395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3089979395 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.315615253 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 189024533 ps |
| CPU time | 16.06 seconds |
| Started | Jul 25 07:35:36 PM PDT 24 |
| Finished | Jul 25 07:35:52 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-2d30fb77-789c-4078-9de7-8b3172b9d2cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315615253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 315615253 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.715841164 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 25589838797 ps |
| CPU time | 416.67 seconds |
| Started | Jul 25 07:35:36 PM PDT 24 |
| Finished | Jul 25 07:42:33 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-171efd69-aede-4b03-80ca-e8675fcbbb1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715841164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_d evice_slow_rsp.715841164 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2797249455 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 1494860683 ps |
| CPU time | 57.51 seconds |
| Started | Jul 25 07:35:37 PM PDT 24 |
| Finished | Jul 25 07:36:35 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-e8513d9f-47fe-4783-88ef-74e696b007e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797249455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2797249455 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.1138669148 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 1717897240 ps |
| CPU time | 54.83 seconds |
| Started | Jul 25 07:35:36 PM PDT 24 |
| Finished | Jul 25 07:36:31 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-5317f8e2-ca43-43bf-992c-9d21388717cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138669148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1138669148 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.1939794777 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 1164621020 ps |
| CPU time | 38.86 seconds |
| Started | Jul 25 07:35:31 PM PDT 24 |
| Finished | Jul 25 07:36:10 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-702873ea-4e0f-4653-85f4-5aca5aee616d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939794777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.1939794777 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3083333343 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 52729895086 ps |
| CPU time | 535.11 seconds |
| Started | Jul 25 07:35:30 PM PDT 24 |
| Finished | Jul 25 07:44:26 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-6202a5a6-2207-47d4-b1ea-00a89d5aeeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083333343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3083333343 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1072122903 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 36035639737 ps |
| CPU time | 617.2 seconds |
| Started | Jul 25 07:35:37 PM PDT 24 |
| Finished | Jul 25 07:45:55 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-56766d60-f07d-4430-8f2e-3c4607853054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072122903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1072122903 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3035229494 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 472395964 ps |
| CPU time | 42.26 seconds |
| Started | Jul 25 07:35:24 PM PDT 24 |
| Finished | Jul 25 07:36:06 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c1e719c4-68f5-4cad-ae14-f2fe9b7a90bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035229494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.3035229494 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.442901274 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 976256600 ps |
| CPU time | 30.71 seconds |
| Started | Jul 25 07:35:37 PM PDT 24 |
| Finished | Jul 25 07:36:08 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-84ce8b92-acb4-4ac0-8c10-56b4bbe6d611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442901274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.442901274 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.4109705844 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 165271119 ps |
| CPU time | 8.82 seconds |
| Started | Jul 25 07:35:23 PM PDT 24 |
| Finished | Jul 25 07:35:32 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-f50771d3-dbc8-486b-8931-38aaaaa2b9cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109705844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.4109705844 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.1245154811 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 10366353860 ps |
| CPU time | 111.34 seconds |
| Started | Jul 25 07:35:24 PM PDT 24 |
| Finished | Jul 25 07:37:16 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-ed7d35a1-6132-41d1-af7f-7c4c3a3a7d35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245154811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.1245154811 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2428226764 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 4283419849 ps |
| CPU time | 72 seconds |
| Started | Jul 25 07:35:24 PM PDT 24 |
| Finished | Jul 25 07:36:36 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-07e4fc1d-f339-404a-9c6b-015943eb91ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428226764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2428226764 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.4161458028 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 49903832 ps |
| CPU time | 6.38 seconds |
| Started | Jul 25 07:35:29 PM PDT 24 |
| Finished | Jul 25 07:35:36 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-4d79562b-abd6-488f-98e8-07877f55eb9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161458028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.4161458028 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.3394701821 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 991275111 ps |
| CPU time | 78.32 seconds |
| Started | Jul 25 07:35:37 PM PDT 24 |
| Finished | Jul 25 07:36:55 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-81a499ac-145d-45d7-a2c4-d839a69c5373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394701821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3394701821 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3245811541 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 882138216 ps |
| CPU time | 73.97 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:37:06 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-c580ce6b-ef15-41b7-8a93-1f3b4a4dcde4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245811541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3245811541 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.263029540 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 214030227 ps |
| CPU time | 58.81 seconds |
| Started | Jul 25 07:35:36 PM PDT 24 |
| Finished | Jul 25 07:36:35 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-2548ccc0-f7c4-48ba-8293-0094de38b4fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263029540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.263029540 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.269314747 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 10363795527 ps |
| CPU time | 461.97 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:43:34 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-63e2503e-6d5d-4e42-8b2e-a6c26bf87388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269314747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.269314747 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2764352869 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 298436187 ps |
| CPU time | 13.35 seconds |
| Started | Jul 25 07:35:37 PM PDT 24 |
| Finished | Jul 25 07:35:50 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-5a6890f7-0743-419d-b667-517ba9e88a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764352869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2764352869 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.4192483830 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 6379846639 ps |
| CPU time | 519.77 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:44:32 PM PDT 24 |
| Peak memory | 603432 kb |
| Host | smart-41610650-92a8-4d81-861f-6886112e3638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192483830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.4192483830 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.1378858410 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 770065288 ps |
| CPU time | 71.42 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:37:18 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-f821f955-a974-4dee-8b7c-5cbca4377d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378858410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .1378858410 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3325478320 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 70642558827 ps |
| CPU time | 1194.39 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:56:02 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-c10d3dd6-85ca-4bc6-831a-54f1b17d7c95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325478320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.3325478320 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1614511853 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 1076611994 ps |
| CPU time | 43.92 seconds |
| Started | Jul 25 07:36:05 PM PDT 24 |
| Finished | Jul 25 07:36:49 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-107d75c9-4901-42e9-9fa3-94231fb422b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614511853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.1614511853 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.831978163 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 249816614 ps |
| CPU time | 11.16 seconds |
| Started | Jul 25 07:36:06 PM PDT 24 |
| Finished | Jul 25 07:36:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-daf563db-68a1-4064-853d-b33feaa9bfa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831978163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.831978163 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.873553049 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 379220199 ps |
| CPU time | 13.97 seconds |
| Started | Jul 25 07:35:54 PM PDT 24 |
| Finished | Jul 25 07:36:08 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-7b6e9b8c-0f6e-480a-b072-d36ee0b31c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873553049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.873553049 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1451973602 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 28339524510 ps |
| CPU time | 284.31 seconds |
| Started | Jul 25 07:35:53 PM PDT 24 |
| Finished | Jul 25 07:40:38 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-7d10cc87-8d13-430c-b0ca-b19daa5b7669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451973602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1451973602 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1442945305 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 37693186796 ps |
| CPU time | 549.84 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:45:02 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-20968f63-11d9-485c-bdca-c1503a6657a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442945305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1442945305 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.3988867911 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 68553483 ps |
| CPU time | 8.78 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:36:01 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-1f1aed5b-6f39-4292-be4d-766ea7c28d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988867911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.3988867911 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3447266011 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 140275039 ps |
| CPU time | 7.44 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:36:14 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-e001e644-9796-4882-8da0-b5997eef3a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447266011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3447266011 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.2649386764 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 46682178 ps |
| CPU time | 6.24 seconds |
| Started | Jul 25 07:35:47 PM PDT 24 |
| Finished | Jul 25 07:35:53 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-33681487-87e9-4a8a-9b5f-851cc44801ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649386764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2649386764 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.4163277858 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 9301513721 ps |
| CPU time | 98.28 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:37:31 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-baa0118c-1f38-4627-8a95-4e1cb6835d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163277858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.4163277858 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.4253947427 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 6363389976 ps |
| CPU time | 111.99 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:37:44 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-2715ce97-eb63-438a-aba7-5663e3cfa478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253947427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.4253947427 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3924169297 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 45283038 ps |
| CPU time | 6.3 seconds |
| Started | Jul 25 07:35:52 PM PDT 24 |
| Finished | Jul 25 07:35:58 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-4ba77ba4-f9fa-4ddb-ac87-e353c4908801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924169297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.3924169297 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2736666724 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2069512907 ps |
| CPU time | 163.19 seconds |
| Started | Jul 25 07:36:06 PM PDT 24 |
| Finished | Jul 25 07:38:49 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-912c4fe4-4351-4304-8684-d23ec1a6640d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736666724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2736666724 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2783593787 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 12629385968 ps |
| CPU time | 486.39 seconds |
| Started | Jul 25 07:36:06 PM PDT 24 |
| Finished | Jul 25 07:44:12 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-8399dc87-bd05-4ba9-ab05-e4ce2a4ed37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783593787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2783593787 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3726840583 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 1670083308 ps |
| CPU time | 94.03 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:37:41 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-d8aa2073-789a-4478-a4ed-2725894af9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726840583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3726840583 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.2445581645 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 1344374154 ps |
| CPU time | 53.07 seconds |
| Started | Jul 25 07:36:05 PM PDT 24 |
| Finished | Jul 25 07:36:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-0ae29b3e-6578-4215-a888-75a28ab7d1f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445581645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.2445581645 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.168775538 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 3387500281 ps |
| CPU time | 211.37 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:39:39 PM PDT 24 |
| Peak memory | 598388 kb |
| Host | smart-2fd3fde6-5a73-46fc-9ee3-79b53ef99961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168775538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.168775538 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.17758768 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 42372431791 ps |
| CPU time | 728.5 seconds |
| Started | Jul 25 07:36:06 PM PDT 24 |
| Finished | Jul 25 07:48:14 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-7e592caf-833b-4bd1-962b-1c4edaf17e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17758768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_de vice_slow_rsp.17758768 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3440839038 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 100672207 ps |
| CPU time | 7.58 seconds |
| Started | Jul 25 07:36:09 PM PDT 24 |
| Finished | Jul 25 07:36:17 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-02cf3c3b-a547-4111-9f30-0c2a48d320e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440839038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.3440839038 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.104803840 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 2572381471 ps |
| CPU time | 96.78 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:37:44 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-76b4ade3-e8b9-42d1-9d27-bf8797988c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104803840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.104803840 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.531364065 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 556087893 ps |
| CPU time | 43.71 seconds |
| Started | Jul 25 07:36:06 PM PDT 24 |
| Finished | Jul 25 07:36:50 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-cbab17e5-e049-4a6f-9094-ead02c9884d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531364065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.531364065 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.116934971 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 52267172964 ps |
| CPU time | 518.31 seconds |
| Started | Jul 25 07:36:08 PM PDT 24 |
| Finished | Jul 25 07:44:46 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-1d100e1c-e7d9-43f7-848d-54860cabb41c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116934971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.116934971 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1034863235 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 41532397466 ps |
| CPU time | 697.36 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:47:45 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-fe85b826-68f5-4d6d-895c-bb9ba81cc4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034863235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1034863235 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.4276859892 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 310753831 ps |
| CPU time | 29.38 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:36:37 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-9f8dd099-5c6f-4155-a9ab-7337c16e84d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276859892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.4276859892 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1862603364 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 148276708 ps |
| CPU time | 12.5 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:36:20 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-5f7a33d6-e778-4cc0-9292-d15e921a4a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862603364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1862603364 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.3916354419 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 161259411 ps |
| CPU time | 8.19 seconds |
| Started | Jul 25 07:36:10 PM PDT 24 |
| Finished | Jul 25 07:36:18 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-9ae28cd9-8c25-4537-8811-8cb6b7b46ee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916354419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3916354419 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1220661089 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 9639613655 ps |
| CPU time | 96.33 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:37:43 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-b766f665-a7c6-47a0-80dd-106d8fc7309d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220661089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1220661089 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3075941737 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 3332421892 ps |
| CPU time | 56.02 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:37:03 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-fb40e1a7-9259-40c1-9911-7452bafee945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075941737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3075941737 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3237201077 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 44496830 ps |
| CPU time | 6.22 seconds |
| Started | Jul 25 07:36:05 PM PDT 24 |
| Finished | Jul 25 07:36:12 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-f4173641-5266-44fa-8c3e-ed16e54b8069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237201077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3237201077 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.1282769896 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 1787949967 ps |
| CPU time | 156.65 seconds |
| Started | Jul 25 07:36:09 PM PDT 24 |
| Finished | Jul 25 07:38:46 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-a4635a68-508a-495c-aaff-cdaaccc514f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282769896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1282769896 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2841601810 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 6063200431 ps |
| CPU time | 243.08 seconds |
| Started | Jul 25 07:36:09 PM PDT 24 |
| Finished | Jul 25 07:40:13 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-fa74beb1-e39b-458e-96f7-2be4fb2a8c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841601810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2841601810 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.449202867 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 322789226 ps |
| CPU time | 34.9 seconds |
| Started | Jul 25 07:36:08 PM PDT 24 |
| Finished | Jul 25 07:36:43 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-f2ccc722-f5d6-432d-9127-a3d0ab8878c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449202867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.449202867 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1646479825 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 2236892568 ps |
| CPU time | 92.87 seconds |
| Started | Jul 25 07:36:27 PM PDT 24 |
| Finished | Jul 25 07:38:00 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-3e6b849c-e41b-4a88-9a1d-4d97b59b4509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646479825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .1646479825 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2618817061 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 27372299204 ps |
| CPU time | 460.66 seconds |
| Started | Jul 25 07:36:19 PM PDT 24 |
| Finished | Jul 25 07:43:59 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-52f03346-e308-475f-a3f6-4ebc69a42492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618817061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.2618817061 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2308430732 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 218063150 ps |
| CPU time | 24.63 seconds |
| Started | Jul 25 07:36:17 PM PDT 24 |
| Finished | Jul 25 07:36:42 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-429ac4ed-e4d6-4371-895f-ad64434fdcd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308430732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2308430732 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.49903804 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 543540761 ps |
| CPU time | 21.19 seconds |
| Started | Jul 25 07:36:19 PM PDT 24 |
| Finished | Jul 25 07:36:40 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-1581b2af-735c-4949-8782-45bcb73c98d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49903804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.49903804 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.2979692653 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 525270560 ps |
| CPU time | 19.11 seconds |
| Started | Jul 25 07:36:18 PM PDT 24 |
| Finished | Jul 25 07:36:37 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-ddec8240-98df-4617-a329-09c7a30b05f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979692653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.2979692653 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2441396817 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 32423099673 ps |
| CPU time | 355.75 seconds |
| Started | Jul 25 07:36:27 PM PDT 24 |
| Finished | Jul 25 07:42:23 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-2bfff28c-b6cc-46c1-aabb-c7be44dfccf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441396817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2441396817 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.3782642181 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 49945260825 ps |
| CPU time | 787.1 seconds |
| Started | Jul 25 07:36:21 PM PDT 24 |
| Finished | Jul 25 07:49:28 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-90bfb6ed-852d-4a82-8414-188b483e4f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782642181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3782642181 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.901056512 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 505329897 ps |
| CPU time | 50.96 seconds |
| Started | Jul 25 07:36:17 PM PDT 24 |
| Finished | Jul 25 07:37:08 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-0a9d60fc-548d-43a2-a05d-0c672686e5a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901056512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.901056512 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1814137789 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 278521174 ps |
| CPU time | 10.59 seconds |
| Started | Jul 25 07:36:18 PM PDT 24 |
| Finished | Jul 25 07:36:29 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-18e2901f-82bf-42e0-ae59-c7bf218fa585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814137789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1814137789 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.498481486 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 47841666 ps |
| CPU time | 6.52 seconds |
| Started | Jul 25 07:36:07 PM PDT 24 |
| Finished | Jul 25 07:36:14 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4fb5fab4-337c-4c05-b852-88ba824f4587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498481486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.498481486 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1852512609 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 6884508762 ps |
| CPU time | 75.85 seconds |
| Started | Jul 25 07:36:22 PM PDT 24 |
| Finished | Jul 25 07:37:38 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-fde60df3-80ec-475f-9175-83c83bdca49c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852512609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1852512609 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.2466144636 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 3800124293 ps |
| CPU time | 65.2 seconds |
| Started | Jul 25 07:36:17 PM PDT 24 |
| Finished | Jul 25 07:37:22 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c3d5799a-8875-4932-8c84-33123434e625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466144636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.2466144636 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1374462951 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 59599344 ps |
| CPU time | 7.33 seconds |
| Started | Jul 25 07:36:10 PM PDT 24 |
| Finished | Jul 25 07:36:17 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f13212cd-c4db-4884-ba91-6a53a4d8d608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374462951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1374462951 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.1976712979 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 5691766015 ps |
| CPU time | 211.57 seconds |
| Started | Jul 25 07:36:19 PM PDT 24 |
| Finished | Jul 25 07:39:51 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-36b73438-fd6e-486d-8038-e2092d735678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976712979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1976712979 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.4269237249 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 15113990414 ps |
| CPU time | 560.14 seconds |
| Started | Jul 25 07:36:27 PM PDT 24 |
| Finished | Jul 25 07:45:47 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-4d1822e3-3115-48d1-b43e-c854a2a861ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269237249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4269237249 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.2228670423 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1998560178 ps |
| CPU time | 263 seconds |
| Started | Jul 25 07:36:18 PM PDT 24 |
| Finished | Jul 25 07:40:41 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-30f35a25-6c1c-4cd9-8767-816d6570864c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228670423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.2228670423 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2929874136 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 581522759 ps |
| CPU time | 89.19 seconds |
| Started | Jul 25 07:36:20 PM PDT 24 |
| Finished | Jul 25 07:37:49 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ef92a875-ab83-41ba-94db-44ce8e75da2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929874136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.2929874136 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2103862068 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 128428465 ps |
| CPU time | 9.6 seconds |
| Started | Jul 25 07:36:19 PM PDT 24 |
| Finished | Jul 25 07:36:29 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-2096d0a2-9bc8-42b7-9f55-4a9263540799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103862068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2103862068 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.4249433648 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3422399292 ps |
| CPU time | 151.01 seconds |
| Started | Jul 25 07:36:19 PM PDT 24 |
| Finished | Jul 25 07:38:50 PM PDT 24 |
| Peak memory | 598256 kb |
| Host | smart-9c900f98-3eaf-428a-81e8-e1088893d808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249433648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.4249433648 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1897154775 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 3295236181 ps |
| CPU time | 137.18 seconds |
| Started | Jul 25 07:36:33 PM PDT 24 |
| Finished | Jul 25 07:38:50 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-2a216c1b-b0d1-4e01-a347-d49d47059a12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897154775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1897154775 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1269360129 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 149618398053 ps |
| CPU time | 2497.51 seconds |
| Started | Jul 25 07:36:49 PM PDT 24 |
| Finished | Jul 25 08:18:27 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-ea599b6c-eca9-4605-a114-1fad27ad9827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269360129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.1269360129 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2351736312 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 174694118 ps |
| CPU time | 19.67 seconds |
| Started | Jul 25 07:36:32 PM PDT 24 |
| Finished | Jul 25 07:36:52 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-59e3b22c-0b01-4173-9f75-f4957a3f736e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351736312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2351736312 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.1903102940 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 323124568 ps |
| CPU time | 26.89 seconds |
| Started | Jul 25 07:36:34 PM PDT 24 |
| Finished | Jul 25 07:37:01 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-8b6b55c5-b953-4678-819b-5f29e768b10a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903102940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1903102940 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.972216076 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 1397816116 ps |
| CPU time | 51.41 seconds |
| Started | Jul 25 07:36:31 PM PDT 24 |
| Finished | Jul 25 07:37:23 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-ee0e1667-66ca-4411-8fb7-568c99cef1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972216076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.972216076 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2783832119 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 34024416694 ps |
| CPU time | 361.49 seconds |
| Started | Jul 25 07:36:39 PM PDT 24 |
| Finished | Jul 25 07:42:41 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-7a89a5cc-e2a3-4dd6-9d4d-315d395c4329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783832119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2783832119 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1593488884 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 48960183133 ps |
| CPU time | 763.5 seconds |
| Started | Jul 25 07:36:38 PM PDT 24 |
| Finished | Jul 25 07:49:22 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-60183f55-2c66-40c1-a544-8559c486df39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593488884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1593488884 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3520453651 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 593120198 ps |
| CPU time | 48.94 seconds |
| Started | Jul 25 07:36:32 PM PDT 24 |
| Finished | Jul 25 07:37:21 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-afb814e7-56d8-48e0-9c20-f767cf867686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520453651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3520453651 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1228686977 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 195423828 ps |
| CPU time | 17.38 seconds |
| Started | Jul 25 07:36:31 PM PDT 24 |
| Finished | Jul 25 07:36:48 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-020e4733-fb81-468d-8b77-fd40b6295194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228686977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1228686977 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.2103560 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 46317722 ps |
| CPU time | 6.55 seconds |
| Started | Jul 25 07:36:18 PM PDT 24 |
| Finished | Jul 25 07:36:25 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-7971b693-232a-4f80-8e12-4481be67f51e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2103560 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.1807340788 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 7399391188 ps |
| CPU time | 72.89 seconds |
| Started | Jul 25 07:36:20 PM PDT 24 |
| Finished | Jul 25 07:37:33 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-c0959a8e-f46c-4c7e-b2ef-cf254a072f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807340788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.1807340788 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.4064708212 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 6380276258 ps |
| CPU time | 107.71 seconds |
| Started | Jul 25 07:36:32 PM PDT 24 |
| Finished | Jul 25 07:38:19 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-9e112427-1c3b-4c32-911c-50cc8b04faa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064708212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.4064708212 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1211132538 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 51076175 ps |
| CPU time | 7.28 seconds |
| Started | Jul 25 07:36:19 PM PDT 24 |
| Finished | Jul 25 07:36:26 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-8bedeb0d-f46d-4251-a204-0b38c76c264a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211132538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1211132538 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.1810654009 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 7061383744 ps |
| CPU time | 255.14 seconds |
| Started | Jul 25 07:36:32 PM PDT 24 |
| Finished | Jul 25 07:40:47 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-2c2af00b-d5b9-45b1-a004-1b7010f3556c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810654009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1810654009 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.3184262951 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 1118518152 ps |
| CPU time | 96.35 seconds |
| Started | Jul 25 07:36:32 PM PDT 24 |
| Finished | Jul 25 07:38:09 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-c7e41862-07a2-4acf-9da6-80e25edd6677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184262951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3184262951 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.775428332 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 680200343 ps |
| CPU time | 207.65 seconds |
| Started | Jul 25 07:36:35 PM PDT 24 |
| Finished | Jul 25 07:40:03 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-ab5c02e9-2e48-44a7-bb24-65371d966b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775428332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_ with_rand_reset.775428332 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2340334967 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 7321217435 ps |
| CPU time | 352.77 seconds |
| Started | Jul 25 07:36:31 PM PDT 24 |
| Finished | Jul 25 07:42:24 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-1e726135-d9bb-42bc-a6f4-83071689a39e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340334967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2340334967 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.3658034559 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 1073820494 ps |
| CPU time | 36.55 seconds |
| Started | Jul 25 07:36:31 PM PDT 24 |
| Finished | Jul 25 07:37:07 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-c8f27bca-c3b9-4685-94f0-fed21404d5c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658034559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3658034559 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.2200010490 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 3584308627 ps |
| CPU time | 224.61 seconds |
| Started | Jul 25 07:36:32 PM PDT 24 |
| Finished | Jul 25 07:40:17 PM PDT 24 |
| Peak memory | 598224 kb |
| Host | smart-242d0ffe-0c25-4794-9b6d-afe96ef9cb50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200010490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2200010490 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.342887885 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 701903634 ps |
| CPU time | 57.58 seconds |
| Started | Jul 25 07:36:45 PM PDT 24 |
| Finished | Jul 25 07:37:42 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b716c583-b7e5-45ba-b3eb-86319e903570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342887885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device. 342887885 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1909824344 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 131399488613 ps |
| CPU time | 2369.61 seconds |
| Started | Jul 25 07:36:44 PM PDT 24 |
| Finished | Jul 25 08:16:14 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-95c66353-7d77-43f9-a5d9-5e441dea50c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909824344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.1909824344 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.796761823 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 1341665010 ps |
| CPU time | 49.68 seconds |
| Started | Jul 25 07:36:56 PM PDT 24 |
| Finished | Jul 25 07:37:46 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-c35c0ba2-b4f5-414b-a795-ef5c88531b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796761823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr .796761823 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2024791597 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 311369431 ps |
| CPU time | 26 seconds |
| Started | Jul 25 07:36:53 PM PDT 24 |
| Finished | Jul 25 07:37:19 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-1b3fc9f9-b5d8-475b-b569-706d3e3994d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024791597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2024791597 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1419414295 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 1891834953 ps |
| CPU time | 65.88 seconds |
| Started | Jul 25 07:36:44 PM PDT 24 |
| Finished | Jul 25 07:37:50 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-f2a8382f-a558-4fab-a53c-5a32edf28a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419414295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1419414295 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.766035887 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 55217357869 ps |
| CPU time | 573.23 seconds |
| Started | Jul 25 07:36:43 PM PDT 24 |
| Finished | Jul 25 07:46:17 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4b3b1e8e-4592-4674-8159-02f49a891ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766035887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.766035887 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2929836365 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 31538338564 ps |
| CPU time | 549.62 seconds |
| Started | Jul 25 07:36:48 PM PDT 24 |
| Finished | Jul 25 07:45:58 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-c278c3a0-4236-4604-ab58-0f79ea453297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929836365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2929836365 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1621637219 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 181382371 ps |
| CPU time | 17.73 seconds |
| Started | Jul 25 07:38:22 PM PDT 24 |
| Finished | Jul 25 07:38:39 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-5a4a6fed-14b0-4d35-ba95-d13bd03c011c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621637219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1621637219 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.4052118404 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 2371060085 ps |
| CPU time | 73.21 seconds |
| Started | Jul 25 07:36:58 PM PDT 24 |
| Finished | Jul 25 07:38:11 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-2d392f9f-208f-4798-8924-680ae0dff9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052118404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4052118404 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.40890407 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 231400129 ps |
| CPU time | 9.35 seconds |
| Started | Jul 25 07:36:43 PM PDT 24 |
| Finished | Jul 25 07:36:53 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-34264585-f982-4bca-9d00-f73714527cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.40890407 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1874708454 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 7202560208 ps |
| CPU time | 75.57 seconds |
| Started | Jul 25 07:36:44 PM PDT 24 |
| Finished | Jul 25 07:38:00 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-e88b4cb7-a84b-4bb1-a132-04c097986147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874708454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1874708454 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2041981377 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 5034350694 ps |
| CPU time | 85.89 seconds |
| Started | Jul 25 07:36:44 PM PDT 24 |
| Finished | Jul 25 07:38:10 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-031fb272-4203-4053-acd3-9e5b469e4c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041981377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2041981377 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.178785571 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 47209553 ps |
| CPU time | 6.14 seconds |
| Started | Jul 25 07:36:45 PM PDT 24 |
| Finished | Jul 25 07:36:52 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-ead1f7a6-8155-4348-8a78-b8502cc0bdbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178785571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays .178785571 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.1261962879 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 14643010979 ps |
| CPU time | 500.62 seconds |
| Started | Jul 25 07:36:54 PM PDT 24 |
| Finished | Jul 25 07:45:15 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-07ec46ac-18f2-4c1f-abb0-5b14687160dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261962879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1261962879 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3573082646 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 6169709096 ps |
| CPU time | 178.4 seconds |
| Started | Jul 25 07:36:54 PM PDT 24 |
| Finished | Jul 25 07:39:53 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-1fffaa34-982e-4647-bb7c-f2f1c9a3e798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573082646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3573082646 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1334919586 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 2828876002 ps |
| CPU time | 123.84 seconds |
| Started | Jul 25 07:36:54 PM PDT 24 |
| Finished | Jul 25 07:38:58 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-3f7fb4b4-c0b6-4176-ac84-7b2eff5ca7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334919586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1334919586 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3304903520 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 4893467857 ps |
| CPU time | 346.86 seconds |
| Started | Jul 25 07:36:53 PM PDT 24 |
| Finished | Jul 25 07:42:40 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-32624584-00c3-41a2-b4cc-a13b1b1783fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304903520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3304903520 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.45136590 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 244920758 ps |
| CPU time | 12.84 seconds |
| Started | Jul 25 07:36:54 PM PDT 24 |
| Finished | Jul 25 07:37:07 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-b290f71f-5d14-4c34-a8cc-aac885d7e9b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45136590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.45136590 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.2242035962 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 58527964808 ps |
| CPU time | 10023.2 seconds |
| Started | Jul 25 07:26:36 PM PDT 24 |
| Finished | Jul 25 10:13:40 PM PDT 24 |
| Peak memory | 639640 kb |
| Host | smart-e5c68d29-a24d-4b79-8464-ac2af1159969 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242035962 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.2242035962 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1102092534 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 4682439592 ps |
| CPU time | 428.32 seconds |
| Started | Jul 25 07:26:25 PM PDT 24 |
| Finished | Jul 25 07:33:33 PM PDT 24 |
| Peak memory | 592520 kb |
| Host | smart-01b5e0cf-8be1-40fc-b037-75ccd45746dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102092534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1102092534 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3415093690 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4776870100 ps |
| CPU time | 229.86 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:31:39 PM PDT 24 |
| Peak memory | 661228 kb |
| Host | smart-fb41e07e-4688-4001-9a6a-f06580fa00e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415093690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3415093690 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3698905670 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 7432348110 ps |
| CPU time | 489.69 seconds |
| Started | Jul 25 07:27:54 PM PDT 24 |
| Finished | Jul 25 07:36:03 PM PDT 24 |
| Peak memory | 639276 kb |
| Host | smart-266c68b0-fed2-4f97-bb7e-6a6bdcb1dd4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698905670 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.3698905670 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1815170582 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 4819203992 ps |
| CPU time | 396.31 seconds |
| Started | Jul 25 07:27:51 PM PDT 24 |
| Finished | Jul 25 07:34:27 PM PDT 24 |
| Peak memory | 597668 kb |
| Host | smart-03e7f751-e60e-4ee7-937f-48f591e64559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815170582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1815170582 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1463122393 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 15801162007 ps |
| CPU time | 1950.93 seconds |
| Started | Jul 25 07:26:34 PM PDT 24 |
| Finished | Jul 25 07:59:06 PM PDT 24 |
| Peak memory | 592936 kb |
| Host | smart-fcf4354c-2d70-451b-b65e-80453fbd1446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463122393 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1463122393 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.854705002 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3344965404 ps |
| CPU time | 129.94 seconds |
| Started | Jul 25 07:26:37 PM PDT 24 |
| Finished | Jul 25 07:28:47 PM PDT 24 |
| Peak memory | 603352 kb |
| Host | smart-5cfb6b2b-6ddb-4418-b13c-e0c9c9aa102e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854705002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.854705002 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1518348307 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 749257208 ps |
| CPU time | 42.63 seconds |
| Started | Jul 25 07:27:35 PM PDT 24 |
| Finished | Jul 25 07:28:18 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ac59d309-c5a0-4734-bad8-150896ca0db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518348307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1518348307 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2333148362 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 144411058422 ps |
| CPU time | 2624.75 seconds |
| Started | Jul 25 07:27:34 PM PDT 24 |
| Finished | Jul 25 08:11:19 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-e05f03b0-69ff-44cf-a19b-5f0dc1bff9a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333148362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2333148362 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3962566680 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 1215391567 ps |
| CPU time | 49.31 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:28:38 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ff392ed7-77d1-4abe-ba3a-a23165288315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962566680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3962566680 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.503943719 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 1243079963 ps |
| CPU time | 41.55 seconds |
| Started | Jul 25 07:36:08 PM PDT 24 |
| Finished | Jul 25 07:36:49 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b433e7f6-4248-4b8b-8cf9-f30e79ff33ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503943719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.503943719 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.2496854691 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2333311341 ps |
| CPU time | 95.99 seconds |
| Started | Jul 25 07:26:58 PM PDT 24 |
| Finished | Jul 25 07:28:34 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e1dabe54-17bb-487e-be4d-a103c9631727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496854691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2496854691 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3432858997 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 23299414997 ps |
| CPU time | 239.01 seconds |
| Started | Jul 25 07:27:34 PM PDT 24 |
| Finished | Jul 25 07:31:33 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-fcfb099f-5554-4f8b-88bc-8c472bac6386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432858997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3432858997 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.699451026 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 16116296505 ps |
| CPU time | 283.61 seconds |
| Started | Jul 25 07:27:36 PM PDT 24 |
| Finished | Jul 25 07:32:20 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-c2ca6c53-52fa-478c-b711-9544b2652f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699451026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.699451026 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.200181623 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 283719413 ps |
| CPU time | 26.82 seconds |
| Started | Jul 25 07:26:57 PM PDT 24 |
| Finished | Jul 25 07:27:24 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5d5fca54-e443-4a31-9df5-900b425485de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200181623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay s.200181623 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.841956065 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 285293529 ps |
| CPU time | 20.74 seconds |
| Started | Jul 25 07:27:36 PM PDT 24 |
| Finished | Jul 25 07:27:57 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-111a4b39-56a7-4da2-b7cc-5bdd136ad210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841956065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.841956065 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.2694309192 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 232095127 ps |
| CPU time | 9.75 seconds |
| Started | Jul 25 07:26:42 PM PDT 24 |
| Finished | Jul 25 07:26:52 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-4976b931-3af0-44fe-8b06-1cb4247c54a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694309192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2694309192 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.852101891 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 8150382334 ps |
| CPU time | 88.08 seconds |
| Started | Jul 25 07:26:42 PM PDT 24 |
| Finished | Jul 25 07:28:11 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-46f66355-4d8c-46bb-bcb6-c23669789e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852101891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.852101891 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1132996260 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 3744526775 ps |
| CPU time | 68.94 seconds |
| Started | Jul 25 07:26:57 PM PDT 24 |
| Finished | Jul 25 07:28:06 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-635d817d-cb2c-4a06-9c7c-bb0678399057 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132996260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1132996260 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1199444784 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 37906580 ps |
| CPU time | 6.02 seconds |
| Started | Jul 25 07:26:43 PM PDT 24 |
| Finished | Jul 25 07:26:49 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-59456448-f27c-4768-9c8c-72acd537f3eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199444784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1199444784 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.309091691 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 7862528601 ps |
| CPU time | 317.85 seconds |
| Started | Jul 25 07:27:51 PM PDT 24 |
| Finished | Jul 25 07:33:09 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-d93cd2e4-7996-4aa9-93fc-a15e824dcf4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309091691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.309091691 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3762085976 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 7986873402 ps |
| CPU time | 283.55 seconds |
| Started | Jul 25 07:27:54 PM PDT 24 |
| Finished | Jul 25 07:32:38 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-b7ceccbe-4d95-4b5c-a5a7-ae889b316167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762085976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3762085976 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.605032309 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 293682172 ps |
| CPU time | 126.93 seconds |
| Started | Jul 25 07:27:48 PM PDT 24 |
| Finished | Jul 25 07:29:55 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-9dbf6096-bb16-4a18-bf5b-6484be1b2aeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605032309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w ith_rand_reset.605032309 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1031023703 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 9792101704 ps |
| CPU time | 520.45 seconds |
| Started | Jul 25 07:27:52 PM PDT 24 |
| Finished | Jul 25 07:36:32 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-648c15f7-bc53-4483-9412-f0badeb6a320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031023703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1031023703 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.778534957 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 24520964 ps |
| CPU time | 5.09 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:27:54 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-b01c07c6-04b6-482b-a47e-3f6c7d3a9d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778534957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.778534957 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.1265571999 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 570143242 ps |
| CPU time | 23.38 seconds |
| Started | Jul 25 07:37:09 PM PDT 24 |
| Finished | Jul 25 07:37:33 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-7d8a9915-2fea-4bad-8d6e-79ec8fadf5e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265571999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .1265571999 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2488708016 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 72714273492 ps |
| CPU time | 1180.93 seconds |
| Started | Jul 25 07:37:07 PM PDT 24 |
| Finished | Jul 25 07:56:49 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f068edc1-5586-40fa-ac0a-4038687b6799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488708016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2488708016 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.1227200823 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 1073155258 ps |
| CPU time | 42.76 seconds |
| Started | Jul 25 07:37:07 PM PDT 24 |
| Finished | Jul 25 07:37:50 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-4d424d4b-a195-493e-98c0-78014eb99698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227200823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.1227200823 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.3419679655 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 941929646 ps |
| CPU time | 32.8 seconds |
| Started | Jul 25 07:37:07 PM PDT 24 |
| Finished | Jul 25 07:37:40 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-71bf6ac6-f6c4-4afb-ab30-250fbc260408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419679655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3419679655 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.689822502 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 2164342810 ps |
| CPU time | 78.15 seconds |
| Started | Jul 25 07:37:17 PM PDT 24 |
| Finished | Jul 25 07:38:35 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-55c60dc3-d5ac-4ca7-936f-1a9c91f27feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689822502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.689822502 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.488499877 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 89991361505 ps |
| CPU time | 1003.92 seconds |
| Started | Jul 25 07:37:08 PM PDT 24 |
| Finished | Jul 25 07:53:52 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d1fbc7c1-0226-44bd-bc74-fcce8c577575 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488499877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.488499877 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.372530135 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 12966333093 ps |
| CPU time | 222.45 seconds |
| Started | Jul 25 07:37:06 PM PDT 24 |
| Finished | Jul 25 07:40:49 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-f41ada8c-b2e8-4a8a-8606-a71cb9c7eecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372530135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.372530135 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3266415367 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 507210726 ps |
| CPU time | 45.44 seconds |
| Started | Jul 25 07:37:05 PM PDT 24 |
| Finished | Jul 25 07:37:50 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-a405223d-4459-485e-bda8-26ed557ab83b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266415367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3266415367 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.361991663 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 178406085 ps |
| CPU time | 16.58 seconds |
| Started | Jul 25 07:37:07 PM PDT 24 |
| Finished | Jul 25 07:37:24 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-1f318c98-e43e-4094-b2d8-715ea957b9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361991663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.361991663 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.3503557331 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 191864467 ps |
| CPU time | 9.12 seconds |
| Started | Jul 25 07:36:54 PM PDT 24 |
| Finished | Jul 25 07:37:03 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-caa269f6-232b-4ba6-a0ba-3e0400be9b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503557331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3503557331 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1020568491 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 7112886739 ps |
| CPU time | 76.49 seconds |
| Started | Jul 25 07:36:58 PM PDT 24 |
| Finished | Jul 25 07:38:15 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-3a65e5f4-fb5e-4c7e-8367-2b93076a8e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020568491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1020568491 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.834326881 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 5067586640 ps |
| CPU time | 86.79 seconds |
| Started | Jul 25 07:37:05 PM PDT 24 |
| Finished | Jul 25 07:38:32 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-4fe38ce6-6641-455e-b60f-78f38fd2dc80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834326881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.834326881 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2520097776 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 43413619 ps |
| CPU time | 5.93 seconds |
| Started | Jul 25 07:36:52 PM PDT 24 |
| Finished | Jul 25 07:36:59 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-716336a1-3830-4600-88d7-52caeddfd3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520097776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2520097776 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2651276208 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 1304446498 ps |
| CPU time | 104.77 seconds |
| Started | Jul 25 07:37:08 PM PDT 24 |
| Finished | Jul 25 07:38:53 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-bddf3d12-3b26-4619-ac9d-5d3fa9a64ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651276208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2651276208 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2508979818 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 3138127538 ps |
| CPU time | 232.29 seconds |
| Started | Jul 25 07:37:09 PM PDT 24 |
| Finished | Jul 25 07:41:01 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-ee9287b8-8933-435b-be4d-cad07eb2a306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508979818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2508979818 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2185254396 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 189530685 ps |
| CPU time | 83.02 seconds |
| Started | Jul 25 07:37:09 PM PDT 24 |
| Finished | Jul 25 07:38:32 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-bd9fe52c-7fbb-49f0-988a-3ec57eedaa3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185254396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.2185254396 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.882319692 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 4029810178 ps |
| CPU time | 491.2 seconds |
| Started | Jul 25 07:37:06 PM PDT 24 |
| Finished | Jul 25 07:45:18 PM PDT 24 |
| Peak memory | 577700 kb |
| Host | smart-77219563-bbe2-49af-8e61-3ece090adc58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882319692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_reset_error.882319692 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1815681948 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 929030006 ps |
| CPU time | 37.58 seconds |
| Started | Jul 25 07:37:07 PM PDT 24 |
| Finished | Jul 25 07:37:45 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-22810871-2c86-4248-9f88-37c910528880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815681948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1815681948 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1338063240 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 589224502 ps |
| CPU time | 25.45 seconds |
| Started | Jul 25 07:37:33 PM PDT 24 |
| Finished | Jul 25 07:37:58 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-33e1ed22-7128-4ffa-b171-64d33f91d059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338063240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1338063240 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.991731322 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 27553957404 ps |
| CPU time | 482.49 seconds |
| Started | Jul 25 07:37:31 PM PDT 24 |
| Finished | Jul 25 07:45:34 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-a559b48a-7b2c-41b7-87a0-2bb5faecc030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991731322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.991731322 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.969356361 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 94615824 ps |
| CPU time | 6.92 seconds |
| Started | Jul 25 07:37:31 PM PDT 24 |
| Finished | Jul 25 07:37:38 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c2614fe2-21f3-4759-9df2-93a11208653e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969356361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr .969356361 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3391571364 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 1148374807 ps |
| CPU time | 39.94 seconds |
| Started | Jul 25 07:37:32 PM PDT 24 |
| Finished | Jul 25 07:38:12 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-128178f3-f815-47d9-99ee-7a2a1017cce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391571364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3391571364 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.1042416377 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1808375280 ps |
| CPU time | 62.02 seconds |
| Started | Jul 25 07:37:07 PM PDT 24 |
| Finished | Jul 25 07:38:09 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-e1b52b46-5c76-42fc-8047-16b3d939720b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042416377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1042416377 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.395935427 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 92665217244 ps |
| CPU time | 869.01 seconds |
| Started | Jul 25 07:37:33 PM PDT 24 |
| Finished | Jul 25 07:52:03 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-29a86318-0474-43cd-8dad-4ff2d7dfc0dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395935427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.395935427 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.157239138 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 30036312820 ps |
| CPU time | 544.16 seconds |
| Started | Jul 25 07:37:32 PM PDT 24 |
| Finished | Jul 25 07:46:36 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-0b999514-c6bc-4ca6-a287-05c24d5ea8c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157239138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.157239138 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.710700399 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 71134229 ps |
| CPU time | 8.68 seconds |
| Started | Jul 25 07:37:33 PM PDT 24 |
| Finished | Jul 25 07:37:42 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-fb683a24-48a5-4c0b-975a-06bb744ab142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710700399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.710700399 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1759731358 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 143610853 ps |
| CPU time | 13.22 seconds |
| Started | Jul 25 07:37:35 PM PDT 24 |
| Finished | Jul 25 07:37:48 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-d335f30f-4f02-43bd-bf80-1c00af9d04a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759731358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1759731358 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.2029045571 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 50940205 ps |
| CPU time | 6.16 seconds |
| Started | Jul 25 07:37:08 PM PDT 24 |
| Finished | Jul 25 07:37:15 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-31d2011b-e976-427b-9c62-3472b5d7fa57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029045571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2029045571 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2688531873 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 9278524418 ps |
| CPU time | 91.51 seconds |
| Started | Jul 25 07:37:48 PM PDT 24 |
| Finished | Jul 25 07:39:19 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-71445243-764d-416f-a43e-e796864db768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688531873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2688531873 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2305656350 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 4659716573 ps |
| CPU time | 76.76 seconds |
| Started | Jul 25 07:37:17 PM PDT 24 |
| Finished | Jul 25 07:38:33 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-c83ab7db-b44c-420f-9276-3b258077c30f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305656350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.2305656350 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2933381385 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 46553822 ps |
| CPU time | 6.92 seconds |
| Started | Jul 25 07:37:08 PM PDT 24 |
| Finished | Jul 25 07:37:15 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-1e688f2b-49d4-4716-b6a9-a5c101c4e89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933381385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.2933381385 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1436146932 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 4142799351 ps |
| CPU time | 344.22 seconds |
| Started | Jul 25 07:37:30 PM PDT 24 |
| Finished | Jul 25 07:43:15 PM PDT 24 |
| Peak memory | 576752 kb |
| Host | smart-4064badd-a89d-48bf-a277-6d6af8d99559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436146932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1436146932 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3791988111 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 1561295567 ps |
| CPU time | 124.93 seconds |
| Started | Jul 25 07:37:33 PM PDT 24 |
| Finished | Jul 25 07:39:38 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-75c1e103-99bb-4000-9101-c438686ca2bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791988111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3791988111 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3256320991 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 450075242 ps |
| CPU time | 112.01 seconds |
| Started | Jul 25 07:37:32 PM PDT 24 |
| Finished | Jul 25 07:39:24 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-5870245d-8d06-49ab-b0af-6bbe88971309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256320991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.3256320991 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3186648300 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 5123643357 ps |
| CPU time | 428.45 seconds |
| Started | Jul 25 07:37:34 PM PDT 24 |
| Finished | Jul 25 07:44:42 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-8e635b05-e27b-4aac-bccc-d83729397620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186648300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3186648300 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1120583767 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 315655729 ps |
| CPU time | 43.43 seconds |
| Started | Jul 25 07:37:31 PM PDT 24 |
| Finished | Jul 25 07:38:14 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-dc76aae7-54b6-435e-8cdf-6049b78e7704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120583767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1120583767 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.1697644306 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 1134915588 ps |
| CPU time | 68.98 seconds |
| Started | Jul 25 07:38:09 PM PDT 24 |
| Finished | Jul 25 07:39:18 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-d9dd35c7-23c0-42ca-9c57-4cbd5251a933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697644306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .1697644306 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1189674714 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 53994171966 ps |
| CPU time | 937.08 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:53:48 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-855be72f-b37c-4c0a-ab8a-7435b850d9e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189674714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1189674714 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1894571099 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 796013361 ps |
| CPU time | 28.53 seconds |
| Started | Jul 25 07:38:14 PM PDT 24 |
| Finished | Jul 25 07:38:43 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-dcbb27d8-f088-4e13-b4ac-e6b57c2a5901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894571099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1894571099 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.29134957 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 419044820 ps |
| CPU time | 30.01 seconds |
| Started | Jul 25 07:38:11 PM PDT 24 |
| Finished | Jul 25 07:38:41 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-1276e9eb-7040-4976-8370-34488addfba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.29134957 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3529071956 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2688936770 ps |
| CPU time | 84.55 seconds |
| Started | Jul 25 07:43:01 PM PDT 24 |
| Finished | Jul 25 07:44:26 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-6b7d04e0-a8a9-4eca-8728-0846c8e27f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529071956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3529071956 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.1838538680 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 45139400753 ps |
| CPU time | 485.32 seconds |
| Started | Jul 25 07:38:14 PM PDT 24 |
| Finished | Jul 25 07:46:20 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-ffc93845-ba11-4ae0-9a3e-c47c5ecdb13c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838538680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1838538680 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2890401994 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 22052604215 ps |
| CPU time | 354.86 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:44:05 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-c1417779-692f-482b-9794-30b2252fb265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890401994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2890401994 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3355313213 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 297135862 ps |
| CPU time | 26.64 seconds |
| Started | Jul 25 07:38:13 PM PDT 24 |
| Finished | Jul 25 07:38:39 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-79ddba91-86a8-4b59-96e2-4bd195e0975c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355313213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.3355313213 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.3038963139 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 93077697 ps |
| CPU time | 9.32 seconds |
| Started | Jul 25 07:38:09 PM PDT 24 |
| Finished | Jul 25 07:38:19 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-f3bd3c4a-ceda-4632-9746-86c32f768ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038963139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3038963139 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2373016383 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 50975833 ps |
| CPU time | 6.39 seconds |
| Started | Jul 25 07:37:34 PM PDT 24 |
| Finished | Jul 25 07:37:40 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-c06bed9d-d948-48d6-9551-8b848cecce1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373016383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2373016383 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2315500961 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 6417171463 ps |
| CPU time | 64.8 seconds |
| Started | Jul 25 07:38:14 PM PDT 24 |
| Finished | Jul 25 07:39:20 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-8f385003-5153-4e1f-9dbd-d511f6cbc336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315500961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2315500961 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.405773242 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 5019081301 ps |
| CPU time | 83.07 seconds |
| Started | Jul 25 07:38:12 PM PDT 24 |
| Finished | Jul 25 07:39:35 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-b6d97021-13b6-4a59-9908-c6e90629b5a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405773242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.405773242 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.1395303030 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 46856887 ps |
| CPU time | 6.7 seconds |
| Started | Jul 25 07:37:31 PM PDT 24 |
| Finished | Jul 25 07:37:37 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-f80320f0-fdc6-48fb-9dcd-a0572852480d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395303030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.1395303030 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1567064599 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 15205274185 ps |
| CPU time | 574.96 seconds |
| Started | Jul 25 07:38:11 PM PDT 24 |
| Finished | Jul 25 07:47:46 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-6548ea65-e42c-42cb-acc3-7d9da3467441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567064599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1567064599 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2057129040 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 9727646458 ps |
| CPU time | 350.56 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:44:01 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-d091d63d-9499-40c6-a8b2-6d0d11bc2bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057129040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2057129040 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3264154469 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 19278739433 ps |
| CPU time | 823.62 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:51:54 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-dac61bf6-2024-485e-9e80-91b795dca986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264154469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3264154469 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.95135315 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 353710591 ps |
| CPU time | 102.63 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:39:53 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-3b72ee2a-ffdd-4de8-94cd-7bda9a0ed7a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95135315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_reset_error.95135315 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2955407299 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 732591661 ps |
| CPU time | 30.54 seconds |
| Started | Jul 25 07:38:13 PM PDT 24 |
| Finished | Jul 25 07:38:44 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-0175d33d-ffd6-488c-bb2d-cc72abc3c4da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955407299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2955407299 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2651395037 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3219339432 ps |
| CPU time | 125.59 seconds |
| Started | Jul 25 07:38:12 PM PDT 24 |
| Finished | Jul 25 07:40:18 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-1fa1b91b-e17f-420a-a987-76005bdf32e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651395037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2651395037 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1772502788 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 55134441997 ps |
| CPU time | 984.59 seconds |
| Started | Jul 25 07:38:14 PM PDT 24 |
| Finished | Jul 25 07:54:39 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-f0043a29-09d0-4f08-b528-8acc19b1818b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772502788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1772502788 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3666738107 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 612835902 ps |
| CPU time | 24.47 seconds |
| Started | Jul 25 07:38:32 PM PDT 24 |
| Finished | Jul 25 07:38:57 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-1a25a19d-a1d2-4e9b-8d1b-f7688b2e9f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666738107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3666738107 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3945482413 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 190638772 ps |
| CPU time | 16.19 seconds |
| Started | Jul 25 07:38:34 PM PDT 24 |
| Finished | Jul 25 07:38:50 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-846bf200-f3df-47cf-8b01-39b8cda4b27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945482413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3945482413 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.3507300959 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 106939911 ps |
| CPU time | 7.01 seconds |
| Started | Jul 25 07:38:11 PM PDT 24 |
| Finished | Jul 25 07:38:18 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-57ee8c46-7db7-4a4a-a4ba-9c6b090ae194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507300959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3507300959 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.128947957 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 89939727196 ps |
| CPU time | 951.85 seconds |
| Started | Jul 25 07:38:12 PM PDT 24 |
| Finished | Jul 25 07:54:04 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-01e8cbfb-8d30-4405-8218-42d6cf5eb942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128947957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.128947957 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2777821511 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 53231053129 ps |
| CPU time | 861.22 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:52:31 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-ec3a6d1f-17a1-48c1-acf1-198913944c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777821511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2777821511 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3067508221 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 582346511 ps |
| CPU time | 46.35 seconds |
| Started | Jul 25 07:38:09 PM PDT 24 |
| Finished | Jul 25 07:38:56 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-9ac766d2-7fbd-46bb-ad6e-c426d6e3d5f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067508221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3067508221 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.1497345106 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 1542791401 ps |
| CPU time | 49.05 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:38:59 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-58cf9186-29c7-4681-bd03-2652379c9f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497345106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1497345106 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1459223023 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 227527473 ps |
| CPU time | 10.16 seconds |
| Started | Jul 25 07:38:10 PM PDT 24 |
| Finished | Jul 25 07:38:20 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-5c5b6d0a-e97f-4866-bdfa-f8cda60d8cf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459223023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1459223023 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.315911150 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 9050416413 ps |
| CPU time | 97.69 seconds |
| Started | Jul 25 07:38:14 PM PDT 24 |
| Finished | Jul 25 07:39:52 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-29868880-cc16-4443-9f4b-5c696787a13b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315911150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.315911150 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.529904274 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 6537638885 ps |
| CPU time | 116.4 seconds |
| Started | Jul 25 07:38:09 PM PDT 24 |
| Finished | Jul 25 07:40:06 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-61de750f-798b-4e53-b494-3149d6c447de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529904274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.529904274 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2662301541 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 48503177 ps |
| CPU time | 6.62 seconds |
| Started | Jul 25 07:38:12 PM PDT 24 |
| Finished | Jul 25 07:38:19 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-b1ebd12d-de0c-4400-aed0-77cf0db422f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662301541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2662301541 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.544077423 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 13107909499 ps |
| CPU time | 518.59 seconds |
| Started | Jul 25 07:38:34 PM PDT 24 |
| Finished | Jul 25 07:47:13 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-ee3eb402-4635-4263-b742-66ac82ca3b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544077423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.544077423 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3793991587 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 518815528 ps |
| CPU time | 174.94 seconds |
| Started | Jul 25 07:38:32 PM PDT 24 |
| Finished | Jul 25 07:41:27 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-903ae121-fb92-44e6-b6e6-bfe998bede4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793991587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3793991587 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3690984767 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 499351755 ps |
| CPU time | 127.72 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:40:37 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-88794bbe-3629-44fa-9124-162ed4250cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690984767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3690984767 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.78350522 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 469972192 ps |
| CPU time | 19.35 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:38:49 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-ebd46a4d-a63e-4abd-ad65-9a802825dfbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78350522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.78350522 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1196776936 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 466542458 ps |
| CPU time | 40.91 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:39:10 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-275bd951-e3c1-4ca9-b596-48fcfcc1dcf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196776936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1196776936 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2026979289 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 93079053984 ps |
| CPU time | 1609.38 seconds |
| Started | Jul 25 07:38:30 PM PDT 24 |
| Finished | Jul 25 08:05:21 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-904dcd18-fde0-4475-94de-867a6b4ffe48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026979289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2026979289 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3919239222 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 1272516404 ps |
| CPU time | 45.41 seconds |
| Started | Jul 25 07:38:34 PM PDT 24 |
| Finished | Jul 25 07:39:20 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a5a031aa-c3f5-4a51-b6f4-a3850686ec11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919239222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3919239222 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2558195746 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 1004944963 ps |
| CPU time | 28.7 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:38:58 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-20c5bc1c-baa8-4b7f-891e-551059f7361f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558195746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2558195746 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.4059995296 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1621302232 ps |
| CPU time | 61.16 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:39:31 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-c4566d9b-8f57-4907-a045-7123ff8985d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059995296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.4059995296 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.608298342 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 34601609029 ps |
| CPU time | 358.4 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:44:26 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-ecc6e0a3-574e-4fdf-89cb-9a23b7da08e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608298342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.608298342 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2474801999 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 58155024300 ps |
| CPU time | 967.24 seconds |
| Started | Jul 25 07:38:30 PM PDT 24 |
| Finished | Jul 25 07:54:37 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-73289783-0431-4153-9ad1-80eaf24bf623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474801999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2474801999 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2255953238 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 376610330 ps |
| CPU time | 29.27 seconds |
| Started | Jul 25 07:38:31 PM PDT 24 |
| Finished | Jul 25 07:39:00 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-24641107-0656-4502-ab05-c9ec220f7015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255953238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2255953238 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3035505956 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 258827899 ps |
| CPU time | 18.42 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:38:47 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-290cc4ff-41b3-43a1-a62f-2ddb5eef9223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035505956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3035505956 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.2234986797 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 52878605 ps |
| CPU time | 6.4 seconds |
| Started | Jul 25 07:38:31 PM PDT 24 |
| Finished | Jul 25 07:38:37 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-f124134f-e424-4fa3-866d-0e542b493130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234986797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2234986797 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2325268650 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 7420069369 ps |
| CPU time | 74.1 seconds |
| Started | Jul 25 07:38:26 PM PDT 24 |
| Finished | Jul 25 07:39:40 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-69ee4583-6c32-4445-86a2-591514ff2386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325268650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2325268650 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1909720978 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 6064610826 ps |
| CPU time | 99.68 seconds |
| Started | Jul 25 07:38:27 PM PDT 24 |
| Finished | Jul 25 07:40:07 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-33b5859a-9deb-4b0a-8f77-dc9be754b2bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909720978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1909720978 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.412216217 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 45205537 ps |
| CPU time | 5.58 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:38:34 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-0703ab26-05fe-4ce9-96d2-7e64b3d54df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412216217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays .412216217 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1566365995 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 8678553086 ps |
| CPU time | 319.24 seconds |
| Started | Jul 25 07:38:31 PM PDT 24 |
| Finished | Jul 25 07:43:50 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-bf8c9ae9-dd2a-4b71-ac79-942c71bae787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566365995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1566365995 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.4021874893 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 1416482551 ps |
| CPU time | 65.42 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:39:33 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-a252cb1d-1e9c-4885-a00e-14b2960c8d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021874893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.4021874893 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3828857088 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 8104995701 ps |
| CPU time | 377.84 seconds |
| Started | Jul 25 07:38:27 PM PDT 24 |
| Finished | Jul 25 07:44:45 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-26d687ad-6e09-4beb-80b4-f181ed057b86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828857088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.3828857088 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2195114433 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 175186835 ps |
| CPU time | 9.44 seconds |
| Started | Jul 25 07:38:34 PM PDT 24 |
| Finished | Jul 25 07:38:43 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-cc2ad230-6dfb-4059-875e-42791e843f97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195114433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2195114433 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3599800641 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3011901660 ps |
| CPU time | 106.87 seconds |
| Started | Jul 25 07:38:27 PM PDT 24 |
| Finished | Jul 25 07:40:14 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-b47acf69-3a10-4a52-a150-18f76865d2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599800641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3599800641 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1004500043 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 96966970342 ps |
| CPU time | 1703.37 seconds |
| Started | Jul 25 07:38:27 PM PDT 24 |
| Finished | Jul 25 08:06:51 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-f35a13b1-ec54-4911-89b6-9bcd9b80e116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004500043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.1004500043 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.265571457 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 995261117 ps |
| CPU time | 37.99 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:39:07 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-242adb77-bcf5-4677-8539-ccb56868f9e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265571457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr .265571457 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.588604391 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 2080546340 ps |
| CPU time | 79.44 seconds |
| Started | Jul 25 07:38:27 PM PDT 24 |
| Finished | Jul 25 07:39:46 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-97d950fe-0534-4d53-82ac-16771732fae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588604391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.588604391 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.3901011878 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 272022007 ps |
| CPU time | 26.84 seconds |
| Started | Jul 25 07:38:30 PM PDT 24 |
| Finished | Jul 25 07:38:57 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-08a68f7e-cf91-4066-96de-891ed0aa9cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901011878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3901011878 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2582752935 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 51605185981 ps |
| CPU time | 510.35 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:47:00 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-6f81e0a5-fff1-487a-a22f-751eeb908850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582752935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.2582752935 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1060605334 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 14115655293 ps |
| CPU time | 239.56 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:42:29 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-4f571ea4-451a-4aab-a174-b98190e6e669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060605334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1060605334 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2675121088 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 548874246 ps |
| CPU time | 45.19 seconds |
| Started | Jul 25 07:38:32 PM PDT 24 |
| Finished | Jul 25 07:39:17 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-1177089e-45bf-4766-b27a-c976810e0113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675121088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2675121088 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.2327107518 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 419948186 ps |
| CPU time | 32.46 seconds |
| Started | Jul 25 07:38:34 PM PDT 24 |
| Finished | Jul 25 07:39:07 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-918b39bc-0ab6-4dcb-b9d5-47a281f008f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327107518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2327107518 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.2073659332 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 195513429 ps |
| CPU time | 8.74 seconds |
| Started | Jul 25 07:38:31 PM PDT 24 |
| Finished | Jul 25 07:38:39 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-26256a78-5b8d-49d7-815a-888cc598aad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073659332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2073659332 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2216706197 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 7259274277 ps |
| CPU time | 76.39 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:39:45 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-158a0477-0c89-4c11-a25b-6262ef061474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216706197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2216706197 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.257890441 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 5456000059 ps |
| CPU time | 87.06 seconds |
| Started | Jul 25 07:38:30 PM PDT 24 |
| Finished | Jul 25 07:39:57 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-200d3b5a-9771-4c5e-9934-7707e14c43a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257890441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.257890441 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3010249500 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 45996260 ps |
| CPU time | 6.29 seconds |
| Started | Jul 25 07:38:28 PM PDT 24 |
| Finished | Jul 25 07:38:34 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-707f7a59-4ca9-4a6f-b44a-5d143228cf5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010249500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.3010249500 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3428696422 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 3257318507 ps |
| CPU time | 127.4 seconds |
| Started | Jul 25 07:38:29 PM PDT 24 |
| Finished | Jul 25 07:40:37 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-25067fb0-faa3-4011-acf7-52cc6402a1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428696422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3428696422 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2789986798 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 367817138 ps |
| CPU time | 34 seconds |
| Started | Jul 25 07:38:36 PM PDT 24 |
| Finished | Jul 25 07:39:11 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-6fb5613c-5337-4fb1-9894-3c6760d15e74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789986798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2789986798 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3701789380 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 1198452187 ps |
| CPU time | 223.13 seconds |
| Started | Jul 25 07:38:44 PM PDT 24 |
| Finished | Jul 25 07:42:27 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-a2c7a083-a461-49b3-aa68-9aca085971fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701789380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3701789380 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1290445712 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 211510146 ps |
| CPU time | 24.31 seconds |
| Started | Jul 25 07:38:31 PM PDT 24 |
| Finished | Jul 25 07:38:56 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8f505bdb-ad43-4202-a2bc-91ad39eed22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290445712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1290445712 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.4019614381 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 625207783 ps |
| CPU time | 27.3 seconds |
| Started | Jul 25 07:38:46 PM PDT 24 |
| Finished | Jul 25 07:39:13 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-378ac92f-7b6b-48a3-b86a-b8c1f010c5aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019614381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .4019614381 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.1052743724 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 106403822265 ps |
| CPU time | 1936.52 seconds |
| Started | Jul 25 07:38:37 PM PDT 24 |
| Finished | Jul 25 08:10:54 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-53fe536d-2a8e-42a6-ad75-015f558b419c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052743724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.1052743724 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3599502003 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 1139732095 ps |
| CPU time | 48.55 seconds |
| Started | Jul 25 07:38:46 PM PDT 24 |
| Finished | Jul 25 07:39:35 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-a18207ed-7fb3-4638-bc1d-f4983454b97d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599502003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3599502003 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.3654769815 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 606918298 ps |
| CPU time | 48.7 seconds |
| Started | Jul 25 07:38:45 PM PDT 24 |
| Finished | Jul 25 07:39:34 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-13405722-bce2-4f0c-bdd0-33bc174dc06b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654769815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3654769815 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1391462107 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 1858324127 ps |
| CPU time | 73.86 seconds |
| Started | Jul 25 07:38:41 PM PDT 24 |
| Finished | Jul 25 07:39:55 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-a4af1b5b-5ded-4fe0-9a74-931f5906c76c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391462107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1391462107 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1963037229 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 80729843451 ps |
| CPU time | 797.86 seconds |
| Started | Jul 25 07:38:38 PM PDT 24 |
| Finished | Jul 25 07:51:56 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-f77fb764-32fe-4438-9c47-f6da1b1831f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963037229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1963037229 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2709137060 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 15055266409 ps |
| CPU time | 264.84 seconds |
| Started | Jul 25 07:41:51 PM PDT 24 |
| Finished | Jul 25 07:46:16 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-3a1469c8-f219-4ceb-9082-bcd6b205d54c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709137060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2709137060 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1345801400 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 603435910 ps |
| CPU time | 56.61 seconds |
| Started | Jul 25 07:38:43 PM PDT 24 |
| Finished | Jul 25 07:39:39 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-2fba9d25-ecb2-4436-95a3-23c71f13900c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345801400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.1345801400 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.1616525702 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1895001740 ps |
| CPU time | 57.47 seconds |
| Started | Jul 25 07:38:45 PM PDT 24 |
| Finished | Jul 25 07:39:43 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-66cb13ba-45e1-4c29-9081-043dfbd82c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616525702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1616525702 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.2958832700 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 255113257 ps |
| CPU time | 9.25 seconds |
| Started | Jul 25 07:38:37 PM PDT 24 |
| Finished | Jul 25 07:38:46 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-2d6781e7-8ddc-48bd-a6b3-ae699e7db95d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958832700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2958832700 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2712461059 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 8927629572 ps |
| CPU time | 98.22 seconds |
| Started | Jul 25 07:38:45 PM PDT 24 |
| Finished | Jul 25 07:40:23 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-f89cfaa9-1335-4564-a1f3-5aadec9718d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712461059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2712461059 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3955536429 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 5928922456 ps |
| CPU time | 92.85 seconds |
| Started | Jul 25 07:38:36 PM PDT 24 |
| Finished | Jul 25 07:40:10 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-26dfddb0-99f7-48ed-86b2-981ba4fb0f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955536429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3955536429 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2299933513 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 41529247 ps |
| CPU time | 6.28 seconds |
| Started | Jul 25 07:38:45 PM PDT 24 |
| Finished | Jul 25 07:38:51 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-bd3591ca-182d-4e06-8280-48d2da1d1ebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299933513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.2299933513 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.2458991739 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 1357536697 ps |
| CPU time | 105.26 seconds |
| Started | Jul 25 07:38:45 PM PDT 24 |
| Finished | Jul 25 07:40:30 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-0c854f5d-f3ae-47a3-b08e-47210f460f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458991739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2458991739 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2804715191 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 12097971404 ps |
| CPU time | 407.35 seconds |
| Started | Jul 25 07:39:17 PM PDT 24 |
| Finished | Jul 25 07:46:04 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-10dc69eb-6a6f-4d6a-859a-1e4675cee35a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804715191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2804715191 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1496587651 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 5846251132 ps |
| CPU time | 435.62 seconds |
| Started | Jul 25 07:38:38 PM PDT 24 |
| Finished | Jul 25 07:45:54 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-12cd3257-339e-4c46-b294-39ebe8067873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496587651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.1496587651 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2443817637 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 65731348 ps |
| CPU time | 25.26 seconds |
| Started | Jul 25 07:38:51 PM PDT 24 |
| Finished | Jul 25 07:39:16 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-448d9fd7-eeac-491d-b18b-45d0e80ac815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443817637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.2443817637 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.635547163 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 54160991 ps |
| CPU time | 8.56 seconds |
| Started | Jul 25 07:38:46 PM PDT 24 |
| Finished | Jul 25 07:38:55 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-b14cce74-f7e9-44dd-be20-1a0f429b182b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635547163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.635547163 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.613548501 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 721886507 ps |
| CPU time | 35.25 seconds |
| Started | Jul 25 07:38:49 PM PDT 24 |
| Finished | Jul 25 07:39:25 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c94b08c8-50a7-4fc0-bb03-e3a7408a4cb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613548501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device. 613548501 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3187194351 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 96891596859 ps |
| CPU time | 1750.04 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 08:08:10 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-fdcfd83e-d296-422b-a031-68025521e768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187194351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3187194351 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1647049307 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 21962003 ps |
| CPU time | 5.22 seconds |
| Started | Jul 25 07:39:03 PM PDT 24 |
| Finished | Jul 25 07:39:09 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-5f37a478-51f5-4ae1-982c-6252c229bc68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647049307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1647049307 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.898255356 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1160475974 ps |
| CPU time | 42.41 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:39:41 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-f843da22-d857-4b16-93ee-8b94357ab805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898255356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.898255356 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.1305901683 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 1478459307 ps |
| CPU time | 59.53 seconds |
| Started | Jul 25 07:38:50 PM PDT 24 |
| Finished | Jul 25 07:39:50 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-8562bd52-0399-4e96-88c0-79fd5abea084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305901683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1305901683 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.4219505133 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 99664038337 ps |
| CPU time | 1071.97 seconds |
| Started | Jul 25 07:38:49 PM PDT 24 |
| Finished | Jul 25 07:56:42 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-c12c788c-a260-44e7-a307-3de61e4ba035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219505133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.4219505133 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2312471595 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 16108681474 ps |
| CPU time | 276.3 seconds |
| Started | Jul 25 07:38:50 PM PDT 24 |
| Finished | Jul 25 07:43:26 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-63f20386-3272-421f-9858-c5e70e06ef56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312471595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2312471595 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.188332157 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 179614708 ps |
| CPU time | 18.56 seconds |
| Started | Jul 25 07:38:53 PM PDT 24 |
| Finished | Jul 25 07:39:12 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-52ebd9b6-4ead-4bb2-b377-6bf6d93aed2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188332157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_dela ys.188332157 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3582193329 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2701999612 ps |
| CPU time | 80.88 seconds |
| Started | Jul 25 07:39:01 PM PDT 24 |
| Finished | Jul 25 07:40:22 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-2b36b7e4-9900-4b4a-a3b7-a25fe9d38917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582193329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3582193329 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2874056305 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 201348171 ps |
| CPU time | 8.43 seconds |
| Started | Jul 25 07:38:50 PM PDT 24 |
| Finished | Jul 25 07:38:59 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-aba572c7-8b68-4557-897b-9538f102391a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874056305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2874056305 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1123691989 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 6605899102 ps |
| CPU time | 68.52 seconds |
| Started | Jul 25 07:38:45 PM PDT 24 |
| Finished | Jul 25 07:39:54 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-623cd89e-e753-4ab9-88cd-5715c552eb1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123691989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1123691989 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.945409241 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 4748665253 ps |
| CPU time | 81.22 seconds |
| Started | Jul 25 07:38:48 PM PDT 24 |
| Finished | Jul 25 07:40:09 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-dc45b1cc-0e94-464b-9159-cc22cd54ac24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945409241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.945409241 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.261108142 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 48524997 ps |
| CPU time | 6.83 seconds |
| Started | Jul 25 07:38:53 PM PDT 24 |
| Finished | Jul 25 07:39:00 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-a7d653af-2bed-43de-96b9-efb1ddb2861a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261108142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .261108142 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.617813308 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4228057516 ps |
| CPU time | 387.98 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:45:27 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-de0eaa12-ec78-4ca9-bb87-868a9f5753f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617813308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.617813308 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1633826429 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 2152434920 ps |
| CPU time | 174.16 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:41:53 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-3ed1f96b-d15b-4ab7-b9f1-23b165df4b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633826429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1633826429 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3861856557 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 9451522089 ps |
| CPU time | 487.27 seconds |
| Started | Jul 25 07:39:05 PM PDT 24 |
| Finished | Jul 25 07:47:12 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-9c4979ee-91da-4ef2-8178-908cd37730bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861856557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3861856557 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3414048076 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 7076843894 ps |
| CPU time | 596.6 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:48:56 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-d4a80223-bfc6-4284-9bad-4abd206fa7ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414048076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3414048076 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.594797302 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 433285282 ps |
| CPU time | 21.58 seconds |
| Started | Jul 25 07:39:03 PM PDT 24 |
| Finished | Jul 25 07:39:25 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-bb04358b-7044-4b90-a138-f50fa4a4ff2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594797302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.594797302 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.3634479788 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 32518894 ps |
| CPU time | 10.41 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:39:10 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-11eb319f-2f51-4fb3-93bf-72f976c2f5e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634479788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .3634479788 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2724124167 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 35471444216 ps |
| CPU time | 562.46 seconds |
| Started | Jul 25 07:39:01 PM PDT 24 |
| Finished | Jul 25 07:48:23 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-74100af5-f31e-4422-8570-4db6e5fabb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724124167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2724124167 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2725016679 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 709883036 ps |
| CPU time | 27.37 seconds |
| Started | Jul 25 07:39:12 PM PDT 24 |
| Finished | Jul 25 07:39:39 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-709ab923-c5d0-4e3a-87da-5b599cf285c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725016679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2725016679 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.235796103 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 2231951478 ps |
| CPU time | 85.18 seconds |
| Started | Jul 25 07:39:13 PM PDT 24 |
| Finished | Jul 25 07:40:38 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-1ef3d479-1c4b-4bfe-8523-22c6cc81e516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235796103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.235796103 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.4019245586 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 187858650 ps |
| CPU time | 18.42 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:39:18 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-468fcc67-887a-45be-b4d3-85b45c653d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019245586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.4019245586 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1877223675 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 32472080169 ps |
| CPU time | 324.72 seconds |
| Started | Jul 25 07:39:04 PM PDT 24 |
| Finished | Jul 25 07:44:29 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-30b14c93-99c4-47c8-874b-5bf077c4dc5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877223675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1877223675 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.375770718 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 15225766066 ps |
| CPU time | 244.65 seconds |
| Started | Jul 25 07:38:58 PM PDT 24 |
| Finished | Jul 25 07:43:03 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-22646a69-975e-43b2-9d5d-2a3ccf384eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375770718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.375770718 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3789884629 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 565901164 ps |
| CPU time | 51.67 seconds |
| Started | Jul 25 07:38:59 PM PDT 24 |
| Finished | Jul 25 07:39:51 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ba2309d7-9f17-45c7-b175-65381d27a23a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789884629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3789884629 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1967699763 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 410726602 ps |
| CPU time | 32.96 seconds |
| Started | Jul 25 07:39:13 PM PDT 24 |
| Finished | Jul 25 07:39:46 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-0a661510-5920-45a9-b436-2df6ac8a1661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967699763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1967699763 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2263749973 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 50496097 ps |
| CPU time | 6.4 seconds |
| Started | Jul 25 07:39:00 PM PDT 24 |
| Finished | Jul 25 07:39:06 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-d75aba6a-be3f-4a8b-9dc4-6404516ddbc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263749973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2263749973 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2192891022 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 9700937996 ps |
| CPU time | 108.31 seconds |
| Started | Jul 25 07:39:00 PM PDT 24 |
| Finished | Jul 25 07:40:49 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-a96c528f-6029-4465-a7f9-15cd5849c9d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192891022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2192891022 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2852670568 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 5342275978 ps |
| CPU time | 88.62 seconds |
| Started | Jul 25 07:39:02 PM PDT 24 |
| Finished | Jul 25 07:40:31 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-9314f391-46b9-4464-aa79-7ba5898ab505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852670568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2852670568 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1583167557 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 45637074 ps |
| CPU time | 6.1 seconds |
| Started | Jul 25 07:39:00 PM PDT 24 |
| Finished | Jul 25 07:39:07 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-4c9f444c-f323-411c-833c-e23ce45d246a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583167557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1583167557 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1556441736 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 2214454823 ps |
| CPU time | 63.64 seconds |
| Started | Jul 25 07:39:14 PM PDT 24 |
| Finished | Jul 25 07:40:18 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-bb0226d6-2f5c-4949-997a-10bb586ec5ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556441736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1556441736 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1037499327 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 25316955433 ps |
| CPU time | 874.89 seconds |
| Started | Jul 25 07:39:12 PM PDT 24 |
| Finished | Jul 25 07:53:47 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-2fdb636a-e588-4e6a-b02f-8edcb14e5fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037499327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1037499327 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.498617567 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 154667768 ps |
| CPU time | 61.45 seconds |
| Started | Jul 25 07:39:13 PM PDT 24 |
| Finished | Jul 25 07:40:14 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-28661a57-7a33-42da-b660-5551b917d713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498617567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_ with_rand_reset.498617567 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.4062052999 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 148736770 ps |
| CPU time | 51.3 seconds |
| Started | Jul 25 07:39:13 PM PDT 24 |
| Finished | Jul 25 07:40:04 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-18150e14-6c61-4301-b9dc-7651dc430519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062052999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.4062052999 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.4241083001 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 695174350 ps |
| CPU time | 28.58 seconds |
| Started | Jul 25 07:39:12 PM PDT 24 |
| Finished | Jul 25 07:39:41 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-dff0a13e-c18c-4d1a-a6b2-14178e5d0c85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241083001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4241083001 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2167020887 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 630891980 ps |
| CPU time | 44.13 seconds |
| Started | Jul 25 07:39:22 PM PDT 24 |
| Finished | Jul 25 07:40:06 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-c285c2b4-3cef-401e-b6e8-056e73dc0ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167020887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .2167020887 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1752642846 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 115288942 ps |
| CPU time | 13.89 seconds |
| Started | Jul 25 07:39:35 PM PDT 24 |
| Finished | Jul 25 07:39:49 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-fddd5d88-c384-4f21-a2da-b2b2de8d9ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752642846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1752642846 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.2262630116 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 478136024 ps |
| CPU time | 36.84 seconds |
| Started | Jul 25 07:39:22 PM PDT 24 |
| Finished | Jul 25 07:39:59 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-c0fcbf3f-da12-479e-99e9-b3c33f21dd9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262630116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2262630116 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2751382486 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 385756507 ps |
| CPU time | 14.74 seconds |
| Started | Jul 25 07:39:24 PM PDT 24 |
| Finished | Jul 25 07:39:39 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2ec6168d-6243-4296-8e0e-4af8e69be71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751382486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2751382486 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3661729373 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 93467324072 ps |
| CPU time | 1058.53 seconds |
| Started | Jul 25 07:39:23 PM PDT 24 |
| Finished | Jul 25 07:57:03 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-82ea8f17-ca50-4c39-ae03-fbde81baa075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661729373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3661729373 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3442222840 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 57398799420 ps |
| CPU time | 888.36 seconds |
| Started | Jul 25 07:39:23 PM PDT 24 |
| Finished | Jul 25 07:54:12 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-191c711e-c193-4802-8e07-07977edc7a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442222840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3442222840 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.1850229049 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 415013567 ps |
| CPU time | 38.5 seconds |
| Started | Jul 25 07:39:22 PM PDT 24 |
| Finished | Jul 25 07:40:00 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-e4499ca8-7038-40ea-8a37-b29949d6c7de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850229049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.1850229049 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3687835690 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 413863369 ps |
| CPU time | 32.78 seconds |
| Started | Jul 25 07:39:23 PM PDT 24 |
| Finished | Jul 25 07:39:56 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-9547f4f6-62da-402d-88ba-9a772c54604f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687835690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3687835690 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2194595330 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 174174204 ps |
| CPU time | 8.35 seconds |
| Started | Jul 25 07:39:14 PM PDT 24 |
| Finished | Jul 25 07:39:22 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-7edf1d7b-fe53-49b8-b464-801d4090cbbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194595330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2194595330 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.172731607 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 4702397044 ps |
| CPU time | 46.46 seconds |
| Started | Jul 25 07:39:27 PM PDT 24 |
| Finished | Jul 25 07:40:14 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-3dda9d61-50a6-4c05-a8ba-35c9f2e9ad81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172731607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.172731607 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.890708165 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 5506130607 ps |
| CPU time | 99.88 seconds |
| Started | Jul 25 07:39:21 PM PDT 24 |
| Finished | Jul 25 07:41:01 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-91d2a888-1e68-4493-98cb-ac24da185d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890708165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.890708165 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3442138730 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 39647765 ps |
| CPU time | 6.27 seconds |
| Started | Jul 25 07:39:27 PM PDT 24 |
| Finished | Jul 25 07:39:33 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-7146a57b-7121-44ed-8a64-776cc44003ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442138730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3442138730 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3671792902 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 655699390 ps |
| CPU time | 51.51 seconds |
| Started | Jul 25 07:39:35 PM PDT 24 |
| Finished | Jul 25 07:40:26 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-fc1c2f74-d062-47ba-9031-2df58dec1bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671792902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3671792902 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3713619812 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 1279453250 ps |
| CPU time | 47.06 seconds |
| Started | Jul 25 07:39:36 PM PDT 24 |
| Finished | Jul 25 07:40:24 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e6dc2e1f-1b74-43c8-b066-b44a2178990c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713619812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3713619812 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3518058635 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 431606828 ps |
| CPU time | 152.04 seconds |
| Started | Jul 25 07:39:36 PM PDT 24 |
| Finished | Jul 25 07:42:09 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-1b532296-88a3-4eb9-9a6f-da6b2f45da56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518058635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3518058635 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2188238431 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 3719380255 ps |
| CPU time | 348.02 seconds |
| Started | Jul 25 07:39:37 PM PDT 24 |
| Finished | Jul 25 07:45:25 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-8fb01e69-6445-4a37-bda8-160d72175a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188238431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.2188238431 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3006077307 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 16789548 ps |
| CPU time | 5.06 seconds |
| Started | Jul 25 07:39:25 PM PDT 24 |
| Finished | Jul 25 07:39:30 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-1c693f40-5827-43f4-b36c-a46ba3224b93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006077307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3006077307 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2586803445 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 57458280060 ps |
| CPU time | 9875.85 seconds |
| Started | Jul 25 07:27:54 PM PDT 24 |
| Finished | Jul 25 10:12:31 PM PDT 24 |
| Peak memory | 642996 kb |
| Host | smart-a0504052-36df-4a68-a6ed-48d0310197fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586803445 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2586803445 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.2425541788 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 12780709916 ps |
| CPU time | 1725.12 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:56:35 PM PDT 24 |
| Peak memory | 590132 kb |
| Host | smart-c040ea50-7f24-4754-a3b7-0b6d4f2cec1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425541788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.2425541788 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.866357113 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4192946342 ps |
| CPU time | 275.24 seconds |
| Started | Jul 25 07:27:51 PM PDT 24 |
| Finished | Jul 25 07:32:27 PM PDT 24 |
| Peak memory | 663520 kb |
| Host | smart-ced1bf65-1d76-46c5-9586-6feed79846fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866357113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.866357113 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.559736016 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 7508796584 ps |
| CPU time | 460.65 seconds |
| Started | Jul 25 07:28:00 PM PDT 24 |
| Finished | Jul 25 07:35:40 PM PDT 24 |
| Peak memory | 645180 kb |
| Host | smart-05babd83-902d-4f3d-87cc-deb52d05d0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559736016 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.559736016 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.1349164457 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3788710183 ps |
| CPU time | 337.09 seconds |
| Started | Jul 25 07:27:54 PM PDT 24 |
| Finished | Jul 25 07:33:31 PM PDT 24 |
| Peak memory | 597692 kb |
| Host | smart-6a0a1e41-5040-49be-9b1d-75eec88facce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349164457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1349164457 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.688350489 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 29428532648 ps |
| CPU time | 4860.01 seconds |
| Started | Jul 25 07:27:50 PM PDT 24 |
| Finished | Jul 25 08:48:51 PM PDT 24 |
| Peak memory | 593188 kb |
| Host | smart-f70efcdc-ce63-48d4-b9a6-81437bc7fccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688350489 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.chip_same_csr_outstanding.688350489 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2859536403 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3781628840 ps |
| CPU time | 243.94 seconds |
| Started | Jul 25 07:27:59 PM PDT 24 |
| Finished | Jul 25 07:32:03 PM PDT 24 |
| Peak memory | 603404 kb |
| Host | smart-02bfa69f-c254-45c1-bfc9-48b5eee082c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859536403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2859536403 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1100878018 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 678418266 ps |
| CPU time | 32.17 seconds |
| Started | Jul 25 07:27:48 PM PDT 24 |
| Finished | Jul 25 07:28:20 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-32be2bf1-9fa7-4f62-95de-639082609d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100878018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 1100878018 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.655752196 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 76325743763 ps |
| CPU time | 1286.42 seconds |
| Started | Jul 25 07:27:50 PM PDT 24 |
| Finished | Jul 25 07:49:17 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-85e8a61f-a2d7-48a2-a836-482ae1cb36a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655752196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de vice_slow_rsp.655752196 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2003489266 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 1114410847 ps |
| CPU time | 43.29 seconds |
| Started | Jul 25 07:27:59 PM PDT 24 |
| Finished | Jul 25 07:28:42 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-3fc01c90-e6cc-4ba5-acf2-908f5c7e6f23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003489266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .2003489266 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.2049176987 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 861555632 ps |
| CPU time | 28.96 seconds |
| Started | Jul 25 07:27:51 PM PDT 24 |
| Finished | Jul 25 07:28:20 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-145755e6-a34d-4014-ba18-cbd29b78edf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049176987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2049176987 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2895944217 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 1401320156 ps |
| CPU time | 54.04 seconds |
| Started | Jul 25 07:27:51 PM PDT 24 |
| Finished | Jul 25 07:28:46 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-45c1881e-d76d-468a-9eef-d524483c00f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895944217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2895944217 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1376389089 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 71343881777 ps |
| CPU time | 764.21 seconds |
| Started | Jul 25 07:27:52 PM PDT 24 |
| Finished | Jul 25 07:40:36 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d126bbfb-6a41-4529-9253-7719c4b32c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376389089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1376389089 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.2181052714 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 50980682076 ps |
| CPU time | 791.23 seconds |
| Started | Jul 25 07:27:52 PM PDT 24 |
| Finished | Jul 25 07:41:03 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-be7d3679-656c-4318-b038-15bfdc62280d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181052714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2181052714 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.1670844089 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 543560009 ps |
| CPU time | 44.1 seconds |
| Started | Jul 25 07:27:52 PM PDT 24 |
| Finished | Jul 25 07:28:36 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-efcaf6d7-7b52-4928-8747-bba9eb7772d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670844089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.1670844089 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.720749576 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 593308355 ps |
| CPU time | 41.22 seconds |
| Started | Jul 25 07:27:48 PM PDT 24 |
| Finished | Jul 25 07:28:29 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-ec830199-f394-4b9e-a9c6-4958d4cc1a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720749576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.720749576 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.3704225914 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 208434320 ps |
| CPU time | 8.74 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:27:58 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-bee685ed-1fe5-40c3-b67c-5148d5e46df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704225914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3704225914 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1496206958 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 6612480916 ps |
| CPU time | 67.65 seconds |
| Started | Jul 25 07:27:50 PM PDT 24 |
| Finished | Jul 25 07:28:57 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-30e76eef-75d6-4a4c-b5c5-2ee5ce356ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496206958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1496206958 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.3354960744 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 4030053394 ps |
| CPU time | 70.5 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:29:00 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-88047853-5649-46da-abe5-d64843be4357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354960744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3354960744 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2111467944 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 53799062 ps |
| CPU time | 7.38 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:27:57 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-32747cf6-8d17-4ba8-8992-e1f28164c94c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111467944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2111467944 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3239933027 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 7827984272 ps |
| CPU time | 331.01 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:33:20 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-d37ca201-a2f9-4084-ad7c-7edcdec1728a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239933027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3239933027 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2009168456 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 1906218380 ps |
| CPU time | 175.36 seconds |
| Started | Jul 25 07:27:48 PM PDT 24 |
| Finished | Jul 25 07:30:44 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ae5c1ee5-0c4d-432a-9c12-7ed61d819d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009168456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2009168456 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3408886190 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 2099696324 ps |
| CPU time | 431.04 seconds |
| Started | Jul 25 07:27:50 PM PDT 24 |
| Finished | Jul 25 07:35:01 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-fb5b9237-1738-44d6-8f69-e752c092f6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408886190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.3408886190 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2477797020 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 145634424 ps |
| CPU time | 51.04 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:28:40 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-27a5f0bd-6187-4d8b-aaec-e7e51d58b381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477797020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.2477797020 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.248255030 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 1509913982 ps |
| CPU time | 61.59 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:28:51 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-4426f190-ff87-40eb-b506-4ca7ed061464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248255030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.248255030 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1266229488 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 876937115 ps |
| CPU time | 69.29 seconds |
| Started | Jul 25 07:39:36 PM PDT 24 |
| Finished | Jul 25 07:40:45 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-eb7ee6ff-9b46-427e-bb04-9f1a0d1639ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266229488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1266229488 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1313243136 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 88724155554 ps |
| CPU time | 1480.56 seconds |
| Started | Jul 25 07:39:36 PM PDT 24 |
| Finished | Jul 25 08:04:17 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-ffec1816-714e-4a35-a774-e9996efc5a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313243136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.1313243136 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3313022123 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 959405834 ps |
| CPU time | 43.03 seconds |
| Started | Jul 25 07:39:47 PM PDT 24 |
| Finished | Jul 25 07:40:30 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-f483ac44-c746-4498-80ee-bb734eb9a0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313022123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.3313022123 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.352545918 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 609438262 ps |
| CPU time | 24.16 seconds |
| Started | Jul 25 07:39:51 PM PDT 24 |
| Finished | Jul 25 07:40:15 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-bacdfdf0-72ae-4254-93ac-d7823e2736d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352545918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.352545918 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.3595671193 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 132723737 ps |
| CPU time | 13.49 seconds |
| Started | Jul 25 07:39:36 PM PDT 24 |
| Finished | Jul 25 07:39:49 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-983150de-f780-4787-8050-03face14399a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595671193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3595671193 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2352936285 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 83403288148 ps |
| CPU time | 807.27 seconds |
| Started | Jul 25 07:39:39 PM PDT 24 |
| Finished | Jul 25 07:53:06 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-c6e2eabc-1226-449d-8b4b-a4655c949def |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352936285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2352936285 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1583064590 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 12499610149 ps |
| CPU time | 208.35 seconds |
| Started | Jul 25 07:39:37 PM PDT 24 |
| Finished | Jul 25 07:43:06 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-7d97093e-9f71-4a45-8c8e-d088ab64151b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583064590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1583064590 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.195392092 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 347626559 ps |
| CPU time | 36.39 seconds |
| Started | Jul 25 07:39:35 PM PDT 24 |
| Finished | Jul 25 07:40:12 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-fbc7f715-d28d-4e10-87ac-90a1b83d25f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195392092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_dela ys.195392092 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3783967195 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 230632089 ps |
| CPU time | 19.33 seconds |
| Started | Jul 25 07:39:48 PM PDT 24 |
| Finished | Jul 25 07:40:07 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-86c92901-5f8a-498b-9450-801fa332bb6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783967195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3783967195 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.2877836157 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 34501276 ps |
| CPU time | 5.6 seconds |
| Started | Jul 25 07:39:47 PM PDT 24 |
| Finished | Jul 25 07:39:53 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-d3750180-68ee-4393-8fca-cbb9ec97d150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877836157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2877836157 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2301206134 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 7371116856 ps |
| CPU time | 75.9 seconds |
| Started | Jul 25 07:39:38 PM PDT 24 |
| Finished | Jul 25 07:40:54 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b9027a8d-0376-4f80-8afd-e6f796dd773e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301206134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2301206134 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1079290852 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 3902050064 ps |
| CPU time | 64.73 seconds |
| Started | Jul 25 07:39:38 PM PDT 24 |
| Finished | Jul 25 07:40:43 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-1d4f9873-8236-4773-977a-fc05b7b12baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079290852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1079290852 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2081326283 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 47917168 ps |
| CPU time | 6.33 seconds |
| Started | Jul 25 07:39:34 PM PDT 24 |
| Finished | Jul 25 07:39:41 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-f57c63df-1e07-4faa-852f-527438b68d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081326283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2081326283 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.826716152 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 4918500397 ps |
| CPU time | 392.07 seconds |
| Started | Jul 25 07:39:47 PM PDT 24 |
| Finished | Jul 25 07:46:20 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-ac4a7e40-1703-4e3a-bf4c-3c129c26c236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826716152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.826716152 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.407576301 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 2393586231 ps |
| CPU time | 187.72 seconds |
| Started | Jul 25 07:39:48 PM PDT 24 |
| Finished | Jul 25 07:42:56 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-582d214b-b263-4896-b7b7-a71b2c19ac3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407576301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.407576301 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.4072285951 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 383857399 ps |
| CPU time | 181.61 seconds |
| Started | Jul 25 07:39:50 PM PDT 24 |
| Finished | Jul 25 07:42:52 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-dbf5a8e9-3021-4530-b5a3-88b9239dc534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072285951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.4072285951 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.634422640 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 57148018 ps |
| CPU time | 21.37 seconds |
| Started | Jul 25 07:39:50 PM PDT 24 |
| Finished | Jul 25 07:40:12 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-bb4ee273-7368-46c6-af96-20d3b4a26f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634422640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_reset_error.634422640 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2001384629 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 265107236 ps |
| CPU time | 33.96 seconds |
| Started | Jul 25 07:39:47 PM PDT 24 |
| Finished | Jul 25 07:40:21 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-2607c47e-96b4-4fd3-8f75-649684cf1302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001384629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2001384629 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.827218185 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 3461228754 ps |
| CPU time | 139.96 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:42:22 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-d621cd22-7e44-476c-8667-aac5b79d324b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827218185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 827218185 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1165413687 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 171364373073 ps |
| CPU time | 3202.61 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 08:33:24 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ffb6cc37-b909-4235-bc7e-5101ca2ad96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165413687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1165413687 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.396752503 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 648643539 ps |
| CPU time | 28.09 seconds |
| Started | Jul 25 07:40:02 PM PDT 24 |
| Finished | Jul 25 07:40:31 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-b3e8a346-b77d-4bdb-9721-9120362647f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396752503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr .396752503 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.2138386042 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 58258215 ps |
| CPU time | 5.57 seconds |
| Started | Jul 25 07:40:02 PM PDT 24 |
| Finished | Jul 25 07:40:08 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-921f3ee8-86a5-4794-b516-46b089cc1bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138386042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2138386042 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.3728419082 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 68337724 ps |
| CPU time | 7.67 seconds |
| Started | Jul 25 07:39:51 PM PDT 24 |
| Finished | Jul 25 07:39:58 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-072cc5c2-8cc9-4f15-bf6f-4a9288092c1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728419082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3728419082 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.2384223050 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 61977164765 ps |
| CPU time | 695.84 seconds |
| Started | Jul 25 07:40:04 PM PDT 24 |
| Finished | Jul 25 07:51:40 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-4d36c706-010d-4be3-9071-71b296c3fffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384223050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.2384223050 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.1438982372 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 39980005631 ps |
| CPU time | 705.05 seconds |
| Started | Jul 25 07:40:03 PM PDT 24 |
| Finished | Jul 25 07:51:48 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-a0857ad9-5578-439f-bd3b-703ada2f1d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438982372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.1438982372 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.1736776028 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 314980520 ps |
| CPU time | 25.74 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:40:27 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-b2f5737b-2d2e-4805-94c3-3f7aa1a9be60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736776028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.1736776028 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.1483645320 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 159970801 ps |
| CPU time | 13.92 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:40:15 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-e3736a28-994d-469c-8c91-4b58e00d4fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483645320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1483645320 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.2864762328 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 240643806 ps |
| CPU time | 9.9 seconds |
| Started | Jul 25 07:39:49 PM PDT 24 |
| Finished | Jul 25 07:39:59 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-d4fb84ff-cdc0-4102-8e6f-71c426c72639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864762328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2864762328 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3207290733 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 8036491413 ps |
| CPU time | 82.37 seconds |
| Started | Jul 25 07:39:49 PM PDT 24 |
| Finished | Jul 25 07:41:11 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-1cef4385-0317-442c-b1da-54d9e9cfa5b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207290733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3207290733 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3291420322 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 3968831825 ps |
| CPU time | 70 seconds |
| Started | Jul 25 07:39:50 PM PDT 24 |
| Finished | Jul 25 07:41:01 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-a711e97b-ada4-4d91-a7b8-0e8976b2f443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291420322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3291420322 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2125269610 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 54290478 ps |
| CPU time | 6.5 seconds |
| Started | Jul 25 07:39:55 PM PDT 24 |
| Finished | Jul 25 07:40:01 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-fe1c2bf4-3543-4612-96eb-aec203ec3192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125269610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2125269610 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2074326592 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 16381350751 ps |
| CPU time | 627.86 seconds |
| Started | Jul 25 07:40:00 PM PDT 24 |
| Finished | Jul 25 07:50:28 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-9bbdc55d-3e51-4232-bc97-b818655f575c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074326592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2074326592 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3942687129 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 8286785365 ps |
| CPU time | 289.32 seconds |
| Started | Jul 25 07:40:02 PM PDT 24 |
| Finished | Jul 25 07:44:51 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-0a8dab0e-f3d4-40a6-99f5-b5ebd1a4505b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942687129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3942687129 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1589661668 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 131539656 ps |
| CPU time | 68.17 seconds |
| Started | Jul 25 07:40:02 PM PDT 24 |
| Finished | Jul 25 07:41:10 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-9851d0ea-e63c-4386-95e7-a1a059ff3263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589661668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1589661668 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2728910604 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2673832488 ps |
| CPU time | 263.74 seconds |
| Started | Jul 25 07:40:00 PM PDT 24 |
| Finished | Jul 25 07:44:24 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-0f1a4634-d8ad-4ca1-ada4-b7fc23c63ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728910604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.2728910604 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2830655331 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 306325345 ps |
| CPU time | 33.46 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:40:35 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-479d865d-91c6-4668-b5df-7ca710ad028e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830655331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2830655331 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.1243756993 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 445687910 ps |
| CPU time | 22.04 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 07:40:35 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-479fd9ff-245a-49bc-8db0-04935ca801f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243756993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .1243756993 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3165996566 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 89812846778 ps |
| CPU time | 1531.52 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 08:05:44 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-00015d64-a55f-42ce-a096-0802fcafc238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165996566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.3165996566 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.643675302 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 304558712 ps |
| CPU time | 30.14 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 07:40:43 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-63470381-9f3b-49c5-a894-f7f2cfeb6cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643675302 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr .643675302 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.3332654407 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 1812956553 ps |
| CPU time | 61.41 seconds |
| Started | Jul 25 07:40:13 PM PDT 24 |
| Finished | Jul 25 07:41:14 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-805d2892-94dd-4242-9cbf-c8e5f3c8ce99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332654407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3332654407 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.348795344 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 2277138574 ps |
| CPU time | 92.49 seconds |
| Started | Jul 25 07:40:02 PM PDT 24 |
| Finished | Jul 25 07:41:35 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-c1d3bf89-6add-420f-b787-aaab584c18b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348795344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.348795344 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3405153047 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 21549661790 ps |
| CPU time | 239.09 seconds |
| Started | Jul 25 07:40:14 PM PDT 24 |
| Finished | Jul 25 07:44:13 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-50d452a0-ba76-4323-8994-849aa84961f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405153047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3405153047 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.4283233009 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 13376129417 ps |
| CPU time | 203.38 seconds |
| Started | Jul 25 07:40:13 PM PDT 24 |
| Finished | Jul 25 07:43:37 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-bff45092-0dbe-4f01-bb14-39be31ef9563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283233009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.4283233009 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.972961691 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 307561494 ps |
| CPU time | 30.95 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:40:33 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-b6b54134-c202-4c13-94b5-3e8713cc4310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972961691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.972961691 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.4210582065 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 285701692 ps |
| CPU time | 21.08 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 07:40:34 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-1492e391-0aaf-4a3e-a0da-35a67b24013d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210582065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4210582065 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2688948052 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 46179369 ps |
| CPU time | 6.35 seconds |
| Started | Jul 25 07:40:04 PM PDT 24 |
| Finished | Jul 25 07:40:11 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-8fc8107c-b853-4d24-bd08-045390e42523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688948052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2688948052 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.3954168181 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 9032128723 ps |
| CPU time | 97.49 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:41:39 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-bce506ef-d3b6-4967-a181-bd13b9389dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954168181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3954168181 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3555260556 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 4022008859 ps |
| CPU time | 65.69 seconds |
| Started | Jul 25 07:40:03 PM PDT 24 |
| Finished | Jul 25 07:41:09 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-fbe6f1e5-35ee-4fb9-a791-d77df8f41cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555260556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3555260556 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2903992753 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 58517324 ps |
| CPU time | 6.93 seconds |
| Started | Jul 25 07:40:01 PM PDT 24 |
| Finished | Jul 25 07:40:08 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-0c37218a-dd78-4539-a682-a1426bf746b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903992753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.2903992753 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.2479240009 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 3540761649 ps |
| CPU time | 343.57 seconds |
| Started | Jul 25 07:40:09 PM PDT 24 |
| Finished | Jul 25 07:45:53 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-e71697eb-8d45-4247-8d13-2985475451db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479240009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2479240009 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1757484926 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 650921675 ps |
| CPU time | 267.59 seconds |
| Started | Jul 25 07:40:19 PM PDT 24 |
| Finished | Jul 25 07:44:46 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-ebf2bc0c-8b3d-43cb-8897-c67d8dfa49d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757484926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.1757484926 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1880819502 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 5145019366 ps |
| CPU time | 453.43 seconds |
| Started | Jul 25 07:40:14 PM PDT 24 |
| Finished | Jul 25 07:47:47 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-38596e02-2147-4f73-873a-5555aef69485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880819502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.1880819502 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2153032115 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 174505347 ps |
| CPU time | 23.28 seconds |
| Started | Jul 25 07:40:19 PM PDT 24 |
| Finished | Jul 25 07:40:42 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-91ef62f4-0a3c-41ee-94a7-e8b41df1183e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153032115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2153032115 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.263826893 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 547173364 ps |
| CPU time | 41.82 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 07:40:54 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-bc223561-b11e-4d2d-8139-1009601cac2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263826893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 263826893 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.4212517296 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 28879759340 ps |
| CPU time | 494.43 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:48:38 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-d29bb2f6-7f71-4654-b7b3-7017591ef694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212517296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.4212517296 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.985655386 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 140122945 ps |
| CPU time | 15.84 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:40:40 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-a14a8e82-41f7-4467-926b-1ca1cc2a3cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985655386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr .985655386 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.3474932257 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 432346220 ps |
| CPU time | 15.91 seconds |
| Started | Jul 25 07:40:25 PM PDT 24 |
| Finished | Jul 25 07:40:42 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-4e3f1d84-ae44-4cb3-9ca6-2ac8c139154b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474932257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3474932257 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1138874477 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 329155231 ps |
| CPU time | 28.51 seconds |
| Started | Jul 25 07:40:11 PM PDT 24 |
| Finished | Jul 25 07:40:40 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-195a80e7-382f-423e-b095-085ebe619e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138874477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1138874477 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1649604410 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 43251602348 ps |
| CPU time | 422.95 seconds |
| Started | Jul 25 07:40:13 PM PDT 24 |
| Finished | Jul 25 07:47:16 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-0c77c5ae-dc58-4fb6-948c-f62331e14e2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649604410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1649604410 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.610027809 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 20011590099 ps |
| CPU time | 324.48 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 07:45:36 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-2c7d5d9b-5c57-4d34-920e-5e77653f9679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610027809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.610027809 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.4029961967 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 464350355 ps |
| CPU time | 37.83 seconds |
| Started | Jul 25 07:40:13 PM PDT 24 |
| Finished | Jul 25 07:40:51 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-de7dcd30-517e-45a5-a6f1-7c53b02a637b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029961967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.4029961967 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.3007534485 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 339887677 ps |
| CPU time | 25.18 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:40:50 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-7d73c34c-1be2-4fee-9b88-5910d73df5aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007534485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3007534485 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1031670090 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 115812932 ps |
| CPU time | 7.35 seconds |
| Started | Jul 25 07:40:19 PM PDT 24 |
| Finished | Jul 25 07:40:27 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-5df51a41-8538-4b59-8f2e-776e46151f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031670090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1031670090 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.316352142 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 7566746052 ps |
| CPU time | 80.35 seconds |
| Started | Jul 25 07:40:11 PM PDT 24 |
| Finished | Jul 25 07:41:32 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-2b690c9b-1990-4cf6-8513-147ac6456744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316352142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.316352142 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2344922980 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 5944256385 ps |
| CPU time | 97.23 seconds |
| Started | Jul 25 07:40:17 PM PDT 24 |
| Finished | Jul 25 07:41:55 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-96d9f2dc-a79f-4678-827f-828d42413ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344922980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2344922980 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.667781604 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 42193095 ps |
| CPU time | 6.37 seconds |
| Started | Jul 25 07:40:12 PM PDT 24 |
| Finished | Jul 25 07:40:19 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-88977fc0-79ef-4ae2-9fc0-cb301349ff37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667781604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays .667781604 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2860330113 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 6604990 ps |
| CPU time | 3.76 seconds |
| Started | Jul 25 07:40:23 PM PDT 24 |
| Finished | Jul 25 07:40:27 PM PDT 24 |
| Peak memory | 565932 kb |
| Host | smart-b3895d28-b3ce-4a80-8f0a-885549524b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860330113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2860330113 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.3605807908 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1663400916 ps |
| CPU time | 111.95 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:42:16 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-081573e0-459c-4dff-8d2f-9ed2f7ed02f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605807908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3605807908 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1836559553 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 6733574551 ps |
| CPU time | 431.18 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:47:35 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-a6597ab0-361b-4955-9c82-c0601a160d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836559553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.1836559553 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1082654290 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 382502559 ps |
| CPU time | 118.65 seconds |
| Started | Jul 25 07:40:25 PM PDT 24 |
| Finished | Jul 25 07:42:23 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-6ea572b1-b2ee-4c51-b084-a864f380f308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082654290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.1082654290 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2536166013 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 145812561 ps |
| CPU time | 9.74 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:40:33 PM PDT 24 |
| Peak memory | 573812 kb |
| Host | smart-25c4545e-24b4-4e65-90d8-03f57606ab3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536166013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2536166013 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3778208219 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 1763444436 ps |
| CPU time | 68.76 seconds |
| Started | Jul 25 07:40:36 PM PDT 24 |
| Finished | Jul 25 07:41:45 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-ffb1e541-2c46-4d23-883d-215880c768bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778208219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3778208219 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2187838597 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 52901088095 ps |
| CPU time | 900.74 seconds |
| Started | Jul 25 07:40:36 PM PDT 24 |
| Finished | Jul 25 07:55:37 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-e1225319-8656-4aa4-b762-fdff3d671269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187838597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2187838597 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3372489051 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 676061796 ps |
| CPU time | 29.37 seconds |
| Started | Jul 25 07:40:36 PM PDT 24 |
| Finished | Jul 25 07:41:06 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-792c5d46-2b5f-4957-8c58-0ba087eb41b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372489051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.3372489051 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.138198298 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 1602820251 ps |
| CPU time | 53.92 seconds |
| Started | Jul 25 07:40:36 PM PDT 24 |
| Finished | Jul 25 07:41:30 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-8add7e38-9ca7-4fcc-b265-31c37003abd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138198298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.138198298 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.162475070 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 1256983966 ps |
| CPU time | 41.92 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:41:06 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-fd8c1091-3795-41f4-98a5-a8ccf7284e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162475070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.162475070 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3386722618 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 89353976116 ps |
| CPU time | 954.17 seconds |
| Started | Jul 25 07:40:39 PM PDT 24 |
| Finished | Jul 25 07:56:34 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-e26dbb3c-0d22-4fdd-b108-f17f79d041bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386722618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3386722618 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2714397256 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 6649814899 ps |
| CPU time | 111.78 seconds |
| Started | Jul 25 07:40:37 PM PDT 24 |
| Finished | Jul 25 07:42:28 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-0452f315-ba1f-41f3-a40c-87210fe2cc51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714397256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2714397256 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.866128568 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 627159387 ps |
| CPU time | 58.14 seconds |
| Started | Jul 25 07:40:37 PM PDT 24 |
| Finished | Jul 25 07:41:35 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f22c45fa-a74a-4c83-8f35-2d51cd6d2b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866128568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_dela ys.866128568 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3092127631 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 1619305696 ps |
| CPU time | 50.5 seconds |
| Started | Jul 25 07:40:40 PM PDT 24 |
| Finished | Jul 25 07:41:30 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-715306bb-087a-47b1-84b9-409c59c3c6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092127631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3092127631 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.455936 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 205203737 ps |
| CPU time | 9.23 seconds |
| Started | Jul 25 07:40:24 PM PDT 24 |
| Finished | Jul 25 07:40:33 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-dce60fb5-227a-4625-afe8-e0f8c0e04a32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.455936 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.1215098873 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 8391501143 ps |
| CPU time | 88.61 seconds |
| Started | Jul 25 07:40:23 PM PDT 24 |
| Finished | Jul 25 07:41:51 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-6df9a157-a9d7-4afd-8a17-2d9a1570e69f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215098873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1215098873 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1027578016 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 5914536838 ps |
| CPU time | 96.73 seconds |
| Started | Jul 25 07:40:25 PM PDT 24 |
| Finished | Jul 25 07:42:02 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-8c6eec43-90dd-41c9-90ca-31215b296222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027578016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1027578016 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.213567267 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 45744332 ps |
| CPU time | 6.41 seconds |
| Started | Jul 25 07:40:23 PM PDT 24 |
| Finished | Jul 25 07:40:30 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-2ebbadf1-118b-4f46-af55-24f87d4cfe94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213567267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .213567267 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.3711382006 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 2128051956 ps |
| CPU time | 64.11 seconds |
| Started | Jul 25 07:40:35 PM PDT 24 |
| Finished | Jul 25 07:41:39 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-87e6b690-8a6c-4c4b-8bb0-0cb36b71bdc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711382006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3711382006 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3850790715 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 7005464876 ps |
| CPU time | 256.03 seconds |
| Started | Jul 25 07:40:41 PM PDT 24 |
| Finished | Jul 25 07:44:58 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-9dc649e3-2918-4178-8722-2a69ac488689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850790715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3850790715 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1699526299 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 285514301 ps |
| CPU time | 155.08 seconds |
| Started | Jul 25 07:40:35 PM PDT 24 |
| Finished | Jul 25 07:43:10 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-2e5f2bef-5533-44c5-aaf2-a867d8f99730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699526299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1699526299 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.446662984 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 832034036 ps |
| CPU time | 264.48 seconds |
| Started | Jul 25 07:40:36 PM PDT 24 |
| Finished | Jul 25 07:45:00 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-8f1d10c9-70fc-4b31-b6df-54092a176a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446662984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_reset_error.446662984 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3739542050 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 179977764 ps |
| CPU time | 22.64 seconds |
| Started | Jul 25 07:40:38 PM PDT 24 |
| Finished | Jul 25 07:41:01 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-7c43c961-1aed-4ad2-b720-63ba0961263d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739542050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3739542050 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3359913145 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 1718629170 ps |
| CPU time | 72.24 seconds |
| Started | Jul 25 07:40:54 PM PDT 24 |
| Finished | Jul 25 07:42:07 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-2ab759fb-0417-46c8-ac67-6cc98f586a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359913145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3359913145 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1125453826 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 73714000858 ps |
| CPU time | 1207.5 seconds |
| Started | Jul 25 07:40:56 PM PDT 24 |
| Finished | Jul 25 08:01:03 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-2b486d50-dd60-4f25-85f1-bba95b1a248f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125453826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1125453826 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.461196452 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 161244402 ps |
| CPU time | 8.93 seconds |
| Started | Jul 25 07:40:56 PM PDT 24 |
| Finished | Jul 25 07:41:05 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-ae8efcd0-a8e5-4efc-b65d-bb1d04e2a9b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461196452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr .461196452 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.95293703 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 360123947 ps |
| CPU time | 27.98 seconds |
| Started | Jul 25 07:40:56 PM PDT 24 |
| Finished | Jul 25 07:41:24 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-6920ad96-efd1-403a-bdf5-fd1db1ea7bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95293703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.95293703 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.2046458976 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1812441673 ps |
| CPU time | 72.02 seconds |
| Started | Jul 25 07:40:57 PM PDT 24 |
| Finished | Jul 25 07:42:09 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f234cad1-4325-4f0d-afd7-4541df020117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046458976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2046458976 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.1630545507 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 64875102341 ps |
| CPU time | 627.2 seconds |
| Started | Jul 25 07:40:56 PM PDT 24 |
| Finished | Jul 25 07:51:23 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-1fed2a2a-d908-43df-a442-916bda000811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630545507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1630545507 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1515120531 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 31250090803 ps |
| CPU time | 518.15 seconds |
| Started | Jul 25 07:40:57 PM PDT 24 |
| Finished | Jul 25 07:49:35 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-afa66ca7-ba4e-425b-8ac9-f5a8b85bff20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515120531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1515120531 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.607103888 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 466940796 ps |
| CPU time | 41.7 seconds |
| Started | Jul 25 07:40:57 PM PDT 24 |
| Finished | Jul 25 07:41:38 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-1c649955-4e60-490b-9c58-93eb90069472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607103888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.607103888 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3551767764 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1676401389 ps |
| CPU time | 50.61 seconds |
| Started | Jul 25 07:40:56 PM PDT 24 |
| Finished | Jul 25 07:41:47 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-a7121c0e-2ead-4396-9137-5d40c70080a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551767764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3551767764 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2261564122 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 243020230 ps |
| CPU time | 9.35 seconds |
| Started | Jul 25 07:40:37 PM PDT 24 |
| Finished | Jul 25 07:40:47 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-3fef65c9-2c0c-4f64-a281-df4f760d22b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261564122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2261564122 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.3091414180 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 5650370020 ps |
| CPU time | 58.92 seconds |
| Started | Jul 25 07:40:54 PM PDT 24 |
| Finished | Jul 25 07:41:53 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e1886960-07da-440f-a5a3-5c7d430e86a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091414180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3091414180 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.164925423 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 5220409633 ps |
| CPU time | 90.73 seconds |
| Started | Jul 25 07:40:55 PM PDT 24 |
| Finished | Jul 25 07:42:26 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-a3091ccc-a05b-46b2-915c-d2b341b8e609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164925423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.164925423 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.2566444514 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 34235958 ps |
| CPU time | 5.52 seconds |
| Started | Jul 25 07:40:57 PM PDT 24 |
| Finished | Jul 25 07:41:02 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-1e22566f-fc23-41e7-865c-ee010efecaf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566444514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.2566444514 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3832700674 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 12411972996 ps |
| CPU time | 461.21 seconds |
| Started | Jul 25 07:40:55 PM PDT 24 |
| Finished | Jul 25 07:48:36 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-b3cda12c-6901-4c39-9246-dfc3f2bd0b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832700674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3832700674 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.291583025 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 4540983257 ps |
| CPU time | 308.2 seconds |
| Started | Jul 25 07:40:54 PM PDT 24 |
| Finished | Jul 25 07:46:02 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-55536a9d-4d32-46ea-9c9b-b274cc0a83cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291583025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.291583025 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.265105755 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 5198577422 ps |
| CPU time | 317.37 seconds |
| Started | Jul 25 07:40:54 PM PDT 24 |
| Finished | Jul 25 07:46:12 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-5f3b1117-5512-42ae-912e-ab9699272005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265105755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_reset_error.265105755 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2623392384 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 742595477 ps |
| CPU time | 33.38 seconds |
| Started | Jul 25 07:40:57 PM PDT 24 |
| Finished | Jul 25 07:41:30 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-8080794a-192c-49ad-b66b-22390fc305e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623392384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2623392384 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.36467598 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1835635545 ps |
| CPU time | 69.97 seconds |
| Started | Jul 25 07:41:08 PM PDT 24 |
| Finished | Jul 25 07:42:18 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-c77796d4-0d36-4baa-aa42-4e301106b8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36467598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.36467598 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3438615386 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 45274323170 ps |
| CPU time | 729.68 seconds |
| Started | Jul 25 07:41:05 PM PDT 24 |
| Finished | Jul 25 07:53:15 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-3671ade5-fe07-4156-87d9-ea7f16d9b4e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438615386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3438615386 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.76177327 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 698559431 ps |
| CPU time | 27.55 seconds |
| Started | Jul 25 07:41:09 PM PDT 24 |
| Finished | Jul 25 07:41:37 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-1c5e8057-beec-4ecc-bb5c-c728d546ae88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76177327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.76177327 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.748985445 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 911504212 ps |
| CPU time | 31.88 seconds |
| Started | Jul 25 07:41:05 PM PDT 24 |
| Finished | Jul 25 07:41:37 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-ba87a0f5-8084-4773-9f52-16f84fba3835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748985445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.748985445 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.3615593993 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1975172150 ps |
| CPU time | 68.81 seconds |
| Started | Jul 25 07:41:05 PM PDT 24 |
| Finished | Jul 25 07:42:14 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-383f63d8-4e09-452c-b778-f8590e3ec807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615593993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3615593993 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2571472411 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 12913797595 ps |
| CPU time | 137.14 seconds |
| Started | Jul 25 07:41:04 PM PDT 24 |
| Finished | Jul 25 07:43:21 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-b85a297b-ac41-4242-95fc-1adb16bf0834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571472411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2571472411 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2363625810 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 40977526161 ps |
| CPU time | 659.83 seconds |
| Started | Jul 25 07:41:09 PM PDT 24 |
| Finished | Jul 25 07:52:09 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-ef68ad58-5c56-4ec1-8286-2db480f24e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363625810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2363625810 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.216804799 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 2129483082 ps |
| CPU time | 70.15 seconds |
| Started | Jul 25 07:41:05 PM PDT 24 |
| Finished | Jul 25 07:42:15 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-78a37e98-1511-4861-99a0-19d56b2f019b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216804799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.216804799 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.3218935281 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 180637709 ps |
| CPU time | 8.13 seconds |
| Started | Jul 25 07:41:03 PM PDT 24 |
| Finished | Jul 25 07:41:12 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-00da2601-74a5-4db3-9927-efe1871b8d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218935281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3218935281 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3324918868 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 8662950482 ps |
| CPU time | 87.07 seconds |
| Started | Jul 25 07:41:08 PM PDT 24 |
| Finished | Jul 25 07:42:35 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-9e4fb589-d145-4ab4-98b0-bf04aa0cafa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324918868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3324918868 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2998592407 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 3870654139 ps |
| CPU time | 59.9 seconds |
| Started | Jul 25 07:41:06 PM PDT 24 |
| Finished | Jul 25 07:42:06 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-3db6fbf5-93fb-49f5-960a-79f8ea9851e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998592407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2998592407 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3466555935 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 42332234 ps |
| CPU time | 5.84 seconds |
| Started | Jul 25 07:41:03 PM PDT 24 |
| Finished | Jul 25 07:41:09 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-c4e83f42-5375-4f98-b5d9-cc9e874dcc9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466555935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3466555935 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2330427029 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 3405669933 ps |
| CPU time | 236.61 seconds |
| Started | Jul 25 07:41:03 PM PDT 24 |
| Finished | Jul 25 07:45:00 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-ed8addc8-5136-42d9-a129-08189567f688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330427029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2330427029 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.4078177679 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 13832246151 ps |
| CPU time | 443.44 seconds |
| Started | Jul 25 07:41:08 PM PDT 24 |
| Finished | Jul 25 07:48:32 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-7fdc2ba7-88f8-49ec-bc19-6378b8e88ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078177679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.4078177679 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.42812639 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 365553930 ps |
| CPU time | 88.22 seconds |
| Started | Jul 25 07:41:06 PM PDT 24 |
| Finished | Jul 25 07:42:35 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-ac5cdea1-97e9-456a-9ee8-dcbdc809dcac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_w ith_rand_reset.42812639 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2317554652 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 161398974 ps |
| CPU time | 54.99 seconds |
| Started | Jul 25 07:41:06 PM PDT 24 |
| Finished | Jul 25 07:42:01 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-990d8a8b-824c-4c83-b9d4-3e8c2d9cd9a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317554652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.2317554652 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.102679894 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 314287832 ps |
| CPU time | 38.89 seconds |
| Started | Jul 25 07:41:03 PM PDT 24 |
| Finished | Jul 25 07:41:42 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c94dfb69-cb49-43f1-a27a-0a46949b5d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102679894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.102679894 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.31579956 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 591861144 ps |
| CPU time | 27.6 seconds |
| Started | Jul 25 07:41:16 PM PDT 24 |
| Finished | Jul 25 07:41:44 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-ff8ee4cf-6f26-4589-a370-be1f2ba26d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31579956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.31579956 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1653267276 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 66237874107 ps |
| CPU time | 1155.1 seconds |
| Started | Jul 25 07:41:16 PM PDT 24 |
| Finished | Jul 25 08:00:32 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-c041976b-46b3-404e-8e3e-9e60fcb63c58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653267276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1653267276 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.124293421 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 958141618 ps |
| CPU time | 33.14 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:41:50 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-ea14079a-7a77-45b5-8396-d1fba1cd8ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124293421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr .124293421 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3037172770 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 420846895 ps |
| CPU time | 17.43 seconds |
| Started | Jul 25 07:41:16 PM PDT 24 |
| Finished | Jul 25 07:41:34 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-f9449fda-6237-4dcd-a715-75b0d7d64db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037172770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3037172770 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.4154900554 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 396615903 ps |
| CPU time | 36.07 seconds |
| Started | Jul 25 07:41:02 PM PDT 24 |
| Finished | Jul 25 07:41:38 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-0ec5051c-c9d3-4e57-9d4a-7bcdb8ea2dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154900554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.4154900554 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3420983795 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 81025541896 ps |
| CPU time | 832.9 seconds |
| Started | Jul 25 07:41:02 PM PDT 24 |
| Finished | Jul 25 07:54:55 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-598d9b9c-c55d-4ef8-8f0e-cc9bd1cddb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420983795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3420983795 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.922734795 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 21549375051 ps |
| CPU time | 374.73 seconds |
| Started | Jul 25 07:41:02 PM PDT 24 |
| Finished | Jul 25 07:47:17 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-9dc8d971-b2fa-4d50-9633-4790ff7622dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922734795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.922734795 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1167383773 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 554984353 ps |
| CPU time | 46.66 seconds |
| Started | Jul 25 07:41:03 PM PDT 24 |
| Finished | Jul 25 07:41:50 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-73e1ab68-e77c-4b53-8d0c-6c8c9059b4d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167383773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.1167383773 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.539738090 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 2066996054 ps |
| CPU time | 61.46 seconds |
| Started | Jul 25 07:41:18 PM PDT 24 |
| Finished | Jul 25 07:42:19 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-cb3e89c8-7cf6-4b94-83cb-0707394c3764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539738090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.539738090 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.2084663935 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 240274236 ps |
| CPU time | 10.38 seconds |
| Started | Jul 25 07:41:09 PM PDT 24 |
| Finished | Jul 25 07:41:20 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-9b7db24e-341e-49e2-9fb5-f584866a6d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084663935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.2084663935 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.1332452873 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 7634533959 ps |
| CPU time | 75.02 seconds |
| Started | Jul 25 07:41:08 PM PDT 24 |
| Finished | Jul 25 07:42:23 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-b3ae3ea7-f5c4-4083-9a75-dc07855786a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332452873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1332452873 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.874782523 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 6265245389 ps |
| CPU time | 105.69 seconds |
| Started | Jul 25 07:41:04 PM PDT 24 |
| Finished | Jul 25 07:42:49 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-c2318e1b-4999-40da-837b-56b7bd6affc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874782523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.874782523 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.2232876697 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 49084915 ps |
| CPU time | 6.31 seconds |
| Started | Jul 25 07:41:04 PM PDT 24 |
| Finished | Jul 25 07:41:11 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-39db8f8e-ea49-4fa3-8470-317357ef1255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232876697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.2232876697 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.109032594 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1032541153 ps |
| CPU time | 79.5 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:42:37 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-04d983b5-3998-49b7-8e3d-668bfe86ac49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109032594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.109032594 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.769145474 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 12683888611 ps |
| CPU time | 453.98 seconds |
| Started | Jul 25 07:41:16 PM PDT 24 |
| Finished | Jul 25 07:48:50 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-38350822-4c05-484b-963f-1095810c165b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769145474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.769145474 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3985077717 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 13629676236 ps |
| CPU time | 618.85 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:51:36 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-08952f82-53ff-4292-8324-39cffec62576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985077717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3985077717 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3369101884 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 3090494037 ps |
| CPU time | 428.38 seconds |
| Started | Jul 25 07:41:18 PM PDT 24 |
| Finished | Jul 25 07:48:26 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-6357ce9d-751f-49f3-a90b-e3ef611ce912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369101884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3369101884 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2965747539 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 645476712 ps |
| CPU time | 31.55 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:41:49 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-0ac06a04-8caa-4e63-84d7-339015478a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965747539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2965747539 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.736842528 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 2898838898 ps |
| CPU time | 128.46 seconds |
| Started | Jul 25 07:41:35 PM PDT 24 |
| Finished | Jul 25 07:43:44 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-7e2b4321-9397-4bbd-94f6-987b8286a10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736842528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device. 736842528 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.564975546 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 57132822645 ps |
| CPU time | 987.22 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:57:56 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-a56e8ec5-f744-4aa4-b4a5-d9139fda9be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564975546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_d evice_slow_rsp.564975546 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2760314978 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 287059862 ps |
| CPU time | 27.94 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:41:57 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-71b88d6f-9796-4281-888f-10ed3d8f7f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760314978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2760314978 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3388247630 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 2144268169 ps |
| CPU time | 70.1 seconds |
| Started | Jul 25 07:41:28 PM PDT 24 |
| Finished | Jul 25 07:42:38 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-aa1ac604-4314-4ca9-81c6-7680fece0dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388247630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3388247630 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1686235210 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 114681968 ps |
| CPU time | 12.12 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:41:29 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-bdcd8941-1185-4f2b-8094-457ae11ddb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686235210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1686235210 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1645162993 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 107109816617 ps |
| CPU time | 1114.07 seconds |
| Started | Jul 25 07:41:35 PM PDT 24 |
| Finished | Jul 25 08:00:10 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-5295ac2c-fc8d-452c-9376-c004e48d1046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645162993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1645162993 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2707195535 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 58532499924 ps |
| CPU time | 973.01 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:57:42 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-d6dcb4f2-06ca-45b0-9161-82f58acacc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707195535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2707195535 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2730553267 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 563605696 ps |
| CPU time | 51.46 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:42:08 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-4b4d5174-8f67-4500-b86a-71c0feeed616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730553267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2730553267 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.4003434574 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1578512434 ps |
| CPU time | 43.79 seconds |
| Started | Jul 25 07:41:33 PM PDT 24 |
| Finished | Jul 25 07:42:17 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-564ec475-7c83-4f85-9d7f-3d501b960115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003434574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4003434574 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2075554262 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 60338759 ps |
| CPU time | 7.03 seconds |
| Started | Jul 25 07:41:16 PM PDT 24 |
| Finished | Jul 25 07:41:24 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-50ff6386-8b23-4592-a0a3-af7926b87e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075554262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2075554262 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.409812079 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 5263369724 ps |
| CPU time | 56.94 seconds |
| Started | Jul 25 07:41:18 PM PDT 24 |
| Finished | Jul 25 07:42:16 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-df3016fd-cec6-47b6-b72b-a209b44c7a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409812079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.409812079 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3632105058 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 5254403475 ps |
| CPU time | 84 seconds |
| Started | Jul 25 07:41:19 PM PDT 24 |
| Finished | Jul 25 07:42:43 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-2eed26a6-8407-4f00-a34f-8b99438c0d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632105058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3632105058 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.835705020 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 59057431 ps |
| CPU time | 7.49 seconds |
| Started | Jul 25 07:41:17 PM PDT 24 |
| Finished | Jul 25 07:41:25 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-e7c2494f-3e32-4c5d-a2a8-9c8cd8b7cbd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835705020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .835705020 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.2683678902 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 5735402678 ps |
| CPU time | 209.38 seconds |
| Started | Jul 25 07:41:36 PM PDT 24 |
| Finished | Jul 25 07:45:06 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-ea0f08f4-237b-4988-8607-aaef42cecaf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683678902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2683678902 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3737933352 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 11827595152 ps |
| CPU time | 435.42 seconds |
| Started | Jul 25 07:41:34 PM PDT 24 |
| Finished | Jul 25 07:48:50 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-fbeb2379-239d-4b53-8001-e9b045b0a124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737933352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3737933352 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.652791521 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 5945037612 ps |
| CPU time | 261.34 seconds |
| Started | Jul 25 07:41:28 PM PDT 24 |
| Finished | Jul 25 07:45:50 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-a0fc3fe1-71e0-4eae-83a2-61544efdcc73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652791521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_ with_rand_reset.652791521 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.698824737 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 16426724380 ps |
| CPU time | 657.86 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:52:27 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-636b154f-4868-449f-ae18-2df81bdf9c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698824737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.698824737 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3297446580 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 225602276 ps |
| CPU time | 27.15 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:41:57 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-34b53056-c7e7-4a9d-a0b0-acec0241dda4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297446580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3297446580 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1659312514 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 500922251 ps |
| CPU time | 46.52 seconds |
| Started | Jul 25 07:41:31 PM PDT 24 |
| Finished | Jul 25 07:42:18 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-7589e286-9e26-4e82-a3f9-6e2352199415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659312514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1659312514 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3627474459 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 126322841607 ps |
| CPU time | 2318.71 seconds |
| Started | Jul 25 07:41:40 PM PDT 24 |
| Finished | Jul 25 08:20:19 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-bfe598af-ab6b-44f0-9b68-98dafa777d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627474459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.3627474459 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.423236121 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 219877840 ps |
| CPU time | 26.16 seconds |
| Started | Jul 25 07:41:42 PM PDT 24 |
| Finished | Jul 25 07:42:08 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-2fdd3714-d72b-4313-b916-dfaf3917bce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423236121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr .423236121 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.1879327696 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 311590388 ps |
| CPU time | 25.48 seconds |
| Started | Jul 25 07:41:40 PM PDT 24 |
| Finished | Jul 25 07:42:05 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-bdb932d2-4118-4b3e-9c20-868d825fbcd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879327696 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1879327696 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.1975131648 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2607538565 ps |
| CPU time | 88.73 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:42:58 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-cd49b2fd-8019-469e-b96d-c3e3863de50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975131648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.1975131648 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.495459724 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 65519988857 ps |
| CPU time | 637.39 seconds |
| Started | Jul 25 07:41:35 PM PDT 24 |
| Finished | Jul 25 07:52:13 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-7922155d-7035-4c80-82b8-6de1f137658d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495459724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.495459724 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3180768435 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 47265835475 ps |
| CPU time | 781.17 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:54:30 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-c2c5fb0d-8015-4440-a80d-203a5a45dad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180768435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3180768435 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.3386056160 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 155520133 ps |
| CPU time | 15.04 seconds |
| Started | Jul 25 07:41:33 PM PDT 24 |
| Finished | Jul 25 07:41:48 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-ba83fe54-5f0e-4297-afd2-1f1329e3c8f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386056160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.3386056160 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.972572661 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 98716740 ps |
| CPU time | 9.24 seconds |
| Started | Jul 25 07:41:41 PM PDT 24 |
| Finished | Jul 25 07:41:50 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-86f1274d-960c-4e8b-a468-9d31bf9fbb6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972572661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.972572661 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1452744896 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 161910313 ps |
| CPU time | 8.58 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:41:38 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-898e4045-28e3-4e26-bb8c-224f84e415ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452744896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1452744896 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.2419003516 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 6457807119 ps |
| CPU time | 66.94 seconds |
| Started | Jul 25 07:41:31 PM PDT 24 |
| Finished | Jul 25 07:42:38 PM PDT 24 |
| Peak memory | 573836 kb |
| Host | smart-1f4ab66e-9e57-4b7e-9a3c-0eea163ba77f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419003516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2419003516 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3982955259 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 4488696802 ps |
| CPU time | 72.61 seconds |
| Started | Jul 25 07:41:30 PM PDT 24 |
| Finished | Jul 25 07:42:43 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-b075bf79-0edc-44fa-8afe-e16456b5046a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982955259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3982955259 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2342639637 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 47741417 ps |
| CPU time | 6.79 seconds |
| Started | Jul 25 07:41:29 PM PDT 24 |
| Finished | Jul 25 07:41:35 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-d32830fe-992c-432d-acf6-19bc2c1410b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342639637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.2342639637 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.1004283178 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 1598672446 ps |
| CPU time | 143.36 seconds |
| Started | Jul 25 07:41:40 PM PDT 24 |
| Finished | Jul 25 07:44:03 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-3c75b0c5-1e70-48a2-9187-4a60d306c941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004283178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1004283178 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.735528597 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 1968349627 ps |
| CPU time | 164.68 seconds |
| Started | Jul 25 07:41:39 PM PDT 24 |
| Finished | Jul 25 07:44:24 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-91b1c553-7fd0-4e09-b8f5-80d993e8ac3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735528597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.735528597 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.70011453 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 105840121 ps |
| CPU time | 7.08 seconds |
| Started | Jul 25 07:41:38 PM PDT 24 |
| Finished | Jul 25 07:41:46 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-cbe4d974-dbb3-433d-9d1f-89199bfc48b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70011453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_w ith_rand_reset.70011453 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.452715340 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 433089138 ps |
| CPU time | 132.41 seconds |
| Started | Jul 25 07:41:41 PM PDT 24 |
| Finished | Jul 25 07:43:53 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-c22865f3-1c97-4699-9950-36d0339f3051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452715340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_reset_error.452715340 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1398653374 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 179474424 ps |
| CPU time | 21.04 seconds |
| Started | Jul 25 07:41:39 PM PDT 24 |
| Finished | Jul 25 07:42:00 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-45db6738-cbb0-4c4b-a19e-5ce1bec07950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398653374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1398653374 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1657683030 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 11710976140 ps |
| CPU time | 733.43 seconds |
| Started | Jul 25 07:28:15 PM PDT 24 |
| Finished | Jul 25 07:40:29 PM PDT 24 |
| Peak memory | 645536 kb |
| Host | smart-f4ed450b-dab9-4d81-ac45-5bd2efea2758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657683030 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.1657683030 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2074161647 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 4198388474 ps |
| CPU time | 340.31 seconds |
| Started | Jul 25 07:28:11 PM PDT 24 |
| Finished | Jul 25 07:33:51 PM PDT 24 |
| Peak memory | 598248 kb |
| Host | smart-5685f45a-f803-4157-833b-6202efe446dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074161647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2074161647 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3498572199 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 26173186706 ps |
| CPU time | 4841.61 seconds |
| Started | Jul 25 07:27:52 PM PDT 24 |
| Finished | Jul 25 08:48:34 PM PDT 24 |
| Peak memory | 592768 kb |
| Host | smart-f79c5902-2b8f-477d-8bd8-d1f31ddf2e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498572199 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3498572199 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.2655955952 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4672868521 ps |
| CPU time | 422.36 seconds |
| Started | Jul 25 07:27:59 PM PDT 24 |
| Finished | Jul 25 07:35:02 PM PDT 24 |
| Peak memory | 598312 kb |
| Host | smart-a08ee7b2-75fa-4e28-8e8d-d3d82069e5f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655955952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.2655955952 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.294923680 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 2147446261 ps |
| CPU time | 92.18 seconds |
| Started | Jul 25 07:28:02 PM PDT 24 |
| Finished | Jul 25 07:29:34 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-c2f7a252-e260-4a4d-9403-793bb0534b4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294923680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.294923680 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1813181411 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 24277750606 ps |
| CPU time | 437.15 seconds |
| Started | Jul 25 07:28:01 PM PDT 24 |
| Finished | Jul 25 07:35:18 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-c89019e1-4074-4022-88b0-740397ffa24f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813181411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1813181411 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1290786014 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 649328891 ps |
| CPU time | 26.47 seconds |
| Started | Jul 25 07:27:59 PM PDT 24 |
| Finished | Jul 25 07:28:26 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-1eb71c39-3989-47ba-812f-961f58e7a17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290786014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1290786014 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1903918765 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 605398310 ps |
| CPU time | 25.28 seconds |
| Started | Jul 25 07:27:59 PM PDT 24 |
| Finished | Jul 25 07:28:24 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-9cb74ac4-896c-4ed2-8b01-d874f372f53a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903918765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1903918765 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.3915490002 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 1854713453 ps |
| CPU time | 64.84 seconds |
| Started | Jul 25 07:27:57 PM PDT 24 |
| Finished | Jul 25 07:29:02 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-0d880ec3-1c17-4078-9a0d-27a86b58614a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915490002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.3915490002 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1882130126 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 6619127056 ps |
| CPU time | 68.32 seconds |
| Started | Jul 25 07:28:01 PM PDT 24 |
| Finished | Jul 25 07:29:09 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-324b148b-1bcf-4b58-bca3-2f84589119bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882130126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1882130126 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2261080652 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 56897162840 ps |
| CPU time | 910.33 seconds |
| Started | Jul 25 07:28:53 PM PDT 24 |
| Finished | Jul 25 07:44:03 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-03a0d4f3-4e00-4c55-a2d2-1b67cdd5b3bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261080652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2261080652 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2792001202 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 64518564 ps |
| CPU time | 8.47 seconds |
| Started | Jul 25 07:28:05 PM PDT 24 |
| Finished | Jul 25 07:28:14 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-3bb6304c-dbb8-4e73-86b7-610869ff95df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792001202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2792001202 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.1784562660 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 446025926 ps |
| CPU time | 35.36 seconds |
| Started | Jul 25 07:28:02 PM PDT 24 |
| Finished | Jul 25 07:28:38 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-403f135e-f7e3-40b3-aff0-9436b8633828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784562660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1784562660 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2734717481 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 43757104 ps |
| CPU time | 5.87 seconds |
| Started | Jul 25 07:27:49 PM PDT 24 |
| Finished | Jul 25 07:27:55 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-52691fd9-27ba-43bf-b59c-70dc8bbd80c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734717481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2734717481 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.168091816 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 9084495977 ps |
| CPU time | 89.14 seconds |
| Started | Jul 25 07:28:00 PM PDT 24 |
| Finished | Jul 25 07:29:29 PM PDT 24 |
| Peak memory | 573800 kb |
| Host | smart-72d9f370-3672-44b7-b4b8-8dd3c6bc0140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168091816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.168091816 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.653920454 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 5449253057 ps |
| CPU time | 93.53 seconds |
| Started | Jul 25 07:28:00 PM PDT 24 |
| Finished | Jul 25 07:29:33 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-9150a1e8-602d-42e2-8b40-c347b061bb53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653920454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.653920454 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3440619100 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 41505326 ps |
| CPU time | 5.8 seconds |
| Started | Jul 25 07:27:52 PM PDT 24 |
| Finished | Jul 25 07:27:58 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-64ee8a69-0426-4204-8e91-f83e2c487eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440619100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3440619100 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.762580355 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 14440294935 ps |
| CPU time | 526.46 seconds |
| Started | Jul 25 07:28:13 PM PDT 24 |
| Finished | Jul 25 07:37:00 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-ab5563b4-d5de-4460-95e8-7576b6be4e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762580355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.762580355 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.835768324 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 738121514 ps |
| CPU time | 55.41 seconds |
| Started | Jul 25 07:28:10 PM PDT 24 |
| Finished | Jul 25 07:29:05 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-220d01eb-eb82-415c-aed4-991aa12346bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835768324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.835768324 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1964084150 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 772567108 ps |
| CPU time | 250.4 seconds |
| Started | Jul 25 07:28:14 PM PDT 24 |
| Finished | Jul 25 07:32:24 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-cad62193-4ff1-458b-bc9d-ecec66a55f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964084150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.1964084150 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.4225734769 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1470367800 ps |
| CPU time | 188.95 seconds |
| Started | Jul 25 07:28:15 PM PDT 24 |
| Finished | Jul 25 07:31:24 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-94ca618a-d905-45e9-a8c4-8fe20b783dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225734769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.4225734769 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.77321912 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 954143434 ps |
| CPU time | 39.59 seconds |
| Started | Jul 25 07:28:00 PM PDT 24 |
| Finished | Jul 25 07:28:40 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-0d830467-6012-4532-ab1c-f89d880cd9d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77321912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.77321912 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.523857690 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 2731910024 ps |
| CPU time | 112.79 seconds |
| Started | Jul 25 07:41:43 PM PDT 24 |
| Finished | Jul 25 07:43:36 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-72ae49be-d7d0-45bc-b7fc-82691d863d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523857690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device. 523857690 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.284781872 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 91663273555 ps |
| CPU time | 1541.91 seconds |
| Started | Jul 25 07:41:42 PM PDT 24 |
| Finished | Jul 25 08:07:25 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-688ce32f-91fa-48e3-9e3e-2db83ec51c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284781872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_d evice_slow_rsp.284781872 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.2734241405 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 202682828 ps |
| CPU time | 22.78 seconds |
| Started | Jul 25 07:41:51 PM PDT 24 |
| Finished | Jul 25 07:42:13 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-c3271593-6e3d-43a0-b446-74e1456beb8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734241405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.2734241405 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.1738422836 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 1696374297 ps |
| CPU time | 52.4 seconds |
| Started | Jul 25 07:41:39 PM PDT 24 |
| Finished | Jul 25 07:42:32 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-31fee17d-a29f-4006-8c7c-829283515e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738422836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1738422836 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.1644404176 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 2115166613 ps |
| CPU time | 75.69 seconds |
| Started | Jul 25 07:41:41 PM PDT 24 |
| Finished | Jul 25 07:42:57 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-798f8406-7c57-46ad-bb0b-de8c0e9e2d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644404176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.1644404176 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1392541353 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 9029866962 ps |
| CPU time | 88.87 seconds |
| Started | Jul 25 07:41:39 PM PDT 24 |
| Finished | Jul 25 07:43:08 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-e6718197-cc19-4bc3-867a-0c26c509ddb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392541353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1392541353 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2685565934 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 60122779569 ps |
| CPU time | 916.57 seconds |
| Started | Jul 25 07:41:40 PM PDT 24 |
| Finished | Jul 25 07:56:57 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-19aafa65-5ec9-467a-9cd2-fa589988d87c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685565934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2685565934 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3450177993 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 583014052 ps |
| CPU time | 47.87 seconds |
| Started | Jul 25 07:41:42 PM PDT 24 |
| Finished | Jul 25 07:42:30 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-3fb21599-55f3-4558-8d40-5aaa571e432a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450177993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3450177993 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.2473966627 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 2723654730 ps |
| CPU time | 78.52 seconds |
| Started | Jul 25 07:41:43 PM PDT 24 |
| Finished | Jul 25 07:43:01 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-c192014f-dadd-4b29-afdd-818c285027d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473966627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2473966627 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.2125183074 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 242184288 ps |
| CPU time | 9.98 seconds |
| Started | Jul 25 07:41:40 PM PDT 24 |
| Finished | Jul 25 07:41:50 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-6fbe1fd0-8e4f-47b6-96f4-3f0cb0b8a543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125183074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.2125183074 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2139732687 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 4783644448 ps |
| CPU time | 48.6 seconds |
| Started | Jul 25 07:41:41 PM PDT 24 |
| Finished | Jul 25 07:42:30 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-68cc4cbb-a4fa-476b-b98f-775a83aebd48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139732687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2139732687 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3548432197 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 4039331335 ps |
| CPU time | 66.3 seconds |
| Started | Jul 25 07:41:42 PM PDT 24 |
| Finished | Jul 25 07:42:48 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-9e364ddb-63ea-4c75-911c-be0ac620d3ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548432197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3548432197 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.351391663 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 40603106 ps |
| CPU time | 5.94 seconds |
| Started | Jul 25 07:41:39 PM PDT 24 |
| Finished | Jul 25 07:41:45 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-6db3a22a-5c96-4d26-a147-a6bed2d7c9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351391663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays .351391663 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.319490456 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1113111010 ps |
| CPU time | 117.51 seconds |
| Started | Jul 25 07:41:52 PM PDT 24 |
| Finished | Jul 25 07:43:50 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-883ebc8e-20a3-464f-915c-98b593bef320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319490456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.319490456 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.271332391 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3002114368 ps |
| CPU time | 216 seconds |
| Started | Jul 25 07:41:52 PM PDT 24 |
| Finished | Jul 25 07:45:28 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-db79d438-fa2c-427b-9434-17247c7f60c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271332391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.271332391 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3774615591 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 141283282 ps |
| CPU time | 62.89 seconds |
| Started | Jul 25 07:41:51 PM PDT 24 |
| Finished | Jul 25 07:42:54 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-564aab9e-eab6-4a40-bee0-a71eb2c314eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774615591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3774615591 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1069370470 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3341448878 ps |
| CPU time | 227.7 seconds |
| Started | Jul 25 07:41:49 PM PDT 24 |
| Finished | Jul 25 07:45:37 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-8f02779a-a731-4547-9029-314c0f028913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069370470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.1069370470 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2247462425 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 242150399 ps |
| CPU time | 13.64 seconds |
| Started | Jul 25 07:41:50 PM PDT 24 |
| Finished | Jul 25 07:42:04 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-c2b6dd29-70de-4635-9513-feba2ced0d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247462425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2247462425 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.1152639198 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 374666708 ps |
| CPU time | 35.71 seconds |
| Started | Jul 25 07:41:50 PM PDT 24 |
| Finished | Jul 25 07:42:26 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-8e780c87-f52a-4fa4-b9a6-5444afb87e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152639198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .1152639198 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3909710815 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 278867258 ps |
| CPU time | 28.34 seconds |
| Started | Jul 25 07:41:49 PM PDT 24 |
| Finished | Jul 25 07:42:18 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-87250b29-9e13-4e42-b628-103d5080ba60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909710815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3909710815 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.800535424 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 2572262913 ps |
| CPU time | 87.45 seconds |
| Started | Jul 25 07:41:54 PM PDT 24 |
| Finished | Jul 25 07:43:22 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-3cab823c-f246-46f6-8c67-2a983055e9be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800535424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.800535424 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.1896682057 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 1242649748 ps |
| CPU time | 41.8 seconds |
| Started | Jul 25 07:41:48 PM PDT 24 |
| Finished | Jul 25 07:42:30 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-1596c88d-3863-4f8d-9f88-558f926835c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896682057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.1896682057 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3434179065 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 30668155165 ps |
| CPU time | 337.8 seconds |
| Started | Jul 25 07:41:52 PM PDT 24 |
| Finished | Jul 25 07:47:30 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-97ccd830-9f5f-4b15-a253-ffbe56797eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434179065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3434179065 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2665614185 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 16801776425 ps |
| CPU time | 283.59 seconds |
| Started | Jul 25 07:41:52 PM PDT 24 |
| Finished | Jul 25 07:46:35 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-095edcc1-4209-4353-9ae6-5a725527396a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665614185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2665614185 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1979245082 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 546231961 ps |
| CPU time | 49.89 seconds |
| Started | Jul 25 07:41:53 PM PDT 24 |
| Finished | Jul 25 07:42:43 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-22c791ef-bc59-47cd-9b5d-924b3878a541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979245082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1979245082 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.2995319751 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 577613404 ps |
| CPU time | 44.7 seconds |
| Started | Jul 25 07:41:49 PM PDT 24 |
| Finished | Jul 25 07:42:34 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-65b5eca6-e421-4c46-a91d-f46d0f3ef2b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995319751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2995319751 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.2871218182 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 186757020 ps |
| CPU time | 8.17 seconds |
| Started | Jul 25 07:41:53 PM PDT 24 |
| Finished | Jul 25 07:42:01 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-4bc395d0-0eff-45bd-b0ca-d715b08debc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871218182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2871218182 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2259840721 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 8659816137 ps |
| CPU time | 88.23 seconds |
| Started | Jul 25 07:41:49 PM PDT 24 |
| Finished | Jul 25 07:43:17 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-08b8a91b-b05a-41b8-901f-c76d228c10f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259840721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2259840721 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1417573955 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 5936211840 ps |
| CPU time | 92.78 seconds |
| Started | Jul 25 07:41:50 PM PDT 24 |
| Finished | Jul 25 07:43:22 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-3e034b29-3b22-49b3-9334-8e3d71a26847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417573955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1417573955 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2098114519 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 49518915 ps |
| CPU time | 6.45 seconds |
| Started | Jul 25 07:41:49 PM PDT 24 |
| Finished | Jul 25 07:41:55 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-6e1dc0d7-4438-4a8d-a592-06871627b779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098114519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.2098114519 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1387924724 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3477008206 ps |
| CPU time | 314.04 seconds |
| Started | Jul 25 07:42:03 PM PDT 24 |
| Finished | Jul 25 07:47:17 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-e354b3ac-abb9-472e-a585-d0ca60624564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387924724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1387924724 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2563770983 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 8215030050 ps |
| CPU time | 310.65 seconds |
| Started | Jul 25 07:42:05 PM PDT 24 |
| Finished | Jul 25 07:47:15 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-b764eea3-8898-4b29-abfc-f3f98a3d2064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563770983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2563770983 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4053920690 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 82197875 ps |
| CPU time | 59.46 seconds |
| Started | Jul 25 07:42:03 PM PDT 24 |
| Finished | Jul 25 07:43:03 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-239709c0-f4d8-441a-ba46-121a2310da9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053920690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.4053920690 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1474350101 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 9043644324 ps |
| CPU time | 485.82 seconds |
| Started | Jul 25 07:42:01 PM PDT 24 |
| Finished | Jul 25 07:50:07 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-611c4505-99cb-4a60-9609-ef92fd1dc2bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474350101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1474350101 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3138034249 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 1302718486 ps |
| CPU time | 51.86 seconds |
| Started | Jul 25 07:41:54 PM PDT 24 |
| Finished | Jul 25 07:42:46 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-eaea28f8-afaa-467a-838d-3a65c392ec81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138034249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3138034249 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1514788891 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 1751099393 ps |
| CPU time | 66.58 seconds |
| Started | Jul 25 07:42:03 PM PDT 24 |
| Finished | Jul 25 07:43:10 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-83d8c5c3-47e2-41b0-832b-f12987dac4a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514788891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1514788891 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3331287635 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 52440662355 ps |
| CPU time | 952.01 seconds |
| Started | Jul 25 07:42:01 PM PDT 24 |
| Finished | Jul 25 07:57:54 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-0d705adf-babf-4329-8ae0-fb4db4bf1654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331287635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3331287635 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.1586741461 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 651250518 ps |
| CPU time | 27.98 seconds |
| Started | Jul 25 07:42:18 PM PDT 24 |
| Finished | Jul 25 07:42:46 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-f9cec279-e6cf-4909-86d1-3a02bd4c8429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586741461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.1586741461 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.4262431463 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 197201391 ps |
| CPU time | 10.73 seconds |
| Started | Jul 25 07:42:19 PM PDT 24 |
| Finished | Jul 25 07:42:30 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-54bb8141-50ac-49c9-94c1-4ac5d3de8709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262431463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.4262431463 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.3360161726 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 247352898 ps |
| CPU time | 22.31 seconds |
| Started | Jul 25 07:42:04 PM PDT 24 |
| Finished | Jul 25 07:42:26 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-8306fa0d-5a6e-4514-bc19-3cb230c0e49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360161726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.3360161726 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1088309756 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 20276327478 ps |
| CPU time | 217 seconds |
| Started | Jul 25 07:42:01 PM PDT 24 |
| Finished | Jul 25 07:45:38 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-d7b43ed3-2de2-43a2-b322-04badd3acce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088309756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1088309756 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.439490236 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 48766617567 ps |
| CPU time | 788.7 seconds |
| Started | Jul 25 07:42:02 PM PDT 24 |
| Finished | Jul 25 07:55:11 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-0d49d266-e2fb-4717-9d98-9af521072886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439490236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.439490236 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.3573261671 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 588861528 ps |
| CPU time | 44.7 seconds |
| Started | Jul 25 07:42:03 PM PDT 24 |
| Finished | Jul 25 07:42:48 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-7422a4a9-8046-483b-a42e-673d5b6b6202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573261671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.3573261671 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.3138312156 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 1875085654 ps |
| CPU time | 54.26 seconds |
| Started | Jul 25 07:42:18 PM PDT 24 |
| Finished | Jul 25 07:43:13 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-6fb5f7eb-fc4d-4884-b2b5-adfa8efce7bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138312156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.3138312156 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.102599608 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 49104913 ps |
| CPU time | 6.38 seconds |
| Started | Jul 25 07:42:02 PM PDT 24 |
| Finished | Jul 25 07:42:09 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-95a1b51b-06b1-45e5-855e-eee24b257c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102599608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.102599608 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1373364616 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 8811560018 ps |
| CPU time | 90.82 seconds |
| Started | Jul 25 07:42:03 PM PDT 24 |
| Finished | Jul 25 07:43:34 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-d9d3f43b-abeb-40d3-bf3d-f6fe8938fb83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373364616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1373364616 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.902743458 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 5727572968 ps |
| CPU time | 94.52 seconds |
| Started | Jul 25 07:42:03 PM PDT 24 |
| Finished | Jul 25 07:43:38 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-787d39c5-c5a9-4c30-8afe-af41907b4827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902743458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.902743458 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.4038635343 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 46742735 ps |
| CPU time | 6.47 seconds |
| Started | Jul 25 07:42:02 PM PDT 24 |
| Finished | Jul 25 07:42:09 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-9f3aef6e-ca50-497d-8eea-c74fbc8e45d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038635343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.4038635343 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2038944236 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 659999014 ps |
| CPU time | 47.07 seconds |
| Started | Jul 25 07:42:19 PM PDT 24 |
| Finished | Jul 25 07:43:06 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-94c453b1-30ed-4959-85a4-88cf63f0f071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038944236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2038944236 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3561204736 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 7294734772 ps |
| CPU time | 231.02 seconds |
| Started | Jul 25 07:42:21 PM PDT 24 |
| Finished | Jul 25 07:46:12 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-73f0fc09-a0cc-4fc0-bcd0-d29a3020bc15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561204736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.3561204736 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.940427311 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 142275249 ps |
| CPU time | 56.63 seconds |
| Started | Jul 25 07:42:19 PM PDT 24 |
| Finished | Jul 25 07:43:15 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-a8e375ad-f032-46b9-900a-dc176ea45bf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940427311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.940427311 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.686684634 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 7601146371 ps |
| CPU time | 425.69 seconds |
| Started | Jul 25 07:42:18 PM PDT 24 |
| Finished | Jul 25 07:49:24 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-d7331527-9213-4bb2-a680-c482333c098b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686684634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_reset_error.686684634 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.610137233 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 837891320 ps |
| CPU time | 35.17 seconds |
| Started | Jul 25 07:42:17 PM PDT 24 |
| Finished | Jul 25 07:42:52 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-4bb1fffa-ffb0-4da6-be6b-a9d0b9f773da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610137233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.610137233 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.500042319 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 370978124 ps |
| CPU time | 18.23 seconds |
| Started | Jul 25 07:42:41 PM PDT 24 |
| Finished | Jul 25 07:42:59 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-584610af-a025-4279-9048-c4429ed27898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500042319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device. 500042319 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1509751493 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 62112840881 ps |
| CPU time | 1053.47 seconds |
| Started | Jul 25 07:42:42 PM PDT 24 |
| Finished | Jul 25 08:00:15 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-3853da2c-37d9-496f-a169-767ad014de04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509751493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1509751493 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.754629 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 58911530 ps |
| CPU time | 8.27 seconds |
| Started | Jul 25 07:42:43 PM PDT 24 |
| Finished | Jul 25 07:42:51 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-9464ad24-4517-4a2c-8bec-58575e31aa72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr.754629 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.2305679914 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 276404406 ps |
| CPU time | 11.34 seconds |
| Started | Jul 25 07:42:41 PM PDT 24 |
| Finished | Jul 25 07:42:53 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-3dd2d210-66b5-49a6-84fe-3aad9f670eba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305679914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2305679914 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.2569424496 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 609546643 ps |
| CPU time | 50.55 seconds |
| Started | Jul 25 07:42:40 PM PDT 24 |
| Finished | Jul 25 07:43:31 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-2fc5a70a-b057-4783-be9b-a6d379bc5549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569424496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2569424496 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.616774339 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 88834101846 ps |
| CPU time | 956.85 seconds |
| Started | Jul 25 07:42:57 PM PDT 24 |
| Finished | Jul 25 07:58:54 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-350e758e-9aee-4e2f-a3c3-b417f707125c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616774339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.616774339 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.226686878 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 13329312436 ps |
| CPU time | 203.69 seconds |
| Started | Jul 25 07:42:42 PM PDT 24 |
| Finished | Jul 25 07:46:06 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-3c1d273f-f0a4-4976-9e35-3dd339be1834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226686878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.226686878 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2539241908 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 1162393535 ps |
| CPU time | 34.66 seconds |
| Started | Jul 25 07:42:38 PM PDT 24 |
| Finished | Jul 25 07:43:13 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-0650ece4-0729-4c95-a018-53db031c34cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539241908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2539241908 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.4255781631 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 54858356 ps |
| CPU time | 6.85 seconds |
| Started | Jul 25 07:42:18 PM PDT 24 |
| Finished | Jul 25 07:42:25 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-e62c7a86-d661-4ccf-8007-e21a7984616d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255781631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.4255781631 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.2568577905 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 9962834099 ps |
| CPU time | 112.16 seconds |
| Started | Jul 25 07:42:19 PM PDT 24 |
| Finished | Jul 25 07:44:11 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-1f649b42-1c85-4561-8804-503fc4b4c321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568577905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.2568577905 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1022333049 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 5267153577 ps |
| CPU time | 79.14 seconds |
| Started | Jul 25 07:42:19 PM PDT 24 |
| Finished | Jul 25 07:43:38 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-5e9f4174-c435-4802-90d9-d1d07f135cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022333049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1022333049 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.469826610 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 56865477 ps |
| CPU time | 6.39 seconds |
| Started | Jul 25 07:42:17 PM PDT 24 |
| Finished | Jul 25 07:42:24 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-df463801-eadf-44bb-aedd-91ad31f60e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469826610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .469826610 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1565641321 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 8125984241 ps |
| CPU time | 316.04 seconds |
| Started | Jul 25 07:42:42 PM PDT 24 |
| Finished | Jul 25 07:47:58 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-8813692f-8f1f-45e8-91fc-f4268c5c1c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565641321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1565641321 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1552373942 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 96266765 ps |
| CPU time | 12.83 seconds |
| Started | Jul 25 07:42:42 PM PDT 24 |
| Finished | Jul 25 07:42:55 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-00c336ec-2421-4114-b71f-e1d50f63a924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552373942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1552373942 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4103961736 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 9629409698 ps |
| CPU time | 462.88 seconds |
| Started | Jul 25 07:42:39 PM PDT 24 |
| Finished | Jul 25 07:50:23 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-b29f16d8-336b-409a-815e-b7e0fae65a2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103961736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.4103961736 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.920067336 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 6554239765 ps |
| CPU time | 570.21 seconds |
| Started | Jul 25 07:42:58 PM PDT 24 |
| Finished | Jul 25 07:52:29 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-31b14c15-4558-4c33-bdc9-43b1a026a299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920067336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_reset_error.920067336 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1446216570 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1094529204 ps |
| CPU time | 45.44 seconds |
| Started | Jul 25 07:42:39 PM PDT 24 |
| Finished | Jul 25 07:43:25 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-1285d347-fd6e-4073-b4e7-a45915ee4f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446216570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1446216570 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1838197152 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 1428983045 ps |
| CPU time | 60.07 seconds |
| Started | Jul 25 07:42:59 PM PDT 24 |
| Finished | Jul 25 07:43:59 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-1573c6a3-e4a7-4506-9b64-a86942d4bd87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838197152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .1838197152 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3948389739 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 136633831819 ps |
| CPU time | 2482.94 seconds |
| Started | Jul 25 07:43:01 PM PDT 24 |
| Finished | Jul 25 08:24:25 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-879994c2-b099-4f2c-8ddd-3aae03389822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948389739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.3948389739 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1257718543 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 139042318 ps |
| CPU time | 16.92 seconds |
| Started | Jul 25 07:43:00 PM PDT 24 |
| Finished | Jul 25 07:43:17 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-68760b93-295b-4dba-afa9-f13a982b7908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257718543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1257718543 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.2447484663 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 1181660843 ps |
| CPU time | 42.7 seconds |
| Started | Jul 25 07:43:04 PM PDT 24 |
| Finished | Jul 25 07:43:47 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8a2b4201-6a76-4b73-b2a2-728a70c45dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447484663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2447484663 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3256445273 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 404908518 ps |
| CPU time | 15.31 seconds |
| Started | Jul 25 07:42:58 PM PDT 24 |
| Finished | Jul 25 07:43:14 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-447c2e59-2483-4e8b-9843-f17df4d96a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256445273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3256445273 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2616848989 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 11920495377 ps |
| CPU time | 123.43 seconds |
| Started | Jul 25 07:43:00 PM PDT 24 |
| Finished | Jul 25 07:45:04 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-0616c504-ff5c-4f4f-b457-0bd47d0c7305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616848989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2616848989 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.3524156876 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 41282336956 ps |
| CPU time | 736.18 seconds |
| Started | Jul 25 07:43:01 PM PDT 24 |
| Finished | Jul 25 07:55:17 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-475268c5-de41-4f02-8595-ff9f04a95bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524156876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.3524156876 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2680964413 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 99007286 ps |
| CPU time | 10.83 seconds |
| Started | Jul 25 07:42:59 PM PDT 24 |
| Finished | Jul 25 07:43:10 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-1fdc373f-25c3-4f27-93cd-497aad05caae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680964413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2680964413 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.2759444041 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 568463033 ps |
| CPU time | 37.37 seconds |
| Started | Jul 25 07:43:00 PM PDT 24 |
| Finished | Jul 25 07:43:37 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-ba388bf1-d8db-4540-9b81-7045c249105f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759444041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2759444041 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3254987581 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 241335341 ps |
| CPU time | 9.79 seconds |
| Started | Jul 25 07:43:02 PM PDT 24 |
| Finished | Jul 25 07:43:11 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-a7f280f1-e423-49d1-ba84-72b58c5dbe94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254987581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3254987581 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.676739045 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 8671268011 ps |
| CPU time | 85.65 seconds |
| Started | Jul 25 07:43:00 PM PDT 24 |
| Finished | Jul 25 07:44:26 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-762fcf0e-8e95-46cd-a669-5b7163098bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676739045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.676739045 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.729605417 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 5261434281 ps |
| CPU time | 84.34 seconds |
| Started | Jul 25 07:42:59 PM PDT 24 |
| Finished | Jul 25 07:44:23 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-6e9cc32d-aca7-4aee-9761-b9696561216c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729605417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.729605417 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.3219862915 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 46147669 ps |
| CPU time | 6.12 seconds |
| Started | Jul 25 07:43:01 PM PDT 24 |
| Finished | Jul 25 07:43:07 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-84096cde-4671-431b-b5ba-132092488199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219862915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.3219862915 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.2380977280 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 11608591362 ps |
| CPU time | 447.67 seconds |
| Started | Jul 25 07:43:02 PM PDT 24 |
| Finished | Jul 25 07:50:30 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-fc885b42-215e-4add-9f6e-bab397ebc2e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380977280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2380977280 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.305059828 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 3016812054 ps |
| CPU time | 503.64 seconds |
| Started | Jul 25 07:43:00 PM PDT 24 |
| Finished | Jul 25 07:51:24 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-7bc00d1b-b41e-4109-99e8-860b3b7ce9ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305059828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.305059828 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1962701670 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 66098050 ps |
| CPU time | 45.39 seconds |
| Started | Jul 25 07:42:59 PM PDT 24 |
| Finished | Jul 25 07:43:44 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-66a294eb-c11e-4076-8dce-26c7fdd39b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962701670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1962701670 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3524207658 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 1220124378 ps |
| CPU time | 56.07 seconds |
| Started | Jul 25 07:43:02 PM PDT 24 |
| Finished | Jul 25 07:43:58 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-673e1291-860e-47af-bf6d-2e747c623286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524207658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3524207658 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1383992889 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 2103709073 ps |
| CPU time | 85.92 seconds |
| Started | Jul 25 07:43:19 PM PDT 24 |
| Finished | Jul 25 07:44:45 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-8373436a-8800-403b-b231-98ed647b5fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383992889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .1383992889 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.976015574 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 101519421432 ps |
| CPU time | 1777.79 seconds |
| Started | Jul 25 07:43:19 PM PDT 24 |
| Finished | Jul 25 08:12:57 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-3ff0b383-9bbe-4888-947d-01987b0aa6d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976015574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_d evice_slow_rsp.976015574 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.840241137 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 563424661 ps |
| CPU time | 23.53 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:43:46 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-d7455938-4114-481f-827c-c77f51a1fce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840241137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .840241137 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.2036674747 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 2227840251 ps |
| CPU time | 79.46 seconds |
| Started | Jul 25 07:43:19 PM PDT 24 |
| Finished | Jul 25 07:44:39 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-81f04a2c-fba0-45fc-b41f-25d356c80b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036674747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.2036674747 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.2195568479 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 218301756 ps |
| CPU time | 10.82 seconds |
| Started | Jul 25 07:43:04 PM PDT 24 |
| Finished | Jul 25 07:43:15 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-dbda1b3f-54a6-4575-a9e9-005186b680a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195568479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2195568479 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.628828249 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 40900278148 ps |
| CPU time | 415.67 seconds |
| Started | Jul 25 07:43:05 PM PDT 24 |
| Finished | Jul 25 07:50:01 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-11980928-aa28-45bd-ba57-b1f8108a52e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628828249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.628828249 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.2579602960 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 3775389549 ps |
| CPU time | 62.21 seconds |
| Started | Jul 25 07:43:18 PM PDT 24 |
| Finished | Jul 25 07:44:21 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-0d0db6d9-9e6e-470a-a46e-65580b563b5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579602960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.2579602960 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.820239253 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 67477886 ps |
| CPU time | 8.84 seconds |
| Started | Jul 25 07:43:02 PM PDT 24 |
| Finished | Jul 25 07:43:11 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-8014c247-db67-41f2-ad09-dabcdb986c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820239253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_dela ys.820239253 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3605778559 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1639740564 ps |
| CPU time | 42.58 seconds |
| Started | Jul 25 07:43:19 PM PDT 24 |
| Finished | Jul 25 07:44:02 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-cbaf3ebf-a42e-4a13-9de1-800234434332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605778559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3605778559 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.417196048 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 216364886 ps |
| CPU time | 9.6 seconds |
| Started | Jul 25 07:43:02 PM PDT 24 |
| Finished | Jul 25 07:43:12 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-d6e87a01-1ffa-4ca9-9699-556087351b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417196048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.417196048 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3436794005 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 9903280074 ps |
| CPU time | 103.97 seconds |
| Started | Jul 25 07:43:00 PM PDT 24 |
| Finished | Jul 25 07:44:44 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-c0e7a5f3-5f65-45d2-b040-848c841c54ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436794005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3436794005 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2589228295 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 6037318880 ps |
| CPU time | 105.82 seconds |
| Started | Jul 25 07:42:59 PM PDT 24 |
| Finished | Jul 25 07:44:45 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-e343277b-5e18-434f-b77b-07b984835a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589228295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2589228295 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1351968034 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 39783474 ps |
| CPU time | 5.91 seconds |
| Started | Jul 25 07:42:58 PM PDT 24 |
| Finished | Jul 25 07:43:04 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-4472c38c-e604-4934-b7a5-caa5a80ab39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351968034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.1351968034 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.2980506052 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 10438895583 ps |
| CPU time | 403.29 seconds |
| Started | Jul 25 07:43:24 PM PDT 24 |
| Finished | Jul 25 07:50:07 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-22c3873d-5ea8-455e-946b-c13c2e771e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980506052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.2980506052 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.4268802777 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 1531931344 ps |
| CPU time | 52.27 seconds |
| Started | Jul 25 07:43:18 PM PDT 24 |
| Finished | Jul 25 07:44:11 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-426d9c61-b566-442b-99f0-0a9180f0f8c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268802777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.4268802777 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.3013337407 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 134038425 ps |
| CPU time | 61.1 seconds |
| Started | Jul 25 07:43:20 PM PDT 24 |
| Finished | Jul 25 07:44:21 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-cd66bc31-1d22-4f78-8557-b2fc41463ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013337407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.3013337407 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3477408414 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 265042838 ps |
| CPU time | 64.45 seconds |
| Started | Jul 25 07:43:21 PM PDT 24 |
| Finished | Jul 25 07:44:25 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-0bc32791-46de-47a8-9daf-e9dfb74b4a72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477408414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.3477408414 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3689508145 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 1338467943 ps |
| CPU time | 57.54 seconds |
| Started | Jul 25 07:43:21 PM PDT 24 |
| Finished | Jul 25 07:44:19 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-f49a29e8-77ba-47d2-a0ce-f674a6c2b206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689508145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3689508145 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2864694843 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 1524926131 ps |
| CPU time | 53.22 seconds |
| Started | Jul 25 07:43:24 PM PDT 24 |
| Finished | Jul 25 07:44:17 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-2ebc8e79-841f-4134-b919-b78baa19d7ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864694843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2864694843 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2193057879 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 22617869141 ps |
| CPU time | 401.7 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:50:03 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ee625fb2-67e9-4407-88c9-11c0e9efc04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193057879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2193057879 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.340858144 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 1076653725 ps |
| CPU time | 39.84 seconds |
| Started | Jul 25 07:48:15 PM PDT 24 |
| Finished | Jul 25 07:48:55 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-7f22d837-0582-40ab-b4bc-6ad8c2079492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340858144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr .340858144 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.4186192549 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 2789187033 ps |
| CPU time | 97.99 seconds |
| Started | Jul 25 07:43:23 PM PDT 24 |
| Finished | Jul 25 07:45:01 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-cba8ea63-cb77-4fff-8053-d1898018875f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186192549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4186192549 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.3225379807 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1113939328 ps |
| CPU time | 38.61 seconds |
| Started | Jul 25 07:43:24 PM PDT 24 |
| Finished | Jul 25 07:44:03 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-28d683e3-3c12-454b-94ac-32edacdb3d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225379807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3225379807 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.203930025 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 79369099770 ps |
| CPU time | 834.3 seconds |
| Started | Jul 25 07:43:57 PM PDT 24 |
| Finished | Jul 25 07:57:52 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-2035cc24-0e81-45fc-8bf0-0d9d2ca1647d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203930025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.203930025 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2244948164 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 67262120270 ps |
| CPU time | 1151.46 seconds |
| Started | Jul 25 07:43:19 PM PDT 24 |
| Finished | Jul 25 08:02:31 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-ff259c90-4c46-46da-8eed-84232b61d0e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244948164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2244948164 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2595609813 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 557644063 ps |
| CPU time | 47.41 seconds |
| Started | Jul 25 07:43:21 PM PDT 24 |
| Finished | Jul 25 07:44:09 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-c1efccab-6a6f-40ec-b6dd-4959c3695a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595609813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.2595609813 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.2048336517 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2173871742 ps |
| CPU time | 60.53 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:44:22 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-46ec98d3-5cee-4dac-bd6f-07cb57288a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048336517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2048336517 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.4003852629 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 193969785 ps |
| CPU time | 8.56 seconds |
| Started | Jul 25 07:43:23 PM PDT 24 |
| Finished | Jul 25 07:43:31 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-fd063948-560e-40bc-bb1d-442a058559d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003852629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.4003852629 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.1553986383 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 8190184623 ps |
| CPU time | 84.26 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:44:46 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-7c54b026-bf6a-4fd8-9262-c7661ab581a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553986383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.1553986383 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3138632906 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 3613066389 ps |
| CPU time | 61.95 seconds |
| Started | Jul 25 07:43:20 PM PDT 24 |
| Finished | Jul 25 07:44:22 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-944d8f7e-4687-49f5-a3c0-d37b1fc7047c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138632906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.3138632906 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1944644419 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 41434394 ps |
| CPU time | 5.77 seconds |
| Started | Jul 25 07:43:23 PM PDT 24 |
| Finished | Jul 25 07:43:29 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e4022fc1-6b1b-4563-8135-37f5ba8bc26a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944644419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1944644419 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3767742384 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 2818152932 ps |
| CPU time | 102.75 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:45:04 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-3a826e68-adec-4cf6-baa2-dc7cec3cd1b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767742384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3767742384 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3836207106 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 3417439954 ps |
| CPU time | 112.65 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:45:15 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-c1bc38c0-30fe-4d8b-8e58-3a25cbf872d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836207106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3836207106 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4218233081 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 768523041 ps |
| CPU time | 299.3 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:48:22 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d17a11cb-2e1b-4619-a327-7789d2ae3cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218233081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.4218233081 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2435437451 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3089929694 ps |
| CPU time | 185.55 seconds |
| Started | Jul 25 07:43:25 PM PDT 24 |
| Finished | Jul 25 07:46:31 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-4ca43089-17fa-47f5-8714-0db64a5d3a52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435437451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.2435437451 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2361582741 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 85469151 ps |
| CPU time | 6.56 seconds |
| Started | Jul 25 07:43:22 PM PDT 24 |
| Finished | Jul 25 07:43:29 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-b7f5a65d-d23b-4b5f-bbaf-ad22e37c5bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361582741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2361582741 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.4106649752 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 721514327 ps |
| CPU time | 34.66 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:44:06 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-e859525d-9f99-4296-a656-3e279e7fda07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106649752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .4106649752 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3965306492 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 67553594017 ps |
| CPU time | 1237.31 seconds |
| Started | Jul 25 07:43:30 PM PDT 24 |
| Finished | Jul 25 08:04:07 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-c51b52c1-3e20-402d-b05f-106c86760f22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965306492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3965306492 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1930760654 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 126110496 ps |
| CPU time | 8.17 seconds |
| Started | Jul 25 07:43:32 PM PDT 24 |
| Finished | Jul 25 07:43:40 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-66a43807-bd7d-47e2-87fe-e4c22d6e02a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930760654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1930760654 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.1551199644 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 2248000364 ps |
| CPU time | 70.27 seconds |
| Started | Jul 25 07:43:40 PM PDT 24 |
| Finished | Jul 25 07:44:50 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-4092b82a-e668-41ad-8e0a-fccc175769e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551199644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1551199644 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.305067549 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 1031577803 ps |
| CPU time | 38.39 seconds |
| Started | Jul 25 07:43:29 PM PDT 24 |
| Finished | Jul 25 07:44:08 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-9fea7198-1753-461b-882b-8f38c7418d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305067549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.305067549 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1357130359 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 36170520836 ps |
| CPU time | 356.93 seconds |
| Started | Jul 25 07:43:29 PM PDT 24 |
| Finished | Jul 25 07:49:26 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-ab9f8bf1-1f35-4400-8b84-655e897599f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357130359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1357130359 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3615282524 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 33684982502 ps |
| CPU time | 555.15 seconds |
| Started | Jul 25 07:43:35 PM PDT 24 |
| Finished | Jul 25 07:52:50 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-94943e71-fa2b-474a-b3bf-b291f4a99162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615282524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3615282524 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.4002310540 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 189801187 ps |
| CPU time | 15.55 seconds |
| Started | Jul 25 07:43:37 PM PDT 24 |
| Finished | Jul 25 07:43:53 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-4a049c2e-ae94-4a27-94ce-a27204d847b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002310540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.4002310540 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.3323677290 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 1176208748 ps |
| CPU time | 32.35 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:44:03 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-397edddd-026b-4e48-9676-b838b3ca618f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323677290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3323677290 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.2691499874 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 41080881 ps |
| CPU time | 5.79 seconds |
| Started | Jul 25 07:43:23 PM PDT 24 |
| Finished | Jul 25 07:43:29 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-3d1fed99-1a5a-47aa-868d-fa6ec9122bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691499874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2691499874 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.620318637 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 7995017706 ps |
| CPU time | 79.35 seconds |
| Started | Jul 25 07:43:33 PM PDT 24 |
| Finished | Jul 25 07:44:53 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-4fa35663-105c-4a04-b1d0-0c00627b0479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620318637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.620318637 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2759265088 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 6203860200 ps |
| CPU time | 94.09 seconds |
| Started | Jul 25 07:43:36 PM PDT 24 |
| Finished | Jul 25 07:45:10 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-11010c8a-120e-4a1e-8180-9909d106a1bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759265088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2759265088 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2996375472 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 54927401 ps |
| CPU time | 6.67 seconds |
| Started | Jul 25 07:43:34 PM PDT 24 |
| Finished | Jul 25 07:43:41 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-438e3cca-61cb-497f-ba08-ac59b5ec1650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996375472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2996375472 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.903851066 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3867059313 ps |
| CPU time | 127.91 seconds |
| Started | Jul 25 07:43:36 PM PDT 24 |
| Finished | Jul 25 07:45:44 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-fd498cad-9e68-47e3-a0fe-df61cdc96a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903851066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.903851066 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2105257943 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 1320407204 ps |
| CPU time | 84.81 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:44:56 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-73b17e4e-c6ff-4ec1-87cf-f9cd0c513ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105257943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2105257943 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1972238459 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4747536331 ps |
| CPU time | 598.39 seconds |
| Started | Jul 25 07:43:35 PM PDT 24 |
| Finished | Jul 25 07:53:33 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-d178a5f8-e427-4458-b0cb-b7eb9e115ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972238459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1972238459 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2062292062 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 904577504 ps |
| CPU time | 217.13 seconds |
| Started | Jul 25 07:43:44 PM PDT 24 |
| Finished | Jul 25 07:47:21 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-cd291742-0a4a-4400-a312-59a1f468953b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062292062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.2062292062 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2673416990 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 669437664 ps |
| CPU time | 30.23 seconds |
| Started | Jul 25 07:43:28 PM PDT 24 |
| Finished | Jul 25 07:43:58 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f5391413-5c26-4565-843f-fd7d9ee9b555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673416990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2673416990 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.53405238 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 363320696 ps |
| CPU time | 37.36 seconds |
| Started | Jul 25 07:43:34 PM PDT 24 |
| Finished | Jul 25 07:44:12 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-b43629d6-097e-4ae8-8b7a-fc9d8a0e2b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53405238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device.53405238 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1442651498 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 129198653240 ps |
| CPU time | 2154.49 seconds |
| Started | Jul 25 07:43:32 PM PDT 24 |
| Finished | Jul 25 08:19:27 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-169bf743-a537-4ff6-bdc4-e20027c152ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442651498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.1442651498 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.858580839 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 179697508 ps |
| CPU time | 20.16 seconds |
| Started | Jul 25 07:43:44 PM PDT 24 |
| Finished | Jul 25 07:44:05 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-3ff007ea-55ca-4ee7-bddd-f9f1d8ac4424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858580839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr .858580839 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.499303872 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 97872917 ps |
| CPU time | 6.69 seconds |
| Started | Jul 25 07:43:34 PM PDT 24 |
| Finished | Jul 25 07:43:41 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-2af3cb6a-2a6d-4bcb-a0d5-f9c451d44946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499303872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.499303872 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.3565294871 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 620386084 ps |
| CPU time | 21.83 seconds |
| Started | Jul 25 07:43:43 PM PDT 24 |
| Finished | Jul 25 07:44:05 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-fb68ebab-b741-4bbe-a359-0b21937d75ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565294871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.3565294871 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3458632374 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 94688097326 ps |
| CPU time | 957.85 seconds |
| Started | Jul 25 07:43:35 PM PDT 24 |
| Finished | Jul 25 07:59:33 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-0383ca45-4ab0-4320-95cc-66427a67b6a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458632374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3458632374 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.605045696 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 20924807670 ps |
| CPU time | 343.92 seconds |
| Started | Jul 25 07:43:30 PM PDT 24 |
| Finished | Jul 25 07:49:14 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-6841734d-d57d-44dc-8660-ee794f7be93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605045696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.605045696 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.115656057 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 602248335 ps |
| CPU time | 48.32 seconds |
| Started | Jul 25 07:43:44 PM PDT 24 |
| Finished | Jul 25 07:44:32 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-79b8cf26-2e24-4d6d-84c6-b4f0cc18e130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115656057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.115656057 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.869465556 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 357616554 ps |
| CPU time | 25.67 seconds |
| Started | Jul 25 07:43:37 PM PDT 24 |
| Finished | Jul 25 07:44:03 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-95d66593-2f59-4ca2-99c7-d7cc11716b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869465556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.869465556 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.880224061 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 171539960 ps |
| CPU time | 7.86 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:43:39 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-2dfecd22-7773-4de1-8bb5-afbd2a6520c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880224061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.880224061 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3099187640 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 9124587971 ps |
| CPU time | 96.09 seconds |
| Started | Jul 25 07:43:36 PM PDT 24 |
| Finished | Jul 25 07:45:12 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-642281bc-3096-4cda-bcc6-2bc9743b5dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099187640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.3099187640 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2451511027 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 5592925174 ps |
| CPU time | 94.65 seconds |
| Started | Jul 25 07:43:30 PM PDT 24 |
| Finished | Jul 25 07:45:05 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-ebfb0234-5bd0-4722-803d-33a3c345dad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451511027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2451511027 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2067829364 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 49821101 ps |
| CPU time | 6.42 seconds |
| Started | Jul 25 07:43:39 PM PDT 24 |
| Finished | Jul 25 07:43:46 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-71ef8999-1cf6-4c59-b899-5c0d2e8811f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067829364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2067829364 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.626642939 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 10037703186 ps |
| CPU time | 342.58 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:49:14 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-d30c3feb-bb29-4b3e-9122-4ecb1ca70f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626642939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.626642939 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2175726951 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 13595563154 ps |
| CPU time | 496.6 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:51:48 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-f924cd4c-81fe-4510-978d-26b0ae28afb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175726951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2175726951 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.4004510671 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 4562139481 ps |
| CPU time | 313.45 seconds |
| Started | Jul 25 07:43:40 PM PDT 24 |
| Finished | Jul 25 07:48:54 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-550a18f8-2101-4890-85a4-51b3fec86219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004510671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.4004510671 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1478557312 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 86101470 ps |
| CPU time | 19.07 seconds |
| Started | Jul 25 07:43:28 PM PDT 24 |
| Finished | Jul 25 07:43:48 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-71539191-2e37-418a-8c36-a74a7b06381e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478557312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1478557312 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3839845850 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 203930397 ps |
| CPU time | 12.01 seconds |
| Started | Jul 25 07:43:31 PM PDT 24 |
| Finished | Jul 25 07:43:43 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-afa143cf-96f1-46da-bca1-4962a7d027e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839845850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3839845850 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2624223294 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 1187288071 ps |
| CPU time | 85.4 seconds |
| Started | Jul 25 07:43:41 PM PDT 24 |
| Finished | Jul 25 07:45:06 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-dd97504f-1f0c-493e-bfdf-3187191c8391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624223294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2624223294 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3585805942 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 129566666661 ps |
| CPU time | 2279.36 seconds |
| Started | Jul 25 07:43:40 PM PDT 24 |
| Finished | Jul 25 08:21:40 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-aba20f37-7428-4672-a8d4-fc0a1656a445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585805942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3585805942 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.887461590 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 72460649 ps |
| CPU time | 6.46 seconds |
| Started | Jul 25 07:43:41 PM PDT 24 |
| Finished | Jul 25 07:43:48 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-ec79f039-c47a-4f7b-974c-efd3549dd1d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887461590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_addr .887461590 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2634414648 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 82122328 ps |
| CPU time | 8.83 seconds |
| Started | Jul 25 07:43:51 PM PDT 24 |
| Finished | Jul 25 07:44:00 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-f233f1eb-6141-4e4f-9b73-0c22aa965c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634414648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2634414648 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.2432750797 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 1943233670 ps |
| CPU time | 59.18 seconds |
| Started | Jul 25 07:43:42 PM PDT 24 |
| Finished | Jul 25 07:44:42 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-155681ae-a2cd-4542-a853-66c40f3a7917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432750797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2432750797 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.63380000 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 93640936708 ps |
| CPU time | 943.49 seconds |
| Started | Jul 25 07:43:52 PM PDT 24 |
| Finished | Jul 25 07:59:36 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-9bbbba88-a0e5-491d-bada-84657223d635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63380000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.63380000 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.2741854838 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 69735775878 ps |
| CPU time | 1161.45 seconds |
| Started | Jul 25 07:43:42 PM PDT 24 |
| Finished | Jul 25 08:03:04 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-2b358945-c471-4350-a9c5-9b90d04ef099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741854838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.2741854838 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1159603128 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 355497756 ps |
| CPU time | 29.53 seconds |
| Started | Jul 25 07:43:53 PM PDT 24 |
| Finished | Jul 25 07:44:22 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-fb47ece6-2db1-45cd-815d-d63343006b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159603128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.1159603128 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.765636241 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 545353379 ps |
| CPU time | 37.56 seconds |
| Started | Jul 25 07:43:44 PM PDT 24 |
| Finished | Jul 25 07:44:22 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-db322fec-2f65-4e12-9b59-b0379007c77f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765636241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.765636241 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.1945246211 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 203487178 ps |
| CPU time | 8.85 seconds |
| Started | Jul 25 07:43:34 PM PDT 24 |
| Finished | Jul 25 07:43:43 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-023ed431-0a25-4fee-b296-66dd84c294e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945246211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1945246211 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2563653721 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 5832753278 ps |
| CPU time | 62.72 seconds |
| Started | Jul 25 07:43:40 PM PDT 24 |
| Finished | Jul 25 07:44:43 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-67846f76-623f-4758-babc-d41101e3e95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563653721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2563653721 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2377008467 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 3957880306 ps |
| CPU time | 66.75 seconds |
| Started | Jul 25 07:43:43 PM PDT 24 |
| Finished | Jul 25 07:44:50 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-fb2c6e56-6cc0-42ba-8e81-84f70b3c9abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377008467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2377008467 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.4281810409 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 43088662 ps |
| CPU time | 6.28 seconds |
| Started | Jul 25 07:43:35 PM PDT 24 |
| Finished | Jul 25 07:43:42 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-0d120e16-4979-4065-8c9b-2243bf2ee449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281810409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.4281810409 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.3918916515 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2677645958 ps |
| CPU time | 94.14 seconds |
| Started | Jul 25 07:43:45 PM PDT 24 |
| Finished | Jul 25 07:45:19 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-e8b3a81b-7bc4-48af-853b-815ae875dea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918916515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3918916515 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2361137331 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 8856986852 ps |
| CPU time | 312.47 seconds |
| Started | Jul 25 07:43:41 PM PDT 24 |
| Finished | Jul 25 07:48:53 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-4adc75cd-efae-46d3-b58a-eb05e6fd2a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361137331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2361137331 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1490488559 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 481153251 ps |
| CPU time | 135.08 seconds |
| Started | Jul 25 07:43:57 PM PDT 24 |
| Finished | Jul 25 07:46:13 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-5df8ebbb-8970-474b-bb01-630209900502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490488559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1490488559 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.494956209 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 9998529538 ps |
| CPU time | 458.94 seconds |
| Started | Jul 25 07:43:45 PM PDT 24 |
| Finished | Jul 25 07:51:24 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-8f3efc53-d146-475b-bc0a-17dab20e9101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494956209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_reset_error.494956209 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1221946434 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 812261048 ps |
| CPU time | 36.98 seconds |
| Started | Jul 25 07:43:42 PM PDT 24 |
| Finished | Jul 25 07:44:20 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-4530cd9d-2e4c-4acd-969b-d0f93d466e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221946434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1221946434 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1701344844 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 6419974617 ps |
| CPU time | 556.49 seconds |
| Started | Jul 25 07:28:46 PM PDT 24 |
| Finished | Jul 25 07:38:02 PM PDT 24 |
| Peak memory | 642172 kb |
| Host | smart-6bbd3b1f-ca1b-4ac6-bc49-d723e409da52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701344844 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.1701344844 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.2848553332 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 6100075356 ps |
| CPU time | 650.34 seconds |
| Started | Jul 25 07:28:42 PM PDT 24 |
| Finished | Jul 25 07:39:33 PM PDT 24 |
| Peak memory | 598400 kb |
| Host | smart-3e83db90-26a8-4041-bb60-e03db5c40c8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848553332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.2848553332 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.2044457269 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 26757121818 ps |
| CPU time | 3046.77 seconds |
| Started | Jul 25 07:28:15 PM PDT 24 |
| Finished | Jul 25 08:19:02 PM PDT 24 |
| Peak memory | 593160 kb |
| Host | smart-1a4eb0f0-a0d1-481d-aaf2-be75b2c1b14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044457269 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.2044457269 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2563604049 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 3354522880 ps |
| CPU time | 203.31 seconds |
| Started | Jul 25 07:28:12 PM PDT 24 |
| Finished | Jul 25 07:31:36 PM PDT 24 |
| Peak memory | 603444 kb |
| Host | smart-905ffa93-704a-4139-a094-4927f1fcb533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563604049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2563604049 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.459261941 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 853530258 ps |
| CPU time | 71.12 seconds |
| Started | Jul 25 07:28:20 PM PDT 24 |
| Finished | Jul 25 07:29:32 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-8ae516c6-5922-44c4-bed5-ecc557f3b566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459261941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.459261941 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3974934077 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 111712416419 ps |
| CPU time | 1915.32 seconds |
| Started | Jul 25 07:28:18 PM PDT 24 |
| Finished | Jul 25 08:00:14 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ab6d19d3-359d-4add-a5ed-6be3064f3e9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974934077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.3974934077 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.398559193 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 611323620 ps |
| CPU time | 27.81 seconds |
| Started | Jul 25 07:28:30 PM PDT 24 |
| Finished | Jul 25 07:28:58 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-3cc2d48e-72c6-4300-b616-fa13750d34bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398559193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr. 398559193 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1783051253 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 267280488 ps |
| CPU time | 12.94 seconds |
| Started | Jul 25 07:28:29 PM PDT 24 |
| Finished | Jul 25 07:28:42 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-cbcbf5a0-bdc8-4eb2-981d-4274dc8a6274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783051253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1783051253 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2820269371 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 2718403210 ps |
| CPU time | 85.3 seconds |
| Started | Jul 25 07:28:12 PM PDT 24 |
| Finished | Jul 25 07:29:38 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-e7a5a979-3b8b-44a2-b7b8-7f01af6c004c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820269371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2820269371 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.3336354228 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 38134090167 ps |
| CPU time | 405.37 seconds |
| Started | Jul 25 07:28:19 PM PDT 24 |
| Finished | Jul 25 07:35:04 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-92c4d11b-f7eb-417f-85dc-2db5979738dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336354228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3336354228 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1971124899 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 17751476355 ps |
| CPU time | 279.6 seconds |
| Started | Jul 25 07:28:21 PM PDT 24 |
| Finished | Jul 25 07:33:00 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-8dd23f19-3d8f-41bf-a329-65f7c300b6ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971124899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1971124899 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3909667677 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 538793066 ps |
| CPU time | 41.67 seconds |
| Started | Jul 25 07:28:18 PM PDT 24 |
| Finished | Jul 25 07:29:00 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-8d49f994-731b-4527-b856-4e228e162a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909667677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.3909667677 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.1907959624 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 1194875012 ps |
| CPU time | 38.75 seconds |
| Started | Jul 25 07:28:31 PM PDT 24 |
| Finished | Jul 25 07:29:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-5c396f48-258f-47dd-a880-8f6d54fa1582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907959624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1907959624 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2065683436 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 44779852 ps |
| CPU time | 6.35 seconds |
| Started | Jul 25 07:28:10 PM PDT 24 |
| Finished | Jul 25 07:28:17 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-d8a2396d-577b-43fb-adfd-e935f48d4a76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065683436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2065683436 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.71528276 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 8419050525 ps |
| CPU time | 88.92 seconds |
| Started | Jul 25 07:28:09 PM PDT 24 |
| Finished | Jul 25 07:29:38 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-6e7f361c-02f3-4912-bc41-ac575912fc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71528276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.71528276 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.263472110 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 5521132074 ps |
| CPU time | 94.29 seconds |
| Started | Jul 25 07:28:13 PM PDT 24 |
| Finished | Jul 25 07:29:47 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-513bec86-7179-438d-b4bb-eb089957bfcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263472110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.263472110 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1357071748 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 48042682 ps |
| CPU time | 6.24 seconds |
| Started | Jul 25 07:28:10 PM PDT 24 |
| Finished | Jul 25 07:28:16 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-f2411b3b-35aa-4060-9946-8ad4c0f4df7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357071748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .1357071748 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.186863188 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 2168851696 ps |
| CPU time | 188.18 seconds |
| Started | Jul 25 07:28:29 PM PDT 24 |
| Finished | Jul 25 07:31:38 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-9f81416a-e1d3-480d-b4bc-092d7ff95fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186863188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.186863188 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.2857577927 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 3704936030 ps |
| CPU time | 123.38 seconds |
| Started | Jul 25 07:28:41 PM PDT 24 |
| Finished | Jul 25 07:30:44 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-61baae41-8b4a-40b0-aa48-52e3f73332c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857577927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2857577927 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2979044930 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 18801513011 ps |
| CPU time | 921.85 seconds |
| Started | Jul 25 07:28:30 PM PDT 24 |
| Finished | Jul 25 07:43:52 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a884da8b-f06a-4cc9-aa74-29a0935d808d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979044930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2979044930 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.905466158 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 535446864 ps |
| CPU time | 161.04 seconds |
| Started | Jul 25 07:28:40 PM PDT 24 |
| Finished | Jul 25 07:31:21 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-5b0add3b-1bc0-4c37-8873-5eb7deff88cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905466158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_reset_error.905466158 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2656996669 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 40898841 ps |
| CPU time | 7.55 seconds |
| Started | Jul 25 07:28:31 PM PDT 24 |
| Finished | Jul 25 07:28:38 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-31d4e535-5771-4e31-8612-005ae5718107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656996669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2656996669 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2134380390 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 712033848 ps |
| CPU time | 55.64 seconds |
| Started | Jul 25 07:43:57 PM PDT 24 |
| Finished | Jul 25 07:44:53 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-cfacba06-74fa-4690-abc0-09ffabb147cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134380390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2134380390 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1572556356 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 50205840948 ps |
| CPU time | 978.77 seconds |
| Started | Jul 25 07:43:50 PM PDT 24 |
| Finished | Jul 25 08:00:09 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-67ce67d8-081e-4023-8efc-b0371605917d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572556356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1572556356 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2349041731 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 339066506 ps |
| CPU time | 15.29 seconds |
| Started | Jul 25 07:43:54 PM PDT 24 |
| Finished | Jul 25 07:44:10 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-db135f9d-0d40-48e6-8db5-2fe697b9b254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349041731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2349041731 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.146727981 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 1611051563 ps |
| CPU time | 52.04 seconds |
| Started | Jul 25 07:43:55 PM PDT 24 |
| Finished | Jul 25 07:44:47 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-dfac20cc-f1ba-4c55-aea1-51659ae377b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146727981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.146727981 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.1470148040 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 327568636 ps |
| CPU time | 13.86 seconds |
| Started | Jul 25 07:43:43 PM PDT 24 |
| Finished | Jul 25 07:43:57 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-46e35bb8-4754-4b5a-84c1-cff58b704bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470148040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1470148040 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.4241680676 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 81118238247 ps |
| CPU time | 844.27 seconds |
| Started | Jul 25 07:43:54 PM PDT 24 |
| Finished | Jul 25 07:57:59 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d6795048-7257-4a54-bf29-7447fa4ffa31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241680676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.4241680676 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.615529906 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 10176591061 ps |
| CPU time | 156.73 seconds |
| Started | Jul 25 07:43:51 PM PDT 24 |
| Finished | Jul 25 07:46:27 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ed072b77-9734-4c97-b14d-80d93d8e7d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615529906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.615529906 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3334866740 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 144142577 ps |
| CPU time | 14.83 seconds |
| Started | Jul 25 07:43:53 PM PDT 24 |
| Finished | Jul 25 07:44:08 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-5d1eec97-3ae1-4826-87a7-f408d2e38fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334866740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3334866740 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.3918384900 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 123970760 ps |
| CPU time | 11.46 seconds |
| Started | Jul 25 07:43:51 PM PDT 24 |
| Finished | Jul 25 07:44:03 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ffc54709-e17f-4a30-90ca-a9ab00bce7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918384900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3918384900 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1342944297 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 180023860 ps |
| CPU time | 8.73 seconds |
| Started | Jul 25 07:43:44 PM PDT 24 |
| Finished | Jul 25 07:43:53 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-8108450c-2185-4c73-8b5e-560f4144dc99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342944297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1342944297 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.2362193233 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 7729989476 ps |
| CPU time | 79.28 seconds |
| Started | Jul 25 07:43:52 PM PDT 24 |
| Finished | Jul 25 07:45:11 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-af369503-95bc-46ae-8f8d-143c861536a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362193233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.2362193233 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1376617914 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 6632265896 ps |
| CPU time | 105.94 seconds |
| Started | Jul 25 07:43:43 PM PDT 24 |
| Finished | Jul 25 07:45:29 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-098e43cf-0686-456d-a76b-f0a0178077a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376617914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1376617914 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1036281527 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 43813583 ps |
| CPU time | 6.55 seconds |
| Started | Jul 25 07:43:42 PM PDT 24 |
| Finished | Jul 25 07:43:48 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-35603899-c716-4af8-9fc6-275368b8279f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036281527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.1036281527 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2586333456 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 16420370916 ps |
| CPU time | 610.68 seconds |
| Started | Jul 25 07:43:58 PM PDT 24 |
| Finished | Jul 25 07:54:09 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-2b429a6b-f715-4786-8d76-9cc4ade4eb0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586333456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2586333456 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1403862456 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 3492759407 ps |
| CPU time | 269.08 seconds |
| Started | Jul 25 07:43:52 PM PDT 24 |
| Finished | Jul 25 07:48:21 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-cc828e70-bcb1-4eb5-ba40-a7a0f6bb358b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403862456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1403862456 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.2121916705 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 134857256 ps |
| CPU time | 31.83 seconds |
| Started | Jul 25 07:43:49 PM PDT 24 |
| Finished | Jul 25 07:44:21 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-adb2a80a-50d1-4407-8939-dafe6aa62a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121916705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.2121916705 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2564254202 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 888023860 ps |
| CPU time | 79.7 seconds |
| Started | Jul 25 07:43:59 PM PDT 24 |
| Finished | Jul 25 07:45:19 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-ac39fdfd-951d-4b8b-9996-bd7bf71dc27d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564254202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2564254202 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2691006851 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 941974721 ps |
| CPU time | 36.97 seconds |
| Started | Jul 25 07:43:51 PM PDT 24 |
| Finished | Jul 25 07:44:28 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-35f7c4b8-8c9c-4794-924d-2bc0460e077f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691006851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2691006851 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.3736975836 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 1435515147 ps |
| CPU time | 55.44 seconds |
| Started | Jul 25 07:47:07 PM PDT 24 |
| Finished | Jul 25 07:48:03 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-6aad406f-8741-43ef-993b-90883d7046e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736975836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .3736975836 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1603533809 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 55185477743 ps |
| CPU time | 1004.48 seconds |
| Started | Jul 25 07:47:20 PM PDT 24 |
| Finished | Jul 25 08:04:05 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-9920ecf8-c199-4f58-bba8-58444f095d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603533809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1603533809 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1014293827 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 578036988 ps |
| CPU time | 22.64 seconds |
| Started | Jul 25 07:47:11 PM PDT 24 |
| Finished | Jul 25 07:47:34 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-7f67d325-369d-40f8-8e68-6a725c684905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014293827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.1014293827 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.321748442 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 1030344255 ps |
| CPU time | 34.65 seconds |
| Started | Jul 25 07:47:13 PM PDT 24 |
| Finished | Jul 25 07:47:48 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-066c377f-5db9-4955-833d-00519c8569cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321748442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.321748442 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2454630496 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 410675041 ps |
| CPU time | 33.68 seconds |
| Started | Jul 25 07:47:11 PM PDT 24 |
| Finished | Jul 25 07:47:44 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-3f4e0313-3467-4839-b9bf-d01cc576b659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454630496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2454630496 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.909508564 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 46331971953 ps |
| CPU time | 462.41 seconds |
| Started | Jul 25 07:47:15 PM PDT 24 |
| Finished | Jul 25 07:54:58 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-891679cf-b02e-4eb3-948f-3ba2e237a3c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909508564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.909508564 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3511905063 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 6266939142 ps |
| CPU time | 102.29 seconds |
| Started | Jul 25 07:47:19 PM PDT 24 |
| Finished | Jul 25 07:49:01 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-f27fd121-0eab-4d2b-a3b9-17b998788412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511905063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3511905063 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.104536924 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 242270819 ps |
| CPU time | 21.63 seconds |
| Started | Jul 25 07:47:09 PM PDT 24 |
| Finished | Jul 25 07:47:30 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-16280b06-0fed-4bb6-9172-15bfdf124b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104536924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.104536924 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1141011198 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 152554382 ps |
| CPU time | 13.36 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:47:38 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-d5164f0e-cf87-4fd9-b560-cf3496a2df11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141011198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1141011198 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.2074812216 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 248374757 ps |
| CPU time | 9.99 seconds |
| Started | Jul 25 07:43:58 PM PDT 24 |
| Finished | Jul 25 07:44:08 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-f3f64389-84a2-4c19-928b-d3774a22be04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074812216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.2074812216 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1435499004 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 5184087312 ps |
| CPU time | 52.11 seconds |
| Started | Jul 25 07:43:53 PM PDT 24 |
| Finished | Jul 25 07:44:45 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-33f97c79-a5d4-4b4c-81dc-e5c008b53073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435499004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1435499004 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3126359754 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 5124832699 ps |
| CPU time | 83.83 seconds |
| Started | Jul 25 07:43:54 PM PDT 24 |
| Finished | Jul 25 07:45:18 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-d881b4e6-558b-49fa-9aa3-646d5d4eefd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126359754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3126359754 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.643008985 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 38895933 ps |
| CPU time | 6.64 seconds |
| Started | Jul 25 07:43:58 PM PDT 24 |
| Finished | Jul 25 07:44:05 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-a45beb72-daaf-471a-947e-cc8f8536520b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643008985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays .643008985 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.1975484705 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1590466723 ps |
| CPU time | 125 seconds |
| Started | Jul 25 07:47:11 PM PDT 24 |
| Finished | Jul 25 07:49:16 PM PDT 24 |
| Peak memory | 576228 kb |
| Host | smart-b5dfbf3f-f572-4142-b1a5-b85f0ee9d3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975484705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1975484705 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3937651748 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 864170223 ps |
| CPU time | 65.18 seconds |
| Started | Jul 25 07:47:07 PM PDT 24 |
| Finished | Jul 25 07:48:13 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-049c7335-a698-4221-b1fd-b90f88013a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937651748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3937651748 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.258677257 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 192180181 ps |
| CPU time | 77.8 seconds |
| Started | Jul 25 07:47:16 PM PDT 24 |
| Finished | Jul 25 07:48:33 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-fcff3119-a4aa-4a27-9cf1-c3d2339645f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258677257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_ with_rand_reset.258677257 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3590781300 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3867324281 ps |
| CPU time | 152.32 seconds |
| Started | Jul 25 07:47:13 PM PDT 24 |
| Finished | Jul 25 07:49:45 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-bc925fd6-2e94-42c8-be05-55e155e65a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590781300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3590781300 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.617901955 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 547906604 ps |
| CPU time | 26.24 seconds |
| Started | Jul 25 07:47:20 PM PDT 24 |
| Finished | Jul 25 07:47:46 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-5c2f7773-8bba-42e9-b277-65a9d1bf5eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617901955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.617901955 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.848658670 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 2620190005 ps |
| CPU time | 88.29 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:48:53 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a5c829b6-b4db-48bc-8b70-14a519dabc26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848658670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 848658670 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3173863874 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 44106341341 ps |
| CPU time | 744.2 seconds |
| Started | Jul 25 07:47:16 PM PDT 24 |
| Finished | Jul 25 07:59:40 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-66a37378-053d-4241-aa53-7fd7a0c7bc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173863874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.3173863874 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.857850849 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 34321355 ps |
| CPU time | 6.94 seconds |
| Started | Jul 25 07:47:22 PM PDT 24 |
| Finished | Jul 25 07:47:29 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-47018171-9058-4ed0-9507-34a4712bf07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857850849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .857850849 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1856033693 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 2542987627 ps |
| CPU time | 91.59 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:48:46 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-cdd95a3e-c119-4e22-939d-de4b6498fdf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856033693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1856033693 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.2042633178 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 592088054 ps |
| CPU time | 24.27 seconds |
| Started | Jul 25 07:47:17 PM PDT 24 |
| Finished | Jul 25 07:47:41 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-6a332993-9259-4043-a299-974c4bf4c59d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042633178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.2042633178 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2935906472 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 62227107406 ps |
| CPU time | 638.28 seconds |
| Started | Jul 25 07:47:07 PM PDT 24 |
| Finished | Jul 25 07:57:45 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-a64b51ab-2433-4906-bc27-96afb688fac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935906472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2935906472 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3291173919 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 60941608401 ps |
| CPU time | 1007.45 seconds |
| Started | Jul 25 07:47:12 PM PDT 24 |
| Finished | Jul 25 08:03:59 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-11360005-fed0-4591-9d7e-05c9e4d27d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291173919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3291173919 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2953767685 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 64065423 ps |
| CPU time | 8.79 seconds |
| Started | Jul 25 07:47:13 PM PDT 24 |
| Finished | Jul 25 07:47:22 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a03d695a-ed56-4ab7-a6e9-4d1f3ba523e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953767685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2953767685 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2968064608 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 48357708 ps |
| CPU time | 6.63 seconds |
| Started | Jul 25 07:47:12 PM PDT 24 |
| Finished | Jul 25 07:47:19 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-36c0492e-c943-4656-a6cf-f124e50820e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968064608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2968064608 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.1472303785 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 188110805 ps |
| CPU time | 8.7 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:47:23 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-9d5595ef-a68f-4d64-b76b-5ab63ca6d82c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472303785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1472303785 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.91618067 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 9870486662 ps |
| CPU time | 94.08 seconds |
| Started | Jul 25 07:47:15 PM PDT 24 |
| Finished | Jul 25 07:48:49 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-30391f90-0edd-45a3-8c0c-e087bcbf28a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91618067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.91618067 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2423177442 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 4896688591 ps |
| CPU time | 81.82 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:48:36 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-cc3d43f1-26cd-4ad3-a761-ee27c2a74eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423177442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.2423177442 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.327295295 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 38911875 ps |
| CPU time | 6.35 seconds |
| Started | Jul 25 07:47:10 PM PDT 24 |
| Finished | Jul 25 07:47:17 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-fde4a4d2-bdbd-473d-a28c-b58eb8af094d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327295295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays .327295295 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.536032325 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 8535442690 ps |
| CPU time | 294.9 seconds |
| Started | Jul 25 07:47:15 PM PDT 24 |
| Finished | Jul 25 07:52:10 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-5d905a9c-49eb-421c-8fd4-27ec1b8a1a32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536032325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.536032325 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2148403303 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 4016150141 ps |
| CPU time | 134.33 seconds |
| Started | Jul 25 07:47:19 PM PDT 24 |
| Finished | Jul 25 07:49:33 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-aaa4c66c-e95f-41f8-a09a-c9a1aab12520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148403303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2148403303 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.1691894314 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 928991632 ps |
| CPU time | 302.47 seconds |
| Started | Jul 25 07:47:13 PM PDT 24 |
| Finished | Jul 25 07:52:16 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-5c4d71f3-0280-438d-90de-7f341d560abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691894314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.1691894314 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.3304711748 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 31791142 ps |
| CPU time | 24.38 seconds |
| Started | Jul 25 07:47:09 PM PDT 24 |
| Finished | Jul 25 07:47:34 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-0134961a-f82f-456e-8503-de9a2cfd851b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304711748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.3304711748 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1141963979 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 665836983 ps |
| CPU time | 29.56 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:47:44 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-529c823b-d5d3-4bc5-b411-7770e0743f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141963979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1141963979 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3767245157 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 967537651 ps |
| CPU time | 44.19 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:10 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-aeed7f7c-6234-4070-a4ff-3841695d3131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767245157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .3767245157 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3121665189 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 31599043351 ps |
| CPU time | 590.05 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:57:26 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-6177ccba-6fa6-485f-9017-85e9504c7761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121665189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.3121665189 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.570061610 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 48562624 ps |
| CPU time | 7.83 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:47:22 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-b5de2710-b73c-4e74-936a-1e9b5eb2eac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570061610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr .570061610 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1440156658 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 40094546 ps |
| CPU time | 6.17 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:47:20 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-fa3273dc-2ade-4381-8b15-3b890c11390e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440156658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1440156658 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2050927998 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 97824240 ps |
| CPU time | 10.63 seconds |
| Started | Jul 25 07:47:06 PM PDT 24 |
| Finished | Jul 25 07:47:16 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-b92d6b06-82b9-48e5-9f15-ff991417c2e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050927998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2050927998 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3369102798 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 10820586936 ps |
| CPU time | 115.05 seconds |
| Started | Jul 25 07:47:08 PM PDT 24 |
| Finished | Jul 25 07:49:03 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-acb2bc68-b14f-49c3-a3c9-496d07009ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369102798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3369102798 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3858773736 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 32010197658 ps |
| CPU time | 534.02 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:56:08 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-1e9ff68f-8d5e-4f3a-b2b1-461d8233d035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858773736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3858773736 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.2208976112 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 86954547 ps |
| CPU time | 9.67 seconds |
| Started | Jul 25 07:47:10 PM PDT 24 |
| Finished | Jul 25 07:47:20 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-09ab9ca0-6c67-4ea4-b301-d14c3afc1a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208976112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.2208976112 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.3850604613 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 1797633940 ps |
| CPU time | 48.03 seconds |
| Started | Jul 25 07:47:16 PM PDT 24 |
| Finished | Jul 25 07:48:05 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-e8932cf7-38ec-48ab-acf7-61ae270221d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850604613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.3850604613 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.196552779 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 51619127 ps |
| CPU time | 6 seconds |
| Started | Jul 25 07:47:09 PM PDT 24 |
| Finished | Jul 25 07:47:15 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-bbc0e196-1c0a-4b40-9d67-49637ae3a6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196552779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.196552779 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.3800946080 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 6031830907 ps |
| CPU time | 62.56 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:48:27 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-629c9835-6a0d-4824-b7a8-d36b1c9e1b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800946080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3800946080 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2356113169 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 7325232476 ps |
| CPU time | 119.46 seconds |
| Started | Jul 25 07:47:12 PM PDT 24 |
| Finished | Jul 25 07:49:11 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-9450c427-3096-4756-939b-6e03d8925b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356113169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2356113169 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1733967891 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 35049658 ps |
| CPU time | 5.75 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:47:30 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-02bcca97-73dc-4748-8ae2-70f9ed2a5d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733967891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.1733967891 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3216391084 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 2475889340 ps |
| CPU time | 209.15 seconds |
| Started | Jul 25 07:47:11 PM PDT 24 |
| Finished | Jul 25 07:50:41 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-9be6836b-08dc-48e5-b2b8-61276849ca0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216391084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3216391084 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1837329344 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 10641192153 ps |
| CPU time | 355.72 seconds |
| Started | Jul 25 07:47:15 PM PDT 24 |
| Finished | Jul 25 07:53:11 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-76c78c2d-a750-4bea-a734-94c76ad1f7d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837329344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1837329344 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4188958121 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 3510984334 ps |
| CPU time | 444.65 seconds |
| Started | Jul 25 07:47:12 PM PDT 24 |
| Finished | Jul 25 07:54:37 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-9e4aa5f2-2798-40a4-a681-b4def58f3c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188958121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.4188958121 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3857927958 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 1533544565 ps |
| CPU time | 249.71 seconds |
| Started | Jul 25 07:47:23 PM PDT 24 |
| Finished | Jul 25 07:51:33 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-6599165a-9e6e-44a6-99a4-42c73fde2286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857927958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3857927958 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.897041478 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 1241331701 ps |
| CPU time | 50.53 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:16 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d0cca554-ee6b-4dc8-9bd4-58b988069844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897041478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.897041478 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3739730153 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 1418289931 ps |
| CPU time | 66.64 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:32 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-dc110729-349b-4d1c-b022-3b504056ae1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739730153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .3739730153 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.500966851 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 117750279442 ps |
| CPU time | 2106.97 seconds |
| Started | Jul 25 07:47:17 PM PDT 24 |
| Finished | Jul 25 08:22:24 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-7caf3bc0-7a86-42e6-94f9-1798cef4d046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500966851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.500966851 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3564298386 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 522775259 ps |
| CPU time | 21.43 seconds |
| Started | Jul 25 07:47:18 PM PDT 24 |
| Finished | Jul 25 07:47:39 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-060ffec4-7590-4bce-b72f-0e2986fa87c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564298386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3564298386 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.4234231074 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 2480015986 ps |
| CPU time | 92.68 seconds |
| Started | Jul 25 07:47:13 PM PDT 24 |
| Finished | Jul 25 07:48:46 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-2777f408-af47-43d3-b704-e3d5cb088ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234231074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.4234231074 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1124073487 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 2223399436 ps |
| CPU time | 77.49 seconds |
| Started | Jul 25 07:47:12 PM PDT 24 |
| Finished | Jul 25 07:48:30 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-bd2750ae-cde3-4a80-bef0-537d7d9c6686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124073487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1124073487 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1628662520 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 42244424982 ps |
| CPU time | 436.32 seconds |
| Started | Jul 25 07:47:17 PM PDT 24 |
| Finished | Jul 25 07:54:34 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-27c28394-7e65-43af-80c0-99d24ff30fcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628662520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1628662520 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.3512199555 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 30186391749 ps |
| CPU time | 500.92 seconds |
| Started | Jul 25 07:47:17 PM PDT 24 |
| Finished | Jul 25 07:55:38 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-a4a092dd-966f-4818-adb6-66b7b004edb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512199555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.3512199555 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.648357635 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 337144022 ps |
| CPU time | 29.47 seconds |
| Started | Jul 25 07:47:16 PM PDT 24 |
| Finished | Jul 25 07:47:46 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-05865fd0-16e7-4c92-bbf5-6097dd9308f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648357635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.648357635 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.3428625842 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1719460788 ps |
| CPU time | 49.89 seconds |
| Started | Jul 25 07:47:16 PM PDT 24 |
| Finished | Jul 25 07:48:06 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-0ce0fc96-3404-4d92-babe-42e5a4eef494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428625842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3428625842 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.493100135 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 57136233 ps |
| CPU time | 6.39 seconds |
| Started | Jul 25 07:47:15 PM PDT 24 |
| Finished | Jul 25 07:47:22 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-e14e1b32-07bb-424f-a404-78a821b9b2dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493100135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.493100135 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.4201732367 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 9647871803 ps |
| CPU time | 107.45 seconds |
| Started | Jul 25 07:47:21 PM PDT 24 |
| Finished | Jul 25 07:49:09 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-8efeccdf-370a-47d7-b91d-c73e5ae35a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201732367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.4201732367 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2115718040 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 6115813347 ps |
| CPU time | 90.66 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:56 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-4466085b-e6d3-4971-9b74-a1d5c3cabc73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115718040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2115718040 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1239969317 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 52573333 ps |
| CPU time | 6.03 seconds |
| Started | Jul 25 07:47:20 PM PDT 24 |
| Finished | Jul 25 07:47:26 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-75b5b9a3-03f2-4a96-bf77-0f04523f5f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239969317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1239969317 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.325495642 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3923568083 ps |
| CPU time | 134.54 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:49:29 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-1e880a37-3e36-40af-bf49-84ea0a817262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325495642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.325495642 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.3471962064 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 5182568216 ps |
| CPU time | 384.05 seconds |
| Started | Jul 25 07:47:14 PM PDT 24 |
| Finished | Jul 25 07:53:38 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-0c42bbdb-6881-4e4f-8e4d-18b511f0d180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471962064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.3471962064 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.682766076 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 2963707071 ps |
| CPU time | 350.07 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:53:16 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-6116c694-9f14-4c5b-ab52-858f60d8ccdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682766076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.682766076 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1275721505 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 348598567 ps |
| CPU time | 16.85 seconds |
| Started | Jul 25 07:47:15 PM PDT 24 |
| Finished | Jul 25 07:47:32 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-adadfc1d-2100-45a3-ba48-2642427dabd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275721505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1275721505 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2862177828 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 618148842 ps |
| CPU time | 50.11 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:48:15 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-dc4d6404-88b2-4942-97ad-bd6725eaa639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862177828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2862177828 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.4187060666 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 98857135409 ps |
| CPU time | 1718.68 seconds |
| Started | Jul 25 07:47:27 PM PDT 24 |
| Finished | Jul 25 08:16:06 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-8247abe6-8c1e-4ac6-a679-0c072751a73b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187060666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.4187060666 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3111280889 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 52533296 ps |
| CPU time | 7.83 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:47:32 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-4fd79be1-e627-4961-b4db-268520de1932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111280889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.3111280889 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2740090648 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 1500809829 ps |
| CPU time | 50.3 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:15 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-10737bf6-79ae-4b44-bee4-6288a1373419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740090648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2740090648 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1255805960 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 270340630 ps |
| CPU time | 26.92 seconds |
| Started | Jul 25 07:47:27 PM PDT 24 |
| Finished | Jul 25 07:47:54 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-99aff3ca-aa05-46bc-b8ad-2046d8a1a529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255805960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1255805960 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2454092062 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 18261709360 ps |
| CPU time | 181.48 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:50:37 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-78ca1075-72eb-4152-bce3-3123a875b7c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454092062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2454092062 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2475517739 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 15405303066 ps |
| CPU time | 270.42 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:51:55 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-6f0552f5-d494-427c-bcc3-52b641591632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475517739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2475517739 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3346128605 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 527217428 ps |
| CPU time | 41.48 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 07:48:07 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-3d5ea39c-9de9-416b-91ad-5f449452c4af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346128605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3346128605 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.859415911 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 2461700519 ps |
| CPU time | 75.53 seconds |
| Started | Jul 25 07:47:31 PM PDT 24 |
| Finished | Jul 25 07:48:47 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-45b9ffbb-03d8-4b6f-b84b-cb26ccf9f73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859415911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.859415911 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.1072558416 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 41485687 ps |
| CPU time | 6.23 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:47:31 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-de78b0fe-3231-447a-9a66-5d8b9a82ba74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072558416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1072558416 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.1476071442 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 8601297141 ps |
| CPU time | 82.55 seconds |
| Started | Jul 25 07:47:29 PM PDT 24 |
| Finished | Jul 25 07:48:51 PM PDT 24 |
| Peak memory | 573880 kb |
| Host | smart-73dbbd6e-7cd4-4117-a5da-f2a6b8395dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476071442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.1476071442 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1479861426 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 3454099324 ps |
| CPU time | 56.48 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 07:48:22 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-ec8eb513-053f-4d62-b84b-059c50cc1367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479861426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.1479861426 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1698288513 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 57150120 ps |
| CPU time | 7.21 seconds |
| Started | Jul 25 07:49:48 PM PDT 24 |
| Finished | Jul 25 07:49:55 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-a9bdf399-3bbe-4010-bf10-d3aada88b898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698288513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1698288513 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.151352774 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 15037857988 ps |
| CPU time | 490.82 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:55:36 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-e97bf16a-60ec-467c-b90a-27564bcf6292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151352774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.151352774 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1687002525 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 8568195194 ps |
| CPU time | 294.43 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 07:52:20 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-a4603363-9141-4375-a2a8-19c83cdce745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687002525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1687002525 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2848838449 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 455223368 ps |
| CPU time | 170.86 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 07:50:17 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-12b32d19-1e90-457f-9504-b45699e971d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848838449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2848838449 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1013229463 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 170649446 ps |
| CPU time | 20.85 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:47:45 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-034595bd-13aa-4ee3-a55e-22647dad051c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013229463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1013229463 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.432531084 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 363600174 ps |
| CPU time | 32.52 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:47:57 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6cbcb2f9-22b8-44c7-8e3c-9c0ee717bbdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432531084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device. 432531084 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.765996212 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 68087984013 ps |
| CPU time | 1178.73 seconds |
| Started | Jul 25 07:47:34 PM PDT 24 |
| Finished | Jul 25 08:07:13 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-712b645b-3a45-4a2e-9567-d3f04f2571d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765996212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.765996212 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2568790570 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 302964673 ps |
| CPU time | 31.25 seconds |
| Started | Jul 25 07:47:27 PM PDT 24 |
| Finished | Jul 25 07:47:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-eff49b36-939f-469f-8025-8e8703a72653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568790570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.2568790570 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.2660388300 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 1835124128 ps |
| CPU time | 55.11 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:20 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-bd75c940-bc29-48d2-8f61-3f6d98e4006e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660388300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2660388300 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.3055325817 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 373101884 ps |
| CPU time | 33.3 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:47:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-b772d6f2-aa54-4e34-a3ee-34368144f7fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055325817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.3055325817 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.691987103 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 101395745208 ps |
| CPU time | 1132.37 seconds |
| Started | Jul 25 07:47:27 PM PDT 24 |
| Finished | Jul 25 08:06:19 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-cda000e9-11e3-439c-8ce7-5cc53c997f9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691987103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.691987103 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.4177188122 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 42623303467 ps |
| CPU time | 704.69 seconds |
| Started | Jul 25 07:47:19 PM PDT 24 |
| Finished | Jul 25 07:59:04 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-20209c46-a759-4ead-8e9a-8d7f689b24b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177188122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.4177188122 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2269410951 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 464207958 ps |
| CPU time | 42.71 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:08 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-23822750-9c6c-4d0c-b767-0e331ce71826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269410951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.2269410951 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.2847085017 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 107240759 ps |
| CPU time | 9.99 seconds |
| Started | Jul 25 07:47:30 PM PDT 24 |
| Finished | Jul 25 07:47:40 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-73c66552-86d8-443d-b72d-31e8426a1fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847085017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2847085017 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.329752127 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 49841332 ps |
| CPU time | 6.55 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:47:32 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-0ad0b95f-45da-456c-8b4a-b7d7322967dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329752127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.329752127 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2943379787 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 9370150940 ps |
| CPU time | 99.66 seconds |
| Started | Jul 25 07:47:28 PM PDT 24 |
| Finished | Jul 25 07:49:08 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-4b450a52-f914-474c-90ca-3374de181670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943379787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2943379787 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2016935861 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 6906466538 ps |
| CPU time | 118.7 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 07:49:25 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-fdfd2c87-606f-4aa7-9782-dc7d87372762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016935861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2016935861 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.640104507 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 37323807 ps |
| CPU time | 5.67 seconds |
| Started | Jul 25 07:47:29 PM PDT 24 |
| Finished | Jul 25 07:47:34 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-a1739eaf-2135-48cf-bf41-755ad168c54c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640104507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .640104507 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2725495598 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3950804220 ps |
| CPU time | 151.13 seconds |
| Started | Jul 25 07:47:28 PM PDT 24 |
| Finished | Jul 25 07:49:59 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-273310fc-6b44-4982-a1ae-ddb974e2de2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725495598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2725495598 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.4152074850 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 2537353945 ps |
| CPU time | 89.43 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 07:48:56 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-247a8844-f7ee-4124-95b4-b5e6efb48319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152074850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.4152074850 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.296816081 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 63032308 ps |
| CPU time | 46.14 seconds |
| Started | Jul 25 07:47:28 PM PDT 24 |
| Finished | Jul 25 07:48:14 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-4a234747-2abc-4474-81dc-0beeb653eb8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296816081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.296816081 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2877491809 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 417348763 ps |
| CPU time | 105.29 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:49:11 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-6c2eea59-3c31-46be-a591-877ed257b299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877491809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.2877491809 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3946397979 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 316975978 ps |
| CPU time | 40.19 seconds |
| Started | Jul 25 07:47:32 PM PDT 24 |
| Finished | Jul 25 07:48:12 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-30c4d4a7-2d2a-4d2c-88a5-88507b54a7a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946397979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3946397979 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3453475552 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 2079788988 ps |
| CPU time | 77.46 seconds |
| Started | Jul 25 07:47:28 PM PDT 24 |
| Finished | Jul 25 07:48:45 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-c64615a7-b64e-49d3-992f-cf0e6360b8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453475552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3453475552 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2412390464 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 92669285220 ps |
| CPU time | 1594.08 seconds |
| Started | Jul 25 07:47:26 PM PDT 24 |
| Finished | Jul 25 08:14:01 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-9d777604-8da8-447d-87ff-d03056a58e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412390464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2412390464 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2293412162 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 161402542 ps |
| CPU time | 17.72 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:47:53 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-d7d5deb8-b342-411d-8635-cca21defa35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293412162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2293412162 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.3624672764 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 67303590 ps |
| CPU time | 8.44 seconds |
| Started | Jul 25 07:47:31 PM PDT 24 |
| Finished | Jul 25 07:47:39 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-0f632b6b-432d-40b9-b15a-88c46241f326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624672764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3624672764 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.927292747 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 2010593921 ps |
| CPU time | 69.12 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:34 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-273117e7-811f-4c20-97f7-a799073ac8b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927292747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.927292747 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.2886834283 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 28362294120 ps |
| CPU time | 299.23 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:52:34 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-06652b21-b73f-46f1-a216-f8ac7245a247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886834283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2886834283 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2344767994 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 33809964493 ps |
| CPU time | 609.6 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:57:35 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-27fe8ca1-0ab7-4c11-a0dd-201ed8c92729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344767994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2344767994 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1484552096 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 390760029 ps |
| CPU time | 31.66 seconds |
| Started | Jul 25 07:47:32 PM PDT 24 |
| Finished | Jul 25 07:48:03 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-8eb9bb6e-cbfd-4372-8eb3-77c950040384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484552096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1484552096 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.327361165 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 400517471 ps |
| CPU time | 13.39 seconds |
| Started | Jul 25 07:47:28 PM PDT 24 |
| Finished | Jul 25 07:47:42 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-1115d45f-e2d3-4094-93cd-e039c6f3b652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327361165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.327361165 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.444881638 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 53962198 ps |
| CPU time | 6.58 seconds |
| Started | Jul 25 07:47:24 PM PDT 24 |
| Finished | Jul 25 07:47:31 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-324deed6-98d4-4e56-a0af-2e4087dd2e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444881638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.444881638 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2131268722 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 9432622861 ps |
| CPU time | 96.31 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:49:01 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-9223bc02-5052-4d48-b0c3-921a4db688a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131268722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2131268722 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.945882924 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 5691375948 ps |
| CPU time | 99.9 seconds |
| Started | Jul 25 07:47:28 PM PDT 24 |
| Finished | Jul 25 07:49:08 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-fbd0f5a4-7ddf-4bfa-be23-97e24bfc6a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945882924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.945882924 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2844262495 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 45825988 ps |
| CPU time | 6.59 seconds |
| Started | Jul 25 07:47:31 PM PDT 24 |
| Finished | Jul 25 07:47:37 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-45b2f3eb-eeb5-42e1-83d1-94171dc56662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844262495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2844262495 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.3062031088 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 1074103222 ps |
| CPU time | 90.7 seconds |
| Started | Jul 25 07:47:27 PM PDT 24 |
| Finished | Jul 25 07:48:58 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-40c7271a-58ec-425b-a5d7-c171237f966a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062031088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3062031088 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3685381503 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 866038024 ps |
| CPU time | 70.35 seconds |
| Started | Jul 25 07:47:25 PM PDT 24 |
| Finished | Jul 25 07:48:36 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-96ad8f93-bc7b-4cee-8f2e-4d6350f4c626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685381503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3685381503 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3187601719 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 719462314 ps |
| CPU time | 142.84 seconds |
| Started | Jul 25 07:47:31 PM PDT 24 |
| Finished | Jul 25 07:49:54 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-02e3ae46-6dab-436b-bc0a-d21ced452f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187601719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3187601719 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1939457139 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1227674477 ps |
| CPU time | 161.95 seconds |
| Started | Jul 25 07:47:31 PM PDT 24 |
| Finished | Jul 25 07:50:13 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-34a7d64e-6d8b-40ac-b827-784ed67cdf65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939457139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1939457139 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3950705647 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1076245922 ps |
| CPU time | 42.09 seconds |
| Started | Jul 25 07:47:31 PM PDT 24 |
| Finished | Jul 25 07:48:13 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-35905486-407a-42b5-9bbd-33a5c072e7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950705647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3950705647 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1884106480 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 2685113629 ps |
| CPU time | 104.67 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:49:27 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-8deefee7-84fd-4b98-8901-0e327ff7c632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884106480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1884106480 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.730545391 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 97768014305 ps |
| CPU time | 1711.44 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 08:16:15 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-83570239-56f4-40a9-8e70-2815dc5cc74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730545391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_d evice_slow_rsp.730545391 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.683548959 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 530538636 ps |
| CPU time | 22.24 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:47:58 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-aeedf345-b3f7-48e5-8b49-1dbb0b082b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683548959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .683548959 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2754394159 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 382321076 ps |
| CPU time | 28.29 seconds |
| Started | Jul 25 07:47:33 PM PDT 24 |
| Finished | Jul 25 07:48:01 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-31c87c7d-d7dc-4291-81d4-3df39ecb365f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754394159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2754394159 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.3700194813 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 1847080562 ps |
| CPU time | 66.31 seconds |
| Started | Jul 25 07:47:41 PM PDT 24 |
| Finished | Jul 25 07:48:48 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-b0f33f76-57c4-4b7d-b219-50add23750cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700194813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3700194813 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2879091610 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 81707133702 ps |
| CPU time | 913.92 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 08:02:49 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-5d905422-e99c-4c8c-b809-6758f0419755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879091610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2879091610 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3533439317 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 68559688957 ps |
| CPU time | 1139.9 seconds |
| Started | Jul 25 07:47:40 PM PDT 24 |
| Finished | Jul 25 08:06:40 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-e2370f26-8adb-43c1-921f-976cb5c60dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533439317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3533439317 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3442046746 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 366530741 ps |
| CPU time | 32.57 seconds |
| Started | Jul 25 07:47:55 PM PDT 24 |
| Finished | Jul 25 07:48:28 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-1706ffa0-cb50-417d-9e0a-d6edb4d944c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442046746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3442046746 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.644581824 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 328301303 ps |
| CPU time | 26.32 seconds |
| Started | Jul 25 07:47:39 PM PDT 24 |
| Finished | Jul 25 07:48:06 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-7ab75e8c-330c-4078-85ce-a0ac909b2217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644581824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.644581824 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.1791105229 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 56432664 ps |
| CPU time | 6.46 seconds |
| Started | Jul 25 07:47:33 PM PDT 24 |
| Finished | Jul 25 07:47:40 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-3da79605-723e-48cd-8e08-e5e2e832f464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791105229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.1791105229 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1985279072 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 8084120192 ps |
| CPU time | 79.21 seconds |
| Started | Jul 25 07:47:34 PM PDT 24 |
| Finished | Jul 25 07:48:53 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-74e45c3e-1700-4eea-9f79-0d18ac646cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985279072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1985279072 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1405571828 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 5821783576 ps |
| CPU time | 93.95 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:49:17 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-8fda723f-77e0-479d-a46e-0cc1465349cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405571828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1405571828 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1795897457 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 55049646 ps |
| CPU time | 6.69 seconds |
| Started | Jul 25 07:47:36 PM PDT 24 |
| Finished | Jul 25 07:47:43 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-9e081c52-b068-4efc-bc8c-7e11cc703948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795897457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1795897457 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.4099172114 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 1510460040 ps |
| CPU time | 113.81 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:49:29 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-af65870a-f4cc-4a82-b6b3-99d411998838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099172114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.4099172114 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3332264805 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 6965675202 ps |
| CPU time | 226.46 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:51:30 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-b049b4b6-1bde-4105-9138-0b16d916f92b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332264805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3332264805 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2038476930 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 240227764 ps |
| CPU time | 97.48 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:49:20 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-0a4dbf79-a3b9-483c-aec8-1c867520c7ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038476930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.2038476930 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.4290062106 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 10975717694 ps |
| CPU time | 498.7 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:56:02 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-cfce6409-4136-43f1-81df-91bf719905f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290062106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.4290062106 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.27532629 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 99352227 ps |
| CPU time | 13.46 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:47:57 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-55e2aa44-73c8-4d36-9bd5-fe6e42a85882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.27532629 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3207573012 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3204139146 ps |
| CPU time | 120.91 seconds |
| Started | Jul 25 07:47:41 PM PDT 24 |
| Finished | Jul 25 07:49:42 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-5c68b88a-9e5c-49c8-aea9-264052b82deb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207573012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .3207573012 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.4160824774 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 54886518 ps |
| CPU time | 8.07 seconds |
| Started | Jul 25 07:47:55 PM PDT 24 |
| Finished | Jul 25 07:48:03 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-0d273d59-7d9e-4e4f-9423-49bd5dfd973c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160824774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.4160824774 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3830570902 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 379787892 ps |
| CPU time | 32.59 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:48:16 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-05694328-d2e3-4463-96b4-d42a1b26b5cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830570902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3830570902 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2695405858 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 623501019 ps |
| CPU time | 55.88 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:45 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-6e9c17f4-469a-4a36-bd21-947768db20c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695405858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2695405858 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2467122208 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 79052664411 ps |
| CPU time | 752.88 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 08:00:16 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-ada0f280-92ee-4416-9345-f6633a368279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467122208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2467122208 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.322876417 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 19171282956 ps |
| CPU time | 297.26 seconds |
| Started | Jul 25 07:47:48 PM PDT 24 |
| Finished | Jul 25 07:52:46 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-384cfc1d-2dcc-4c7d-955d-04e09ce4a5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322876417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.322876417 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3576542494 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 439586702 ps |
| CPU time | 35.24 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:48:19 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-d27d703c-0497-4c5f-abe9-403f666b0cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576542494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3576542494 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.2929786566 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 565986754 ps |
| CPU time | 38.79 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:48:22 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-8482b544-c642-40eb-81b4-3cf250785c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929786566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2929786566 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.520017732 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 178418628 ps |
| CPU time | 8.53 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:47:50 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-bab2a42e-4492-4e5c-bdcd-2f4a041101da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520017732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.520017732 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1886848750 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 8684919038 ps |
| CPU time | 89.35 seconds |
| Started | Jul 25 07:47:32 PM PDT 24 |
| Finished | Jul 25 07:49:01 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-5568082e-ecab-4f7e-87ac-0cc62af26555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886848750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1886848750 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3128505108 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 3429351424 ps |
| CPU time | 58.61 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:48 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-7c6258f1-f651-4073-b079-6d37df36a309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128505108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3128505108 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2931616951 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 47236257 ps |
| CPU time | 6.34 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:47:49 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-1c887f1c-fcaf-4ee0-b0a2-203460ada370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931616951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2931616951 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.668914970 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 338500755 ps |
| CPU time | 30.61 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:20 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-c2884de5-951e-47c2-b886-c807afb0de06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668914970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.668914970 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3867919951 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 7974405479 ps |
| CPU time | 259.91 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:52:03 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-de86749e-2b6b-45f4-8a88-178dde0f112c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867919951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3867919951 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3871912652 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 1385598187 ps |
| CPU time | 214.32 seconds |
| Started | Jul 25 07:47:44 PM PDT 24 |
| Finished | Jul 25 07:51:18 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-b362c4f9-f0da-408a-ae4d-b1e962daabe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871912652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.3871912652 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.821708252 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 4635761609 ps |
| CPU time | 291.23 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:52:33 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-cc3fd115-2d4f-4456-a8ab-7cee673a7bf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821708252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_reset_error.821708252 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.253207306 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 934237281 ps |
| CPU time | 35.43 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:48:18 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-9504bf2f-b587-41fb-a669-dc3e206096d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253207306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.253207306 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.4019733877 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 9645384160 ps |
| CPU time | 899.67 seconds |
| Started | Jul 25 07:29:12 PM PDT 24 |
| Finished | Jul 25 07:44:12 PM PDT 24 |
| Peak memory | 652684 kb |
| Host | smart-2275aac9-7ad1-4dcf-a188-a5b835488eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019733877 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.4019733877 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.834203491 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 5699794396 ps |
| CPU time | 595.51 seconds |
| Started | Jul 25 07:29:10 PM PDT 24 |
| Finished | Jul 25 07:39:06 PM PDT 24 |
| Peak memory | 598972 kb |
| Host | smart-aacf310f-9ad2-4048-ae31-8a3078fc717d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834203491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.834203491 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3337048206 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 30580110334 ps |
| CPU time | 3926.95 seconds |
| Started | Jul 25 07:28:40 PM PDT 24 |
| Finished | Jul 25 08:34:07 PM PDT 24 |
| Peak memory | 592960 kb |
| Host | smart-79a6d2f9-03e8-4845-a020-2974059a124e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337048206 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3337048206 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.795554731 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3241857656 ps |
| CPU time | 218.39 seconds |
| Started | Jul 25 07:28:40 PM PDT 24 |
| Finished | Jul 25 07:32:18 PM PDT 24 |
| Peak memory | 603328 kb |
| Host | smart-4403f095-ceba-4865-8a85-5026b86aa8db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795554731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.795554731 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.2210305201 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 290020391 ps |
| CPU time | 17.54 seconds |
| Started | Jul 25 07:28:51 PM PDT 24 |
| Finished | Jul 25 07:29:09 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-dbc17d59-df76-4aba-802e-33b11fc24ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210305201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 2210305201 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3805083600 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 38290739152 ps |
| CPU time | 713.38 seconds |
| Started | Jul 25 07:28:52 PM PDT 24 |
| Finished | Jul 25 07:40:46 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-c396cc04-16ac-4549-bd8f-c8396a57ba88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805083600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.3805083600 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.4159037369 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 841630920 ps |
| CPU time | 33.56 seconds |
| Started | Jul 25 07:28:58 PM PDT 24 |
| Finished | Jul 25 07:29:31 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ed458464-c852-440d-91ae-91eec9a9bce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159037369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .4159037369 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1179098689 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 263318832 ps |
| CPU time | 22.16 seconds |
| Started | Jul 25 07:29:00 PM PDT 24 |
| Finished | Jul 25 07:29:23 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-e766c703-9d73-4dcf-a9e5-8ae643b425ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179098689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1179098689 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.2524973446 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 36091571 ps |
| CPU time | 6.71 seconds |
| Started | Jul 25 07:28:52 PM PDT 24 |
| Finished | Jul 25 07:28:59 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-9060fa00-7a64-4955-acda-a5735f08f950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524973446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2524973446 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2076140984 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 87704539246 ps |
| CPU time | 797.55 seconds |
| Started | Jul 25 07:28:49 PM PDT 24 |
| Finished | Jul 25 07:42:07 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-07431b56-b3cd-4d88-a8c2-1d2062293473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076140984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2076140984 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3175736179 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 45626386906 ps |
| CPU time | 798.91 seconds |
| Started | Jul 25 07:28:52 PM PDT 24 |
| Finished | Jul 25 07:42:11 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-53b84ad1-61b5-43c3-904c-848f2b47d718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175736179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3175736179 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3166167241 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 582058247 ps |
| CPU time | 52.89 seconds |
| Started | Jul 25 07:28:51 PM PDT 24 |
| Finished | Jul 25 07:29:44 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-19de81fd-6955-477b-b807-ea4ceab00a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166167241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3166167241 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2020064286 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 1541129234 ps |
| CPU time | 45.03 seconds |
| Started | Jul 25 07:29:00 PM PDT 24 |
| Finished | Jul 25 07:29:45 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-6aacc73c-31cd-4457-95da-c16f76ddb2ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020064286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2020064286 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.1104170950 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 39041927 ps |
| CPU time | 5.69 seconds |
| Started | Jul 25 07:28:39 PM PDT 24 |
| Finished | Jul 25 07:28:45 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-04145f94-628b-4731-8510-269aa1315cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104170950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1104170950 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2402918331 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 8507668500 ps |
| CPU time | 79.98 seconds |
| Started | Jul 25 07:28:45 PM PDT 24 |
| Finished | Jul 25 07:30:06 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-30899311-3d45-4528-857d-889b7af0db9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402918331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2402918331 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3231227942 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 5382994947 ps |
| CPU time | 93.05 seconds |
| Started | Jul 25 07:28:53 PM PDT 24 |
| Finished | Jul 25 07:30:26 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-5ca451ff-7442-4ffa-beb2-7638cc0f51a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231227942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3231227942 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.2663317188 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 40340867 ps |
| CPU time | 6.12 seconds |
| Started | Jul 25 07:28:46 PM PDT 24 |
| Finished | Jul 25 07:28:52 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-f6417511-fbba-4fcb-af0a-ccf87ff0c633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663317188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .2663317188 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.627215616 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 11194724498 ps |
| CPU time | 441.63 seconds |
| Started | Jul 25 07:29:11 PM PDT 24 |
| Finished | Jul 25 07:36:32 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-239cc8e7-88c1-4a99-9a1f-2510cd1893f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627215616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.627215616 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2877238376 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 623946454 ps |
| CPU time | 276.83 seconds |
| Started | Jul 25 07:29:10 PM PDT 24 |
| Finished | Jul 25 07:33:47 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-ea13754c-e39b-4d31-9a2e-62bae0f12b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877238376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.2877238376 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.2309254137 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 183778348 ps |
| CPU time | 48.98 seconds |
| Started | Jul 25 07:29:09 PM PDT 24 |
| Finished | Jul 25 07:29:58 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-727dc3a0-01d3-4557-b8f8-b203f6f52697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309254137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.2309254137 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1110076964 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 31343207 ps |
| CPU time | 7 seconds |
| Started | Jul 25 07:28:59 PM PDT 24 |
| Finished | Jul 25 07:29:06 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-af76842b-c621-4fef-8c29-8b9aa6c85d6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110076964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1110076964 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.1401436782 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 2466732237 ps |
| CPU time | 124.78 seconds |
| Started | Jul 25 07:47:46 PM PDT 24 |
| Finished | Jul 25 07:49:51 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-f820611d-0546-42e3-99b2-cc993a4d2e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401436782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .1401436782 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1909624530 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 74695533230 ps |
| CPU time | 1352.84 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 08:10:16 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-c897392a-17b2-4f71-b840-4180d4b6230d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909624530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1909624530 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3375104542 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 98852192 ps |
| CPU time | 12.47 seconds |
| Started | Jul 25 07:47:35 PM PDT 24 |
| Finished | Jul 25 07:47:48 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-a0a0e068-0292-490c-836f-cadbe92f9f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375104542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3375104542 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.564135444 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 1078572286 ps |
| CPU time | 34.91 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:48:18 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-87cd2f02-4e0e-457d-acb0-b281f6d00343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564135444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.564135444 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.3459007933 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 621738741 ps |
| CPU time | 49.04 seconds |
| Started | Jul 25 07:47:44 PM PDT 24 |
| Finished | Jul 25 07:48:33 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b5036019-8137-4cd9-a06f-f08564e88d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459007933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.3459007933 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1218770092 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 92739719573 ps |
| CPU time | 1070.35 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 08:05:34 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-e29502c0-c846-4b08-a778-13a4f54d5344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218770092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1218770092 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.3876386437 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 7282279839 ps |
| CPU time | 127.69 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:49:50 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-56a6027a-1c7f-4821-b47d-f3b53845afd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876386437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.3876386437 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3222927243 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 327658993 ps |
| CPU time | 28.46 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:48:11 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-81e37aa0-f09e-49b4-8f16-b9775b1771d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222927243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.3222927243 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.2261206915 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 1521244751 ps |
| CPU time | 44.49 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:48:27 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-997eafe3-5fd7-46b0-a9af-540d4b5508c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261206915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2261206915 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.684640829 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 54156419 ps |
| CPU time | 7.09 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:47:50 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-98f97d95-6fb4-4ccd-901c-98d41b7c532b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684640829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.684640829 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.215560622 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 9394435563 ps |
| CPU time | 95.45 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:49:18 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d8824b81-beee-4bac-9f96-d0f68cb14e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215560622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.215560622 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.316466872 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 4979152834 ps |
| CPU time | 83.51 seconds |
| Started | Jul 25 07:47:52 PM PDT 24 |
| Finished | Jul 25 07:49:15 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-3526cd57-7b16-4a8d-b030-9447598c9876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316466872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.316466872 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3836790880 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 42276739 ps |
| CPU time | 6.18 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:47:48 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-e79c9865-6da0-4fea-ab74-8327ee97e7f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836790880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.3836790880 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.3325785159 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 1820732667 ps |
| CPU time | 54.39 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:48:36 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9d7d33ad-995d-4d62-a78f-cfb219ffea06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325785159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.3325785159 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.520675647 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 5795940383 ps |
| CPU time | 199.23 seconds |
| Started | Jul 25 07:47:44 PM PDT 24 |
| Finished | Jul 25 07:51:03 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-1b9dd6a3-0d28-4123-ba5e-effd98c7dca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520675647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.520675647 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3722384871 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 833780525 ps |
| CPU time | 85.38 seconds |
| Started | Jul 25 07:47:43 PM PDT 24 |
| Finished | Jul 25 07:49:09 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-a53e89a7-97e6-42dd-9822-c731a960c74c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722384871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3722384871 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2924829450 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 10875777137 ps |
| CPU time | 444.21 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:55:14 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-8a9a45d4-ab03-4e15-b35f-28c4167b131f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924829450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2924829450 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.906189384 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 129545107 ps |
| CPU time | 7.96 seconds |
| Started | Jul 25 07:47:46 PM PDT 24 |
| Finished | Jul 25 07:47:54 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-f634dc0d-49d6-4564-a20f-31a4b4ee654d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906189384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.906189384 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.2329195547 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 949241039 ps |
| CPU time | 62.29 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:52 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-488fe350-4eeb-40a9-8592-19800e4f86ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329195547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2329195547 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3141633575 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 30753106733 ps |
| CPU time | 466.83 seconds |
| Started | Jul 25 07:47:55 PM PDT 24 |
| Finished | Jul 25 07:55:42 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-b35c0ef4-5a43-4875-81d9-83bcc89cc640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141633575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.3141633575 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.904756460 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 804905461 ps |
| CPU time | 30.37 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:19 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-7dce2d9c-0f90-4bbd-8445-a5e9183a4e6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904756460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr .904756460 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.2889059335 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1206329371 ps |
| CPU time | 39.9 seconds |
| Started | Jul 25 07:47:54 PM PDT 24 |
| Finished | Jul 25 07:48:34 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-f3444be4-afe3-4c1b-9c29-aa7f527c5489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889059335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2889059335 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.111613937 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 120429763 ps |
| CPU time | 7.25 seconds |
| Started | Jul 25 07:47:55 PM PDT 24 |
| Finished | Jul 25 07:48:02 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-a8b65294-4ab6-4db1-9e3a-13e33a58332f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111613937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.111613937 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.740382131 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 16895967372 ps |
| CPU time | 176.15 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:50:45 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-fce8d04f-defa-42d2-b643-bd01dca99eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740382131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.740382131 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.51251458 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 48888628175 ps |
| CPU time | 863.97 seconds |
| Started | Jul 25 07:47:55 PM PDT 24 |
| Finished | Jul 25 08:02:19 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-83399eb9-e6e2-4ba8-9072-1163ba2857a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51251458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.51251458 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3130181495 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 525643178 ps |
| CPU time | 44.13 seconds |
| Started | Jul 25 07:47:46 PM PDT 24 |
| Finished | Jul 25 07:48:30 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-04b05961-3977-4c42-837d-2f1d64eae3e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130181495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3130181495 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.29266896 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 2447476522 ps |
| CPU time | 75.74 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:49:05 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-eae58170-d8ec-4a85-9c42-801e470b1c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29266896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.29266896 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.1418876859 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 224568985 ps |
| CPU time | 9.18 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:47:52 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-299c8f5f-098a-4e38-9a42-057744942f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418876859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.1418876859 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.313470147 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 9016715134 ps |
| CPU time | 95.73 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:49:21 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-24f3d5ca-2829-4afe-a1af-ec9562f053b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313470147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.313470147 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1859641439 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 6139028749 ps |
| CPU time | 95.31 seconds |
| Started | Jul 25 07:47:46 PM PDT 24 |
| Finished | Jul 25 07:49:21 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-a93b2ebf-addd-4012-a868-dde3c408d806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859641439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1859641439 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2175394161 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 52076497 ps |
| CPU time | 6.6 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:47:56 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-3526cefc-7636-4f1d-bbb4-47de948bd1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175394161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2175394161 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.843630950 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 3410148344 ps |
| CPU time | 240.95 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:51:50 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-115fc5a7-5e9c-465b-9ff6-57392b947c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843630950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.843630950 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.797079997 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 2768066537 ps |
| CPU time | 192 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:50:57 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-de157cd0-820a-4251-947e-9603e7bf04d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797079997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.797079997 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2402533369 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 8712217411 ps |
| CPU time | 456.91 seconds |
| Started | Jul 25 07:47:33 PM PDT 24 |
| Finished | Jul 25 07:55:10 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-278949c6-97dd-4c79-b0ba-47a575b1f164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402533369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2402533369 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.713962885 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 534011242 ps |
| CPU time | 189.52 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:50:55 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-c91bf52f-927a-4740-9980-622094f5db04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713962885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.713962885 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1577242569 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 128456440 ps |
| CPU time | 16.91 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:48:02 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-3cdc52ca-9b9c-41ce-b7f6-a3251977d2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577242569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1577242569 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.883605621 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 409502290 ps |
| CPU time | 19.25 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:48:21 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-4fc0d924-06ec-48b8-8546-cf3ec914cd54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883605621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 883605621 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3637970315 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 76879820291 ps |
| CPU time | 1371.75 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 08:10:41 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-6ea621d9-93cf-4a0b-89a3-4dbd220bf990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637970315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.3637970315 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1900379876 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 108854616 ps |
| CPU time | 8.03 seconds |
| Started | Jul 25 07:47:46 PM PDT 24 |
| Finished | Jul 25 07:47:54 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-e857b5a2-a97c-47ad-b905-8f7b48ab839f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900379876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1900379876 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.348817059 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 502096477 ps |
| CPU time | 38.69 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 07:48:44 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-31063d30-0dab-4c5a-9cc3-6cba72c72a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348817059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.348817059 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.2647700668 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 2174520802 ps |
| CPU time | 69.6 seconds |
| Started | Jul 25 07:47:38 PM PDT 24 |
| Finished | Jul 25 07:48:47 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-6c986195-6bfd-4e13-bd3a-c05165b0823f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647700668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2647700668 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2194632713 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 30699337183 ps |
| CPU time | 304.52 seconds |
| Started | Jul 25 07:47:42 PM PDT 24 |
| Finished | Jul 25 07:52:47 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-ec3679c1-828e-4b80-9ecb-e922c6fd29b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194632713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2194632713 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1265699998 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 7607070015 ps |
| CPU time | 121.99 seconds |
| Started | Jul 25 07:47:44 PM PDT 24 |
| Finished | Jul 25 07:49:46 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-2f6acc78-d25f-4745-866b-de44469997b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265699998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1265699998 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.151083344 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 183841096 ps |
| CPU time | 15.38 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:04 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-7a9623e1-3a99-4092-9380-6bb3241e3b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151083344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_dela ys.151083344 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.268071570 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2015452028 ps |
| CPU time | 59.66 seconds |
| Started | Jul 25 07:47:52 PM PDT 24 |
| Finished | Jul 25 07:48:52 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-6bf06ca4-05b7-4d7a-adea-569032b8ef2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268071570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.268071570 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.882444179 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 249080414 ps |
| CPU time | 9.66 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:47:54 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d49f8522-4193-4947-aab7-cb52840747cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882444179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.882444179 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1623453408 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 5050472355 ps |
| CPU time | 75.11 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:49:00 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-2020a930-78c9-466a-9cf9-fe3159eb9a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623453408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1623453408 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.884411221 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 58998930 ps |
| CPU time | 6.89 seconds |
| Started | Jul 25 07:47:48 PM PDT 24 |
| Finished | Jul 25 07:47:55 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-2319c8b7-1b1f-44de-b902-64a3f3024ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884411221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .884411221 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3678470408 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 479936638 ps |
| CPU time | 40.25 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:44 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-e59985de-cb04-44d1-a8d6-f456e346327e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678470408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3678470408 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3763612153 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 2077514538 ps |
| CPU time | 71.91 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:49:15 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-17c4b97f-5ad2-4a94-8eb2-201f7d851bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763612153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3763612153 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1301991165 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 1652883745 ps |
| CPU time | 189.74 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:51:13 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-ca5537d2-7488-4657-9300-885d2382705f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301991165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1301991165 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1309765311 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 2720183074 ps |
| CPU time | 284.79 seconds |
| Started | Jul 25 07:47:57 PM PDT 24 |
| Finished | Jul 25 07:52:42 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-e256927d-1dda-4837-a0f1-7649f68a0622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309765311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1309765311 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.286013731 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 1015787655 ps |
| CPU time | 39.44 seconds |
| Started | Jul 25 07:47:45 PM PDT 24 |
| Finished | Jul 25 07:48:25 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c8bcc6d0-64d2-4806-b09f-c4b3b6c3373b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286013731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.286013731 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2307328938 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 1375238856 ps |
| CPU time | 51.96 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:56 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-bb3fe6af-71fb-481c-90d9-9f675f37f246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307328938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .2307328938 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3166093979 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 65558989546 ps |
| CPU time | 1134.05 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 08:06:57 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-5b75757a-a579-4cc4-a241-db435a5a6354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166093979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3166093979 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1040399096 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 49114216 ps |
| CPU time | 7.47 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:11 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-2a0d3f9c-e71f-4a1e-8bf2-0b9497251d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040399096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1040399096 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.3588046927 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 1648669212 ps |
| CPU time | 54.02 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:57 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-c0f93122-19d8-42b5-928a-a3301152347d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588046927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.3588046927 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1194033225 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 295024503 ps |
| CPU time | 24.09 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:48:26 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-2ec439fc-abf9-43ed-a679-e2922ac22dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194033225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1194033225 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.628161003 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 36454833984 ps |
| CPU time | 381.22 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 07:54:27 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-c81c2fdb-c39e-4752-a0cf-ef74fcfba125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628161003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.628161003 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.620203435 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 21060024464 ps |
| CPU time | 365.51 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:54:10 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-961e702a-2a69-4b7c-9702-cf83a60d3fa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620203435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.620203435 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.832988086 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 101440170 ps |
| CPU time | 11.02 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:48:15 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-b9f24195-6f32-450c-926e-56a9c887ad98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832988086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_dela ys.832988086 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2662717664 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 147091286 ps |
| CPU time | 7.69 seconds |
| Started | Jul 25 07:47:58 PM PDT 24 |
| Finished | Jul 25 07:48:05 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-6618bc1d-f1bc-44ce-9b5b-d7c2738ca7d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662717664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2662717664 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3212098200 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 213431885 ps |
| CPU time | 8.81 seconds |
| Started | Jul 25 07:47:58 PM PDT 24 |
| Finished | Jul 25 07:48:07 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-48080bbb-b8af-4ff4-9d30-73781cded887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212098200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3212098200 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3642684950 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 5862147052 ps |
| CPU time | 60.29 seconds |
| Started | Jul 25 07:47:50 PM PDT 24 |
| Finished | Jul 25 07:48:51 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-722d33cc-ec69-467f-a4e4-677109dcf691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642684950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.3642684950 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1803001457 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 4993740518 ps |
| CPU time | 79.53 seconds |
| Started | Jul 25 07:48:06 PM PDT 24 |
| Finished | Jul 25 07:49:25 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-f6b3036e-babe-420c-86d7-bff0b12de3c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803001457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1803001457 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.120264001 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 42905083 ps |
| CPU time | 6.21 seconds |
| Started | Jul 25 07:48:01 PM PDT 24 |
| Finished | Jul 25 07:48:07 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-d1d0d711-207f-496d-8e0a-a81bddc8da8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120264001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .120264001 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.2356579996 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 7433896133 ps |
| CPU time | 228.08 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:51:52 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-9e3a95a5-72c1-41cc-bfef-413c75efdcc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356579996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2356579996 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.323193571 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3002757592 ps |
| CPU time | 100.64 seconds |
| Started | Jul 25 07:48:01 PM PDT 24 |
| Finished | Jul 25 07:49:42 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-de3b5190-5395-41eb-88cb-7a3c08fdbe72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323193571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.323193571 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3317776841 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 524271595 ps |
| CPU time | 163.36 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:50:32 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-9447ec4e-b222-4c24-a3b5-d2d10f1485a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317776841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3317776841 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2848958036 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 80152898 ps |
| CPU time | 21.07 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:24 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-4dd469e1-7e35-48e4-b602-e1eea035a621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848958036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.2848958036 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1144568240 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 1188827277 ps |
| CPU time | 46.17 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:48:50 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-2107a70e-e3e9-4b47-8089-2d85483f6bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144568240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1144568240 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.3881413859 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 1194875254 ps |
| CPU time | 51.67 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 07:48:57 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-9098ce7a-0c46-4b3c-8a2a-368e61b0b14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881413859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .3881413859 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1172642030 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 55994577422 ps |
| CPU time | 967.92 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 08:04:12 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-7c65012c-9703-4558-81d2-8dd31174da82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172642030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.1172642030 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1243959762 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 303379561 ps |
| CPU time | 33.07 seconds |
| Started | Jul 25 07:47:49 PM PDT 24 |
| Finished | Jul 25 07:48:23 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-5cf64e5e-d3ae-4789-812c-351b8341090a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243959762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.1243959762 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3974168923 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 1581520886 ps |
| CPU time | 47.36 seconds |
| Started | Jul 25 07:47:58 PM PDT 24 |
| Finished | Jul 25 07:48:45 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a9cff79d-df52-4344-ad79-b6a9340dfb09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974168923 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3974168923 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.435595636 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 1114540954 ps |
| CPU time | 39.23 seconds |
| Started | Jul 25 07:48:01 PM PDT 24 |
| Finished | Jul 25 07:48:41 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-74668729-b20e-4ec0-b20e-31f27d8f9022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435595636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.435595636 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1997407363 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 106640280083 ps |
| CPU time | 1122.79 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 08:06:46 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-536af944-2c16-46f4-90ce-5866489a431d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997407363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1997407363 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1250161375 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 33868739858 ps |
| CPU time | 635.67 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:58:38 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-9fb90758-1a25-410c-a50d-50cba63b8042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250161375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1250161375 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.3142722872 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 455417609 ps |
| CPU time | 38.58 seconds |
| Started | Jul 25 07:47:48 PM PDT 24 |
| Finished | Jul 25 07:48:27 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-3bdfffe0-8d09-4d9c-80ab-35626dc17d37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142722872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.3142722872 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1173087367 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 493793641 ps |
| CPU time | 34.41 seconds |
| Started | Jul 25 07:48:06 PM PDT 24 |
| Finished | Jul 25 07:48:40 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-5ed61fb4-511c-465c-bf07-39dc13a43333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173087367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1173087367 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.10971178 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 185310434 ps |
| CPU time | 8.09 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:11 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-6d943e3a-2a94-46c1-a91e-374bafcbb3f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10971178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.10971178 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3486597671 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 5148684539 ps |
| CPU time | 52.49 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:48:54 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-303d0d55-1901-4e61-8db7-ea7f290e9d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486597671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3486597671 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.2040630214 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 4148520196 ps |
| CPU time | 67.99 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:49:12 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-6d5ffd18-8cba-4591-821d-07d526ace2b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040630214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.2040630214 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3705250646 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 47355272 ps |
| CPU time | 5.61 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:48:10 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-fbe85601-8bfa-4863-b92d-ca9214f12324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705250646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3705250646 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.3324716591 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 1920568043 ps |
| CPU time | 155.7 seconds |
| Started | Jul 25 07:48:01 PM PDT 24 |
| Finished | Jul 25 07:50:37 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-fb0161d0-4a31-4a11-884c-a370d2808dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324716591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.3324716591 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.3563090156 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 5167627852 ps |
| CPU time | 159.47 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:50:42 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-c9b0f848-e8bd-40df-b969-76b1bf24a7c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563090156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.3563090156 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3259356089 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 14499468348 ps |
| CPU time | 775.34 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 08:00:58 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-81d1db92-ad20-4086-8fce-268ac44bb5d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259356089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.3259356089 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3281207787 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 1161360174 ps |
| CPU time | 46.15 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:49 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-21b6aef2-b68c-4334-8451-b7ca37bd4f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281207787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3281207787 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2351560267 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 583926962 ps |
| CPU time | 38.26 seconds |
| Started | Jul 25 07:48:15 PM PDT 24 |
| Finished | Jul 25 07:48:54 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-ff6f4874-3437-4888-8a3b-5189e250c9af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351560267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .2351560267 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.2803278267 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 117378907949 ps |
| CPU time | 2138.66 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 08:23:45 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-69d34060-b519-424a-a553-153bbbfa8877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803278267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.2803278267 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.1942885265 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 797499304 ps |
| CPU time | 31.78 seconds |
| Started | Jul 25 07:48:06 PM PDT 24 |
| Finished | Jul 25 07:48:38 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-67a0767f-6b4e-4352-bd6c-35c02c7ffc97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942885265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.1942885265 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.783341515 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 693371483 ps |
| CPU time | 24.46 seconds |
| Started | Jul 25 07:48:21 PM PDT 24 |
| Finished | Jul 25 07:48:45 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-d8b6a2d3-7bcf-484d-9829-bcdc5651a618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783341515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.783341515 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.355105999 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 188693443 ps |
| CPU time | 18.65 seconds |
| Started | Jul 25 07:48:03 PM PDT 24 |
| Finished | Jul 25 07:48:22 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-73101d32-5cec-4e68-8b2a-4d4cbec8a4c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355105999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.355105999 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2583303273 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 76655856284 ps |
| CPU time | 866.99 seconds |
| Started | Jul 25 07:48:15 PM PDT 24 |
| Finished | Jul 25 08:02:43 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-6ca22ebe-0e19-46e2-94a9-11f3577779f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583303273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2583303273 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.597759113 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 14811367602 ps |
| CPU time | 236.37 seconds |
| Started | Jul 25 07:48:14 PM PDT 24 |
| Finished | Jul 25 07:52:11 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-71f008dd-3804-4d2d-98fd-9cadcd7ba13c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597759113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.597759113 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1770352301 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 446548885 ps |
| CPU time | 32.76 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:48:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f803b218-0f54-4627-a50f-b779b0572ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770352301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1770352301 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.2203540627 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 1960836984 ps |
| CPU time | 52.81 seconds |
| Started | Jul 25 07:48:15 PM PDT 24 |
| Finished | Jul 25 07:49:08 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-a0df6234-5bdf-4b76-82cc-747b439609f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203540627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.2203540627 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.1077946293 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 225472017 ps |
| CPU time | 9.1 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:48:14 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ce27c565-d58e-48eb-837c-3e15325e52ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077946293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1077946293 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2914910927 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 7660087321 ps |
| CPU time | 81.32 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:49:24 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-dd411f9f-02a1-43a6-87ad-aa07161952a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914910927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2914910927 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2416544894 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 4768363583 ps |
| CPU time | 79.94 seconds |
| Started | Jul 25 07:48:02 PM PDT 24 |
| Finished | Jul 25 07:49:22 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-ac8ce09e-1057-46d5-88e5-6a920cfffff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416544894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2416544894 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.814051524 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 42531869 ps |
| CPU time | 5.82 seconds |
| Started | Jul 25 07:47:50 PM PDT 24 |
| Finished | Jul 25 07:47:56 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-80a79538-245b-40de-b522-85ef150680dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814051524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays .814051524 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2204210324 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 219648563 ps |
| CPU time | 23.14 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 07:48:28 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-03487f4f-abbd-4d4b-a283-0896ce11481a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204210324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2204210324 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.292592348 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 3085977372 ps |
| CPU time | 229.27 seconds |
| Started | Jul 25 07:48:20 PM PDT 24 |
| Finished | Jul 25 07:52:10 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-32511c84-d0ca-4211-81c9-b37f397dc71e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292592348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.292592348 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3579667628 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 371197408 ps |
| CPU time | 68.49 seconds |
| Started | Jul 25 07:48:09 PM PDT 24 |
| Finished | Jul 25 07:49:18 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-2ba717ad-d88e-4750-b934-7fe85a955fb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579667628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3579667628 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2716225998 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 4306870502 ps |
| CPU time | 344.16 seconds |
| Started | Jul 25 07:48:08 PM PDT 24 |
| Finished | Jul 25 07:53:52 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-b6632131-fdc0-4adf-83b8-37893058592f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716225998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2716225998 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2917411001 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 593237750 ps |
| CPU time | 25.39 seconds |
| Started | Jul 25 07:48:06 PM PDT 24 |
| Finished | Jul 25 07:48:31 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-66e57cda-87bc-41d7-9ba2-1f0f0965d59d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917411001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2917411001 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2402313417 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 771728940 ps |
| CPU time | 26.32 seconds |
| Started | Jul 25 07:48:20 PM PDT 24 |
| Finished | Jul 25 07:48:47 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-b4f37818-e40b-4eee-9c26-44603758b9b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402313417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2402313417 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3440514364 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 44016313576 ps |
| CPU time | 731.89 seconds |
| Started | Jul 25 07:48:16 PM PDT 24 |
| Finished | Jul 25 08:00:28 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-684398f4-5fd8-49e9-b7f7-986fb2f332c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440514364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3440514364 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.3487726112 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 324285318 ps |
| CPU time | 33.21 seconds |
| Started | Jul 25 07:48:24 PM PDT 24 |
| Finished | Jul 25 07:48:57 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-1b26ff1c-19bb-4e4f-893b-4fa38a4d7d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487726112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.3487726112 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3865791054 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 192209848 ps |
| CPU time | 18.76 seconds |
| Started | Jul 25 07:48:21 PM PDT 24 |
| Finished | Jul 25 07:48:40 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-196c830a-dc53-4aec-bf82-f2e0d570ef61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865791054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3865791054 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.1570264038 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 599896649 ps |
| CPU time | 49.95 seconds |
| Started | Jul 25 07:48:25 PM PDT 24 |
| Finished | Jul 25 07:49:15 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-5aea23e4-67eb-462f-8464-36c6c0f6258d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570264038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1570264038 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.507915633 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 39829696761 ps |
| CPU time | 410.59 seconds |
| Started | Jul 25 07:48:15 PM PDT 24 |
| Finished | Jul 25 07:55:06 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-8cac3524-92ef-40bd-ae09-3e222accf57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507915633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.507915633 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.4177266547 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 60765600481 ps |
| CPU time | 1109.95 seconds |
| Started | Jul 25 07:48:13 PM PDT 24 |
| Finished | Jul 25 08:06:43 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-add3b8dd-a7e1-4f7a-9ddc-eb9d19676bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177266547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.4177266547 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2796817100 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 283817146 ps |
| CPU time | 25.45 seconds |
| Started | Jul 25 07:48:13 PM PDT 24 |
| Finished | Jul 25 07:48:39 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-21b3fa74-7f19-4138-aa96-973c364b4cb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796817100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.2796817100 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1392356000 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 420474983 ps |
| CPU time | 31.25 seconds |
| Started | Jul 25 07:48:22 PM PDT 24 |
| Finished | Jul 25 07:48:53 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-76508dca-92cc-4099-96a3-788d151640bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392356000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1392356000 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.639650059 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 47785409 ps |
| CPU time | 6.54 seconds |
| Started | Jul 25 07:48:14 PM PDT 24 |
| Finished | Jul 25 07:48:20 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f50ab6b0-f972-4e88-9825-f0e3ea74994c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639650059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.639650059 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1061318435 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 9178865057 ps |
| CPU time | 98.07 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 07:49:43 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-ad411c36-3190-4ab9-82d1-dac60f375a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061318435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1061318435 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1869397886 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 5849396106 ps |
| CPU time | 96.99 seconds |
| Started | Jul 25 07:48:04 PM PDT 24 |
| Finished | Jul 25 07:49:41 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-7fc34bd6-377b-4944-ac42-856c997d0e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869397886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1869397886 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3483070503 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 37644582 ps |
| CPU time | 5.74 seconds |
| Started | Jul 25 07:48:05 PM PDT 24 |
| Finished | Jul 25 07:48:11 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-62d4d897-cc0f-4be7-8e90-cfc8d814ce60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483070503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.3483070503 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.863982082 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 681248032 ps |
| CPU time | 20.12 seconds |
| Started | Jul 25 07:48:22 PM PDT 24 |
| Finished | Jul 25 07:48:42 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-20467b35-df35-47d5-98f3-b82ee77bed3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863982082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.863982082 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1079194730 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 3686902637 ps |
| CPU time | 288 seconds |
| Started | Jul 25 07:48:37 PM PDT 24 |
| Finished | Jul 25 07:53:26 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-4aa37953-d718-496d-a23b-0c824d95575f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079194730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1079194730 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.642266857 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 373325463 ps |
| CPU time | 124.33 seconds |
| Started | Jul 25 07:48:38 PM PDT 24 |
| Finished | Jul 25 07:50:43 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-528cc779-8174-4caa-89fc-1c9685bcc593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642266857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_ with_rand_reset.642266857 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2727099208 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 5850166855 ps |
| CPU time | 351.21 seconds |
| Started | Jul 25 07:48:38 PM PDT 24 |
| Finished | Jul 25 07:54:29 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-61e9f3a0-8cc6-47ab-adeb-22941be84d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727099208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2727099208 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2251323241 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 83200967 ps |
| CPU time | 11.47 seconds |
| Started | Jul 25 07:48:22 PM PDT 24 |
| Finished | Jul 25 07:48:33 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-3921be95-b48b-43b6-a066-6507f0cfa3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251323241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.2251323241 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1664088930 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 1828763335 ps |
| CPU time | 73.71 seconds |
| Started | Jul 25 07:48:41 PM PDT 24 |
| Finished | Jul 25 07:49:55 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-87c2c2aa-a3be-4385-a6d7-5af756165bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664088930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1664088930 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2845785115 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 48469823246 ps |
| CPU time | 884.89 seconds |
| Started | Jul 25 07:48:40 PM PDT 24 |
| Finished | Jul 25 08:03:25 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-3be743db-85a5-422b-9bc4-c389f8ecf2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845785115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2845785115 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.4248757114 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 224173951 ps |
| CPU time | 24.97 seconds |
| Started | Jul 25 07:48:44 PM PDT 24 |
| Finished | Jul 25 07:49:09 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-0b176124-4387-438e-9b17-5458abd51dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248757114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.4248757114 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.2895077024 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 220645772 ps |
| CPU time | 16.4 seconds |
| Started | Jul 25 07:48:43 PM PDT 24 |
| Finished | Jul 25 07:49:00 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d29ff7d4-b23b-4df3-b11c-1dcd455d01cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895077024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.2895077024 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.2191080665 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 1284670137 ps |
| CPU time | 44.95 seconds |
| Started | Jul 25 07:48:37 PM PDT 24 |
| Finished | Jul 25 07:49:22 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ac5a0e57-c1be-4c3a-a246-bab8c068a59c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191080665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2191080665 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1403103779 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 108504193877 ps |
| CPU time | 1154.8 seconds |
| Started | Jul 25 07:48:38 PM PDT 24 |
| Finished | Jul 25 08:07:53 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-a61de4c6-e2d3-406a-9b78-31971ed9df4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403103779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1403103779 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3878448959 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 14866066830 ps |
| CPU time | 244.73 seconds |
| Started | Jul 25 07:48:43 PM PDT 24 |
| Finished | Jul 25 07:52:48 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-c1cb8092-8064-4029-9355-b964d9beb00e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878448959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3878448959 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.2790491306 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 422900612 ps |
| CPU time | 36.05 seconds |
| Started | Jul 25 07:48:39 PM PDT 24 |
| Finished | Jul 25 07:49:15 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-68d608cb-f51e-46ee-affa-72ae02e7fbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790491306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.2790491306 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1127371408 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 1692124655 ps |
| CPU time | 50.95 seconds |
| Started | Jul 25 07:48:41 PM PDT 24 |
| Finished | Jul 25 07:49:32 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-53431330-646e-4cf5-9130-d07a77dedfb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127371408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1127371408 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1396998631 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 226677866 ps |
| CPU time | 9.39 seconds |
| Started | Jul 25 07:48:38 PM PDT 24 |
| Finished | Jul 25 07:48:48 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-5463273f-0d95-440b-85d0-7764d9c9aebe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396998631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1396998631 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.235613862 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 9181440685 ps |
| CPU time | 93.74 seconds |
| Started | Jul 25 07:48:39 PM PDT 24 |
| Finished | Jul 25 07:50:12 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-7d5f1ddb-bbd7-4ee3-a7aa-467c31e34b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235613862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.235613862 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.782554834 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 5972178432 ps |
| CPU time | 101.64 seconds |
| Started | Jul 25 07:48:36 PM PDT 24 |
| Finished | Jul 25 07:50:18 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-3cefc4c5-fe77-49a0-971e-6bb3ae589aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782554834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.782554834 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3653074091 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 42708543 ps |
| CPU time | 6.02 seconds |
| Started | Jul 25 07:48:39 PM PDT 24 |
| Finished | Jul 25 07:48:45 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-690dab42-44a3-4d3d-972e-9e5a20cff04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653074091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.3653074091 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.1829437585 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 3925554835 ps |
| CPU time | 280.59 seconds |
| Started | Jul 25 07:48:40 PM PDT 24 |
| Finished | Jul 25 07:53:21 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-3c7f8328-57c0-4f80-8c38-f3dfb9d8dfa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829437585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1829437585 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3880597735 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 1639819364 ps |
| CPU time | 115.54 seconds |
| Started | Jul 25 07:48:44 PM PDT 24 |
| Finished | Jul 25 07:50:39 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-ff06a5d8-d118-42a2-afe6-f6a9f03ad823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880597735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3880597735 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.680433410 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 1219863023 ps |
| CPU time | 199.03 seconds |
| Started | Jul 25 07:48:43 PM PDT 24 |
| Finished | Jul 25 07:52:02 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-782238b4-5f41-463c-8d2c-acf930b937e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680433410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_rand_reset.680433410 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.1727511229 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 4235664919 ps |
| CPU time | 205.93 seconds |
| Started | Jul 25 07:48:40 PM PDT 24 |
| Finished | Jul 25 07:52:06 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-6c84fd72-ca71-476f-bc83-3af595b131f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727511229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.1727511229 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1668469283 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 864210316 ps |
| CPU time | 39.26 seconds |
| Started | Jul 25 07:48:41 PM PDT 24 |
| Finished | Jul 25 07:49:21 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ae2eb36e-93ef-4988-952b-313cbd077ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668469283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1668469283 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2939130087 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 876750169 ps |
| CPU time | 39.79 seconds |
| Started | Jul 25 07:48:56 PM PDT 24 |
| Finished | Jul 25 07:49:36 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-56aad44a-cac3-46ed-856e-b340447ded98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939130087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2939130087 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3156791815 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 21573052718 ps |
| CPU time | 356.11 seconds |
| Started | Jul 25 07:48:58 PM PDT 24 |
| Finished | Jul 25 07:54:54 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-930e7183-e6a9-4e4c-8c84-4eb5b68bba88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156791815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3156791815 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3551517543 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 451686284 ps |
| CPU time | 19.71 seconds |
| Started | Jul 25 07:48:57 PM PDT 24 |
| Finished | Jul 25 07:49:17 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-64169371-3205-4685-ab1b-d633cc6dd4f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551517543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3551517543 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.205395690 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 157886231 ps |
| CPU time | 15.12 seconds |
| Started | Jul 25 07:48:55 PM PDT 24 |
| Finished | Jul 25 07:49:10 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-fcd50492-cf9c-4b8a-a71c-4fe7a14f14fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205395690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.205395690 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.4077641959 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 164321892 ps |
| CPU time | 9.16 seconds |
| Started | Jul 25 07:48:56 PM PDT 24 |
| Finished | Jul 25 07:49:05 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-94dfde81-8567-495a-8d69-bf42bb779c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077641959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.4077641959 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.2892303242 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 22703961683 ps |
| CPU time | 221.15 seconds |
| Started | Jul 25 07:48:54 PM PDT 24 |
| Finished | Jul 25 07:52:35 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-c6f2c9e0-f77b-40d8-80bb-5021d155d18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892303242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.2892303242 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3436322533 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 61238226271 ps |
| CPU time | 1152.46 seconds |
| Started | Jul 25 07:48:56 PM PDT 24 |
| Finished | Jul 25 08:08:09 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-16ae968d-018c-4537-a773-2678114d2fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436322533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3436322533 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2921468929 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 639940387 ps |
| CPU time | 54.4 seconds |
| Started | Jul 25 07:48:59 PM PDT 24 |
| Finished | Jul 25 07:49:54 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-e948056b-4c7c-4c50-a7ef-66dd83957f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921468929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.2921468929 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.348478811 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 2461798085 ps |
| CPU time | 71.42 seconds |
| Started | Jul 25 07:48:57 PM PDT 24 |
| Finished | Jul 25 07:50:08 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-85adfbad-3909-4621-a379-ef0b26b118ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348478811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.348478811 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.4043956260 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 44250382 ps |
| CPU time | 6.59 seconds |
| Started | Jul 25 07:48:38 PM PDT 24 |
| Finished | Jul 25 07:48:45 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-865da908-3071-43d8-ad9e-a55e80283cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043956260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.4043956260 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2112590279 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 8472677319 ps |
| CPU time | 88.59 seconds |
| Started | Jul 25 07:48:57 PM PDT 24 |
| Finished | Jul 25 07:50:26 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-01f39596-3fe7-46b9-a901-fea530dd6497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112590279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2112590279 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2595059020 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 6804352211 ps |
| CPU time | 112.31 seconds |
| Started | Jul 25 07:48:55 PM PDT 24 |
| Finished | Jul 25 07:50:48 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-8ece3de4-dae5-4a87-a69b-de9905ee4100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595059020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2595059020 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.580743254 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 48249251 ps |
| CPU time | 6.21 seconds |
| Started | Jul 25 07:48:55 PM PDT 24 |
| Finished | Jul 25 07:49:02 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-8605cc9f-0567-46b7-87aa-bf7c2d2c1513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580743254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays .580743254 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1821742356 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 4359514173 ps |
| CPU time | 149.92 seconds |
| Started | Jul 25 07:48:56 PM PDT 24 |
| Finished | Jul 25 07:51:26 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-131a647f-7884-4190-a64c-07d2169e5f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821742356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1821742356 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3497383441 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 2951903974 ps |
| CPU time | 204.54 seconds |
| Started | Jul 25 07:48:55 PM PDT 24 |
| Finished | Jul 25 07:52:19 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-7ea5261a-f30e-4b83-8edf-0dd9af3f9a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497383441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3497383441 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.299172492 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 691735140 ps |
| CPU time | 414.05 seconds |
| Started | Jul 25 07:48:57 PM PDT 24 |
| Finished | Jul 25 07:55:51 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-06720423-179a-4442-811d-41dcaec6a17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299172492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_ with_rand_reset.299172492 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.550935061 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 150728052 ps |
| CPU time | 57.74 seconds |
| Started | Jul 25 07:48:57 PM PDT 24 |
| Finished | Jul 25 07:49:54 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-c69a576b-4319-48f2-8d28-514f61934366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550935061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.550935061 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.1611408050 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 301893597 ps |
| CPU time | 34.03 seconds |
| Started | Jul 25 07:48:54 PM PDT 24 |
| Finished | Jul 25 07:49:28 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-1ffd5b16-3daa-4a8c-8fee-3748564efb8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611408050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1611408050 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2144684322 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 3582295903 ps |
| CPU time | 143.72 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:51:26 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-4659949c-a45f-41b6-bc2c-e2de1867794e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144684322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2144684322 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3572696655 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 1315561286 ps |
| CPU time | 55.59 seconds |
| Started | Jul 25 07:49:05 PM PDT 24 |
| Finished | Jul 25 07:50:00 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-268f553b-696b-429c-9caf-494976b69ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572696655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3572696655 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3312025148 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 611830212 ps |
| CPU time | 46.81 seconds |
| Started | Jul 25 07:49:07 PM PDT 24 |
| Finished | Jul 25 07:49:54 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-7af7f6d6-2413-463d-af64-bf060bfa0893 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312025148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3312025148 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.2152548656 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 91976953 ps |
| CPU time | 10 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:49:12 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-af7ee183-c5e7-4c8f-ac9e-2cd7a3fd235e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152548656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2152548656 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.1869715853 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 28427449859 ps |
| CPU time | 304.84 seconds |
| Started | Jul 25 07:49:03 PM PDT 24 |
| Finished | Jul 25 07:54:08 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-6fc480d2-14a5-422d-b659-77642b0ce3a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869715853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.1869715853 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.497702765 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 33359320580 ps |
| CPU time | 557.27 seconds |
| Started | Jul 25 07:49:03 PM PDT 24 |
| Finished | Jul 25 07:58:21 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-4854db31-7728-4b0c-929b-c4ec227eda01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497702765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.497702765 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3393690055 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 131882227 ps |
| CPU time | 14.6 seconds |
| Started | Jul 25 07:48:56 PM PDT 24 |
| Finished | Jul 25 07:49:11 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-8be80186-93ac-4494-988b-9c444aaf249f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393690055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3393690055 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.1563412840 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 2768443197 ps |
| CPU time | 79.35 seconds |
| Started | Jul 25 07:49:05 PM PDT 24 |
| Finished | Jul 25 07:50:24 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-dad34369-4ae7-44e1-af50-90902f57e4c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563412840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1563412840 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.3200304215 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 204941740 ps |
| CPU time | 8.75 seconds |
| Started | Jul 25 07:48:58 PM PDT 24 |
| Finished | Jul 25 07:49:07 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-a6843d73-2544-4815-9088-7739326f7dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200304215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3200304215 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2530976657 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 7036425082 ps |
| CPU time | 71.63 seconds |
| Started | Jul 25 07:48:58 PM PDT 24 |
| Finished | Jul 25 07:50:09 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-46f2c369-bcfc-4873-bcd8-c0da59bda2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530976657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2530976657 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.726214740 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 3754711400 ps |
| CPU time | 59.74 seconds |
| Started | Jul 25 07:48:55 PM PDT 24 |
| Finished | Jul 25 07:49:55 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-4f50fb0e-154f-4899-87bf-a869a52fd0d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726214740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.726214740 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3399394751 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 56069879 ps |
| CPU time | 6.78 seconds |
| Started | Jul 25 07:48:55 PM PDT 24 |
| Finished | Jul 25 07:49:02 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-e3bdf86b-a601-43fb-8149-0ae884468368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399394751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3399394751 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.840554972 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 4426861739 ps |
| CPU time | 168.62 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:51:51 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-1340b422-eea8-4f42-8027-c59f7bf7be0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840554972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.840554972 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3570126922 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 1166580920 ps |
| CPU time | 32.21 seconds |
| Started | Jul 25 07:49:05 PM PDT 24 |
| Finished | Jul 25 07:49:37 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-97f5f671-1d1a-46d6-b53f-f52a29ff421d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570126922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3570126922 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3729349076 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2929022959 ps |
| CPU time | 255.64 seconds |
| Started | Jul 25 07:49:04 PM PDT 24 |
| Finished | Jul 25 07:53:20 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-b00cb693-dcf4-46e2-9d2b-3b185363fa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729349076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3729349076 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.426215678 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 3125429097 ps |
| CPU time | 157.39 seconds |
| Started | Jul 25 07:49:22 PM PDT 24 |
| Finished | Jul 25 07:52:00 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-c8f08743-8935-424b-97e5-f75f5b7ad4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426215678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_reset_error.426215678 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3775365804 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 1126387419 ps |
| CPU time | 47.47 seconds |
| Started | Jul 25 07:49:01 PM PDT 24 |
| Finished | Jul 25 07:49:48 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-9c42cddd-ece3-4e19-9208-c5b8c1980d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775365804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3775365804 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.889193850 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 8976751640 ps |
| CPU time | 813.71 seconds |
| Started | Jul 25 07:29:38 PM PDT 24 |
| Finished | Jul 25 07:43:12 PM PDT 24 |
| Peak memory | 648616 kb |
| Host | smart-2650ba62-c647-481f-936b-5c54abe557b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889193850 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.889193850 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1845815181 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4216870200 ps |
| CPU time | 400.52 seconds |
| Started | Jul 25 07:29:34 PM PDT 24 |
| Finished | Jul 25 07:36:14 PM PDT 24 |
| Peak memory | 596984 kb |
| Host | smart-ba9c54b7-63b3-4b2a-bfa6-11dd481a9263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845815181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1845815181 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3622394315 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 28754848985 ps |
| CPU time | 4278.54 seconds |
| Started | Jul 25 07:29:09 PM PDT 24 |
| Finished | Jul 25 08:40:28 PM PDT 24 |
| Peak memory | 593376 kb |
| Host | smart-24ce99ec-7ac3-47bf-a18c-243ac2341f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622394315 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3622394315 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.2644302295 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4440694378 ps |
| CPU time | 369.05 seconds |
| Started | Jul 25 07:29:12 PM PDT 24 |
| Finished | Jul 25 07:35:21 PM PDT 24 |
| Peak memory | 598608 kb |
| Host | smart-5bd5cc13-7b59-4bb5-9a62-0c0cb895bcc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644302295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.2644302295 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.2661746968 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 1111541987 ps |
| CPU time | 87.16 seconds |
| Started | Jul 25 07:29:23 PM PDT 24 |
| Finished | Jul 25 07:30:51 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-0e19a461-29ac-477b-950b-fa298a079db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661746968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 2661746968 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.61539480 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 108285554612 ps |
| CPU time | 1855.76 seconds |
| Started | Jul 25 07:29:27 PM PDT 24 |
| Finished | Jul 25 08:00:23 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-f0f8b9fb-d186-448a-9c81-e30093b8f17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61539480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_dev ice_slow_rsp.61539480 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.134564847 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 259064369 ps |
| CPU time | 12.77 seconds |
| Started | Jul 25 07:29:23 PM PDT 24 |
| Finished | Jul 25 07:29:36 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-e1701c55-ad71-465d-9ab5-8646e746a91f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134564847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr. 134564847 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.2330966682 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 2175990546 ps |
| CPU time | 69.07 seconds |
| Started | Jul 25 07:29:27 PM PDT 24 |
| Finished | Jul 25 07:30:36 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a53e89d9-5b39-4344-b909-2c6c63635a3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330966682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2330966682 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.4018571845 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 139722240 ps |
| CPU time | 7.69 seconds |
| Started | Jul 25 07:29:23 PM PDT 24 |
| Finished | Jul 25 07:29:30 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-8463af04-53bc-4124-a66d-4b564182850d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018571845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.4018571845 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2088725489 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 20898074960 ps |
| CPU time | 210.16 seconds |
| Started | Jul 25 07:29:25 PM PDT 24 |
| Finished | Jul 25 07:32:55 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-a5a636f2-f9e6-4778-9e2a-c349f71f916a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088725489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2088725489 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.968300688 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 43885980083 ps |
| CPU time | 758.84 seconds |
| Started | Jul 25 07:29:26 PM PDT 24 |
| Finished | Jul 25 07:42:05 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-50afaeda-b71e-4857-af7a-2dba0fccd93c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968300688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.968300688 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2846457257 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 139385346 ps |
| CPU time | 14.74 seconds |
| Started | Jul 25 07:29:29 PM PDT 24 |
| Finished | Jul 25 07:29:44 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ea5ba16e-b765-482f-ad0a-c16af3947f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846457257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.2846457257 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.2261557092 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 333010542 ps |
| CPU time | 24.13 seconds |
| Started | Jul 25 07:30:18 PM PDT 24 |
| Finished | Jul 25 07:30:42 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-08a8f8c4-df85-4bd6-8f67-cff2af69e06a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261557092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2261557092 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.1781224353 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 208863928 ps |
| CPU time | 9.06 seconds |
| Started | Jul 25 07:29:11 PM PDT 24 |
| Finished | Jul 25 07:29:20 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-82f12811-200a-407f-ab93-5a58de2b359e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781224353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1781224353 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.16446594 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 6879371799 ps |
| CPU time | 74.02 seconds |
| Started | Jul 25 07:29:23 PM PDT 24 |
| Finished | Jul 25 07:30:38 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-ed321136-5b31-40ae-bd9e-1d9c740e845f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16446594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.16446594 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2595579474 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 3913276230 ps |
| CPU time | 64.64 seconds |
| Started | Jul 25 07:29:24 PM PDT 24 |
| Finished | Jul 25 07:30:29 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-6b13afe7-0234-4dbc-8e9e-9b3f67840350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595579474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2595579474 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3926117081 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 43441108 ps |
| CPU time | 6.45 seconds |
| Started | Jul 25 07:29:22 PM PDT 24 |
| Finished | Jul 25 07:29:28 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-42887b2c-a36f-4da4-bab9-15e5b0ff437f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926117081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3926117081 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.4256391298 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 881026030 ps |
| CPU time | 69.1 seconds |
| Started | Jul 25 07:29:29 PM PDT 24 |
| Finished | Jul 25 07:30:38 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-00490f73-7a4a-417e-b6c9-451e55448bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256391298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4256391298 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1869108522 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 3377292205 ps |
| CPU time | 290.88 seconds |
| Started | Jul 25 07:29:35 PM PDT 24 |
| Finished | Jul 25 07:34:26 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-609a236e-b385-4ce8-8452-508fc1da844c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869108522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1869108522 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1561378606 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 4403456068 ps |
| CPU time | 264.28 seconds |
| Started | Jul 25 07:29:37 PM PDT 24 |
| Finished | Jul 25 07:34:01 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-05736086-0720-4e66-929a-498686c33b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561378606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1561378606 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1443524655 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 37668548 ps |
| CPU time | 7.14 seconds |
| Started | Jul 25 07:29:24 PM PDT 24 |
| Finished | Jul 25 07:29:31 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-0519bfc7-0bb3-4310-a888-dffa43dcc00e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443524655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1443524655 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.2741614262 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 619605634 ps |
| CPU time | 55.51 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:49:58 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-cafe275e-aadd-44b3-bb16-cc8236a52630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741614262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2741614262 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3076665469 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 60588264346 ps |
| CPU time | 1037.22 seconds |
| Started | Jul 25 07:49:22 PM PDT 24 |
| Finished | Jul 25 08:06:40 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-eb2f3536-8071-4dfa-8703-15d862c301d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076665469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3076665469 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.1405131025 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 485047014 ps |
| CPU time | 20.32 seconds |
| Started | Jul 25 07:49:11 PM PDT 24 |
| Finished | Jul 25 07:49:32 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-cd95976a-fe73-4e65-ab33-0719e05a5a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405131025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.1405131025 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.2459887686 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 1940420662 ps |
| CPU time | 65.82 seconds |
| Started | Jul 25 07:49:07 PM PDT 24 |
| Finished | Jul 25 07:50:13 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-bd861a6e-2fbb-4d23-9f2c-f1fe24d74f89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459887686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2459887686 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.529031524 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 29761495 ps |
| CPU time | 5.69 seconds |
| Started | Jul 25 07:49:05 PM PDT 24 |
| Finished | Jul 25 07:49:11 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-1dd5953c-ecc0-43e3-aeca-a225fa9d7cc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529031524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.529031524 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2957686545 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 100902372140 ps |
| CPU time | 1063.66 seconds |
| Started | Jul 25 07:49:21 PM PDT 24 |
| Finished | Jul 25 08:07:05 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-223fa675-4167-4d45-b854-51905fe81e7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957686545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2957686545 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3663127604 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 30868265019 ps |
| CPU time | 513.84 seconds |
| Started | Jul 25 07:49:05 PM PDT 24 |
| Finished | Jul 25 07:57:39 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-74a4d9a0-a97b-46a3-a65d-e8995988f078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663127604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3663127604 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2075997620 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 94097831 ps |
| CPU time | 10.98 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:49:13 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-8912a312-d6f5-4829-8e59-5cafab262b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075997620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2075997620 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.1118281549 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 586583282 ps |
| CPU time | 19.93 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:49:22 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-3eec5229-2e28-44c1-b8a5-ed8509199d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118281549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1118281549 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1341851554 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 221156852 ps |
| CPU time | 10.22 seconds |
| Started | Jul 25 07:49:02 PM PDT 24 |
| Finished | Jul 25 07:49:13 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-2ed24f6b-9ef4-42dc-976e-e50e76702712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341851554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1341851554 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.653147144 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 8106567456 ps |
| CPU time | 89.76 seconds |
| Started | Jul 25 07:49:09 PM PDT 24 |
| Finished | Jul 25 07:50:39 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-730b6c2d-c2a8-4df8-8e3e-493b2865e5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653147144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.653147144 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3730419823 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 4322925154 ps |
| CPU time | 63.91 seconds |
| Started | Jul 25 07:49:22 PM PDT 24 |
| Finished | Jul 25 07:50:26 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-673cc782-b527-43a2-8c8c-f3d832f9efa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730419823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3730419823 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.390212644 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 42922546 ps |
| CPU time | 5.69 seconds |
| Started | Jul 25 07:49:21 PM PDT 24 |
| Finished | Jul 25 07:49:27 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-0c092e82-7e7f-4fc5-81f4-f0978793773f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390212644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays .390212644 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2970604839 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 952631487 ps |
| CPU time | 69.09 seconds |
| Started | Jul 25 07:49:08 PM PDT 24 |
| Finished | Jul 25 07:50:17 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-b2b2482c-fb42-455a-8162-beceab9fb699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970604839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2970604839 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2185572046 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 338972166 ps |
| CPU time | 84.27 seconds |
| Started | Jul 25 07:49:21 PM PDT 24 |
| Finished | Jul 25 07:50:45 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-54379e17-d4f9-45a9-8dd5-277a84c4b9cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185572046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2185572046 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.2131761473 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 26815113 ps |
| CPU time | 5.86 seconds |
| Started | Jul 25 07:49:06 PM PDT 24 |
| Finished | Jul 25 07:49:12 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-f02c1672-88b0-4f8f-8af1-414984d1f42f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131761473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2131761473 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.295174961 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 2501175570 ps |
| CPU time | 110.67 seconds |
| Started | Jul 25 07:49:14 PM PDT 24 |
| Finished | Jul 25 07:51:05 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-1324355e-2e3c-4cfa-9cbf-6de1027b7507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295174961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device. 295174961 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2875975627 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 119851303941 ps |
| CPU time | 2181.16 seconds |
| Started | Jul 25 07:49:15 PM PDT 24 |
| Finished | Jul 25 08:25:37 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-cb36bcc2-2250-40c3-9a65-11edb85f4f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875975627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.2875975627 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1281087637 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 133503342 ps |
| CPU time | 15.82 seconds |
| Started | Jul 25 07:49:15 PM PDT 24 |
| Finished | Jul 25 07:49:31 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-8142138f-3e40-4f71-8a66-332eee9f176f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281087637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1281087637 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.3645245730 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 1879403077 ps |
| CPU time | 66.37 seconds |
| Started | Jul 25 07:49:13 PM PDT 24 |
| Finished | Jul 25 07:50:19 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-91842051-0a9a-435d-b13d-9268ab704f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645245730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3645245730 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.3823264506 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 586203195 ps |
| CPU time | 47.4 seconds |
| Started | Jul 25 07:49:18 PM PDT 24 |
| Finished | Jul 25 07:50:05 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-2471820a-14d5-4556-8528-23d3be9a8747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823264506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.3823264506 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2706632346 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 58986463629 ps |
| CPU time | 671.09 seconds |
| Started | Jul 25 07:49:14 PM PDT 24 |
| Finished | Jul 25 08:00:25 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-ffcf7519-f873-4a01-97f6-5ad7f94ac37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706632346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2706632346 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.397355363 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 21341669145 ps |
| CPU time | 371.75 seconds |
| Started | Jul 25 07:49:14 PM PDT 24 |
| Finished | Jul 25 07:55:26 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-2c9b7760-46a1-46a6-affa-8426666ac460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397355363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.397355363 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2568500986 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 395840153 ps |
| CPU time | 30.58 seconds |
| Started | Jul 25 07:49:14 PM PDT 24 |
| Finished | Jul 25 07:49:45 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-4bd48d43-8730-47a1-924e-2d40b0b857a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568500986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2568500986 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.4120880608 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 186821107 ps |
| CPU time | 17.33 seconds |
| Started | Jul 25 07:49:23 PM PDT 24 |
| Finished | Jul 25 07:49:41 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-68753e4b-4ea0-49f7-806f-124d987d9033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120880608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.4120880608 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.3766718509 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 162176066 ps |
| CPU time | 8.21 seconds |
| Started | Jul 25 07:49:35 PM PDT 24 |
| Finished | Jul 25 07:49:44 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-3959aa2a-b7fe-42b7-b1f0-19dd2636a38c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766718509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3766718509 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.3072147431 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 5877762359 ps |
| CPU time | 58.85 seconds |
| Started | Jul 25 07:49:14 PM PDT 24 |
| Finished | Jul 25 07:50:13 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-8948265b-ca5a-4e0e-ae21-1a0fb8c236a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072147431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.3072147431 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2359206918 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 4254515163 ps |
| CPU time | 67.83 seconds |
| Started | Jul 25 07:49:17 PM PDT 24 |
| Finished | Jul 25 07:50:25 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-e0a32bad-0e94-46ff-b135-60c360287098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359206918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2359206918 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3404672748 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 57781208 ps |
| CPU time | 7.22 seconds |
| Started | Jul 25 07:49:03 PM PDT 24 |
| Finished | Jul 25 07:49:10 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-673c5e3c-761a-4691-bcad-199b458a7e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404672748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3404672748 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2916931854 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 2188981966 ps |
| CPU time | 151.99 seconds |
| Started | Jul 25 07:49:13 PM PDT 24 |
| Finished | Jul 25 07:51:46 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-0558aec6-833b-42c3-871c-ad65f6fa97be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916931854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2916931854 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.217724472 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 52017430 ps |
| CPU time | 15.94 seconds |
| Started | Jul 25 07:49:17 PM PDT 24 |
| Finished | Jul 25 07:49:33 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-80d8fc3b-c7a5-4983-a737-c70b0b0fb3d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217724472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_ with_rand_reset.217724472 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3523832061 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 3103969944 ps |
| CPU time | 361.97 seconds |
| Started | Jul 25 07:49:23 PM PDT 24 |
| Finished | Jul 25 07:55:26 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-a86d8d95-3c84-4afd-bf8f-d7342dda3335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523832061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.3523832061 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2013451275 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 1302484592 ps |
| CPU time | 57.98 seconds |
| Started | Jul 25 07:49:18 PM PDT 24 |
| Finished | Jul 25 07:50:16 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-34964778-1039-4ce7-a011-6c42ac7c2141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013451275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2013451275 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2325883427 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1276311775 ps |
| CPU time | 89.19 seconds |
| Started | Jul 25 07:49:24 PM PDT 24 |
| Finished | Jul 25 07:50:53 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-779077b2-d639-4207-bbd7-1fd027e4b95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325883427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2325883427 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2255432879 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 873979567 ps |
| CPU time | 30.58 seconds |
| Started | Jul 25 07:49:27 PM PDT 24 |
| Finished | Jul 25 07:49:58 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-f9d50aeb-c6dc-4539-b4d0-eba859552af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255432879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2255432879 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.189837304 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 564008760 ps |
| CPU time | 19.11 seconds |
| Started | Jul 25 07:49:23 PM PDT 24 |
| Finished | Jul 25 07:49:43 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-0607ec48-89c9-4f30-b596-4b90c836f5e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189837304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.189837304 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.3067523806 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 2138666590 ps |
| CPU time | 61.51 seconds |
| Started | Jul 25 07:49:15 PM PDT 24 |
| Finished | Jul 25 07:50:16 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d21e9a7f-5df5-429c-8b87-c7f331dd0a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067523806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3067523806 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.757957033 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 99324315974 ps |
| CPU time | 1024.71 seconds |
| Started | Jul 25 07:49:25 PM PDT 24 |
| Finished | Jul 25 08:06:30 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-92b68cc3-0632-4f8a-9a26-a28f8b11f798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757957033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.757957033 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.1549111967 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 67509444146 ps |
| CPU time | 1280.43 seconds |
| Started | Jul 25 07:49:28 PM PDT 24 |
| Finished | Jul 25 08:10:49 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-f71dfe92-4847-435b-98bf-bbc25b22497e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549111967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.1549111967 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.951200127 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 345763728 ps |
| CPU time | 29.24 seconds |
| Started | Jul 25 07:49:24 PM PDT 24 |
| Finished | Jul 25 07:49:54 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-bb918612-28cb-4942-84f4-6b6f0bbb0ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951200127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.951200127 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1706077447 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 1064376585 ps |
| CPU time | 31.28 seconds |
| Started | Jul 25 07:49:30 PM PDT 24 |
| Finished | Jul 25 07:50:02 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-8b707080-db34-448c-b2b4-60bee7bde8e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706077447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1706077447 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3755333361 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 46646932 ps |
| CPU time | 6.44 seconds |
| Started | Jul 25 07:49:30 PM PDT 24 |
| Finished | Jul 25 07:49:37 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-a9e92e40-4619-469c-a22b-4e1a377c5166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755333361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3755333361 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1133131832 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 7565097165 ps |
| CPU time | 78.5 seconds |
| Started | Jul 25 07:49:14 PM PDT 24 |
| Finished | Jul 25 07:50:32 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-8adc846c-2d5c-4346-8456-7f1f490291b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133131832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1133131832 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.948952543 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 5332293643 ps |
| CPU time | 80.39 seconds |
| Started | Jul 25 07:49:13 PM PDT 24 |
| Finished | Jul 25 07:50:33 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-7731182d-acd6-4ac2-9280-ec894a91bfe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948952543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.948952543 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.127067354 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 50243837 ps |
| CPU time | 5.94 seconds |
| Started | Jul 25 07:49:18 PM PDT 24 |
| Finished | Jul 25 07:49:24 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e279b878-3356-4df9-be7a-35144f132996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127067354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .127067354 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3094859755 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 3226892783 ps |
| CPU time | 307.67 seconds |
| Started | Jul 25 07:49:24 PM PDT 24 |
| Finished | Jul 25 07:54:32 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-2886f489-6ae8-4411-9f55-411741b1aa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094859755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3094859755 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2191811082 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 981395721 ps |
| CPU time | 80.03 seconds |
| Started | Jul 25 07:49:24 PM PDT 24 |
| Finished | Jul 25 07:50:44 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-22ea0f55-2069-445f-b189-cb3c51e71b36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191811082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2191811082 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.213294387 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1580241012 ps |
| CPU time | 188.07 seconds |
| Started | Jul 25 07:49:29 PM PDT 24 |
| Finished | Jul 25 07:52:37 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-06bdd932-6b89-4ac4-8eb7-8f6762122480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213294387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.213294387 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2002268893 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 5466031440 ps |
| CPU time | 322.39 seconds |
| Started | Jul 25 07:49:30 PM PDT 24 |
| Finished | Jul 25 07:54:53 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-d3961440-9568-4df5-a4b2-6df3120a8bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002268893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2002268893 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1065708482 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 132215177 ps |
| CPU time | 17.16 seconds |
| Started | Jul 25 07:49:24 PM PDT 24 |
| Finished | Jul 25 07:49:41 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-24a96bb6-9f90-400b-87cf-c7c38a14a5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065708482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1065708482 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1052598988 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 1534893684 ps |
| CPU time | 62.91 seconds |
| Started | Jul 25 07:49:28 PM PDT 24 |
| Finished | Jul 25 07:50:32 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-b2df0b7b-dd51-467e-a6e3-76d4eebe0748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052598988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .1052598988 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3181777735 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 260082592 ps |
| CPU time | 31.54 seconds |
| Started | Jul 25 07:49:32 PM PDT 24 |
| Finished | Jul 25 07:50:04 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-667f2af0-4c3a-4db9-ac08-1232a34d5f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181777735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3181777735 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.963213145 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 1489840811 ps |
| CPU time | 46.55 seconds |
| Started | Jul 25 07:49:30 PM PDT 24 |
| Finished | Jul 25 07:50:17 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d12af568-1e34-498d-9165-0d66985587a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963213145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.963213145 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.4048626706 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 2460253430 ps |
| CPU time | 88.02 seconds |
| Started | Jul 25 07:49:30 PM PDT 24 |
| Finished | Jul 25 07:50:58 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-a65fa787-e16f-4090-addd-292eba36c8eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048626706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.4048626706 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3006764559 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 71105078036 ps |
| CPU time | 809.13 seconds |
| Started | Jul 25 07:49:29 PM PDT 24 |
| Finished | Jul 25 08:02:59 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-d5b96234-7b65-4e18-b525-6ad388d0215e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006764559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3006764559 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.689983593 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3994215815 ps |
| CPU time | 65.58 seconds |
| Started | Jul 25 07:49:25 PM PDT 24 |
| Finished | Jul 25 07:50:31 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-8a66646b-0c75-4798-9522-9c3ddc451e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689983593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.689983593 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2219943572 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 190975343 ps |
| CPU time | 18.57 seconds |
| Started | Jul 25 07:49:31 PM PDT 24 |
| Finished | Jul 25 07:49:49 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-8b7d37b9-f41d-42f0-91f3-821dac7269a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219943572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.2219943572 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.2394772276 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 312811038 ps |
| CPU time | 22.41 seconds |
| Started | Jul 25 07:49:28 PM PDT 24 |
| Finished | Jul 25 07:49:51 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-b6e28de8-a99b-4424-8ba9-4ed3565273d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394772276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.2394772276 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1497722096 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 46742872 ps |
| CPU time | 6.36 seconds |
| Started | Jul 25 07:49:26 PM PDT 24 |
| Finished | Jul 25 07:49:33 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-f3705929-2a82-4c61-9241-2e8b4b54a2b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497722096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1497722096 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.3813539678 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 7971001785 ps |
| CPU time | 79.37 seconds |
| Started | Jul 25 07:49:29 PM PDT 24 |
| Finished | Jul 25 07:50:48 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-7db9d7b9-6c6f-4098-a06a-383cf8865896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813539678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.3813539678 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2838150542 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 6256247664 ps |
| CPU time | 104.3 seconds |
| Started | Jul 25 07:49:26 PM PDT 24 |
| Finished | Jul 25 07:51:11 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-8b692708-7848-4ef3-9eda-4f04a51f78de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838150542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2838150542 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.4145722784 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 50497997 ps |
| CPU time | 6.28 seconds |
| Started | Jul 25 07:49:26 PM PDT 24 |
| Finished | Jul 25 07:49:33 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9c47783d-b043-4448-8341-3d83204aaa07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145722784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.4145722784 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.403572913 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 3321451181 ps |
| CPU time | 123.61 seconds |
| Started | Jul 25 07:49:37 PM PDT 24 |
| Finished | Jul 25 07:51:40 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-23a96680-21f2-4d74-836e-de62aa3f1617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403572913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.403572913 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3804997924 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 4409763435 ps |
| CPU time | 142.08 seconds |
| Started | Jul 25 07:49:32 PM PDT 24 |
| Finished | Jul 25 07:51:54 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-31f4a197-7a4f-4a23-9c84-8d643c13e52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804997924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3804997924 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.240326137 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 2732446902 ps |
| CPU time | 122.15 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 07:51:36 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-de4a3a1f-d1e3-45e2-881e-e400eb2aa597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240326137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.240326137 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3005604914 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3741837027 ps |
| CPU time | 265.02 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 07:53:59 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-d278924b-0a2f-48ce-bb76-3bffd8a56d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005604914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3005604914 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3994144745 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 782512854 ps |
| CPU time | 32.17 seconds |
| Started | Jul 25 07:49:35 PM PDT 24 |
| Finished | Jul 25 07:50:07 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-695575eb-78c7-448d-9c4b-5a56b264a41a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994144745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3994144745 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.1146627928 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 734926409 ps |
| CPU time | 66.85 seconds |
| Started | Jul 25 07:49:36 PM PDT 24 |
| Finished | Jul 25 07:50:43 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-f8141e9e-ac00-4730-8a9e-7ef313fa2ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146627928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .1146627928 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2103395082 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 168783561 ps |
| CPU time | 21.55 seconds |
| Started | Jul 25 07:49:36 PM PDT 24 |
| Finished | Jul 25 07:49:57 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-584ed8b6-d857-436b-b186-5624246c657d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103395082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2103395082 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.116626385 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 2456235506 ps |
| CPU time | 85.54 seconds |
| Started | Jul 25 07:49:36 PM PDT 24 |
| Finished | Jul 25 07:51:01 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-48c5dc99-a691-4a01-9ef0-d2703780e3dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116626385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.116626385 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.643795179 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 1929174873 ps |
| CPU time | 64.37 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 07:50:38 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-615915a3-473e-497b-bed2-99da03ac6e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643795179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.643795179 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.2747464842 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 96317982767 ps |
| CPU time | 1096.04 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 08:07:51 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-839c62a5-19f1-453c-a516-cd8118bcaafe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747464842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.2747464842 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1139113070 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 13637543441 ps |
| CPU time | 228.49 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 07:53:23 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-15bb65de-c3f4-4acd-8197-40d5556871e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139113070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1139113070 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.649986289 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 360940609 ps |
| CPU time | 32.92 seconds |
| Started | Jul 25 07:49:33 PM PDT 24 |
| Finished | Jul 25 07:50:06 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-7e6e3ab3-1301-4359-9d25-763f5cc83fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649986289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.649986289 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.3458551193 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 1195402537 ps |
| CPU time | 33.42 seconds |
| Started | Jul 25 07:49:33 PM PDT 24 |
| Finished | Jul 25 07:50:07 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b7542fef-0441-4f11-a850-10d7a69f7334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458551193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.3458551193 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.2404055416 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 203149129 ps |
| CPU time | 8.48 seconds |
| Started | Jul 25 07:49:38 PM PDT 24 |
| Finished | Jul 25 07:49:47 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-bc2cdb30-1245-4901-9e73-8c98fbfb9ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404055416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2404055416 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2285112336 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 6776428394 ps |
| CPU time | 64.1 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 07:50:39 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-5d9776a9-ff8d-4ba8-9817-54abdcc74766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285112336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2285112336 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.4067222608 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 4516680256 ps |
| CPU time | 77.81 seconds |
| Started | Jul 25 07:49:32 PM PDT 24 |
| Finished | Jul 25 07:50:50 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-ec0df5ec-296e-4f7d-861d-75519d369e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067222608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.4067222608 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.2246275039 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 42184271 ps |
| CPU time | 6.37 seconds |
| Started | Jul 25 07:49:33 PM PDT 24 |
| Finished | Jul 25 07:49:39 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-57da425b-ed8c-43f7-8d92-269c322fcfb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246275039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.2246275039 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2236497979 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 2782062533 ps |
| CPU time | 215.68 seconds |
| Started | Jul 25 07:49:34 PM PDT 24 |
| Finished | Jul 25 07:53:10 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-cf40d26d-39c8-4f3c-81ef-a275924dad8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236497979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2236497979 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3706994891 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 7984374502 ps |
| CPU time | 273.92 seconds |
| Started | Jul 25 07:49:35 PM PDT 24 |
| Finished | Jul 25 07:54:09 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-36db84de-380e-452c-a4ca-5c772b7e9494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706994891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3706994891 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1747699279 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 8779143737 ps |
| CPU time | 366.55 seconds |
| Started | Jul 25 07:49:38 PM PDT 24 |
| Finished | Jul 25 07:55:44 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-69e7bad6-ceb4-4056-9bb2-cdea0d480f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747699279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.1747699279 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2310683498 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 147254666 ps |
| CPU time | 36.45 seconds |
| Started | Jul 25 07:49:43 PM PDT 24 |
| Finished | Jul 25 07:50:19 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-e3d22701-3fa9-43e8-b16c-c47ea031e471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310683498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2310683498 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3715265012 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 851799206 ps |
| CPU time | 35.79 seconds |
| Started | Jul 25 07:49:35 PM PDT 24 |
| Finished | Jul 25 07:50:11 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-6669850f-fe71-481b-afd4-6ef7f83117c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715265012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3715265012 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2738266890 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 2621677518 ps |
| CPU time | 111.75 seconds |
| Started | Jul 25 07:49:49 PM PDT 24 |
| Finished | Jul 25 07:51:40 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-d806a64e-cbe4-426b-acb8-b1e457aea749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738266890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2738266890 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.171427310 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 65734226478 ps |
| CPU time | 1136.74 seconds |
| Started | Jul 25 07:49:43 PM PDT 24 |
| Finished | Jul 25 08:08:40 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-91c014a8-8178-4644-8bc3-3a1f98ebe477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171427310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d evice_slow_rsp.171427310 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1146962133 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1573344095 ps |
| CPU time | 66.33 seconds |
| Started | Jul 25 07:49:44 PM PDT 24 |
| Finished | Jul 25 07:50:50 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-d473b165-c3f3-4dad-9dac-e52f6abf554c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146962133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1146962133 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.3481686264 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 147639053 ps |
| CPU time | 14.07 seconds |
| Started | Jul 25 07:49:43 PM PDT 24 |
| Finished | Jul 25 07:49:57 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-175ddfa2-6d7c-4de5-a8cb-355ce24f3518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481686264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.3481686264 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.1606614412 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 1499320624 ps |
| CPU time | 50.3 seconds |
| Started | Jul 25 07:49:35 PM PDT 24 |
| Finished | Jul 25 07:50:26 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-3503ab29-b795-4319-b5c7-24ec8ffe695d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606614412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.1606614412 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.727088209 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 38412802923 ps |
| CPU time | 408.08 seconds |
| Started | Jul 25 07:49:38 PM PDT 24 |
| Finished | Jul 25 07:56:26 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f2df20c8-3e27-4eab-b45a-a24baac775ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727088209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.727088209 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3841434091 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 48086031917 ps |
| CPU time | 909.65 seconds |
| Started | Jul 25 07:49:42 PM PDT 24 |
| Finished | Jul 25 08:04:52 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-848f929e-049e-451f-9b8e-5f11f5fb6e09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841434091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3841434091 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.643639397 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 38234048 ps |
| CPU time | 6.48 seconds |
| Started | Jul 25 07:49:33 PM PDT 24 |
| Finished | Jul 25 07:49:39 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-2ada4d9c-5778-4d93-b81e-3d337ab25977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643639397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.643639397 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1433711812 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 402969226 ps |
| CPU time | 32.48 seconds |
| Started | Jul 25 07:49:44 PM PDT 24 |
| Finished | Jul 25 07:50:17 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-4b6b8050-5ba1-4784-9d0e-e61a01c4a3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433711812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1433711812 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.285136455 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 229842434 ps |
| CPU time | 10 seconds |
| Started | Jul 25 07:49:31 PM PDT 24 |
| Finished | Jul 25 07:49:42 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-94082603-3d9c-43d7-9a9c-ba1d4bad12f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285136455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.285136455 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2899994452 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 9308542545 ps |
| CPU time | 90.91 seconds |
| Started | Jul 25 07:49:40 PM PDT 24 |
| Finished | Jul 25 07:51:11 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-bbb57bf7-acbf-4e03-8430-0ed3f047250b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899994452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2899994452 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2513229679 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 4381662363 ps |
| CPU time | 68.14 seconds |
| Started | Jul 25 07:49:37 PM PDT 24 |
| Finished | Jul 25 07:50:46 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-7b07fe8e-cc91-46f5-809b-e2fc3dbb7d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513229679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2513229679 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2628801689 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 51103797 ps |
| CPU time | 6.57 seconds |
| Started | Jul 25 07:49:36 PM PDT 24 |
| Finished | Jul 25 07:49:42 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-8861c9c6-450f-4418-ab03-0c49190cd3aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628801689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2628801689 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1495015814 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3057383337 ps |
| CPU time | 260.26 seconds |
| Started | Jul 25 07:49:47 PM PDT 24 |
| Finished | Jul 25 07:54:07 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-eb5d98fd-cb2c-41f1-aee0-06226e8f3c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495015814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1495015814 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.470785392 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 2985166399 ps |
| CPU time | 229.75 seconds |
| Started | Jul 25 07:49:44 PM PDT 24 |
| Finished | Jul 25 07:53:34 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-94ac352b-fcb1-4a1a-9ec6-d22796dbe101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470785392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.470785392 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3499172919 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 717700849 ps |
| CPU time | 100.68 seconds |
| Started | Jul 25 07:49:43 PM PDT 24 |
| Finished | Jul 25 07:51:24 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-4b92deda-6aef-4f77-90c6-bc44b98d5b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499172919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3499172919 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3659667224 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 3148368657 ps |
| CPU time | 166.2 seconds |
| Started | Jul 25 07:49:46 PM PDT 24 |
| Finished | Jul 25 07:52:33 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-ec3cb762-5191-400a-a83d-f6d0c3119287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659667224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3659667224 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3029819725 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 242476988 ps |
| CPU time | 12.91 seconds |
| Started | Jul 25 07:49:45 PM PDT 24 |
| Finished | Jul 25 07:49:58 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-2ebabb55-3714-499c-8b8b-16c739436c82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029819725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3029819725 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1087543886 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 3299083158 ps |
| CPU time | 122.25 seconds |
| Started | Jul 25 07:49:46 PM PDT 24 |
| Finished | Jul 25 07:51:49 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-5c1cb7ee-3200-4286-91a9-769ec81d9470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087543886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1087543886 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.4276599821 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 57848602030 ps |
| CPU time | 1076.79 seconds |
| Started | Jul 25 07:49:47 PM PDT 24 |
| Finished | Jul 25 08:07:44 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-2b5ae133-cbce-40b1-bc9d-3e29af3c1222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276599821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.4276599821 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2385570144 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 146338833 ps |
| CPU time | 9.37 seconds |
| Started | Jul 25 07:49:54 PM PDT 24 |
| Finished | Jul 25 07:50:04 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-72747f9a-18b7-47f2-ad32-3b0f6eaacc4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385570144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2385570144 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2944357010 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 2080325196 ps |
| CPU time | 66.93 seconds |
| Started | Jul 25 07:49:58 PM PDT 24 |
| Finished | Jul 25 07:51:05 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-e191fa21-eb53-496d-8dd0-d1012238d748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944357010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2944357010 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.2428032099 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 1390054527 ps |
| CPU time | 51.21 seconds |
| Started | Jul 25 07:49:47 PM PDT 24 |
| Finished | Jul 25 07:50:38 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-e59d5f50-11d9-4562-9f80-f2bddfa194b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428032099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2428032099 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3389770046 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 60529550388 ps |
| CPU time | 633.75 seconds |
| Started | Jul 25 07:49:47 PM PDT 24 |
| Finished | Jul 25 08:00:21 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-5af336b3-c786-4bf7-8c7b-ba37d50c5f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389770046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3389770046 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2487169634 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 31312402954 ps |
| CPU time | 561.92 seconds |
| Started | Jul 25 07:49:44 PM PDT 24 |
| Finished | Jul 25 07:59:06 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-2a68d8a6-1ab3-4e4b-ac42-ddd3f0fbb676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487169634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2487169634 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.5392315 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 610121076 ps |
| CPU time | 52.75 seconds |
| Started | Jul 25 07:49:47 PM PDT 24 |
| Finished | Jul 25 07:50:40 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-5aee6898-a3cd-42db-ada8-5848a144152b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5392315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_delays.5392315 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1940930583 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 2299975334 ps |
| CPU time | 72.08 seconds |
| Started | Jul 25 07:49:47 PM PDT 24 |
| Finished | Jul 25 07:50:59 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-bc5f2120-d62f-497d-bd3e-da8c953296cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940930583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1940930583 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.53600729 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 43470452 ps |
| CPU time | 5.95 seconds |
| Started | Jul 25 07:49:46 PM PDT 24 |
| Finished | Jul 25 07:49:52 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-2c897e46-9c8e-41e6-b607-9e480babaf5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53600729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.53600729 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2926928572 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 6840507405 ps |
| CPU time | 72.03 seconds |
| Started | Jul 25 07:49:43 PM PDT 24 |
| Finished | Jul 25 07:50:55 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-00624368-5400-4b4b-805f-bc7531c2cac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926928572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2926928572 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.578752291 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 6485322017 ps |
| CPU time | 106.76 seconds |
| Started | Jul 25 07:49:44 PM PDT 24 |
| Finished | Jul 25 07:51:31 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e035d90b-7d3a-46f4-be6c-69edcff88bc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578752291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.578752291 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3323438622 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 53093386 ps |
| CPU time | 6.26 seconds |
| Started | Jul 25 07:49:44 PM PDT 24 |
| Finished | Jul 25 07:49:50 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-7d300819-e369-45be-8108-73ffa7ae3f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323438622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.3323438622 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3988240842 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 4094757633 ps |
| CPU time | 344.33 seconds |
| Started | Jul 25 07:49:52 PM PDT 24 |
| Finished | Jul 25 07:55:37 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-39133662-9302-4c81-b1b6-af39be150916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988240842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3988240842 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3147318152 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 13523820733 ps |
| CPU time | 450.86 seconds |
| Started | Jul 25 07:49:53 PM PDT 24 |
| Finished | Jul 25 07:57:24 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-92d9f9ea-33c4-4383-b348-1abc68662bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147318152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3147318152 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.357857304 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 557939590 ps |
| CPU time | 136.14 seconds |
| Started | Jul 25 07:49:58 PM PDT 24 |
| Finished | Jul 25 07:52:14 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-a6d9a1bf-dff4-45a5-a145-fbfa259cfc7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357857304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.357857304 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.139021279 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 206387732 ps |
| CPU time | 23.68 seconds |
| Started | Jul 25 07:49:57 PM PDT 24 |
| Finished | Jul 25 07:50:20 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-c39b1459-1876-41e0-951d-533dd2848e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139021279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.139021279 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3218993621 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 1915122579 ps |
| CPU time | 79.27 seconds |
| Started | Jul 25 07:49:54 PM PDT 24 |
| Finished | Jul 25 07:51:14 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e819a9e9-5be4-4b38-9491-a15fe285a351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218993621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .3218993621 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1582487171 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 12815789845 ps |
| CPU time | 202.91 seconds |
| Started | Jul 25 07:49:52 PM PDT 24 |
| Finished | Jul 25 07:53:16 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-503261f7-a47d-4326-8097-eafd2036eca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582487171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1582487171 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3103408784 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 129227615 ps |
| CPU time | 14.27 seconds |
| Started | Jul 25 07:49:58 PM PDT 24 |
| Finished | Jul 25 07:50:13 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ad36ebdb-a25b-4714-9b59-3fc0a5fe8442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103408784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3103408784 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.78759422 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 866241794 ps |
| CPU time | 28.35 seconds |
| Started | Jul 25 07:49:57 PM PDT 24 |
| Finished | Jul 25 07:50:25 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-0b705a5f-8348-4945-bd0d-f1e11a981847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78759422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.78759422 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1760623017 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2017259600 ps |
| CPU time | 75.94 seconds |
| Started | Jul 25 07:49:53 PM PDT 24 |
| Finished | Jul 25 07:51:09 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c45bf71b-6429-4293-ba77-051ce771f9bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760623017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1760623017 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3051150022 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 37507332826 ps |
| CPU time | 380.28 seconds |
| Started | Jul 25 07:49:54 PM PDT 24 |
| Finished | Jul 25 07:56:15 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-15c7a036-7c22-449f-a509-cde5765b3486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051150022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3051150022 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.1625335210 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 5574747911 ps |
| CPU time | 95.1 seconds |
| Started | Jul 25 07:49:56 PM PDT 24 |
| Finished | Jul 25 07:51:31 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-41acfdbc-64f9-492b-83a0-de3fb57a0658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625335210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1625335210 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4100292029 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 526793828 ps |
| CPU time | 48.31 seconds |
| Started | Jul 25 07:49:58 PM PDT 24 |
| Finished | Jul 25 07:50:46 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-ea45886d-38de-46a9-b71b-e5f35f9d5b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100292029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.4100292029 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2488362284 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 1579452518 ps |
| CPU time | 42.46 seconds |
| Started | Jul 25 07:49:58 PM PDT 24 |
| Finished | Jul 25 07:50:41 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-7ee488b9-04d3-4596-91e9-a950d88b1522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488362284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2488362284 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2483260646 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 53119907 ps |
| CPU time | 6.92 seconds |
| Started | Jul 25 07:49:53 PM PDT 24 |
| Finished | Jul 25 07:50:01 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-cb1d7d05-eb7e-4113-ad7a-c260a540cc1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483260646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2483260646 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.2668706657 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 7507455955 ps |
| CPU time | 76.82 seconds |
| Started | Jul 25 07:49:55 PM PDT 24 |
| Finished | Jul 25 07:51:12 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-25f6af92-c323-4d5c-a814-7493f340017a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668706657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.2668706657 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2427418326 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 3848379090 ps |
| CPU time | 54.26 seconds |
| Started | Jul 25 07:49:57 PM PDT 24 |
| Finished | Jul 25 07:50:51 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-ed879388-6230-4480-913d-5bb52f2cc2a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427418326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2427418326 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3410257020 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 37021921 ps |
| CPU time | 5.49 seconds |
| Started | Jul 25 07:49:54 PM PDT 24 |
| Finished | Jul 25 07:50:00 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-92201fd1-a316-4c28-ba70-2a802a9f5231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410257020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3410257020 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.2983016210 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 4894814970 ps |
| CPU time | 403.32 seconds |
| Started | Jul 25 07:49:56 PM PDT 24 |
| Finished | Jul 25 07:56:40 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-a25bbf82-09ac-4252-bdbb-72cc44bdc074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983016210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2983016210 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2063021617 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 1065710422 ps |
| CPU time | 75 seconds |
| Started | Jul 25 07:49:56 PM PDT 24 |
| Finished | Jul 25 07:51:12 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-7cceca75-1f56-459e-a205-47271abb74b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063021617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.2063021617 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1651374296 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 4705184509 ps |
| CPU time | 190.37 seconds |
| Started | Jul 25 07:49:55 PM PDT 24 |
| Finished | Jul 25 07:53:06 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-27476ffe-18c9-452c-bd9f-47de8b08be6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651374296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.1651374296 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.797483855 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 80906602 ps |
| CPU time | 6.84 seconds |
| Started | Jul 25 07:49:57 PM PDT 24 |
| Finished | Jul 25 07:50:04 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-a9e8aace-128f-4c3d-b1e2-e0b088d1946c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797483855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.797483855 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.456277531 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 386237083 ps |
| CPU time | 22.96 seconds |
| Started | Jul 25 07:50:12 PM PDT 24 |
| Finished | Jul 25 07:50:35 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-b1f965e1-7d9f-47f4-8555-8cd335014123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456277531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device. 456277531 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1048897151 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 105114603352 ps |
| CPU time | 1859.26 seconds |
| Started | Jul 25 07:50:04 PM PDT 24 |
| Finished | Jul 25 08:21:04 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-b71ee8e3-a3f8-4446-96e3-d404e2b5f67c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048897151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1048897151 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1573664824 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1396817685 ps |
| CPU time | 54.55 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:51:01 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-b69566cd-bb7d-4d8e-a100-cb2f5a8e2e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573664824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1573664824 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1342067704 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1394335053 ps |
| CPU time | 48.27 seconds |
| Started | Jul 25 07:50:12 PM PDT 24 |
| Finished | Jul 25 07:51:00 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ec4de46a-6079-4c47-aebb-5741cb572421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342067704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1342067704 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2528630213 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 38411867 ps |
| CPU time | 6.37 seconds |
| Started | Jul 25 07:50:12 PM PDT 24 |
| Finished | Jul 25 07:50:18 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-3ffdf7a0-c68e-4938-a2d3-414ccec578ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528630213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2528630213 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3901388877 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 58150391422 ps |
| CPU time | 642.69 seconds |
| Started | Jul 25 07:50:05 PM PDT 24 |
| Finished | Jul 25 08:00:47 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-7df11ff6-bd3f-4b4d-a7f9-803ff5e8a443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901388877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3901388877 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3134659371 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 13711842445 ps |
| CPU time | 230.39 seconds |
| Started | Jul 25 07:50:08 PM PDT 24 |
| Finished | Jul 25 07:53:58 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-e80e9e04-c740-423f-8b8b-603e459c5d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134659371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3134659371 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.685505304 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 422632466 ps |
| CPU time | 36.97 seconds |
| Started | Jul 25 07:50:03 PM PDT 24 |
| Finished | Jul 25 07:50:40 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-3a9bd62f-a2a9-44ca-bb3d-93e51bbfbdc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685505304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.685505304 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.2684752594 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 379346846 ps |
| CPU time | 29.69 seconds |
| Started | Jul 25 07:50:08 PM PDT 24 |
| Finished | Jul 25 07:50:37 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-9a5b4e33-e145-4d14-bde8-7e6c063a170b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684752594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.2684752594 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.15137646 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 228517178 ps |
| CPU time | 9.91 seconds |
| Started | Jul 25 07:49:57 PM PDT 24 |
| Finished | Jul 25 07:50:07 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-7c1c2ff9-3f70-400e-b0d9-da952117ac79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.15137646 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.683187980 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 8062072769 ps |
| CPU time | 92.86 seconds |
| Started | Jul 25 07:50:07 PM PDT 24 |
| Finished | Jul 25 07:51:40 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-bd3c75a9-cbfb-4bcd-8338-f6e273b46086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683187980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.683187980 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.4243673089 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 6918233133 ps |
| CPU time | 125.73 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:52:11 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-73118e6f-4863-4fb5-9bd9-f557f82dbdfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243673089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.4243673089 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.52888640 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 51136344 ps |
| CPU time | 6.13 seconds |
| Started | Jul 25 07:50:13 PM PDT 24 |
| Finished | Jul 25 07:50:19 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-fd1d4ede-1c76-4cb3-90d5-580dfaedf555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52888640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays.52888640 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.4126771879 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 11401420506 ps |
| CPU time | 417.67 seconds |
| Started | Jul 25 07:50:12 PM PDT 24 |
| Finished | Jul 25 07:57:10 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-e2607da7-e2b2-40ef-b7d3-7401497e6e50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126771879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.4126771879 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.3396953010 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 4433323392 ps |
| CPU time | 159.65 seconds |
| Started | Jul 25 07:50:02 PM PDT 24 |
| Finished | Jul 25 07:52:42 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-bec9baa8-7d06-4398-9436-f8d110190efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396953010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.3396953010 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3725605675 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 2657830519 ps |
| CPU time | 356.59 seconds |
| Started | Jul 25 07:50:14 PM PDT 24 |
| Finished | Jul 25 07:56:10 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-911414a0-a736-404d-9962-ba8ec7ccd255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725605675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3725605675 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3342283732 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4921597868 ps |
| CPU time | 365.46 seconds |
| Started | Jul 25 07:50:05 PM PDT 24 |
| Finished | Jul 25 07:56:11 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-c601a2d6-7c6d-492b-8bc4-055c7f5645ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342283732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.3342283732 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1380313008 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 267340851 ps |
| CPU time | 35.55 seconds |
| Started | Jul 25 07:50:04 PM PDT 24 |
| Finished | Jul 25 07:50:40 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2752ccd3-8d1d-4ad7-b12e-d4c98ebca810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380313008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1380313008 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1906399250 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 486670984 ps |
| CPU time | 34.35 seconds |
| Started | Jul 25 07:50:11 PM PDT 24 |
| Finished | Jul 25 07:50:46 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-cbc6cb01-ff5f-4918-8886-3cfba56b411a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906399250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1906399250 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.128826817 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 22113164137 ps |
| CPU time | 362.47 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:56:09 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-1c7bf1ab-8cd4-430c-83a1-d94c383279fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128826817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.128826817 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.4060594056 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 510271193 ps |
| CPU time | 21.47 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:50:28 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-c3cde1fd-db9d-4090-a0be-b2622854b32c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060594056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.4060594056 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.912135966 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 293011571 ps |
| CPU time | 22.17 seconds |
| Started | Jul 25 07:50:14 PM PDT 24 |
| Finished | Jul 25 07:50:36 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-863c9cf1-ccd8-4b2a-92db-0177881ad6a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912135966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.912135966 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1222467044 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 513689205 ps |
| CPU time | 45.93 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:50:52 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-a4a38267-7ff7-4a8a-b5d5-4d3196aea4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222467044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1222467044 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1112480570 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 9887917680 ps |
| CPU time | 99.63 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:51:46 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6ab03b64-0149-4824-97e7-16e01b1be4e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112480570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.1112480570 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3568533561 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 20135022302 ps |
| CPU time | 324.64 seconds |
| Started | Jul 25 07:50:09 PM PDT 24 |
| Finished | Jul 25 07:55:33 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-e712ff71-e648-4e8c-ab0c-67697b88638b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568533561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3568533561 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3029717047 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 517338420 ps |
| CPU time | 40.56 seconds |
| Started | Jul 25 07:50:07 PM PDT 24 |
| Finished | Jul 25 07:50:48 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-890da69b-1441-4703-80aa-22d6056e80bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029717047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3029717047 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.122253028 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 397715975 ps |
| CPU time | 13.63 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:50:20 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-9440ed8c-a3da-4760-9606-4d1f7bed0907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122253028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.122253028 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.1787249470 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 225815830 ps |
| CPU time | 9.49 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:50:16 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9f0cb639-fd2d-46ab-b4f7-e945ad48fd3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787249470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1787249470 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.1512830115 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 9512809496 ps |
| CPU time | 96.06 seconds |
| Started | Jul 25 07:50:08 PM PDT 24 |
| Finished | Jul 25 07:51:44 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-b1c5913d-ab39-49cc-af95-4bb63da0dcf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512830115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1512830115 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.1228336578 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 4778181811 ps |
| CPU time | 84.76 seconds |
| Started | Jul 25 07:50:06 PM PDT 24 |
| Finished | Jul 25 07:51:31 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-224ec9cd-9c89-458e-adf7-f1493f0abd8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228336578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.1228336578 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2409251908 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 50061812 ps |
| CPU time | 6.53 seconds |
| Started | Jul 25 07:50:12 PM PDT 24 |
| Finished | Jul 25 07:50:18 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-651a6017-0403-477b-b0f6-4c409c65c4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409251908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.2409251908 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3690357359 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4918918928 ps |
| CPU time | 189.81 seconds |
| Started | Jul 25 07:50:14 PM PDT 24 |
| Finished | Jul 25 07:53:24 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-739f9d5c-d1ed-4630-88da-24a82f6c5b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690357359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3690357359 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.3620517720 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 868949865 ps |
| CPU time | 66.36 seconds |
| Started | Jul 25 07:50:19 PM PDT 24 |
| Finished | Jul 25 07:51:25 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-76af63e0-3137-45a6-9b46-6ee34f1cfa2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620517720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.3620517720 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.699821062 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 312595805 ps |
| CPU time | 100.87 seconds |
| Started | Jul 25 07:50:15 PM PDT 24 |
| Finished | Jul 25 07:51:56 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ac626e60-815a-4f53-8ee8-220d782cc178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699821062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_ with_rand_reset.699821062 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1379923790 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 72652202 ps |
| CPU time | 26.48 seconds |
| Started | Jul 25 07:50:18 PM PDT 24 |
| Finished | Jul 25 07:50:44 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-595c7370-9629-4d5a-85a0-f057521ab9a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379923790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1379923790 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3959456900 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 322657311 ps |
| CPU time | 13.93 seconds |
| Started | Jul 25 07:50:11 PM PDT 24 |
| Finished | Jul 25 07:50:25 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-ffbbfa87-f03b-4241-881d-756ded9b4793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959456900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3959456900 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.188773967 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 12681492280 ps |
| CPU time | 991.42 seconds |
| Started | Jul 25 07:29:53 PM PDT 24 |
| Finished | Jul 25 07:46:25 PM PDT 24 |
| Peak memory | 650808 kb |
| Host | smart-a745f1ee-32c4-4ee0-8cea-7c3fd01ddcd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188773967 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.188773967 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.309190607 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 3650305108 ps |
| CPU time | 304.3 seconds |
| Started | Jul 25 07:29:57 PM PDT 24 |
| Finished | Jul 25 07:35:01 PM PDT 24 |
| Peak memory | 596408 kb |
| Host | smart-e37c4921-cf3a-4993-b122-691544025675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309190607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.309190607 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.4002078502 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 29994636370 ps |
| CPU time | 2918.91 seconds |
| Started | Jul 25 07:29:37 PM PDT 24 |
| Finished | Jul 25 08:18:16 PM PDT 24 |
| Peak memory | 593504 kb |
| Host | smart-721b397e-b2ea-4add-b6c5-9b59e150ac7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002078502 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.4002078502 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1504063927 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 1659583529 ps |
| CPU time | 73.15 seconds |
| Started | Jul 25 07:29:57 PM PDT 24 |
| Finished | Jul 25 07:31:10 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d0de87a2-5797-4a26-afd9-63bf0a6f904b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504063927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1504063927 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2723602404 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 85477678201 ps |
| CPU time | 1436.98 seconds |
| Started | Jul 25 07:29:54 PM PDT 24 |
| Finished | Jul 25 07:53:51 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-6e338df7-9307-46ab-aa83-92cd0a3b1180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723602404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2723602404 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1245298522 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 190343445 ps |
| CPU time | 18.59 seconds |
| Started | Jul 25 07:29:52 PM PDT 24 |
| Finished | Jul 25 07:30:11 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-61c59e9d-9578-46e9-8cd8-c1bcf040fce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245298522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .1245298522 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.742923546 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 592086883 ps |
| CPU time | 47.22 seconds |
| Started | Jul 25 07:29:53 PM PDT 24 |
| Finished | Jul 25 07:30:40 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-bb056d78-d1b0-4cee-9630-0168a57c83e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742923546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.742923546 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.3976204578 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 944990025 ps |
| CPU time | 35.72 seconds |
| Started | Jul 25 07:29:42 PM PDT 24 |
| Finished | Jul 25 07:30:18 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-fbd805f5-79ea-4494-87f8-cfd0db6e98cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976204578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3976204578 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1432353103 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 88737342020 ps |
| CPU time | 908.92 seconds |
| Started | Jul 25 07:29:52 PM PDT 24 |
| Finished | Jul 25 07:45:01 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-799b784b-bd22-4de3-927c-a72348638ce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432353103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1432353103 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3838963289 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 15762785103 ps |
| CPU time | 255.7 seconds |
| Started | Jul 25 07:29:53 PM PDT 24 |
| Finished | Jul 25 07:34:09 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c4781cc1-ae12-4e14-b0f7-85c4c710b4a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838963289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3838963289 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2435357837 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 378388771 ps |
| CPU time | 38.53 seconds |
| Started | Jul 25 07:29:53 PM PDT 24 |
| Finished | Jul 25 07:30:32 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-59a67c4a-4ed9-4d1c-a7f3-624226202bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435357837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2435357837 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.254905290 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 383268597 ps |
| CPU time | 27.39 seconds |
| Started | Jul 25 07:29:52 PM PDT 24 |
| Finished | Jul 25 07:30:19 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-f74cfca4-1fdb-43bb-bdd1-bdb6b05abeda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254905290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.254905290 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.3183098965 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 50550390 ps |
| CPU time | 6.38 seconds |
| Started | Jul 25 07:29:35 PM PDT 24 |
| Finished | Jul 25 07:29:41 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-68e2d503-b921-4995-8eb4-07a4ee418d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183098965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3183098965 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4003159988 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 8337704292 ps |
| CPU time | 92.85 seconds |
| Started | Jul 25 07:29:41 PM PDT 24 |
| Finished | Jul 25 07:31:14 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-9c8d8608-34b9-4cd9-a319-a2df86184cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003159988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4003159988 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.4282770098 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 5658208226 ps |
| CPU time | 99.13 seconds |
| Started | Jul 25 07:29:41 PM PDT 24 |
| Finished | Jul 25 07:31:20 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-4c90c4c1-f755-4de4-94bf-2c4047a96b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282770098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.4282770098 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3630145504 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 49662086 ps |
| CPU time | 6.68 seconds |
| Started | Jul 25 07:29:32 PM PDT 24 |
| Finished | Jul 25 07:29:39 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-ad05abcd-ec89-45e3-9720-c7860fe81651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630145504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .3630145504 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.3913720016 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 6967013936 ps |
| CPU time | 277.96 seconds |
| Started | Jul 25 07:29:52 PM PDT 24 |
| Finished | Jul 25 07:34:30 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-835797a8-375b-496f-9a6a-87c5bddca35e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913720016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3913720016 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1979820695 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 3649625618 ps |
| CPU time | 271.44 seconds |
| Started | Jul 25 07:29:55 PM PDT 24 |
| Finished | Jul 25 07:34:27 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-8e8133c0-c465-4bb1-b22e-695f49af2cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979820695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1979820695 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.201822489 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 538896014 ps |
| CPU time | 250.86 seconds |
| Started | Jul 25 07:29:54 PM PDT 24 |
| Finished | Jul 25 07:34:05 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-8fd155e1-8f73-4a07-8626-abd090a9035d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201822489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w ith_rand_reset.201822489 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3087331643 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 103164692 ps |
| CPU time | 30.55 seconds |
| Started | Jul 25 07:29:52 PM PDT 24 |
| Finished | Jul 25 07:30:23 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-6c88e6d3-4115-4045-b64c-7bf9fdef1717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087331643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.3087331643 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.597846825 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 174537212 ps |
| CPU time | 23.3 seconds |
| Started | Jul 25 07:29:54 PM PDT 24 |
| Finished | Jul 25 07:30:17 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-788a4f75-0973-40b9-b021-620b3770d5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597846825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.597846825 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.492981680 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 1222347388 ps |
| CPU time | 47.45 seconds |
| Started | Jul 25 07:50:15 PM PDT 24 |
| Finished | Jul 25 07:51:02 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-83cbe177-8216-45df-ae6c-b51f038bff8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492981680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device. 492981680 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.891181636 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2641037223 ps |
| CPU time | 43.06 seconds |
| Started | Jul 25 07:50:16 PM PDT 24 |
| Finished | Jul 25 07:50:59 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-e70c9883-90c3-44a6-8ac3-1472262a34a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891181636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.891181636 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2235828687 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 830611908 ps |
| CPU time | 31.83 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 07:50:57 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-0e75d02b-40ad-498f-b227-f689b3de9398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235828687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.2235828687 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1352712440 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 306947268 ps |
| CPU time | 12.69 seconds |
| Started | Jul 25 07:50:16 PM PDT 24 |
| Finished | Jul 25 07:50:28 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-cbc1b2a3-7946-42c6-bfbc-16da0847d684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352712440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1352712440 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.4207525637 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1796330503 ps |
| CPU time | 60.87 seconds |
| Started | Jul 25 07:50:19 PM PDT 24 |
| Finished | Jul 25 07:51:20 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-bfb211ab-41be-4898-afbb-2a9314aa82e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207525637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.4207525637 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2898319474 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 42904404475 ps |
| CPU time | 460.91 seconds |
| Started | Jul 25 07:50:17 PM PDT 24 |
| Finished | Jul 25 07:57:58 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-06b91874-1226-4860-b41d-85366551f80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898319474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2898319474 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3289296119 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 10675810239 ps |
| CPU time | 177.85 seconds |
| Started | Jul 25 07:50:17 PM PDT 24 |
| Finished | Jul 25 07:53:15 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-6de4745c-aa69-4cf3-b073-73be5bfcb6d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289296119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3289296119 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.986517658 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 327398825 ps |
| CPU time | 26.84 seconds |
| Started | Jul 25 07:50:18 PM PDT 24 |
| Finished | Jul 25 07:50:45 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-efe6f155-ba13-4722-b6ae-56be30299530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986517658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_dela ys.986517658 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2437669820 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 571738598 ps |
| CPU time | 38.27 seconds |
| Started | Jul 25 07:50:18 PM PDT 24 |
| Finished | Jul 25 07:50:56 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-ae9a035f-2ba0-4140-b931-1e811d6b858e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437669820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2437669820 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.907199653 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 221227229 ps |
| CPU time | 9.49 seconds |
| Started | Jul 25 07:50:16 PM PDT 24 |
| Finished | Jul 25 07:50:25 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-e349deed-c257-46dc-a5f8-39f1dec1e13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907199653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.907199653 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.4131865705 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 7999890022 ps |
| CPU time | 76.81 seconds |
| Started | Jul 25 07:50:15 PM PDT 24 |
| Finished | Jul 25 07:51:32 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-99712d49-32dc-42a1-b7c0-143f5140b329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131865705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.4131865705 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.617938847 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 3956081646 ps |
| CPU time | 68.6 seconds |
| Started | Jul 25 07:50:16 PM PDT 24 |
| Finished | Jul 25 07:51:25 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-64832408-631b-49d6-8f74-a08c2512f611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617938847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.617938847 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.610621978 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 48099004 ps |
| CPU time | 6.03 seconds |
| Started | Jul 25 07:50:18 PM PDT 24 |
| Finished | Jul 25 07:50:24 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-87ff1fb4-0886-4f6a-92f9-7adf64cc721c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610621978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays .610621978 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.1030683502 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6167084468 ps |
| CPU time | 226.28 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 07:54:11 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-51829723-d47c-4a95-a234-d69cd38120fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030683502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.1030683502 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3000199523 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 3410751704 ps |
| CPU time | 272.9 seconds |
| Started | Jul 25 07:50:24 PM PDT 24 |
| Finished | Jul 25 07:54:57 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-da0ac819-d62d-4279-aa35-cb7f9c5c0bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000199523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3000199523 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.4054586173 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 262129239 ps |
| CPU time | 117.44 seconds |
| Started | Jul 25 07:50:26 PM PDT 24 |
| Finished | Jul 25 07:52:24 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-8e893e65-2f04-4b73-97dc-9a470cf580eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054586173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.4054586173 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.4172237973 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 2260152822 ps |
| CPU time | 186.88 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 07:53:31 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-d4860d55-d67a-4a6e-95d4-af244dd1283e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172237973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.4172237973 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.1552772753 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 622181147 ps |
| CPU time | 25.48 seconds |
| Started | Jul 25 07:50:26 PM PDT 24 |
| Finished | Jul 25 07:50:52 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f5cdfc38-4251-4aaa-85c6-c78cf0bba0eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552772753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.1552772753 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.3332688439 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 2193971262 ps |
| CPU time | 85.31 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 07:51:51 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-5b2ee26c-270d-4522-ac4a-08258fc07735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332688439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .3332688439 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.357473633 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 79023657061 ps |
| CPU time | 1436.09 seconds |
| Started | Jul 25 07:50:28 PM PDT 24 |
| Finished | Jul 25 08:14:24 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-2cd48e99-372d-40b9-b5c9-924d970d6645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357473633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d evice_slow_rsp.357473633 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2851858733 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 384539332 ps |
| CPU time | 16.57 seconds |
| Started | Jul 25 07:50:26 PM PDT 24 |
| Finished | Jul 25 07:50:42 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-2c1ec44a-3920-41f9-8b2d-278f9543a76c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851858733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2851858733 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.1290499959 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 1652753346 ps |
| CPU time | 59.43 seconds |
| Started | Jul 25 07:50:23 PM PDT 24 |
| Finished | Jul 25 07:51:23 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-f70e0ebe-76f3-41dd-981b-e482a375c29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290499959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1290499959 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.491693139 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 604515042 ps |
| CPU time | 47.59 seconds |
| Started | Jul 25 07:50:27 PM PDT 24 |
| Finished | Jul 25 07:51:14 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-878b15d5-91dc-4704-865e-1bee2510b7d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491693139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.491693139 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3325264891 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 98169873349 ps |
| CPU time | 997.11 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 08:07:03 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f6cbe440-0917-4660-9e7d-accbca9cc985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325264891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3325264891 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2113531386 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 45446921631 ps |
| CPU time | 768.69 seconds |
| Started | Jul 25 07:50:28 PM PDT 24 |
| Finished | Jul 25 08:03:17 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-4175187d-a4b0-4540-aca6-e5c4ed242e36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113531386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2113531386 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2627501683 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 297773113 ps |
| CPU time | 25.8 seconds |
| Started | Jul 25 07:50:24 PM PDT 24 |
| Finished | Jul 25 07:50:50 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-afce151c-f8fe-481c-b330-b0a4c7efcaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627501683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2627501683 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.2277152503 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 323561400 ps |
| CPU time | 25.83 seconds |
| Started | Jul 25 07:50:26 PM PDT 24 |
| Finished | Jul 25 07:50:52 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-76bea9bc-6955-4628-b096-96bdb42adf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277152503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.2277152503 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.1040839834 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 47502237 ps |
| CPU time | 6.36 seconds |
| Started | Jul 25 07:50:24 PM PDT 24 |
| Finished | Jul 25 07:50:31 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-28e424bf-e0a4-4be9-ace9-94428fce6818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040839834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1040839834 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2336069603 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 8540454806 ps |
| CPU time | 87.15 seconds |
| Started | Jul 25 07:50:24 PM PDT 24 |
| Finished | Jul 25 07:51:52 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-86bd812d-f4bf-4d18-a646-22185fa581a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336069603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2336069603 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2151001667 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 5313264519 ps |
| CPU time | 89.15 seconds |
| Started | Jul 25 07:50:27 PM PDT 24 |
| Finished | Jul 25 07:51:57 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-830fd19c-2a89-4e90-9b52-33951522225e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151001667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2151001667 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.344784026 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 51208306 ps |
| CPU time | 6.33 seconds |
| Started | Jul 25 07:50:27 PM PDT 24 |
| Finished | Jul 25 07:50:34 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-804ea99b-d1de-4b0d-823f-378a82db717a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344784026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays .344784026 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.550744040 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 2606790535 ps |
| CPU time | 73.98 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 07:51:39 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-84a66385-04fc-464f-95bb-ee43380d3ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550744040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.550744040 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3023923203 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 340300647 ps |
| CPU time | 96.79 seconds |
| Started | Jul 25 07:50:24 PM PDT 24 |
| Finished | Jul 25 07:52:01 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-5ede1d0e-1adc-4628-a07c-cc803c2f46f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023923203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3023923203 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2758037552 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 767491242 ps |
| CPU time | 227.11 seconds |
| Started | Jul 25 07:50:28 PM PDT 24 |
| Finished | Jul 25 07:54:15 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-64616446-c255-4e43-95f8-1ae16a0bec57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758037552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2758037552 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.2630627873 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 328502077 ps |
| CPU time | 36.21 seconds |
| Started | Jul 25 07:50:25 PM PDT 24 |
| Finished | Jul 25 07:51:01 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-a70af27b-1fa5-44f9-ba9b-23afaaa2e890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630627873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2630627873 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1805731364 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 2823031345 ps |
| CPU time | 109.14 seconds |
| Started | Jul 25 07:50:36 PM PDT 24 |
| Finished | Jul 25 07:52:25 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-08ee9be6-d5f8-4f01-8c87-c2d5aca50ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805731364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1805731364 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.327740693 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 58694047299 ps |
| CPU time | 1124.84 seconds |
| Started | Jul 25 07:50:39 PM PDT 24 |
| Finished | Jul 25 08:09:24 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-747fc545-6fcf-46ca-9b8d-30d32945bf51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327740693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.327740693 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3826114060 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 949186519 ps |
| CPU time | 35.26 seconds |
| Started | Jul 25 07:50:35 PM PDT 24 |
| Finished | Jul 25 07:51:11 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-681bebd4-6468-4f37-ab02-7233ecb545fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826114060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.3826114060 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2691091593 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 1771821773 ps |
| CPU time | 51.86 seconds |
| Started | Jul 25 07:50:37 PM PDT 24 |
| Finished | Jul 25 07:51:29 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-42f6e61f-814d-4777-8433-38b4079e3c6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691091593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2691091593 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.1461809920 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 1674951137 ps |
| CPU time | 60.95 seconds |
| Started | Jul 25 07:50:29 PM PDT 24 |
| Finished | Jul 25 07:51:30 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-54551585-db7c-497c-bda9-77baa23b2aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461809920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1461809920 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.4034614583 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 2608147216 ps |
| CPU time | 26.79 seconds |
| Started | Jul 25 07:50:39 PM PDT 24 |
| Finished | Jul 25 07:51:06 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-9f07bfe8-cbbe-445c-bb6b-4945e9510147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034614583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.4034614583 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1476539600 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 11495424629 ps |
| CPU time | 176 seconds |
| Started | Jul 25 07:50:35 PM PDT 24 |
| Finished | Jul 25 07:53:31 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-90f450a8-e722-4e15-b7db-dd9394dbf9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476539600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1476539600 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2173713499 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 472161121 ps |
| CPU time | 42.17 seconds |
| Started | Jul 25 07:50:37 PM PDT 24 |
| Finished | Jul 25 07:51:20 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-ed7bc969-b1e4-455c-aeec-91a829bd1eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173713499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2173713499 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3705802173 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 354680140 ps |
| CPU time | 25.4 seconds |
| Started | Jul 25 07:50:39 PM PDT 24 |
| Finished | Jul 25 07:51:05 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-84373a1a-c8b5-49a5-a495-4721d31d812b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705802173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3705802173 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.3967142095 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 42030722 ps |
| CPU time | 6.04 seconds |
| Started | Jul 25 07:50:28 PM PDT 24 |
| Finished | Jul 25 07:50:35 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-833b8772-3579-4b15-832a-702af082c4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967142095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3967142095 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.1487976159 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 6466787610 ps |
| CPU time | 66.43 seconds |
| Started | Jul 25 07:50:28 PM PDT 24 |
| Finished | Jul 25 07:51:35 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-9e73bb50-51d0-4159-b64b-fdf3ddea760b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487976159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.1487976159 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1739138562 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 5199199805 ps |
| CPU time | 86.6 seconds |
| Started | Jul 25 07:50:26 PM PDT 24 |
| Finished | Jul 25 07:51:53 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-4396fdcd-fa04-4f82-82cf-3cc715c2ea13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739138562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1739138562 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2664578989 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 43894457 ps |
| CPU time | 6.16 seconds |
| Started | Jul 25 07:50:27 PM PDT 24 |
| Finished | Jul 25 07:50:33 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-134c54b2-83a5-454e-853e-5e7efca31d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664578989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2664578989 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2025883485 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 1787539827 ps |
| CPU time | 159.21 seconds |
| Started | Jul 25 07:50:37 PM PDT 24 |
| Finished | Jul 25 07:53:16 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-f3665305-1951-4156-a197-bc14e344560a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025883485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2025883485 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.4257498730 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 4117217991 ps |
| CPU time | 142.22 seconds |
| Started | Jul 25 07:50:37 PM PDT 24 |
| Finished | Jul 25 07:52:59 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-aa0e93d1-1168-49c8-9b86-b3f3adbc7d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257498730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.4257498730 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2578195572 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 269373944 ps |
| CPU time | 83.51 seconds |
| Started | Jul 25 07:50:35 PM PDT 24 |
| Finished | Jul 25 07:51:58 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-aa43a714-0be2-430d-9be8-d7251273545b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578195572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2578195572 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.502947906 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 9038577408 ps |
| CPU time | 352.34 seconds |
| Started | Jul 25 07:50:36 PM PDT 24 |
| Finished | Jul 25 07:56:28 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-e8eef40f-f562-4cdd-af05-b2f9edb77f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502947906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_reset_error.502947906 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.1944369543 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1354920591 ps |
| CPU time | 45.7 seconds |
| Started | Jul 25 07:50:36 PM PDT 24 |
| Finished | Jul 25 07:51:22 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-059f56cf-5f06-46b7-9cbf-2be6e45917cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944369543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1944369543 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2281357813 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 1513129902 ps |
| CPU time | 57.18 seconds |
| Started | Jul 25 07:50:39 PM PDT 24 |
| Finished | Jul 25 07:51:36 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-00c8e1d5-2150-48ec-b9dc-02732f55e493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281357813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2281357813 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3552954855 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 34321352630 ps |
| CPU time | 642.8 seconds |
| Started | Jul 25 07:50:48 PM PDT 24 |
| Finished | Jul 25 08:01:31 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-9c3249a4-43ed-4f8a-87f6-c9ffbe68e147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552954855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3552954855 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2560100235 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 350801987 ps |
| CPU time | 17.26 seconds |
| Started | Jul 25 07:50:48 PM PDT 24 |
| Finished | Jul 25 07:51:06 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f9519898-fd06-4a04-9b0f-e1336474c259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560100235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2560100235 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1097025520 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 570593526 ps |
| CPU time | 44.01 seconds |
| Started | Jul 25 07:50:48 PM PDT 24 |
| Finished | Jul 25 07:51:32 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-2ae79f70-7e1c-42da-ac04-bae93ec673c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097025520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1097025520 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3173799528 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 2011451023 ps |
| CPU time | 72.85 seconds |
| Started | Jul 25 07:50:38 PM PDT 24 |
| Finished | Jul 25 07:51:51 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7b4a6f5b-08ae-4696-878f-7e19f1ccb99a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173799528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3173799528 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3125980805 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 90607430260 ps |
| CPU time | 1044.69 seconds |
| Started | Jul 25 07:50:37 PM PDT 24 |
| Finished | Jul 25 08:08:02 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-1f5801e8-5294-4afa-a033-77915f62d781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125980805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3125980805 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3681971436 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 62923303946 ps |
| CPU time | 1211.82 seconds |
| Started | Jul 25 07:50:37 PM PDT 24 |
| Finished | Jul 25 08:10:50 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-f5a1fe5f-e7ab-4670-b2b4-ec7c1bd2dde2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681971436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3681971436 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.717640374 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 329357562 ps |
| CPU time | 28.98 seconds |
| Started | Jul 25 07:50:39 PM PDT 24 |
| Finished | Jul 25 07:51:08 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-51322f68-b37e-4729-8fe9-bdc4add24249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717640374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela ys.717640374 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.4273457761 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 478532440 ps |
| CPU time | 36.33 seconds |
| Started | Jul 25 07:50:49 PM PDT 24 |
| Finished | Jul 25 07:51:25 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d83188d0-b06f-4d70-a796-03feb0ef9d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273457761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.4273457761 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3614093370 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 225288055 ps |
| CPU time | 9.65 seconds |
| Started | Jul 25 07:50:36 PM PDT 24 |
| Finished | Jul 25 07:50:46 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-86170435-f0f2-467c-80e6-7774856b919a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614093370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3614093370 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1873804007 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 8908451606 ps |
| CPU time | 89.41 seconds |
| Started | Jul 25 07:50:36 PM PDT 24 |
| Finished | Jul 25 07:52:05 PM PDT 24 |
| Peak memory | 573852 kb |
| Host | smart-7d7b04e2-ae7c-4ff0-bcc3-53e7eb3020d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873804007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1873804007 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3943040055 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 5327475168 ps |
| CPU time | 92.44 seconds |
| Started | Jul 25 07:50:39 PM PDT 24 |
| Finished | Jul 25 07:52:12 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-94c96a94-63f6-46f1-b9c6-339dce423f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943040055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3943040055 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3073872180 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 49657008 ps |
| CPU time | 6.68 seconds |
| Started | Jul 25 07:50:36 PM PDT 24 |
| Finished | Jul 25 07:50:43 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-42bd8aef-ffd8-42cf-90a1-6c419f5762b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073872180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.3073872180 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1385942381 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 4185010582 ps |
| CPU time | 179.46 seconds |
| Started | Jul 25 07:50:46 PM PDT 24 |
| Finished | Jul 25 07:53:46 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-9b2aba58-88f7-404d-965d-7c337de6c359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385942381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1385942381 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2357868954 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 5805092283 ps |
| CPU time | 210.07 seconds |
| Started | Jul 25 07:50:48 PM PDT 24 |
| Finished | Jul 25 07:54:18 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-afd99036-c3ef-4070-86ff-c5eeb89d7b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357868954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2357868954 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1592817440 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 7109115236 ps |
| CPU time | 560.47 seconds |
| Started | Jul 25 07:50:50 PM PDT 24 |
| Finished | Jul 25 08:00:11 PM PDT 24 |
| Peak memory | 576932 kb |
| Host | smart-b28ce1e8-fb15-44b5-a330-db7674d8d2bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592817440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.1592817440 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.355957484 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 812808837 ps |
| CPU time | 36.53 seconds |
| Started | Jul 25 07:50:51 PM PDT 24 |
| Finished | Jul 25 07:51:28 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-91e1611d-6611-4f0d-9466-8ea0b478ec3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355957484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.355957484 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.34788565 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1645272178 ps |
| CPU time | 68.96 seconds |
| Started | Jul 25 07:50:56 PM PDT 24 |
| Finished | Jul 25 07:52:05 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-f07f2dc9-d85e-418c-bcfe-45bdcdbe1e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34788565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device.34788565 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.4176742231 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 41523385613 ps |
| CPU time | 766.14 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 08:03:48 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-d2f79ce9-de35-4f50-91e2-aea2f93f4886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176742231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.4176742231 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3459522014 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 1459697202 ps |
| CPU time | 53.86 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:51:56 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-8230c876-9a10-4bfd-8908-c66973ca881f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459522014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.3459522014 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.4011616030 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 191129132 ps |
| CPU time | 19.53 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:51:22 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-e015db73-2a3b-4146-b8dc-5ba54728128e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011616030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.4011616030 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2571138155 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 467848409 ps |
| CPU time | 20.14 seconds |
| Started | Jul 25 07:50:48 PM PDT 24 |
| Finished | Jul 25 07:51:09 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e2078203-60c7-4311-a11b-2640b69acb99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571138155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2571138155 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.822723594 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 57566965248 ps |
| CPU time | 633.88 seconds |
| Started | Jul 25 07:50:47 PM PDT 24 |
| Finished | Jul 25 08:01:21 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-ebef0ae9-95c8-491c-bcbc-001b8193872c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822723594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.822723594 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3383530719 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 65967773054 ps |
| CPU time | 1209.18 seconds |
| Started | Jul 25 07:50:54 PM PDT 24 |
| Finished | Jul 25 08:11:03 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-72611bb5-be77-4fd1-a555-f85f05464273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383530719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3383530719 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.430544712 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 37770025 ps |
| CPU time | 6.32 seconds |
| Started | Jul 25 07:50:49 PM PDT 24 |
| Finished | Jul 25 07:50:55 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-03efdfec-f381-4847-b036-126fba80dcd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430544712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_dela ys.430544712 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3838402422 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 255098034 ps |
| CPU time | 10.99 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:51:13 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c2951eab-e6cf-4e93-ba95-1fccbe9d566e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838402422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3838402422 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.4147434984 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 48577404 ps |
| CPU time | 6.58 seconds |
| Started | Jul 25 07:50:47 PM PDT 24 |
| Finished | Jul 25 07:50:54 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-e41bf68a-665b-43cd-bfd8-e4f2f9ea9b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147434984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.4147434984 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1149490075 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 8669493059 ps |
| CPU time | 88.72 seconds |
| Started | Jul 25 07:50:47 PM PDT 24 |
| Finished | Jul 25 07:52:16 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-2e4d95d4-1e78-48f9-9cc2-45c77e9ea283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149490075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1149490075 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3640769323 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 4504332248 ps |
| CPU time | 70.05 seconds |
| Started | Jul 25 07:50:54 PM PDT 24 |
| Finished | Jul 25 07:52:04 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-cb4e3d75-d114-48d3-998a-3478cd401bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640769323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3640769323 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.838207014 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 41307752 ps |
| CPU time | 5.78 seconds |
| Started | Jul 25 07:50:48 PM PDT 24 |
| Finished | Jul 25 07:50:54 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-3dacc2a6-588e-43ce-b9d2-b5986d62bcf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838207014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .838207014 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.644597883 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 11358340478 ps |
| CPU time | 445.05 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:58:28 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-2a1b8cce-3b64-40cf-86ba-545c7584f659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644597883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.644597883 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.877773958 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 5595711 ps |
| CPU time | 3.89 seconds |
| Started | Jul 25 07:51:03 PM PDT 24 |
| Finished | Jul 25 07:51:07 PM PDT 24 |
| Peak memory | 565400 kb |
| Host | smart-dad3696e-4455-4320-8406-2007381423e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877773958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.877773958 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2829884001 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 27823451 ps |
| CPU time | 47.6 seconds |
| Started | Jul 25 07:51:01 PM PDT 24 |
| Finished | Jul 25 07:51:49 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-433371e1-c3de-48fd-8b87-bb925c9074bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829884001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.2829884001 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1078394698 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 1101476134 ps |
| CPU time | 45.29 seconds |
| Started | Jul 25 07:51:10 PM PDT 24 |
| Finished | Jul 25 07:51:56 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-a09053b5-ee33-485c-ab4a-de09f091dde9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078394698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1078394698 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2378451189 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 720703559 ps |
| CPU time | 58.16 seconds |
| Started | Jul 25 07:51:17 PM PDT 24 |
| Finished | Jul 25 07:52:15 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-25f8182d-0cd8-4cf6-ac1f-77e6c9dc2c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378451189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2378451189 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1453392473 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 2919066939 ps |
| CPU time | 50.76 seconds |
| Started | Jul 25 07:51:11 PM PDT 24 |
| Finished | Jul 25 07:52:02 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-ab75523e-340f-4fb7-b5df-5664d26379e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453392473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1453392473 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3083375233 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 73486695 ps |
| CPU time | 6.21 seconds |
| Started | Jul 25 07:51:12 PM PDT 24 |
| Finished | Jul 25 07:51:18 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-2f54a9d5-f976-4a4b-9a2f-e3b2e58cdee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083375233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.3083375233 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1701690712 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 230199316 ps |
| CPU time | 10.89 seconds |
| Started | Jul 25 07:51:10 PM PDT 24 |
| Finished | Jul 25 07:51:21 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-4f1a7d9f-32aa-4601-92ba-9d500bf19e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701690712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1701690712 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.2798752017 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 1574781260 ps |
| CPU time | 56.17 seconds |
| Started | Jul 25 07:51:03 PM PDT 24 |
| Finished | Jul 25 07:51:59 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ae28e64b-c56c-4a6c-b080-94879e2decd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798752017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2798752017 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.898931948 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 21221973371 ps |
| CPU time | 212.48 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:54:35 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-e6ded9f5-a2b8-4561-9726-7fa673d0d3d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898931948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.898931948 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.2090801521 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 14266777273 ps |
| CPU time | 246.44 seconds |
| Started | Jul 25 07:51:05 PM PDT 24 |
| Finished | Jul 25 07:55:11 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-6f734037-2187-4a27-94e0-6f9cb9ab82c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090801521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.2090801521 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.3249388671 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 626081471 ps |
| CPU time | 52.61 seconds |
| Started | Jul 25 07:51:03 PM PDT 24 |
| Finished | Jul 25 07:51:56 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-b0ff027a-b824-4e20-925a-ba6bdb5675ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249388671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.3249388671 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.2590997215 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 2406267519 ps |
| CPU time | 75.38 seconds |
| Started | Jul 25 07:51:11 PM PDT 24 |
| Finished | Jul 25 07:52:26 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-cb970e6b-c14b-4e5e-b004-75359cba022a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590997215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2590997215 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.3981426171 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 204892920 ps |
| CPU time | 8.78 seconds |
| Started | Jul 25 07:51:02 PM PDT 24 |
| Finished | Jul 25 07:51:10 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a8c537f3-7921-4f6f-9f5c-f17550daba4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981426171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3981426171 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.421807954 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 6070043709 ps |
| CPU time | 64.33 seconds |
| Started | Jul 25 07:50:57 PM PDT 24 |
| Finished | Jul 25 07:52:02 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-78dd4d91-5e51-485b-8f89-0c961706738b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421807954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.421807954 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.1805057180 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 5852023455 ps |
| CPU time | 93.88 seconds |
| Started | Jul 25 07:51:05 PM PDT 24 |
| Finished | Jul 25 07:52:39 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-0756cec9-d175-4fca-ad10-823b41185d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805057180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.1805057180 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1961827939 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 54529907 ps |
| CPU time | 6.95 seconds |
| Started | Jul 25 07:51:05 PM PDT 24 |
| Finished | Jul 25 07:51:12 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-9402341d-1252-4193-b0c9-0678f4fe19b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961827939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1961827939 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1269722465 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 946487196 ps |
| CPU time | 75.02 seconds |
| Started | Jul 25 07:51:13 PM PDT 24 |
| Finished | Jul 25 07:52:28 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-35e7a77b-455d-4029-abec-37f80c5ed777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269722465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1269722465 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.513720669 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 3931755265 ps |
| CPU time | 153.63 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 07:53:55 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-69dec12d-1d85-4237-a64b-bac29cefea70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513720669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.513720669 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.497053755 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 524152281 ps |
| CPU time | 174.64 seconds |
| Started | Jul 25 07:51:14 PM PDT 24 |
| Finished | Jul 25 07:54:09 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-058a36d9-7ef7-4b2b-ae38-a7fc7da93a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497053755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_ with_rand_reset.497053755 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3603595475 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 150838307 ps |
| CPU time | 81.32 seconds |
| Started | Jul 25 07:51:14 PM PDT 24 |
| Finished | Jul 25 07:52:36 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-9f7c2ed9-b1fe-4f04-a990-fafb5e5decad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603595475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3603595475 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.990749492 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 789658661 ps |
| CPU time | 33.95 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 07:51:56 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-960515e2-41e3-4975-9605-3f8205c68743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990749492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.990749492 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1730967047 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 480055822 ps |
| CPU time | 34.45 seconds |
| Started | Jul 25 07:51:11 PM PDT 24 |
| Finished | Jul 25 07:51:46 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-abb25d27-206e-46af-9e44-27cb82e0cf69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730967047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1730967047 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1425014567 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 5900276911 ps |
| CPU time | 98.81 seconds |
| Started | Jul 25 07:51:18 PM PDT 24 |
| Finished | Jul 25 07:52:57 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-3425df2e-3109-4ee2-bd21-76c2bbec52a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425014567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1425014567 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2147351723 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 203830011 ps |
| CPU time | 20.82 seconds |
| Started | Jul 25 07:51:14 PM PDT 24 |
| Finished | Jul 25 07:51:35 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-97a53589-1a25-4043-913b-3cbb11980c75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147351723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.2147351723 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3323233971 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 497194475 ps |
| CPU time | 38.27 seconds |
| Started | Jul 25 07:51:14 PM PDT 24 |
| Finished | Jul 25 07:51:52 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-308b8bec-035c-4aac-b2f1-c87b40511b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323233971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3323233971 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1917293110 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 1957127852 ps |
| CPU time | 64.9 seconds |
| Started | Jul 25 07:51:14 PM PDT 24 |
| Finished | Jul 25 07:52:19 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-2572bfc5-81ab-467f-9e91-5c62c938952a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917293110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1917293110 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.209673422 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 11032390576 ps |
| CPU time | 110.89 seconds |
| Started | Jul 25 07:51:15 PM PDT 24 |
| Finished | Jul 25 07:53:06 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-33306f34-7dd3-47c8-bc19-8c331f3afb74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209673422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.209673422 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2916258326 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 60666054693 ps |
| CPU time | 1045.03 seconds |
| Started | Jul 25 07:51:13 PM PDT 24 |
| Finished | Jul 25 08:08:38 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-ebf6624b-4121-47de-bf54-2c1077ee877d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916258326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2916258326 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2908923349 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 535100152 ps |
| CPU time | 42.09 seconds |
| Started | Jul 25 07:51:14 PM PDT 24 |
| Finished | Jul 25 07:51:57 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-983f6451-e495-47c3-827f-da9c38160342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908923349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2908923349 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2214119573 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 2443521287 ps |
| CPU time | 71.59 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 07:52:33 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-14b875d6-8071-4966-9091-fc9595865dd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214119573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2214119573 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.1079719731 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 137006446 ps |
| CPU time | 6.81 seconds |
| Started | Jul 25 07:51:12 PM PDT 24 |
| Finished | Jul 25 07:51:19 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-f16f1140-1a20-4cfd-a690-3b5d08c8bb72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079719731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1079719731 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.4215069039 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 9127573984 ps |
| CPU time | 99.28 seconds |
| Started | Jul 25 07:51:12 PM PDT 24 |
| Finished | Jul 25 07:52:51 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-aa331951-9dff-44b7-a9c0-76b62c3fb08d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215069039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.4215069039 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4068215673 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 5194316617 ps |
| CPU time | 87.88 seconds |
| Started | Jul 25 07:51:12 PM PDT 24 |
| Finished | Jul 25 07:52:40 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-02c2cafb-2778-4b8f-be29-b5169c7d44f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068215673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4068215673 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1458902403 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 50481394 ps |
| CPU time | 6.73 seconds |
| Started | Jul 25 07:51:17 PM PDT 24 |
| Finished | Jul 25 07:51:24 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-038a4bfd-3401-487d-a101-2498a45fca30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458902403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1458902403 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.2259188221 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 987907677 ps |
| CPU time | 73.28 seconds |
| Started | Jul 25 07:51:11 PM PDT 24 |
| Finished | Jul 25 07:52:25 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-0a94db72-7f8c-4501-a45d-30cb47546502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259188221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2259188221 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.594010337 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 2476811116 ps |
| CPU time | 198.44 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 07:54:40 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0c737aba-3da0-424d-8af0-4de7eaca6859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594010337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.594010337 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2382583496 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 6680030696 ps |
| CPU time | 342.88 seconds |
| Started | Jul 25 07:51:11 PM PDT 24 |
| Finished | Jul 25 07:56:54 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-279519ce-3ebb-46de-9152-03443c10e1ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382583496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.2382583496 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.110361756 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 1527785380 ps |
| CPU time | 122.54 seconds |
| Started | Jul 25 07:51:11 PM PDT 24 |
| Finished | Jul 25 07:53:13 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-3f7da5d8-1197-4275-a703-17a131d857a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110361756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.110361756 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1603053754 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 94833126 ps |
| CPU time | 6.61 seconds |
| Started | Jul 25 07:51:13 PM PDT 24 |
| Finished | Jul 25 07:51:20 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-b1cbe04e-ced4-48bf-a71a-e4c235687024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603053754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1603053754 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.1385995729 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 2345178417 ps |
| CPU time | 96.58 seconds |
| Started | Jul 25 07:51:26 PM PDT 24 |
| Finished | Jul 25 07:53:02 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-4317b234-7e05-4f61-bc11-2003cdf53c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385995729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .1385995729 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1229550434 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 157501178311 ps |
| CPU time | 2717.51 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 08:36:40 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-51369f00-e26e-4b1a-b1af-7857b8782fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229550434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1229550434 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2559443920 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 193488280 ps |
| CPU time | 21.53 seconds |
| Started | Jul 25 07:51:25 PM PDT 24 |
| Finished | Jul 25 07:51:47 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-7a982e24-f7a9-4fbf-885d-d2454ff77435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559443920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.2559443920 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1092284593 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 156635797 ps |
| CPU time | 7.83 seconds |
| Started | Jul 25 07:51:24 PM PDT 24 |
| Finished | Jul 25 07:51:32 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-4ef85a87-ecdf-4b08-8fc9-3c396899e74e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092284593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1092284593 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.2279549199 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 554575582 ps |
| CPU time | 44.95 seconds |
| Started | Jul 25 07:51:23 PM PDT 24 |
| Finished | Jul 25 07:52:08 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-33307d4e-015c-4121-b17d-267034ecc037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279549199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.2279549199 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.975000516 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 65715215887 ps |
| CPU time | 688.19 seconds |
| Started | Jul 25 07:51:23 PM PDT 24 |
| Finished | Jul 25 08:02:52 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-aad710b7-9cdd-4ff7-ae38-fb687265ede5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975000516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.975000516 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2461409244 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 52048737783 ps |
| CPU time | 950.03 seconds |
| Started | Jul 25 07:51:24 PM PDT 24 |
| Finished | Jul 25 08:07:15 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-4905545e-d65b-4925-8f06-e63b8669a377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461409244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2461409244 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.342794741 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 329618456 ps |
| CPU time | 30.29 seconds |
| Started | Jul 25 07:51:25 PM PDT 24 |
| Finished | Jul 25 07:51:55 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-b3cc6cb9-e316-4d05-aab4-0cb037d569d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342794741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.342794741 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.898947495 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1013799594 ps |
| CPU time | 26.21 seconds |
| Started | Jul 25 07:51:25 PM PDT 24 |
| Finished | Jul 25 07:51:52 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-1bd98c20-8a02-47d0-9398-91f859f558c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898947495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.898947495 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.170440263 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 187635880 ps |
| CPU time | 8.37 seconds |
| Started | Jul 25 07:51:15 PM PDT 24 |
| Finished | Jul 25 07:51:23 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0f6fbb4f-797e-4f1f-b6b8-7705bd4ea672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170440263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.170440263 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2050651660 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 9950754220 ps |
| CPU time | 99.55 seconds |
| Started | Jul 25 07:51:23 PM PDT 24 |
| Finished | Jul 25 07:53:03 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-47363934-51a3-4d53-b4b3-4a1848c724d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050651660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2050651660 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.974356897 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 5065515553 ps |
| CPU time | 85.11 seconds |
| Started | Jul 25 07:51:24 PM PDT 24 |
| Finished | Jul 25 07:52:49 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c09182c0-0aa6-4551-aaea-8f590246e9ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974356897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.974356897 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2314977349 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 41292315 ps |
| CPU time | 6.12 seconds |
| Started | Jul 25 07:51:27 PM PDT 24 |
| Finished | Jul 25 07:51:33 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-ce711196-52e9-4886-863e-38a07ccd518d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314977349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2314977349 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2580293579 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 8833797683 ps |
| CPU time | 336.81 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 07:56:59 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-87c94c2d-b520-4fef-bd27-ffc4e3cdacec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580293579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2580293579 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.1588945803 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 9540478556 ps |
| CPU time | 378.75 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:57:53 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-c6465b1d-d4b4-4567-8428-6f50e85ac3ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588945803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.1588945803 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3913234270 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 10321337846 ps |
| CPU time | 516.3 seconds |
| Started | Jul 25 07:51:26 PM PDT 24 |
| Finished | Jul 25 08:00:03 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-93045056-34e9-464c-a0cd-d55ba5321fed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913234270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3913234270 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1604060892 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 285572929 ps |
| CPU time | 80.42 seconds |
| Started | Jul 25 07:51:36 PM PDT 24 |
| Finished | Jul 25 07:52:56 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-27831572-c7b8-4c36-b6d7-1fd5ca8a12fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604060892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1604060892 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.878510571 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 534053197 ps |
| CPU time | 24.98 seconds |
| Started | Jul 25 07:51:22 PM PDT 24 |
| Finished | Jul 25 07:51:47 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-c330402d-0365-46ae-82fe-eb4d282d7fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878510571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.878510571 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.2447942196 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 3283452827 ps |
| CPU time | 135.41 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:53:50 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-50782c81-632a-4319-95cd-49f90a753c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447942196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2447942196 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3853473477 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 31385459178 ps |
| CPU time | 535.25 seconds |
| Started | Jul 25 07:51:35 PM PDT 24 |
| Finished | Jul 25 08:00:30 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-9523f14e-b09c-45c1-9855-1842b9630761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853473477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.3853473477 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3576031360 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 988340276 ps |
| CPU time | 42.11 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:52:16 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-61a24f22-7b6e-4723-a3bc-89ee81cffe06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576031360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.3576031360 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.1361149721 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 437494529 ps |
| CPU time | 32.95 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:52:07 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0d1e2681-25d2-4274-bab9-cbbee7ff9f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361149721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1361149721 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1217315348 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 1481987149 ps |
| CPU time | 48.85 seconds |
| Started | Jul 25 07:51:38 PM PDT 24 |
| Finished | Jul 25 07:52:27 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-e3fefb4b-748d-49ba-bbc4-fba29b0b7d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217315348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1217315348 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3783629332 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 107206241493 ps |
| CPU time | 1145.11 seconds |
| Started | Jul 25 07:51:45 PM PDT 24 |
| Finished | Jul 25 08:10:51 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-4e291c97-ce3a-43e8-a0c7-81dfae946c52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783629332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3783629332 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1160627897 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 14893481349 ps |
| CPU time | 247.57 seconds |
| Started | Jul 25 07:51:37 PM PDT 24 |
| Finished | Jul 25 07:55:44 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d509ba4d-80c8-4784-bc9a-e69d3f0e3821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160627897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1160627897 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.65798207 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 342123134 ps |
| CPU time | 29.75 seconds |
| Started | Jul 25 07:51:38 PM PDT 24 |
| Finished | Jul 25 07:52:08 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-fa6b5e68-c2e0-45eb-aa12-e6e2d9223c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65798207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_delay s.65798207 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.4010438939 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1485333974 ps |
| CPU time | 51.91 seconds |
| Started | Jul 25 07:58:55 PM PDT 24 |
| Finished | Jul 25 07:59:48 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-b528b206-552b-45e1-b526-db7555f2b0fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010438939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.4010438939 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.1130242426 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 52850788 ps |
| CPU time | 6.4 seconds |
| Started | Jul 25 07:51:36 PM PDT 24 |
| Finished | Jul 25 07:51:42 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-4d1f6e3c-752d-45f7-847f-0e8ba82b3fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130242426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1130242426 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3693844789 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 6331354094 ps |
| CPU time | 64.77 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:52:39 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-dff1ffb7-e61b-4d82-aa95-bab5e6febf22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693844789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3693844789 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3316032233 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 6183303899 ps |
| CPU time | 92.81 seconds |
| Started | Jul 25 07:51:35 PM PDT 24 |
| Finished | Jul 25 07:53:08 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-09d18062-e934-4764-9a71-e02936f6cd0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316032233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3316032233 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.704035874 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 48773046 ps |
| CPU time | 5.81 seconds |
| Started | Jul 25 07:51:36 PM PDT 24 |
| Finished | Jul 25 07:51:42 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-9b154a57-116e-4978-b3f8-60bade1b032a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704035874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .704035874 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.985645888 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3657879551 ps |
| CPU time | 120.33 seconds |
| Started | Jul 25 07:51:37 PM PDT 24 |
| Finished | Jul 25 07:53:38 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c1866289-cf32-46ee-aea3-ad283e3aa0a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985645888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.985645888 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3139982248 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 3670167248 ps |
| CPU time | 121.97 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:53:37 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-58b51cf3-da0b-490e-932c-d425fcd999cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139982248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3139982248 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1971722894 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 42990449 ps |
| CPU time | 25.86 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:52:00 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-c45d432b-954c-4d49-a55a-f2900252d950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971722894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1971722894 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.735542056 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 2810300099 ps |
| CPU time | 217.26 seconds |
| Started | Jul 25 07:51:36 PM PDT 24 |
| Finished | Jul 25 07:55:13 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-246c4cbf-5d34-4a5d-91c6-37efb83e64d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735542056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.735542056 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3911964057 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 318803892 ps |
| CPU time | 35.58 seconds |
| Started | Jul 25 07:51:44 PM PDT 24 |
| Finished | Jul 25 07:52:20 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-081ae574-818c-4e51-aa86-7461042ec99c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911964057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3911964057 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1447106947 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1038834057 ps |
| CPU time | 73.62 seconds |
| Started | Jul 25 07:51:46 PM PDT 24 |
| Finished | Jul 25 07:53:00 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-ac408d47-f58e-4e20-b795-dfcda6fc19a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447106947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1447106947 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3634609756 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 14266255977 ps |
| CPU time | 224.76 seconds |
| Started | Jul 25 07:51:47 PM PDT 24 |
| Finished | Jul 25 07:55:32 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-10233a6d-ef78-4798-9e51-4f0dffd538f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634609756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.3634609756 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2979007520 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 221461443 ps |
| CPU time | 23.23 seconds |
| Started | Jul 25 07:51:45 PM PDT 24 |
| Finished | Jul 25 07:52:09 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-8df66178-0d66-4766-a6d3-4768f117d1ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979007520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2979007520 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.805260502 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 329212473 ps |
| CPU time | 27.5 seconds |
| Started | Jul 25 07:51:46 PM PDT 24 |
| Finished | Jul 25 07:52:13 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-0b82ff20-c1b6-436e-a289-e8d763ab705a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805260502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.805260502 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.150350616 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 386598784 ps |
| CPU time | 32.11 seconds |
| Started | Jul 25 07:51:49 PM PDT 24 |
| Finished | Jul 25 07:52:21 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-fefafe46-9e17-4dd0-aba9-37f6c1a1e96f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150350616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.150350616 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2093555057 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 16251892549 ps |
| CPU time | 165.54 seconds |
| Started | Jul 25 07:51:46 PM PDT 24 |
| Finished | Jul 25 07:54:31 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-50164522-f70c-4e5f-ae65-c92dbf4d445b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093555057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2093555057 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1791159171 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 13463272994 ps |
| CPU time | 222.68 seconds |
| Started | Jul 25 07:51:48 PM PDT 24 |
| Finished | Jul 25 07:55:31 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-7565fb21-8f05-41f5-a26d-16e6eab48435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791159171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1791159171 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.4173032039 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 250819059 ps |
| CPU time | 20.81 seconds |
| Started | Jul 25 07:51:44 PM PDT 24 |
| Finished | Jul 25 07:52:05 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-80a4a744-ae68-4bf0-a448-2cf9adb2d91a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173032039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.4173032039 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.3655467065 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 355350044 ps |
| CPU time | 25.35 seconds |
| Started | Jul 25 07:51:47 PM PDT 24 |
| Finished | Jul 25 07:52:12 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-df2e408b-9b95-4241-9f58-aac498c6929f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655467065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.3655467065 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.2273984489 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 49689598 ps |
| CPU time | 6.51 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:51:40 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-0c8f9ab8-62f6-4ea7-8985-d3343c885488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273984489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2273984489 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.3733249562 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 9935056170 ps |
| CPU time | 100.49 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:53:15 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-8237003d-5ea9-4207-a559-4af653a9a7fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733249562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.3733249562 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.14881988 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 4503287935 ps |
| CPU time | 68.66 seconds |
| Started | Jul 25 07:51:46 PM PDT 24 |
| Finished | Jul 25 07:52:55 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-3dac8dac-d675-44f1-ab9f-72a781183cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14881988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.14881988 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2693785479 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 49094433 ps |
| CPU time | 6.31 seconds |
| Started | Jul 25 07:51:34 PM PDT 24 |
| Finished | Jul 25 07:51:40 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-8d800292-cfe6-4338-aecf-516a3b9f2bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693785479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2693785479 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1195088691 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 943760866 ps |
| CPU time | 72.17 seconds |
| Started | Jul 25 07:51:48 PM PDT 24 |
| Finished | Jul 25 07:53:01 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-08ff1058-f5e9-4d9d-8199-0fbcca259ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195088691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1195088691 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3852644347 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 670177401 ps |
| CPU time | 258.17 seconds |
| Started | Jul 25 07:51:44 PM PDT 24 |
| Finished | Jul 25 07:56:02 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-fa7a1d28-e1a7-41e6-afb3-37c7710fa6d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852644347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.3852644347 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3153808298 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 17612802521 ps |
| CPU time | 872.68 seconds |
| Started | Jul 25 07:51:46 PM PDT 24 |
| Finished | Jul 25 08:06:20 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-79e0d42b-a3d2-453c-8b37-67f0ff5d8ed6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153808298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3153808298 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.543016849 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 119918540 ps |
| CPU time | 16.19 seconds |
| Started | Jul 25 07:51:45 PM PDT 24 |
| Finished | Jul 25 07:52:01 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-eaf30731-39e6-405f-86b9-3b7aa49fd383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543016849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.543016849 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2408560579 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4622564742 ps |
| CPU time | 298.76 seconds |
| Started | Jul 25 07:53:51 PM PDT 24 |
| Finished | Jul 25 07:58:51 PM PDT 24 |
| Peak memory | 608384 kb |
| Host | smart-1b83637a-c7b8-4980-a610-6ad16ed50cff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408560579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2408560579 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.2193392126 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 13599388684 ps |
| CPU time | 1561.93 seconds |
| Started | Jul 25 07:53:41 PM PDT 24 |
| Finished | Jul 25 08:19:43 PM PDT 24 |
| Peak memory | 608480 kb |
| Host | smart-141cd584-f2e2-4532-a4c4-fccf9eb9ed9f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193392126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 193392126 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.251675652 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 4273081388 ps |
| CPU time | 356.94 seconds |
| Started | Jul 25 08:03:54 PM PDT 24 |
| Finished | Jul 25 08:09:51 PM PDT 24 |
| Peak memory | 621404 kb |
| Host | smart-991319ec-b64e-4a93-847f-47c137cf7205 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 51675652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.251675652 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3099108181 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2486027000 ps |
| CPU time | 301.89 seconds |
| Started | Jul 25 07:59:17 PM PDT 24 |
| Finished | Jul 25 08:04:20 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-64204fc5-62c4-4b62-981f-30a0208527a9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3099108181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3099108181 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.4062010133 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 3165489552 ps |
| CPU time | 350.52 seconds |
| Started | Jul 25 08:01:50 PM PDT 24 |
| Finished | Jul 25 08:07:41 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-cdd5b96d-3c9a-49da-83ec-b50d7bce966f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062010133 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.4062010133 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.293001142 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3070659553 ps |
| CPU time | 309.54 seconds |
| Started | Jul 25 08:02:23 PM PDT 24 |
| Finished | Jul 25 08:07:34 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-48397428-4b3f-481a-9e91-143eb3619327 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930 01142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.293001142 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3951499661 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 3257875698 ps |
| CPU time | 248.41 seconds |
| Started | Jul 25 08:02:58 PM PDT 24 |
| Finished | Jul 25 08:07:07 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-d7eaf549-c3af-4ab6-9853-06631a01d5cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951499661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3951499661 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.233759841 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3008623784 ps |
| CPU time | 258.1 seconds |
| Started | Jul 25 08:01:40 PM PDT 24 |
| Finished | Jul 25 08:05:58 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-c34bd1c1-0edd-424f-a274-a68c3b38f0bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233759841 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.233759841 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.3205127851 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2695842400 ps |
| CPU time | 221.39 seconds |
| Started | Jul 25 08:01:11 PM PDT 24 |
| Finished | Jul 25 08:04:53 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-4a33eadc-15ff-4954-83aa-808e635407c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205127851 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3205127851 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.1897877165 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2753927695 ps |
| CPU time | 365.88 seconds |
| Started | Jul 25 08:01:14 PM PDT 24 |
| Finished | Jul 25 08:07:20 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-68e89ec0-ab84-435d-a5f5-50a86ef29b1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897877165 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.1897877165 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.493764748 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 3093782700 ps |
| CPU time | 326.52 seconds |
| Started | Jul 25 08:04:55 PM PDT 24 |
| Finished | Jul 25 08:10:22 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-40acbb92-a9f5-428d-b027-7b16b6cf6002 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493764748 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.493764748 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2846503870 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3127734715 ps |
| CPU time | 334.1 seconds |
| Started | Jul 25 08:02:04 PM PDT 24 |
| Finished | Jul 25 08:07:38 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-b9283ed6-1f0d-4c51-b21b-3ae8db05d2db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2846503870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2846503870 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2871487579 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 4056575966 ps |
| CPU time | 476.74 seconds |
| Started | Jul 25 08:00:17 PM PDT 24 |
| Finished | Jul 25 08:08:14 PM PDT 24 |
| Peak memory | 624404 kb |
| Host | smart-e0f3402b-4215-4cc0-95ef-28a315f72e34 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2871487579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.2871487579 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.456382868 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 8728287660 ps |
| CPU time | 2713.12 seconds |
| Started | Jul 25 08:04:50 PM PDT 24 |
| Finished | Jul 25 08:50:04 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-748827a3-2ecf-4bcf-85fe-8d60fbb916f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=456382868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.456382868 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1981787575 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 7533747366 ps |
| CPU time | 1612.07 seconds |
| Started | Jul 25 08:02:38 PM PDT 24 |
| Finished | Jul 25 08:29:30 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-b0b8c642-96ca-4807-b0f4-1985a1f076cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981787575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.1981787575 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.55262344 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 5763629014 ps |
| CPU time | 711.14 seconds |
| Started | Jul 25 08:01:28 PM PDT 24 |
| Finished | Jul 25 08:13:20 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-6788fc99-48b6-4ad2-90ed-7c611acfa985 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=55262344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.55262344 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4160866120 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 254427711624 ps |
| CPU time | 12684.5 seconds |
| Started | Jul 25 08:02:26 PM PDT 24 |
| Finished | Jul 25 11:33:52 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-9c3bda7a-b98e-4c57-9b22-f8bd0acd0830 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160866120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4160866120 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3116726883 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4388074414 ps |
| CPU time | 404.07 seconds |
| Started | Jul 25 08:00:46 PM PDT 24 |
| Finished | Jul 25 08:07:31 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-02daf640-2035-40f4-8dab-039cadcfbc78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116726883 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3116726883 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3857357762 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 6588805506 ps |
| CPU time | 548.49 seconds |
| Started | Jul 25 08:07:52 PM PDT 24 |
| Finished | Jul 25 08:17:01 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-62eac267-440e-48e3-b8fe-ffec8ea5e27c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3857357762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3857357762 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1113482356 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 3645320534 ps |
| CPU time | 238.72 seconds |
| Started | Jul 25 08:05:39 PM PDT 24 |
| Finished | Jul 25 08:09:38 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-57fd8276-a08b-4c94-a604-ac84c70f831f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113482356 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1113482356 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1153474682 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 9580281692 ps |
| CPU time | 866.18 seconds |
| Started | Jul 25 08:01:52 PM PDT 24 |
| Finished | Jul 25 08:16:18 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-86763344-dc1c-44b9-b924-be8717a39e61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1153474682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1153474682 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2603269909 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4513551680 ps |
| CPU time | 711.72 seconds |
| Started | Jul 25 08:02:47 PM PDT 24 |
| Finished | Jul 25 08:14:39 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-7a1ee057-1e0c-45ed-aed6-bc424a74a84a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2603269909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.2603269909 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3849642863 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 8181448062 ps |
| CPU time | 1000.48 seconds |
| Started | Jul 25 08:04:43 PM PDT 24 |
| Finished | Jul 25 08:21:25 PM PDT 24 |
| Peak memory | 616760 kb |
| Host | smart-50adeba9-0ea0-43e5-a896-73071a4f9cca |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849642863 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.3849642863 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.864897407 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 7271234104 ps |
| CPU time | 515.37 seconds |
| Started | Jul 25 08:01:49 PM PDT 24 |
| Finished | Jul 25 08:10:25 PM PDT 24 |
| Peak memory | 621860 kb |
| Host | smart-6fc82659-072b-417c-90bc-fd80ed8c0b7f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=864897407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.864897407 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3102159658 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3489184126 ps |
| CPU time | 630.66 seconds |
| Started | Jul 25 08:02:47 PM PDT 24 |
| Finished | Jul 25 08:13:18 PM PDT 24 |
| Peak memory | 612720 kb |
| Host | smart-3a66f586-ec91-4655-aa77-0ab081bc358a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102159658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3102159658 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.786605792 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 4154587932 ps |
| CPU time | 684.05 seconds |
| Started | Jul 25 08:02:28 PM PDT 24 |
| Finished | Jul 25 08:13:52 PM PDT 24 |
| Peak memory | 613440 kb |
| Host | smart-ed73bd3a-e3d4-46df-9fe4-b41f6f77700b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786605792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.786605792 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1026392304 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3545625280 ps |
| CPU time | 653.11 seconds |
| Started | Jul 25 08:03:57 PM PDT 24 |
| Finished | Jul 25 08:14:51 PM PDT 24 |
| Peak memory | 613832 kb |
| Host | smart-5eb0a97b-9f8a-4318-91db-413bdec76008 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026392304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1026392304 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1288542454 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 5457676948 ps |
| CPU time | 622.57 seconds |
| Started | Jul 25 08:02:29 PM PDT 24 |
| Finished | Jul 25 08:12:52 PM PDT 24 |
| Peak memory | 613560 kb |
| Host | smart-23760949-b334-48c9-9cca-41ca2cb08a74 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288542454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1288542454 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.42987334 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 5406002080 ps |
| CPU time | 621.74 seconds |
| Started | Jul 25 08:07:36 PM PDT 24 |
| Finished | Jul 25 08:17:58 PM PDT 24 |
| Peak memory | 613520 kb |
| Host | smart-3f7a8d18-6786-4d83-9bf4-ac8872efe2c7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42987334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.42987334 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1226057472 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2813546285 ps |
| CPU time | 194.52 seconds |
| Started | Jul 25 08:01:56 PM PDT 24 |
| Finished | Jul 25 08:05:11 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-95226f21-b873-49f0-b479-579e28bb93c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226057472 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1226057472 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2457294793 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3029473416 ps |
| CPU time | 432.73 seconds |
| Started | Jul 25 08:01:58 PM PDT 24 |
| Finished | Jul 25 08:09:11 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-eabf7e55-12b3-4c80-867e-d1ed3b6426f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457294793 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2457294793 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2192022897 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2029021836 ps |
| CPU time | 191.74 seconds |
| Started | Jul 25 08:08:50 PM PDT 24 |
| Finished | Jul 25 08:12:02 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-d6d13214-61dc-4a5e-a488-a74da13af00e |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192022897 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2192022897 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1192200204 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3735319192 ps |
| CPU time | 349.7 seconds |
| Started | Jul 25 08:03:14 PM PDT 24 |
| Finished | Jul 25 08:09:04 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-27f497ef-7309-43e8-bc59-d5d6bae9dd9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192200204 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1192200204 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4196631543 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 4922473536 ps |
| CPU time | 510.77 seconds |
| Started | Jul 25 08:09:41 PM PDT 24 |
| Finished | Jul 25 08:18:12 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-40fb0e98-88a5-4a20-b876-429b15363000 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196631543 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.4196631543 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3072635093 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 5547751606 ps |
| CPU time | 581.58 seconds |
| Started | Jul 25 08:09:38 PM PDT 24 |
| Finished | Jul 25 08:19:19 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-36edccfe-fc0c-4630-891f-946545a0cbe0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072635093 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3072635093 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2110806929 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 4646548894 ps |
| CPU time | 539.22 seconds |
| Started | Jul 25 08:03:11 PM PDT 24 |
| Finished | Jul 25 08:12:10 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-93469c85-2a15-4613-9bbc-588c44d71e40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110806929 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2110806929 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2800884547 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 12228017630 ps |
| CPU time | 1238.78 seconds |
| Started | Jul 25 08:03:04 PM PDT 24 |
| Finished | Jul 25 08:23:43 PM PDT 24 |
| Peak memory | 611336 kb |
| Host | smart-4182845e-7581-4e0d-b92d-38f313f24965 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800884547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2800884547 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2049727519 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3292923622 ps |
| CPU time | 422.94 seconds |
| Started | Jul 25 08:04:53 PM PDT 24 |
| Finished | Jul 25 08:11:56 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-59df53e3-2238-4ff3-a1dd-949dcb9d588e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049727519 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2049727519 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1466554853 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 4751913148 ps |
| CPU time | 694.46 seconds |
| Started | Jul 25 08:03:54 PM PDT 24 |
| Finished | Jul 25 08:15:29 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-0906cd30-f50e-449e-91f8-c7f989a0588c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466554853 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1466554853 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4001162621 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2780829488 ps |
| CPU time | 274.78 seconds |
| Started | Jul 25 08:02:55 PM PDT 24 |
| Finished | Jul 25 08:07:30 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-a8312f68-55fe-43ef-9237-55d3aee6d8c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001162621 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.4001162621 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.3352201188 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 71318519384 ps |
| CPU time | 13955 seconds |
| Started | Jul 25 08:00:37 PM PDT 24 |
| Finished | Jul 25 11:53:14 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-e2b099b2-e75c-4f0f-b00e-f3e165b0736a |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3352201188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.3352201188 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3473752095 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 15975494136 ps |
| CPU time | 3566.31 seconds |
| Started | Jul 25 08:01:53 PM PDT 24 |
| Finished | Jul 25 09:01:20 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-9a889f3c-d6ea-40d1-bff8-881306100df1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473752095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3473752095 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3109737977 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 83477673353 ps |
| CPU time | 12288.9 seconds |
| Started | Jul 25 08:02:54 PM PDT 24 |
| Finished | Jul 25 11:27:45 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-1cd49ffb-d68e-471d-8409-e8bf3e389fe2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3109737977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3109737977 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.2272803546 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 2504508062 ps |
| CPU time | 246.22 seconds |
| Started | Jul 25 08:02:47 PM PDT 24 |
| Finished | Jul 25 08:06:54 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-ad6b7d59-e6f4-486e-9763-1d2c49ba2e37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272803546 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2272803546 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1081431872 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 8412243540 ps |
| CPU time | 871.72 seconds |
| Started | Jul 25 08:02:21 PM PDT 24 |
| Finished | Jul 25 08:16:53 PM PDT 24 |
| Peak memory | 611636 kb |
| Host | smart-c4c58478-3801-45d1-8e55-f08ed41c427b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081431872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1081431872 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.1284432935 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2170129144 ps |
| CPU time | 272.07 seconds |
| Started | Jul 25 08:05:13 PM PDT 24 |
| Finished | Jul 25 08:09:45 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-6b862314-6c00-45a5-86b3-185c07e4c205 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284432935 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1284432935 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3229650655 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 5296774790 ps |
| CPU time | 790.45 seconds |
| Started | Jul 25 08:00:38 PM PDT 24 |
| Finished | Jul 25 08:13:49 PM PDT 24 |
| Peak memory | 611796 kb |
| Host | smart-ba785fae-2bac-4919-a46c-93bd52238a2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3229650655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3229650655 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.3858073908 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 7314292604 ps |
| CPU time | 2459.6 seconds |
| Started | Jul 25 08:00:07 PM PDT 24 |
| Finished | Jul 25 08:41:07 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-ff99e984-81fd-4058-8df3-04af724cf89d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858073908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3858073908 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2533701824 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 7286582962 ps |
| CPU time | 1592.91 seconds |
| Started | Jul 25 08:01:28 PM PDT 24 |
| Finished | Jul 25 08:28:02 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-198774c1-71ed-4be2-be8d-fe757aa77978 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2533701824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2533701824 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3123443493 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 5840351962 ps |
| CPU time | 982.91 seconds |
| Started | Jul 25 08:03:22 PM PDT 24 |
| Finished | Jul 25 08:19:46 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-913c2261-5bb9-4e0a-a360-b7f2250e3346 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123443493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3123443493 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.4006799665 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3189756768 ps |
| CPU time | 537.88 seconds |
| Started | Jul 25 08:00:49 PM PDT 24 |
| Finished | Jul 25 08:09:47 PM PDT 24 |
| Peak memory | 616108 kb |
| Host | smart-769a7bf8-99da-456f-bc4b-441fe7e7ebf5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006799665 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.4006799665 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3001074565 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 7633533640 ps |
| CPU time | 1851.18 seconds |
| Started | Jul 25 08:03:35 PM PDT 24 |
| Finished | Jul 25 08:34:27 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-e617edf0-05f3-4e34-894e-48ee282f7c7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001074565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3001074565 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3499568759 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2637240850 ps |
| CPU time | 327.28 seconds |
| Started | Jul 25 08:02:32 PM PDT 24 |
| Finished | Jul 25 08:08:00 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-7197ac78-714c-472c-8e23-34045b704918 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34 99568759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3499568759 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1931488573 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3224917938 ps |
| CPU time | 309.75 seconds |
| Started | Jul 25 08:01:25 PM PDT 24 |
| Finished | Jul 25 08:06:35 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-4fb8e8fa-7d5a-4ba5-a808-124461994ba4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931488573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1931488573 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1137626331 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3726241480 ps |
| CPU time | 498.52 seconds |
| Started | Jul 25 08:05:14 PM PDT 24 |
| Finished | Jul 25 08:13:33 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-5a47d60b-ac6d-46a4-836e-9ea039295643 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1137626331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1137626331 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1996626351 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3480337016 ps |
| CPU time | 235.3 seconds |
| Started | Jul 25 07:59:40 PM PDT 24 |
| Finished | Jul 25 08:03:37 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-24511843-5db3-4be1-b6ec-1ebcfce189d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996626351 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1996626351 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3570951765 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2273073506 ps |
| CPU time | 255.46 seconds |
| Started | Jul 25 08:00:18 PM PDT 24 |
| Finished | Jul 25 08:04:34 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-0d068e4b-0426-46ef-8b5c-cc155f08e90e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570951765 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3570951765 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.944840207 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 3367088242 ps |
| CPU time | 320.44 seconds |
| Started | Jul 25 08:00:06 PM PDT 24 |
| Finished | Jul 25 08:05:27 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-918eef74-4133-4d41-8f38-5261d62f3829 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944840207 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_example_manufacturer.944840207 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.99368936 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 2068964376 ps |
| CPU time | 123.24 seconds |
| Started | Jul 25 07:58:51 PM PDT 24 |
| Finished | Jul 25 08:00:54 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-bb149b45-01cb-4c35-a8f4-324356d85e14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99368936 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_example_rom.99368936 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1943943880 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 58741944449 ps |
| CPU time | 10384.6 seconds |
| Started | Jul 25 08:00:27 PM PDT 24 |
| Finished | Jul 25 10:53:33 PM PDT 24 |
| Peak memory | 625452 kb |
| Host | smart-46cd6339-a3d6-42b0-813f-3e85e4f481e4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1943943880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1943943880 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.2911783062 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 4719613602 ps |
| CPU time | 731.66 seconds |
| Started | Jul 25 08:03:56 PM PDT 24 |
| Finished | Jul 25 08:16:09 PM PDT 24 |
| Peak memory | 611720 kb |
| Host | smart-c8a77674-c7b2-433b-8547-2af840f422a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2911783062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2911783062 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.364865068 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 5532989832 ps |
| CPU time | 1292.04 seconds |
| Started | Jul 25 08:01:10 PM PDT 24 |
| Finished | Jul 25 08:22:43 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-b909c751-c3e7-4d22-920f-ef9f883b9fe8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364865068 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_flash_ctrl_access.364865068 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.832213933 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5729592445 ps |
| CPU time | 1002.14 seconds |
| Started | Jul 25 07:59:43 PM PDT 24 |
| Finished | Jul 25 08:16:25 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-b6e01ca6-8ebe-4f39-9933-5f587b1aaac3 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832213933 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.832213933 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3710959719 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 7522222829 ps |
| CPU time | 1353.35 seconds |
| Started | Jul 25 08:02:39 PM PDT 24 |
| Finished | Jul 25 08:25:13 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-56b82019-3be6-424a-80d1-1b5e39241ad5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710959719 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3710959719 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1924540954 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 6348264951 ps |
| CPU time | 1101.22 seconds |
| Started | Jul 25 07:58:57 PM PDT 24 |
| Finished | Jul 25 08:17:19 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-aa60dee9-4c0c-424f-8783-d0a49b767377 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924540954 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1924540954 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2487510551 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3362418452 ps |
| CPU time | 307.37 seconds |
| Started | Jul 25 08:02:58 PM PDT 24 |
| Finished | Jul 25 08:08:06 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-28f57916-70fc-4263-8782-9b2467f88219 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487510551 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2487510551 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1305107495 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 5162410698 ps |
| CPU time | 493.85 seconds |
| Started | Jul 25 07:58:59 PM PDT 24 |
| Finished | Jul 25 08:07:14 PM PDT 24 |
| Peak memory | 611456 kb |
| Host | smart-64ccead9-6206-483d-8a12-ca770caaa296 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13 05107495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1305107495 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.852445295 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4870788444 ps |
| CPU time | 1255.91 seconds |
| Started | Jul 25 08:03:29 PM PDT 24 |
| Finished | Jul 25 08:24:25 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-8d0773c3-3f99-4ec6-8df1-e67e2f361d86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852445295 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.852445295 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.697871479 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3795256387 ps |
| CPU time | 673.11 seconds |
| Started | Jul 25 08:01:27 PM PDT 24 |
| Finished | Jul 25 08:12:42 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-0a23bd77-11f0-4d71-b5f2-4cc36206948d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=697871479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.697871479 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3130220274 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4709614914 ps |
| CPU time | 616.57 seconds |
| Started | Jul 25 08:03:15 PM PDT 24 |
| Finished | Jul 25 08:13:32 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-0087a2d0-b51c-44a1-8365-ca118ebf5abd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3130220274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3130220274 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.4165443811 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3059645184 ps |
| CPU time | 438.45 seconds |
| Started | Jul 25 08:02:35 PM PDT 24 |
| Finished | Jul 25 08:09:54 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-d20336e0-cb5d-4d5c-b3fd-6c950324c3b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165443 811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.4165443811 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1162086020 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 26107102129 ps |
| CPU time | 2032.5 seconds |
| Started | Jul 25 08:00:48 PM PDT 24 |
| Finished | Jul 25 08:34:41 PM PDT 24 |
| Peak memory | 614236 kb |
| Host | smart-17fc695b-0a45-4a84-9599-105ee34f0866 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1162086020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1162086020 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1893666583 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 2866465286 ps |
| CPU time | 251.51 seconds |
| Started | Jul 25 08:04:36 PM PDT 24 |
| Finished | Jul 25 08:08:48 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-f4d06a13-85e8-4ec9-ae0a-9e457a3c7603 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1893666583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1893666583 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.303330990 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 3133079751 ps |
| CPU time | 233.25 seconds |
| Started | Jul 25 08:05:41 PM PDT 24 |
| Finished | Jul 25 08:09:35 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-f887f283-7cee-48b1-aa39-88e3220202b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303330990 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_gpio_smoketest.303330990 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.1768307702 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 3024900260 ps |
| CPU time | 302.33 seconds |
| Started | Jul 25 08:03:50 PM PDT 24 |
| Finished | Jul 25 08:08:52 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-011a3ed7-0e7a-4db3-b1ef-399fb97b0323 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768307702 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1768307702 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2713827842 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 3496319384 ps |
| CPU time | 362.56 seconds |
| Started | Jul 25 08:04:46 PM PDT 24 |
| Finished | Jul 25 08:10:49 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-95df39e7-7ed4-4588-8868-3dbed149b0e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713827842 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.2713827842 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1301511834 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3086353915 ps |
| CPU time | 339.11 seconds |
| Started | Jul 25 08:04:17 PM PDT 24 |
| Finished | Jul 25 08:09:57 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-9acc747b-9edd-4572-9271-f0ef3b3dddc4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301511834 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1301511834 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.835612580 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 7627229868 ps |
| CPU time | 1505.55 seconds |
| Started | Jul 25 08:01:10 PM PDT 24 |
| Finished | Jul 25 08:26:16 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-60292e72-6236-4367-9e99-166b7ea4a555 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835612580 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_hmac_multistream.835612580 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.1362406014 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 2845252520 ps |
| CPU time | 261.56 seconds |
| Started | Jul 25 08:00:47 PM PDT 24 |
| Finished | Jul 25 08:05:09 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-c3891f4f-7670-4b54-88b8-7f760d4c5a3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362406014 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.1362406014 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.1940527105 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 3675908280 ps |
| CPU time | 338.82 seconds |
| Started | Jul 25 08:03:46 PM PDT 24 |
| Finished | Jul 25 08:09:25 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-d9fef144-2465-4bd6-934a-e77e4e4d0e26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940527105 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1940527105 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2698123735 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 3905995640 ps |
| CPU time | 489.06 seconds |
| Started | Jul 25 07:59:50 PM PDT 24 |
| Finished | Jul 25 08:07:59 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-b0881172-3146-40ea-98b0-9d7dfdfffcfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698123735 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2698123735 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2252025378 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5380777596 ps |
| CPU time | 782.04 seconds |
| Started | Jul 25 08:01:53 PM PDT 24 |
| Finished | Jul 25 08:14:56 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-8ac39747-74a4-48d7-9a18-1b5522014b10 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252025378 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2252025378 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1349940079 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4632603090 ps |
| CPU time | 703.73 seconds |
| Started | Jul 25 07:59:02 PM PDT 24 |
| Finished | Jul 25 08:10:46 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-955bc4a6-d4f8-4f0d-8150-c6abad555577 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349940079 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1349940079 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.618680408 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 5496241864 ps |
| CPU time | 684.06 seconds |
| Started | Jul 25 08:00:52 PM PDT 24 |
| Finished | Jul 25 08:12:17 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-0f9c4da8-ec0f-4c07-8017-d4913ee77591 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618680408 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.618680408 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2187596898 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 64957380496 ps |
| CPU time | 10952.5 seconds |
| Started | Jul 25 07:58:42 PM PDT 24 |
| Finished | Jul 25 11:01:17 PM PDT 24 |
| Peak memory | 625324 kb |
| Host | smart-1d15d646-171b-4c8a-a42a-0ba50f4dcfed |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2187596898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2187596898 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.395424427 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 11836308150 ps |
| CPU time | 2520.02 seconds |
| Started | Jul 25 08:03:57 PM PDT 24 |
| Finished | Jul 25 08:45:58 PM PDT 24 |
| Peak memory | 618780 kb |
| Host | smart-f16deb2b-8e64-4261-b633-609c8a679d2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954 24427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.395424427 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.878478844 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 10439899628 ps |
| CPU time | 1805.1 seconds |
| Started | Jul 25 08:05:45 PM PDT 24 |
| Finished | Jul 25 08:35:51 PM PDT 24 |
| Peak memory | 618232 kb |
| Host | smart-b2c5aa33-7650-4ef7-870b-e512521d1f9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=878478844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.878478844 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1816109000 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 13484830280 ps |
| CPU time | 2726.35 seconds |
| Started | Jul 25 08:01:35 PM PDT 24 |
| Finished | Jul 25 08:47:02 PM PDT 24 |
| Peak memory | 618884 kb |
| Host | smart-905b0dae-829f-4cf9-9ee5-e322532f887c |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1816109000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.1816109000 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3225444496 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 11172771540 ps |
| CPU time | 2394.81 seconds |
| Started | Jul 25 08:01:13 PM PDT 24 |
| Finished | Jul 25 08:41:08 PM PDT 24 |
| Peak memory | 611732 kb |
| Host | smart-ff582850-208c-41c2-bdfd-f3e9b7735f4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254 44496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3225444496 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.622674513 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3015762320 ps |
| CPU time | 229.76 seconds |
| Started | Jul 25 08:02:46 PM PDT 24 |
| Finished | Jul 25 08:06:37 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-91aa3ac5-cd75-4b38-8ee3-90f9478877e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622674513 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.622674513 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.696270643 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3471850368 ps |
| CPU time | 286.86 seconds |
| Started | Jul 25 08:01:23 PM PDT 24 |
| Finished | Jul 25 08:06:10 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-585fc294-4ae3-4995-a7af-66e884800027 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696270643 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.696270643 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.577315845 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2228945474 ps |
| CPU time | 221.88 seconds |
| Started | Jul 25 08:00:25 PM PDT 24 |
| Finished | Jul 25 08:04:07 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-3bbdf15d-f017-43be-9e69-be14497ed946 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577315845 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_idle.577315845 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2986173248 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 2800954396 ps |
| CPU time | 276.32 seconds |
| Started | Jul 25 08:01:53 PM PDT 24 |
| Finished | Jul 25 08:06:30 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-8799dc0a-9737-493e-82f2-291499264539 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986173248 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2986173248 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.863677326 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3410972606 ps |
| CPU time | 327.07 seconds |
| Started | Jul 25 08:01:51 PM PDT 24 |
| Finished | Jul 25 08:07:19 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-6ec5e856-2919-48b5-9081-8522a0dbe0ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863677326 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.863677326 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1103464692 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2679336045 ps |
| CPU time | 342.63 seconds |
| Started | Jul 25 08:03:41 PM PDT 24 |
| Finished | Jul 25 08:09:25 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-63c1913a-3fc9-43f2-89ad-c7bcf52e068e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103464692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1103464692 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2676396065 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 3204695152 ps |
| CPU time | 222 seconds |
| Started | Jul 25 08:00:25 PM PDT 24 |
| Finished | Jul 25 08:04:07 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-43690a00-8304-4a86-9524-61f8192887f1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26763960 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2676396065 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.3982675423 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2446457472 ps |
| CPU time | 242.65 seconds |
| Started | Jul 25 08:02:59 PM PDT 24 |
| Finished | Jul 25 08:07:02 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-e25c6ab5-f560-4cbe-b59e-7e4165163d9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982675423 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.3982675423 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2232804941 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 2888633910 ps |
| CPU time | 301.34 seconds |
| Started | Jul 25 08:06:39 PM PDT 24 |
| Finished | Jul 25 08:11:42 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-d4d4cde8-fec1-4c1d-abad-13e578a4914e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232804941 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2232804941 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2630440522 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2469204249 ps |
| CPU time | 150.78 seconds |
| Started | Jul 25 08:00:46 PM PDT 24 |
| Finished | Jul 25 08:03:18 PM PDT 24 |
| Peak memory | 620712 kb |
| Host | smart-187b35b6-7859-44b9-acfd-1189ff017600 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630440522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2630440522 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1772012094 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3576220947 ps |
| CPU time | 201.42 seconds |
| Started | Jul 25 08:01:24 PM PDT 24 |
| Finished | Jul 25 08:04:46 PM PDT 24 |
| Peak memory | 622340 kb |
| Host | smart-bc69572e-4bf6-4bc9-81cf-a592551ae46d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772012094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1772012094 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3195245416 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4160132248 ps |
| CPU time | 152.9 seconds |
| Started | Jul 25 08:00:02 PM PDT 24 |
| Finished | Jul 25 08:02:35 PM PDT 24 |
| Peak memory | 620340 kb |
| Host | smart-f296cd61-2a81-4cfb-a5ae-832f3e79ab5e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195245416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3195245416 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1529773591 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 7215991718 ps |
| CPU time | 570.47 seconds |
| Started | Jul 25 07:59:11 PM PDT 24 |
| Finished | Jul 25 08:08:42 PM PDT 24 |
| Peak memory | 621140 kb |
| Host | smart-8611b272-a4b7-4933-82ec-125b74c23445 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529773591 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.1529773591 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4270113347 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2308494943 ps |
| CPU time | 130.97 seconds |
| Started | Jul 25 08:00:40 PM PDT 24 |
| Finished | Jul 25 08:02:52 PM PDT 24 |
| Peak memory | 618572 kb |
| Host | smart-0c1ceeab-e687-469e-809c-8b9702130e6a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4270113347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.4270113347 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2730698675 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2867809439 ps |
| CPU time | 128.1 seconds |
| Started | Jul 25 07:59:58 PM PDT 24 |
| Finished | Jul 25 08:02:06 PM PDT 24 |
| Peak memory | 618712 kb |
| Host | smart-c8890d58-4de0-4360-aa56-a4b50d0f5b36 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730698675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2730698675 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2694502867 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 52244077255 ps |
| CPU time | 6080.64 seconds |
| Started | Jul 25 07:59:16 PM PDT 24 |
| Finished | Jul 25 09:40:37 PM PDT 24 |
| Peak memory | 621100 kb |
| Host | smart-fb08e286-4934-4fc1-8899-021f930afba5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694502867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.2694502867 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2751199759 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 10710779806 ps |
| CPU time | 1100.11 seconds |
| Started | Jul 25 08:02:13 PM PDT 24 |
| Finished | Jul 25 08:20:34 PM PDT 24 |
| Peak memory | 620744 kb |
| Host | smart-79f8fa1e-a5fe-40ca-af78-71427e8bf4a2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751199759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2751199759 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2173588369 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 48782865037 ps |
| CPU time | 5538.6 seconds |
| Started | Jul 25 08:00:16 PM PDT 24 |
| Finished | Jul 25 09:32:36 PM PDT 24 |
| Peak memory | 620008 kb |
| Host | smart-15a5b807-f89e-49d0-8e83-d8f94cc2cbe5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173588369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.2173588369 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2652594013 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 17616142574 ps |
| CPU time | 4596.35 seconds |
| Started | Jul 25 08:01:43 PM PDT 24 |
| Finished | Jul 25 09:18:21 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-916f43ed-5e7a-44da-9e2f-9ca8f2d2567a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2652594013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2652594013 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.557410763 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 24613373918 ps |
| CPU time | 3998.86 seconds |
| Started | Jul 25 08:09:25 PM PDT 24 |
| Finished | Jul 25 09:16:04 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-794d0bcd-3506-4879-b015-e66c5ca6fd56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557410763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.557410763 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3233813192 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3641556760 ps |
| CPU time | 418.5 seconds |
| Started | Jul 25 07:59:27 PM PDT 24 |
| Finished | Jul 25 08:06:26 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-f6d7df4c-e14a-455b-8e8b-a5982fa9be5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233813192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3233813192 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.3246549052 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 5793890080 ps |
| CPU time | 1090.26 seconds |
| Started | Jul 25 08:01:21 PM PDT 24 |
| Finished | Jul 25 08:19:32 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-d082fa95-fb30-4054-a6f6-11956f12bda3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3246549052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3246549052 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1505650706 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 8938100900 ps |
| CPU time | 2064.13 seconds |
| Started | Jul 25 08:05:53 PM PDT 24 |
| Finished | Jul 25 08:40:17 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-3bc5ecf9-01a9-442c-aa89-762241bfd931 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505650706 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1505650706 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2588936018 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 26558653508 ps |
| CPU time | 5940.52 seconds |
| Started | Jul 25 08:00:20 PM PDT 24 |
| Finished | Jul 25 09:39:22 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-3d9a2b4b-cd90-48c8-8715-c5383c3e235d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258893 6018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2588936018 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1612444888 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2868152218 ps |
| CPU time | 324 seconds |
| Started | Jul 25 08:01:58 PM PDT 24 |
| Finished | Jul 25 08:07:23 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-9e400737-783a-4348-b9c4-dc86afe3184c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612444888 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1612444888 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3407888732 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4908281544 ps |
| CPU time | 614.58 seconds |
| Started | Jul 25 08:00:48 PM PDT 24 |
| Finished | Jul 25 08:11:03 PM PDT 24 |
| Peak memory | 611828 kb |
| Host | smart-6c0ecd2a-d14c-4b0f-8a97-f225164398d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3407888732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3407888732 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3559484211 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 6925260386 ps |
| CPU time | 950.44 seconds |
| Started | Jul 25 07:58:38 PM PDT 24 |
| Finished | Jul 25 08:14:29 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-c795f456-2c7d-4f81-b80a-841f0430e063 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3559484211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3559484211 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3578255834 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 6738792488 ps |
| CPU time | 1412.1 seconds |
| Started | Jul 25 08:01:30 PM PDT 24 |
| Finished | Jul 25 08:25:03 PM PDT 24 |
| Peak memory | 611388 kb |
| Host | smart-7b73653d-f8ef-487f-8f1c-1724a722a3db |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3578255834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3578255834 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3087139755 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 6598841660 ps |
| CPU time | 979.4 seconds |
| Started | Jul 25 08:00:42 PM PDT 24 |
| Finished | Jul 25 08:17:02 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-f09f631b-2d73-4b56-94a1-74284494908a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3087139755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3087139755 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.669060709 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4130701106 ps |
| CPU time | 759.58 seconds |
| Started | Jul 25 07:59:56 PM PDT 24 |
| Finished | Jul 25 08:12:36 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-863efe38-c053-46d6-991a-ae9f1ddfb185 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=669060709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.669060709 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.378551246 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2530959854 ps |
| CPU time | 293.35 seconds |
| Started | Jul 25 08:03:44 PM PDT 24 |
| Finished | Jul 25 08:08:38 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-d661f281-ca4b-4889-bbc0-562db0d25ec9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378551246 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.378551246 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.4271643789 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4365199800 ps |
| CPU time | 661.12 seconds |
| Started | Jul 25 08:04:22 PM PDT 24 |
| Finished | Jul 25 08:15:24 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-f5d5a631-af38-4698-b9b2-21cc507a985c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271643789 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.4271643789 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3835217723 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 10680207680 ps |
| CPU time | 660.51 seconds |
| Started | Jul 25 08:04:00 PM PDT 24 |
| Finished | Jul 25 08:15:01 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-2ca5a700-ca39-4513-8a59-2877af6bb4b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835217723 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3835217723 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.4051473597 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5709609296 ps |
| CPU time | 1540.05 seconds |
| Started | Jul 25 08:08:39 PM PDT 24 |
| Finished | Jul 25 08:34:20 PM PDT 24 |
| Peak memory | 625572 kb |
| Host | smart-268e7686-1e8c-45b8-afb2-3127fb183e17 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4051473597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.4051473597 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3856172063 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 11851459920 ps |
| CPU time | 1663.74 seconds |
| Started | Jul 25 08:01:06 PM PDT 24 |
| Finished | Jul 25 08:28:50 PM PDT 24 |
| Peak memory | 612048 kb |
| Host | smart-cd0560b8-9d0f-4c5f-8cba-2ed09d6b80dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856 172063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3856172063 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2281470881 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 18459043912 ps |
| CPU time | 2433.33 seconds |
| Started | Jul 25 08:03:08 PM PDT 24 |
| Finished | Jul 25 08:43:42 PM PDT 24 |
| Peak memory | 611600 kb |
| Host | smart-dc7746ec-f1b1-404b-8e18-e11852ceb041 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228 1470881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.2281470881 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.728824127 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 14397745900 ps |
| CPU time | 1564.49 seconds |
| Started | Jul 25 08:08:08 PM PDT 24 |
| Finished | Jul 25 08:34:13 PM PDT 24 |
| Peak memory | 612132 kb |
| Host | smart-bc92c5e5-13ef-4358-8a80-d34ad6d5e494 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=728824127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.728824127 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3684269326 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 21927556544 ps |
| CPU time | 1732.59 seconds |
| Started | Jul 25 08:02:53 PM PDT 24 |
| Finished | Jul 25 08:31:46 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-44a65980-1336-4031-93a8-a4cfa0446499 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3684269326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3684269326 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2810828783 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 8710350296 ps |
| CPU time | 925.65 seconds |
| Started | Jul 25 08:08:07 PM PDT 24 |
| Finished | Jul 25 08:23:33 PM PDT 24 |
| Peak memory | 611584 kb |
| Host | smart-5d82c1e8-6395-46f9-a8d1-d2995df87626 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810828783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2810828783 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2249341881 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 7806252736 ps |
| CPU time | 474.24 seconds |
| Started | Jul 25 08:02:17 PM PDT 24 |
| Finished | Jul 25 08:10:11 PM PDT 24 |
| Peak memory | 618336 kb |
| Host | smart-958b651d-fe4a-4c4d-b2dc-c6bc16a97e67 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2249341881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2249341881 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.856564263 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3329058795 ps |
| CPU time | 381.38 seconds |
| Started | Jul 25 08:01:20 PM PDT 24 |
| Finished | Jul 25 08:07:42 PM PDT 24 |
| Peak memory | 616900 kb |
| Host | smart-8da82293-2867-4e8d-9e58-d5c8e30fe26e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=856564263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.856564263 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3243450465 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6677080150 ps |
| CPU time | 456.61 seconds |
| Started | Jul 25 08:09:33 PM PDT 24 |
| Finished | Jul 25 08:17:10 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-b23e8a20-97af-4782-b530-eb7c3fc8c21e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243450465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3243450465 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4252098576 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 7239770165 ps |
| CPU time | 451.73 seconds |
| Started | Jul 25 08:00:56 PM PDT 24 |
| Finished | Jul 25 08:08:28 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-2164ce23-ef57-483e-b5c1-b781a53534bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252098576 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.4252098576 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1031817577 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 22770228407 ps |
| CPU time | 2582.22 seconds |
| Started | Jul 25 08:08:10 PM PDT 24 |
| Finished | Jul 25 08:51:12 PM PDT 24 |
| Peak memory | 612176 kb |
| Host | smart-b95ab1d2-5e03-40bc-8235-4f422a224c24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1031817577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1031817577 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2443980905 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 22249729850 ps |
| CPU time | 1696.14 seconds |
| Started | Jul 25 08:03:08 PM PDT 24 |
| Finished | Jul 25 08:31:24 PM PDT 24 |
| Peak memory | 611696 kb |
| Host | smart-bc6c5894-93aa-4352-b572-37938c970d77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2443980905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2443980905 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3108132312 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 39073012656 ps |
| CPU time | 3554.64 seconds |
| Started | Jul 25 08:08:02 PM PDT 24 |
| Finished | Jul 25 09:07:18 PM PDT 24 |
| Peak memory | 612432 kb |
| Host | smart-111b136a-a67f-49ab-a6b7-c87d685b3a49 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108132312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3108132312 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1337313995 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2588865456 ps |
| CPU time | 285.7 seconds |
| Started | Jul 25 08:02:49 PM PDT 24 |
| Finished | Jul 25 08:07:35 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-d81c7622-2135-4011-b33a-e0d60f5df64a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337313995 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1337313995 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1515696407 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4035105080 ps |
| CPU time | 461.18 seconds |
| Started | Jul 25 08:01:14 PM PDT 24 |
| Finished | Jul 25 08:08:56 PM PDT 24 |
| Peak memory | 616932 kb |
| Host | smart-978b990b-6372-4862-add7-c986e1c3c35e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1515696407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1515696407 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1340237332 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5294113812 ps |
| CPU time | 443.48 seconds |
| Started | Jul 25 08:03:13 PM PDT 24 |
| Finished | Jul 25 08:10:36 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-72c5e6de-4f07-440f-bca5-9c03ba86047f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13402373 32 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1340237332 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.781532323 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5525361730 ps |
| CPU time | 640.08 seconds |
| Started | Jul 25 08:01:51 PM PDT 24 |
| Finished | Jul 25 08:12:32 PM PDT 24 |
| Peak memory | 611412 kb |
| Host | smart-637cda64-e6ca-4668-89d2-44cbaf786e67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=781532323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.781532323 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4214091807 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 6484980680 ps |
| CPU time | 391.85 seconds |
| Started | Jul 25 08:04:52 PM PDT 24 |
| Finished | Jul 25 08:11:24 PM PDT 24 |
| Peak memory | 611256 kb |
| Host | smart-86e97575-fd62-44d0-9099-ea1b8a0c49dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214091807 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.4214091807 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4039837746 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 6696256584 ps |
| CPU time | 1079.51 seconds |
| Started | Jul 25 08:02:54 PM PDT 24 |
| Finished | Jul 25 08:20:54 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-369c21c8-95fd-4eb3-8fde-41122b747165 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039837746 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.4039837746 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.650950769 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5101274062 ps |
| CPU time | 483.76 seconds |
| Started | Jul 25 08:00:17 PM PDT 24 |
| Finished | Jul 25 08:08:23 PM PDT 24 |
| Peak memory | 611244 kb |
| Host | smart-1bdb3ce5-af4b-4983-8781-73f2d21efb4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650950769 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.650950769 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3881739146 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5160877154 ps |
| CPU time | 454.19 seconds |
| Started | Jul 25 08:06:50 PM PDT 24 |
| Finished | Jul 25 08:14:25 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-d0e5e814-0046-495f-825b-7a82e7937333 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881739146 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3881739146 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1977215335 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4253304184 ps |
| CPU time | 434.79 seconds |
| Started | Jul 25 08:01:02 PM PDT 24 |
| Finished | Jul 25 08:08:17 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-a4bbad90-7290-4834-805d-4d1443917c57 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197 7215335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1977215335 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.274738882 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 8309879043 ps |
| CPU time | 496.57 seconds |
| Started | Jul 25 07:59:57 PM PDT 24 |
| Finished | Jul 25 08:08:14 PM PDT 24 |
| Peak memory | 625384 kb |
| Host | smart-50dc297f-54f8-43c6-ba64-4e78a2ad6516 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274738882 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.274738882 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1684088604 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 6398237922 ps |
| CPU time | 717.18 seconds |
| Started | Jul 25 08:00:56 PM PDT 24 |
| Finished | Jul 25 08:12:54 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-5dfdedf4-682f-46fd-8adf-7c8c3b7bd57c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684088604 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1684088604 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.848751107 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3998590148 ps |
| CPU time | 634.7 seconds |
| Started | Jul 25 08:00:18 PM PDT 24 |
| Finished | Jul 25 08:10:53 PM PDT 24 |
| Peak memory | 642048 kb |
| Host | smart-90301fbe-d348-4b56-b8bc-6799da41edea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 848751107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.848751107 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.908440498 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2952503492 ps |
| CPU time | 230 seconds |
| Started | Jul 25 08:04:54 PM PDT 24 |
| Finished | Jul 25 08:08:44 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-06e68cd4-6866-4205-8663-cbc503cad7a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908440498 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.908440498 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2757976374 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4461565738 ps |
| CPU time | 564.02 seconds |
| Started | Jul 25 08:00:16 PM PDT 24 |
| Finished | Jul 25 08:09:41 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-c281cd8b-5dd0-49bb-ab2f-d8f8860dccc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757976374 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2757976374 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3226541697 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2506369112 ps |
| CPU time | 269.51 seconds |
| Started | Jul 25 07:59:51 PM PDT 24 |
| Finished | Jul 25 08:04:21 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-21fdc7ad-a7ae-4728-a4fc-a2f575ec8f8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226541697 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.3226541697 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.611203187 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3148741224 ps |
| CPU time | 307.59 seconds |
| Started | Jul 25 08:04:24 PM PDT 24 |
| Finished | Jul 25 08:09:32 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-563994a1-74d0-4552-917d-11495dba90a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=611203187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.611203187 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2109300289 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2795476587 ps |
| CPU time | 231.21 seconds |
| Started | Jul 25 08:04:45 PM PDT 24 |
| Finished | Jul 25 08:08:36 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-7ddfa282-b453-43e6-89f1-a9f252ee493d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109300289 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2109300289 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.268451027 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 5337297126 ps |
| CPU time | 1030.87 seconds |
| Started | Jul 25 08:00:52 PM PDT 24 |
| Finished | Jul 25 08:18:04 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-316209ec-2870-4a90-90d8-128b2af9f13f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=268451027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.268451027 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3983256877 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 6365521244 ps |
| CPU time | 443.46 seconds |
| Started | Jul 25 08:03:43 PM PDT 24 |
| Finished | Jul 25 08:11:07 PM PDT 24 |
| Peak memory | 621128 kb |
| Host | smart-41e07be5-14c6-4bda-97cc-837c4af99887 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983256877 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3983256877 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.4155618240 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 3041726108 ps |
| CPU time | 291.48 seconds |
| Started | Jul 25 08:06:17 PM PDT 24 |
| Finished | Jul 25 08:11:08 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-ce4b8817-3edd-4a87-8bd1-cd9037b545ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155618240 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.4155618240 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1940465675 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2918826760 ps |
| CPU time | 242.57 seconds |
| Started | Jul 25 08:02:47 PM PDT 24 |
| Finished | Jul 25 08:06:50 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-673362b9-b5f3-43dc-b58a-43d1bb74226b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940465675 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1940465675 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1110304435 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 2764789428 ps |
| CPU time | 270.62 seconds |
| Started | Jul 25 08:05:28 PM PDT 24 |
| Finished | Jul 25 08:09:59 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-d070e276-78bf-4fe8-bf65-15283d618b73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110304435 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1110304435 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1736440270 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2713327240 ps |
| CPU time | 250.8 seconds |
| Started | Jul 25 08:04:24 PM PDT 24 |
| Finished | Jul 25 08:08:35 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-9a64609d-209a-49c1-98dd-8fd67404ca72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736440 270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1736440270 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3207028357 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 9129597872 ps |
| CPU time | 1728.9 seconds |
| Started | Jul 25 07:59:53 PM PDT 24 |
| Finished | Jul 25 08:28:42 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-45f62a73-b494-496d-aa0d-78572cbdaf69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207028357 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3207028357 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2077405223 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 7458564112 ps |
| CPU time | 403.22 seconds |
| Started | Jul 25 08:02:10 PM PDT 24 |
| Finished | Jul 25 08:08:53 PM PDT 24 |
| Peak memory | 611276 kb |
| Host | smart-b5030227-8c8f-4b2f-bdd6-a91236ce653c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077405223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.2077405223 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4094444730 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7594521292 ps |
| CPU time | 827.91 seconds |
| Started | Jul 25 08:04:09 PM PDT 24 |
| Finished | Jul 25 08:17:57 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-5b4a5e09-d8bb-4916-9265-5862d82219ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094444730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.4094444730 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3711072190 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6754109843 ps |
| CPU time | 589.23 seconds |
| Started | Jul 25 07:58:21 PM PDT 24 |
| Finished | Jul 25 08:08:11 PM PDT 24 |
| Peak memory | 625556 kb |
| Host | smart-12c3e720-afd4-49af-8319-fb51f004a3c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711072190 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3711072190 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2422482172 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 4690544059 ps |
| CPU time | 644.7 seconds |
| Started | Jul 25 08:06:22 PM PDT 24 |
| Finished | Jul 25 08:17:08 PM PDT 24 |
| Peak memory | 625560 kb |
| Host | smart-30723c98-82a7-4855-b2af-3fe49e1fce3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422482172 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2422482172 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.547833782 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3447800508 ps |
| CPU time | 330.29 seconds |
| Started | Jul 25 08:01:13 PM PDT 24 |
| Finished | Jul 25 08:06:43 PM PDT 24 |
| Peak memory | 619708 kb |
| Host | smart-53f4fc07-9ee2-4245-b8ae-06b3fb7846eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547833782 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.547833782 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.4136163458 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3349567208 ps |
| CPU time | 387.53 seconds |
| Started | Jul 25 08:01:26 PM PDT 24 |
| Finished | Jul 25 08:07:53 PM PDT 24 |
| Peak memory | 620120 kb |
| Host | smart-a1410ab3-2f78-4c0e-ae6b-5f1f787f3631 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136163458 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.4136163458 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.747238315 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3932720980 ps |
| CPU time | 742.68 seconds |
| Started | Jul 25 08:03:04 PM PDT 24 |
| Finished | Jul 25 08:15:29 PM PDT 24 |
| Peak memory | 611276 kb |
| Host | smart-3a97fbd0-8d16-4e9f-b53a-6692483eeaa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747238315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.747238315 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2827239838 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4087441619 ps |
| CPU time | 539.17 seconds |
| Started | Jul 25 08:04:18 PM PDT 24 |
| Finished | Jul 25 08:13:18 PM PDT 24 |
| Peak memory | 611396 kb |
| Host | smart-7a186253-3e95-46f3-af80-6e4c455fa893 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827239838 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2827239838 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3433568072 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3128394692 ps |
| CPU time | 241.34 seconds |
| Started | Jul 25 08:06:14 PM PDT 24 |
| Finished | Jul 25 08:10:15 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-9abf4be5-8d23-4f13-bc26-5a7ee7a4f048 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433568072 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3433568072 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.21812596 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 20028868439 ps |
| CPU time | 3840.55 seconds |
| Started | Jul 25 08:04:23 PM PDT 24 |
| Finished | Jul 25 09:08:25 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-be8292d2-fd3c-4b6d-86e3-cd4e098a62de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812596 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.21812596 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1334669597 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4945018711 ps |
| CPU time | 739.73 seconds |
| Started | Jul 25 08:02:55 PM PDT 24 |
| Finished | Jul 25 08:15:17 PM PDT 24 |
| Peak memory | 614568 kb |
| Host | smart-ed5d7050-ea78-4e19-8e87-3d670bfeea77 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334669597 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1334669597 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1847607512 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3330013182 ps |
| CPU time | 400.06 seconds |
| Started | Jul 25 08:00:01 PM PDT 24 |
| Finished | Jul 25 08:06:42 PM PDT 24 |
| Peak memory | 614080 kb |
| Host | smart-40ed94da-1bc5-4515-85cf-a6a8ae5a6f0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847607512 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1847607512 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4038786957 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2838382840 ps |
| CPU time | 354.16 seconds |
| Started | Jul 25 08:01:52 PM PDT 24 |
| Finished | Jul 25 08:07:47 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-b369a031-9fd5-42db-91c1-f714cafd8ce7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038786957 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.4038786957 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2487914130 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6626073998 ps |
| CPU time | 655.73 seconds |
| Started | Jul 25 08:00:41 PM PDT 24 |
| Finished | Jul 25 08:11:38 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-545f127a-58c7-427d-a1f4-05f0c14b95e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487914130 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2487914130 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.1152619172 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3495108210 ps |
| CPU time | 299.7 seconds |
| Started | Jul 25 08:03:20 PM PDT 24 |
| Finished | Jul 25 08:08:20 PM PDT 24 |
| Peak memory | 617848 kb |
| Host | smart-583a42bc-0b53-4c7a-b900-6d18b334cd31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152619172 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.1152619172 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.2190637151 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4612514704 ps |
| CPU time | 618.53 seconds |
| Started | Jul 25 07:58:26 PM PDT 24 |
| Finished | Jul 25 08:08:45 PM PDT 24 |
| Peak memory | 625392 kb |
| Host | smart-193cf712-13e6-4a13-bb55-d43cf7c5e0b8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190637151 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2190637151 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2811861608 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 7918409848 ps |
| CPU time | 1059.48 seconds |
| Started | Jul 25 08:01:21 PM PDT 24 |
| Finished | Jul 25 08:19:01 PM PDT 24 |
| Peak memory | 619288 kb |
| Host | smart-b9727901-2042-4fd7-9631-f31f36195845 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811861608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2811861608 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1033563199 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4540095178 ps |
| CPU time | 613.41 seconds |
| Started | Jul 25 08:01:25 PM PDT 24 |
| Finished | Jul 25 08:11:41 PM PDT 24 |
| Peak memory | 625400 kb |
| Host | smart-4a01b43c-2b11-40f7-847b-55afe082ca00 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033563199 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1033563199 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1466194399 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 3799599400 ps |
| CPU time | 643.29 seconds |
| Started | Jul 25 08:00:22 PM PDT 24 |
| Finished | Jul 25 08:11:05 PM PDT 24 |
| Peak memory | 625368 kb |
| Host | smart-413ee53c-4525-47b0-8394-1bb1a5cade5f |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466194399 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1466194399 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2057640550 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 4156356040 ps |
| CPU time | 584.58 seconds |
| Started | Jul 25 08:00:35 PM PDT 24 |
| Finished | Jul 25 08:10:21 PM PDT 24 |
| Peak memory | 625324 kb |
| Host | smart-a8cb844e-0c39-4f01-a17a-0664e4aef301 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057640550 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2057640550 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2623126929 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3106583368 ps |
| CPU time | 418.2 seconds |
| Started | Jul 25 08:03:16 PM PDT 24 |
| Finished | Jul 25 08:10:15 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-3571e9cd-2614-482f-a9bd-025dc6e7e14a |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623126929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2623126929 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.587312415 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8044640200 ps |
| CPU time | 2115.21 seconds |
| Started | Jul 25 07:59:05 PM PDT 24 |
| Finished | Jul 25 08:34:21 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-334d121a-2e77-42ee-8eec-0cf9af902b85 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58731 2415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.587312415 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.3478248912 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12353521260 ps |
| CPU time | 3380.62 seconds |
| Started | Jul 25 08:00:31 PM PDT 24 |
| Finished | Jul 25 08:56:53 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-bb227a78-b5b5-43fe-8188-0dca6254c3f5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3478248912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3478248912 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.193190176 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2829162460 ps |
| CPU time | 291.49 seconds |
| Started | Jul 25 07:58:54 PM PDT 24 |
| Finished | Jul 25 08:03:46 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-94ee4025-72ca-4d2b-85c5-aaf3e3c0259b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193190176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.193190176 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1638795989 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 3868011646 ps |
| CPU time | 491.91 seconds |
| Started | Jul 25 07:59:08 PM PDT 24 |
| Finished | Jul 25 08:07:20 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-8f7df969-51a6-4427-9c61-3683ce82a8e3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163879598 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1638795989 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.142541191 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 19456046922 ps |
| CPU time | 4648.1 seconds |
| Started | Jul 25 08:00:45 PM PDT 24 |
| Finished | Jul 25 09:18:15 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-0f9d6664-7a8f-4836-b799-626c901a0c3e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=142541191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.142541191 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.4067659525 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2741880720 ps |
| CPU time | 249.71 seconds |
| Started | Jul 25 08:00:41 PM PDT 24 |
| Finished | Jul 25 08:04:51 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-01846f22-ccd7-4ec5-ab08-006f8e500921 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067659525 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.4067659525 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.2887049416 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 4471233607 ps |
| CPU time | 307.57 seconds |
| Started | Jul 25 08:00:02 PM PDT 24 |
| Finished | Jul 25 08:05:15 PM PDT 24 |
| Peak memory | 623052 kb |
| Host | smart-4be5ad04-168f-4d7e-b22f-493f0c8b6382 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2887049416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2887049416 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.1157543109 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 2332959444 ps |
| CPU time | 157.51 seconds |
| Started | Jul 25 08:02:39 PM PDT 24 |
| Finished | Jul 25 08:05:17 PM PDT 24 |
| Peak memory | 623688 kb |
| Host | smart-77163773-a792-43a6-be17-5c51e6eae38e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157543109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1157543109 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.2917114646 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4698791241 ps |
| CPU time | 488.45 seconds |
| Started | Jul 25 08:02:03 PM PDT 24 |
| Finished | Jul 25 08:10:12 PM PDT 24 |
| Peak memory | 621708 kb |
| Host | smart-843fea6e-6d9e-46a8-8cbb-5403ea397f4d |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917114646 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2917114646 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.1079900154 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 14840350030 ps |
| CPU time | 3802.26 seconds |
| Started | Jul 25 08:06:48 PM PDT 24 |
| Finished | Jul 25 09:10:11 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-172dffb6-975f-4649-a8ca-156f020b7c77 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079900154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.1079900154 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.3867318482 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 14780047584 ps |
| CPU time | 3495.88 seconds |
| Started | Jul 25 08:09:36 PM PDT 24 |
| Finished | Jul 25 09:07:53 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-94bd6261-9d80-4e96-9532-8c614fcd3274 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867318482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.3867318482 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3685467957 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15806710196 ps |
| CPU time | 3588.29 seconds |
| Started | Jul 25 08:05:38 PM PDT 24 |
| Finished | Jul 25 09:05:27 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-72e5caa9-486a-4c80-9861-4a8bdee9bef0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685467957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3685467957 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.4079074310 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 14807533200 ps |
| CPU time | 3569.59 seconds |
| Started | Jul 25 08:09:38 PM PDT 24 |
| Finished | Jul 25 09:09:08 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-fd81ede4-d71d-41f6-8462-77c1ebd11990 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079074310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.4079074310 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1905331144 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 10730204424 ps |
| CPU time | 3280.24 seconds |
| Started | Jul 25 08:07:26 PM PDT 24 |
| Finished | Jul 25 09:02:06 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-fc2088be-6bb8-4517-881f-cd0215d3b7d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905331144 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1905331144 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3333121685 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 24501401090 ps |
| CPU time | 6747.97 seconds |
| Started | Jul 25 08:08:25 PM PDT 24 |
| Finished | Jul 25 10:00:54 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-668b9014-ed03-492e-a570-da602f451fd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3333121685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3333121685 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.434149200 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 24174330530 ps |
| CPU time | 5949.83 seconds |
| Started | Jul 25 08:11:20 PM PDT 24 |
| Finished | Jul 25 09:50:31 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-e3260a82-28d9-4252-81e0-ca0de3a56efb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=434149200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.434149200 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.76398019 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 23697908728 ps |
| CPU time | 7332.96 seconds |
| Started | Jul 25 08:12:27 PM PDT 24 |
| Finished | Jul 25 10:14:41 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-e93da54b-d33b-491f-b1bd-2e0d491a4732 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=76398019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.76398019 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1604429889 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 18432028200 ps |
| CPU time | 4624.66 seconds |
| Started | Jul 25 08:11:21 PM PDT 24 |
| Finished | Jul 25 09:28:26 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-13c453ad-6881-4d39-886d-5a720e9899de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604429889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1604429889 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1369004217 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 15732042500 ps |
| CPU time | 4225.81 seconds |
| Started | Jul 25 08:10:05 PM PDT 24 |
| Finished | Jul 25 09:20:31 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-266d2497-f490-4fed-8314-abf7cd50e0f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1369004217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1369004217 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2195293395 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 15737969340 ps |
| CPU time | 3682.3 seconds |
| Started | Jul 25 08:08:31 PM PDT 24 |
| Finished | Jul 25 09:09:54 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-7999a5eb-fac7-4ae2-ab76-17d9fec5f532 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2195293395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2195293395 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.691896312 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 16019618440 ps |
| CPU time | 5264.51 seconds |
| Started | Jul 25 08:10:02 PM PDT 24 |
| Finished | Jul 25 09:37:47 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-fa230424-c2f0-4743-87ea-886061263e0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=691896312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.691896312 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1903084543 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 15262745980 ps |
| CPU time | 4202.67 seconds |
| Started | Jul 25 08:07:34 PM PDT 24 |
| Finished | Jul 25 09:17:37 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-877a457e-a14d-45b6-8461-ec93e4b0b133 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1903084543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1903084543 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3737543350 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11690130942 ps |
| CPU time | 3371.21 seconds |
| Started | Jul 25 08:10:25 PM PDT 24 |
| Finished | Jul 25 09:06:36 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-ec76c3c1-dac0-4484-a6e4-d3b998fdba9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737543350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3737543350 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1337612428 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 15129547144 ps |
| CPU time | 4254.17 seconds |
| Started | Jul 25 08:10:18 PM PDT 24 |
| Finished | Jul 25 09:21:13 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-aca889c2-49e2-4f00-89d6-6960ae947f4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337612428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1337612428 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3082678597 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 15874770824 ps |
| CPU time | 3673.84 seconds |
| Started | Jul 25 08:09:24 PM PDT 24 |
| Finished | Jul 25 09:10:39 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-7999e274-4ea6-404f-b863-45668797f4e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082678597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3082678597 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2669724935 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 16033252704 ps |
| CPU time | 3903.09 seconds |
| Started | Jul 25 08:12:21 PM PDT 24 |
| Finished | Jul 25 09:17:25 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-d42e72bb-72de-4f89-82e4-6a7fbc24aa99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266972 4935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2669724935 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3116457803 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 14670297752 ps |
| CPU time | 4244.56 seconds |
| Started | Jul 25 08:12:21 PM PDT 24 |
| Finished | Jul 25 09:23:07 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-2b6574fd-975f-4884-8baa-dc15fa943589 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116457803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3116457803 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4271900163 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 11542573884 ps |
| CPU time | 3043.46 seconds |
| Started | Jul 25 08:08:56 PM PDT 24 |
| Finished | Jul 25 08:59:40 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-e7e5053a-09c3-4116-8a4b-e1996db12968 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4271900163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4271900163 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2056251464 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 10418399228 ps |
| CPU time | 2454.08 seconds |
| Started | Jul 25 08:03:59 PM PDT 24 |
| Finished | Jul 25 08:44:55 PM PDT 24 |
| Peak memory | 625012 kb |
| Host | smart-6c23490c-0422-4bca-9cf3-cad9e6b00db2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20562 51464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2056251464 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1812032853 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 10837942116 ps |
| CPU time | 2071.13 seconds |
| Started | Jul 25 08:03:11 PM PDT 24 |
| Finished | Jul 25 08:37:44 PM PDT 24 |
| Peak memory | 625004 kb |
| Host | smart-faa50375-e251-44ed-ae2c-cd50b7975939 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18120 32853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.1812032853 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.892943113 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 11596363875 ps |
| CPU time | 2274.51 seconds |
| Started | Jul 25 08:04:32 PM PDT 24 |
| Finished | Jul 25 08:42:29 PM PDT 24 |
| Peak memory | 625004 kb |
| Host | smart-2d2d2c74-4a96-451f-9fd5-b809d47c14c4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=892943113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.892943113 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2963862044 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 24700248943 ps |
| CPU time | 2101.91 seconds |
| Started | Jul 25 08:02:42 PM PDT 24 |
| Finished | Jul 25 08:37:45 PM PDT 24 |
| Peak memory | 620904 kb |
| Host | smart-adefb8fd-1d03-44f1-b1a9-2447b43dd49e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2963862044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2963862044 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3005101078 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 28497723368 ps |
| CPU time | 2289.41 seconds |
| Started | Jul 25 08:02:44 PM PDT 24 |
| Finished | Jul 25 08:40:54 PM PDT 24 |
| Peak memory | 622300 kb |
| Host | smart-56635eea-0680-4d9c-b67a-1ea8f4f03448 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3005101078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3005101078 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1321061894 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 31085848428 ps |
| CPU time | 2853.84 seconds |
| Started | Jul 25 08:04:06 PM PDT 24 |
| Finished | Jul 25 08:51:40 PM PDT 24 |
| Peak memory | 621832 kb |
| Host | smart-24899ad7-a843-4d7a-ba05-3e68d4bf6618 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321061894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1321061894 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3496948790 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 15100079300 ps |
| CPU time | 4066.55 seconds |
| Started | Jul 25 08:09:32 PM PDT 24 |
| Finished | Jul 25 09:17:19 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-c888f8f0-d4c8-4ac6-88e1-ee66eb76e5ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496948790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3496948790 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2351407146 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 15323373780 ps |
| CPU time | 3811.18 seconds |
| Started | Jul 25 08:07:08 PM PDT 24 |
| Finished | Jul 25 09:10:39 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-5a801ce8-37be-40cb-94c7-59c16418d69f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351407146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2351407146 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.894597210 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 14775303670 ps |
| CPU time | 3692.5 seconds |
| Started | Jul 25 08:09:23 PM PDT 24 |
| Finished | Jul 25 09:10:56 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-1a4807a7-7d8f-403a-ab67-f207524541a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894597210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_ no_meas.894597210 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.645834038 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 26157940032 ps |
| CPU time | 5839.23 seconds |
| Started | Jul 25 08:11:00 PM PDT 24 |
| Finished | Jul 25 09:48:21 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-055b94ab-b881-432f-9596-c427e96346ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645834038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.645834038 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.1647937725 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 25385459840 ps |
| CPU time | 3847.9 seconds |
| Started | Jul 25 08:04:52 PM PDT 24 |
| Finished | Jul 25 09:09:01 PM PDT 24 |
| Peak memory | 612616 kb |
| Host | smart-9cb2a9f0-36b3-4a44-a3c8-1f69a371a730 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647937725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1647937725 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2921153852 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 23543762520 ps |
| CPU time | 5695.37 seconds |
| Started | Jul 25 08:09:35 PM PDT 24 |
| Finished | Jul 25 09:44:32 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-9b40366c-5345-497c-8dd5-c9e5c6d5c9b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2921153852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2921153852 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1376440196 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 23611884256 ps |
| CPU time | 7171.81 seconds |
| Started | Jul 25 08:10:06 PM PDT 24 |
| Finished | Jul 25 10:09:38 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-3652d1b3-f045-4789-b349-2bc78cac084c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1376440196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.1376440196 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.673808443 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 24493651750 ps |
| CPU time | 5649.34 seconds |
| Started | Jul 25 08:08:02 PM PDT 24 |
| Finished | Jul 25 09:42:12 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-65959ea9-3df4-4aef-a66d-25b770f95fbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=673808443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.673808443 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2999812940 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 22332981220 ps |
| CPU time | 5626.85 seconds |
| Started | Jul 25 08:08:20 PM PDT 24 |
| Finished | Jul 25 09:42:07 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-edcfa584-31c6-4d5e-a742-ce6eacffbb12 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2999812940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2999812940 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2429044104 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 17742054600 ps |
| CPU time | 4306.3 seconds |
| Started | Jul 25 08:09:18 PM PDT 24 |
| Finished | Jul 25 09:21:05 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-4009ad60-bf0b-4bde-a1f4-ca74ba299549 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2429044104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.2429044104 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.840270819 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 15410092079 ps |
| CPU time | 3426.74 seconds |
| Started | Jul 25 08:10:03 PM PDT 24 |
| Finished | Jul 25 09:07:10 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-3376c2eb-8652-47c1-96d1-b825210a6365 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840270819 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.840270819 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2898826983 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 14505387578 ps |
| CPU time | 3520.69 seconds |
| Started | Jul 25 08:07:37 PM PDT 24 |
| Finished | Jul 25 09:06:18 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-60655cf7-eb1c-4d0b-87b5-d89cd5b236e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898826983 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2898826983 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1600675996 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 14841740438 ps |
| CPU time | 3771.09 seconds |
| Started | Jul 25 08:06:11 PM PDT 24 |
| Finished | Jul 25 09:09:03 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-17152295-9efe-4f1f-a4f8-c3a22749e196 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600675996 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1600675996 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1892214459 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 13409230740 ps |
| CPU time | 4022.52 seconds |
| Started | Jul 25 08:06:09 PM PDT 24 |
| Finished | Jul 25 09:13:12 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-da6682fb-9396-4281-8978-da53c85ce800 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892214459 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1892214459 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2421539984 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 10899287202 ps |
| CPU time | 2905.87 seconds |
| Started | Jul 25 08:05:03 PM PDT 24 |
| Finished | Jul 25 08:53:29 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-38ba5c73-992e-4a38-b128-77022243e7d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421539984 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2421539984 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1592390204 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 14230887910 ps |
| CPU time | 3498.27 seconds |
| Started | Jul 25 08:08:07 PM PDT 24 |
| Finished | Jul 25 09:06:26 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-db623f0d-f974-4aad-a8c9-8d88c3d77ccf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592390204 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1592390204 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1508493494 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 15371424904 ps |
| CPU time | 3572.11 seconds |
| Started | Jul 25 08:09:36 PM PDT 24 |
| Finished | Jul 25 09:09:09 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-cfbd2231-e2bd-491a-b2ba-fdbc50ca32e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508493494 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1508493494 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3585872610 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 14514041408 ps |
| CPU time | 4302.77 seconds |
| Started | Jul 25 08:09:49 PM PDT 24 |
| Finished | Jul 25 09:21:33 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-7755df62-408b-4466-92a7-5d5cedfa1be2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585872610 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3585872610 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2991817536 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 13713518119 ps |
| CPU time | 4334.15 seconds |
| Started | Jul 25 08:08:22 PM PDT 24 |
| Finished | Jul 25 09:20:36 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-25490964-a2ba-4fd9-b922-db251f51a106 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991817536 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2991817536 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2147506957 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 11422493441 ps |
| CPU time | 2844.69 seconds |
| Started | Jul 25 08:09:04 PM PDT 24 |
| Finished | Jul 25 08:56:29 PM PDT 24 |
| Peak memory | 611840 kb |
| Host | smart-b18147ea-eb55-43bb-a108-c1c4f0357542 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147506957 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2147506957 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.4104965201 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 14787462332 ps |
| CPU time | 3980.59 seconds |
| Started | Jul 25 08:06:27 PM PDT 24 |
| Finished | Jul 25 09:12:48 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-11503a0d-21da-4cb9-98db-86bd8524e00e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4104965201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.4104965201 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2485139098 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 17557148108 ps |
| CPU time | 3787.63 seconds |
| Started | Jul 25 08:07:02 PM PDT 24 |
| Finished | Jul 25 09:10:10 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-9a400325-f475-40d9-ac85-cb946c72cc21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485139098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2485139098 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3631322685 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5007145786 ps |
| CPU time | 425.14 seconds |
| Started | Jul 25 08:05:13 PM PDT 24 |
| Finished | Jul 25 08:12:19 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-929bbf4d-1593-430f-b21e-f889971717d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631322685 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3631322685 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.1770455586 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 4997794913 ps |
| CPU time | 215.49 seconds |
| Started | Jul 25 08:02:11 PM PDT 24 |
| Finished | Jul 25 08:05:47 PM PDT 24 |
| Peak memory | 620320 kb |
| Host | smart-e7eda0e3-aa5e-4df4-ad3d-80d9a86366f4 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1770455586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1770455586 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.3318943049 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2135422740 ps |
| CPU time | 95.18 seconds |
| Started | Jul 25 08:02:25 PM PDT 24 |
| Finished | Jul 25 08:04:00 PM PDT 24 |
| Peak memory | 618364 kb |
| Host | smart-f4d9bfe5-4a4b-43f8-a1f8-12698d71c5b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318943049 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3318943049 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.4014742299 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 12431280300 ps |
| CPU time | 1724.6 seconds |
| Started | Jul 25 08:04:59 PM PDT 24 |
| Finished | Jul 25 08:33:44 PM PDT 24 |
| Peak memory | 604468 kb |
| Host | smart-1cf426db-a8a8-4600-b14f-d3f061272c56 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014742299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.4014742299 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.423773224 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13547371520 ps |
| CPU time | 1342.27 seconds |
| Started | Jul 25 08:05:08 PM PDT 24 |
| Finished | Jul 25 08:27:30 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-6672648f-17d1-4d3f-beec-7f7d6f421cbd |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423773224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.423773224 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3249011727 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 2664036912 ps |
| CPU time | 336.29 seconds |
| Started | Jul 25 08:06:18 PM PDT 24 |
| Finished | Jul 25 08:11:55 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-300a5378-5bf7-4704-9cfe-af27746a910d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3249011727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3249011727 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2305333267 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 19620024256 ps |
| CPU time | 696.7 seconds |
| Started | Jul 25 08:10:24 PM PDT 24 |
| Finished | Jul 25 08:22:01 PM PDT 24 |
| Peak memory | 620376 kb |
| Host | smart-f49dd60a-ab5d-4004-ad98-602e4ad3b373 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2305333267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2305333267 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.3289659051 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 2821341096 ps |
| CPU time | 226.82 seconds |
| Started | Jul 25 08:09:46 PM PDT 24 |
| Finished | Jul 25 08:13:33 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-cc011fb5-f085-47ee-af00-b9d092126743 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289659051 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3289659051 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.870487843 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 3087230822 ps |
| CPU time | 287.94 seconds |
| Started | Jul 25 08:07:12 PM PDT 24 |
| Finished | Jul 25 08:12:00 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-337c0fe6-72d5-420f-b2f6-a9da4053c43e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8704 87843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.870487843 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2798055206 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3627197901 ps |
| CPU time | 270.86 seconds |
| Started | Jul 25 08:15:50 PM PDT 24 |
| Finished | Jul 25 08:20:21 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-a02f3bae-e5b7-4dff-a9f1-e5fc3269a5c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798055206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2798055206 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.734855189 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 3101072560 ps |
| CPU time | 242.44 seconds |
| Started | Jul 25 08:09:09 PM PDT 24 |
| Finished | Jul 25 08:13:11 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-51af8c01-7c45-4091-8f49-773c7d827152 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734855189 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.734855189 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.341087960 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 2120066936 ps |
| CPU time | 165.08 seconds |
| Started | Jul 25 08:08:25 PM PDT 24 |
| Finished | Jul 25 08:11:10 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-0469ed9c-8c7a-4c9f-83d1-bfdbfadd93ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341087960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.341087960 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.136288467 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 3063800258 ps |
| CPU time | 351.2 seconds |
| Started | Jul 25 08:08:52 PM PDT 24 |
| Finished | Jul 25 08:14:44 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-f590f5c5-e206-48b1-bf1b-b6001ba40064 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136288467 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.136288467 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.1438705773 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2666319800 ps |
| CPU time | 190.31 seconds |
| Started | Jul 25 08:15:46 PM PDT 24 |
| Finished | Jul 25 08:18:57 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-8eb8792f-5141-4b1d-ac37-2b43a14b4228 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438705773 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1438705773 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2364524117 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3232439956 ps |
| CPU time | 299.19 seconds |
| Started | Jul 25 08:07:54 PM PDT 24 |
| Finished | Jul 25 08:12:53 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-bbf40d82-ae3f-4307-bea5-bc7d33b0ea7e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2364524117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2364524117 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2933604047 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 5976705600 ps |
| CPU time | 489.93 seconds |
| Started | Jul 25 08:08:06 PM PDT 24 |
| Finished | Jul 25 08:16:17 PM PDT 24 |
| Peak memory | 620208 kb |
| Host | smart-516d9c2b-e600-4a0e-bde1-13f1fd22eeec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2933604047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2933604047 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.4092989107 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 9901300344 ps |
| CPU time | 2343.53 seconds |
| Started | Jul 25 08:08:24 PM PDT 24 |
| Finished | Jul 25 08:47:28 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-f931ef28-2573-426a-8165-99c92a9c8a56 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4092989107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.4092989107 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4190253298 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 5907887534 ps |
| CPU time | 1308.45 seconds |
| Started | Jul 25 08:10:14 PM PDT 24 |
| Finished | Jul 25 08:32:02 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-c7691bf4-4d20-4c3b-8bdd-baae96addfb0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190253298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.4190253298 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1452849462 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 13321123992 ps |
| CPU time | 1722.45 seconds |
| Started | Jul 25 08:07:39 PM PDT 24 |
| Finished | Jul 25 08:36:22 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-d14610ce-ebfc-42e9-bd18-9bcb83381dcf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452849462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1452849462 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3116839614 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 7669927448 ps |
| CPU time | 1343.8 seconds |
| Started | Jul 25 08:08:41 PM PDT 24 |
| Finished | Jul 25 08:31:05 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-8c16b21e-c4f9-4ac1-9138-96ce78a5e807 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3116839614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3116839614 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2615112335 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4495047960 ps |
| CPU time | 363.52 seconds |
| Started | Jul 25 08:07:01 PM PDT 24 |
| Finished | Jul 25 08:13:05 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-9bc747e7-8633-4c40-b52a-f10e8b8c1ae8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2615112335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.2615112335 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1344351043 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 255409386380 ps |
| CPU time | 12216.4 seconds |
| Started | Jul 25 08:09:10 PM PDT 24 |
| Finished | Jul 25 11:32:47 PM PDT 24 |
| Peak memory | 611372 kb |
| Host | smart-47997f65-739d-4312-b500-8723562aa494 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344351043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1344351043 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1515840255 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3213921544 ps |
| CPU time | 284.08 seconds |
| Started | Jul 25 08:08:54 PM PDT 24 |
| Finished | Jul 25 08:13:38 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-be24f258-0165-4d7e-b9a6-c18d55e158d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515840255 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1515840255 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.931866897 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 3934203480 ps |
| CPU time | 470.39 seconds |
| Started | Jul 25 08:06:14 PM PDT 24 |
| Finished | Jul 25 08:14:05 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-4d2963b0-4569-49be-a093-600cbf0f7aea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931866897 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.931866897 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1423539088 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 7255661678 ps |
| CPU time | 397.21 seconds |
| Started | Jul 25 08:08:26 PM PDT 24 |
| Finished | Jul 25 08:15:04 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-85c367c5-b860-40c7-a4f6-3134089bf461 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1423539088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1423539088 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2717508603 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3165684274 ps |
| CPU time | 359.47 seconds |
| Started | Jul 25 08:16:19 PM PDT 24 |
| Finished | Jul 25 08:22:19 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-e834e2dd-a9e2-4328-b01e-95e6d849c172 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717508603 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2717508603 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1779277320 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 9572914864 ps |
| CPU time | 653.21 seconds |
| Started | Jul 25 08:07:26 PM PDT 24 |
| Finished | Jul 25 08:18:19 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-4700fcf4-e778-4d54-a6f9-255aa6fc5b3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1779277320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1779277320 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2252882913 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 6001371384 ps |
| CPU time | 564.22 seconds |
| Started | Jul 25 08:10:15 PM PDT 24 |
| Finished | Jul 25 08:19:39 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-f3b3ba5b-4577-441a-acab-da4d2cb680bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2252882913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2252882913 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1928323710 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 8886404576 ps |
| CPU time | 1165.78 seconds |
| Started | Jul 25 08:13:18 PM PDT 24 |
| Finished | Jul 25 08:32:44 PM PDT 24 |
| Peak memory | 617696 kb |
| Host | smart-c42a35a5-ab50-4f20-8121-801d8c5f09fa |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928323710 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.1928323710 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4211200056 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 28082511697 ps |
| CPU time | 4177.09 seconds |
| Started | Jul 25 08:16:32 PM PDT 24 |
| Finished | Jul 25 09:26:10 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-9a3fe9a6-cdb6-441b-98a0-80de32677cd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211200056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.4211200056 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.386133931 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 6503337862 ps |
| CPU time | 489.99 seconds |
| Started | Jul 25 08:21:51 PM PDT 24 |
| Finished | Jul 25 08:30:01 PM PDT 24 |
| Peak memory | 621912 kb |
| Host | smart-f4713ea3-dee6-453d-a248-8e1f1ff2bcbd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=386133931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.386133931 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1614090870 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 4512367556 ps |
| CPU time | 702.9 seconds |
| Started | Jul 25 08:11:02 PM PDT 24 |
| Finished | Jul 25 08:22:46 PM PDT 24 |
| Peak memory | 613480 kb |
| Host | smart-7dcbb56e-16d0-4710-8654-42e8c7cfa69f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614090870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1614090870 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1057609898 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 3838620480 ps |
| CPU time | 818.44 seconds |
| Started | Jul 25 08:11:28 PM PDT 24 |
| Finished | Jul 25 08:25:07 PM PDT 24 |
| Peak memory | 613416 kb |
| Host | smart-0deca909-dfde-4f25-8c7d-878898a37185 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057609898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1057609898 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2991155654 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3818549352 ps |
| CPU time | 799.66 seconds |
| Started | Jul 25 08:12:49 PM PDT 24 |
| Finished | Jul 25 08:26:09 PM PDT 24 |
| Peak memory | 613768 kb |
| Host | smart-e5177c50-d8bb-4923-8971-1bbf2bc8ca6a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991155654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2991155654 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3873549477 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 4649645504 ps |
| CPU time | 608.48 seconds |
| Started | Jul 25 08:11:54 PM PDT 24 |
| Finished | Jul 25 08:22:02 PM PDT 24 |
| Peak memory | 613492 kb |
| Host | smart-3ee5bf54-8485-445a-a668-e7d35d02e4ee |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873549477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3873549477 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1395222409 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4922992300 ps |
| CPU time | 698.42 seconds |
| Started | Jul 25 08:11:40 PM PDT 24 |
| Finished | Jul 25 08:23:19 PM PDT 24 |
| Peak memory | 612724 kb |
| Host | smart-28e8269c-1ea6-4de7-b6bd-75222d860ce0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395222409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1395222409 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3249693439 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 4764528520 ps |
| CPU time | 722.3 seconds |
| Started | Jul 25 08:10:58 PM PDT 24 |
| Finished | Jul 25 08:23:01 PM PDT 24 |
| Peak memory | 613836 kb |
| Host | smart-3c481fd3-b8b1-48bd-bef3-f6b0ab5f4093 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249693439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3249693439 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3668874427 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2888941665 ps |
| CPU time | 321.88 seconds |
| Started | Jul 25 08:12:12 PM PDT 24 |
| Finished | Jul 25 08:17:34 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-bdd26e00-eaa4-45c6-b35c-c2d0793e719c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668874427 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3668874427 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1885175194 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 4099675022 ps |
| CPU time | 540.63 seconds |
| Started | Jul 25 08:11:32 PM PDT 24 |
| Finished | Jul 25 08:20:33 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-ca89b86b-46b1-478b-8d8e-e2b808fa22ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885175194 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1885175194 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2853289093 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 1970505190 ps |
| CPU time | 181.1 seconds |
| Started | Jul 25 08:14:06 PM PDT 24 |
| Finished | Jul 25 08:17:08 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-da2406af-90f7-4d2e-a04a-238974a8edf8 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853289093 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2853289093 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.5325982 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 5427631120 ps |
| CPU time | 379.22 seconds |
| Started | Jul 25 08:11:15 PM PDT 24 |
| Finished | Jul 25 08:17:35 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-a1554869-f4cc-4f96-94d4-8cae70b8a6ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5325982 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.5325982 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3266385370 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 4315527196 ps |
| CPU time | 419.62 seconds |
| Started | Jul 25 08:20:55 PM PDT 24 |
| Finished | Jul 25 08:27:55 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-36465794-a8e2-4c7d-a561-8d2ec91f63c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266385370 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3266385370 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3359428468 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3811467454 ps |
| CPU time | 430.79 seconds |
| Started | Jul 25 08:21:55 PM PDT 24 |
| Finished | Jul 25 08:29:06 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-df85d87f-437d-4b51-82bc-cad196f82ded |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359428468 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3359428468 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2758427334 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 4854628648 ps |
| CPU time | 468.96 seconds |
| Started | Jul 25 08:21:28 PM PDT 24 |
| Finished | Jul 25 08:29:17 PM PDT 24 |
| Peak memory | 611144 kb |
| Host | smart-a6d78d26-6f9b-40ee-adc0-1c3192fd6113 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758427334 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2758427334 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.4103794877 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 11681339652 ps |
| CPU time | 1403.09 seconds |
| Started | Jul 25 08:09:57 PM PDT 24 |
| Finished | Jul 25 08:33:20 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-9d1dee4a-94ee-4d4b-b381-74c95be27927 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103794877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.4103794877 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.792746713 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 3387633100 ps |
| CPU time | 605.53 seconds |
| Started | Jul 25 08:11:18 PM PDT 24 |
| Finished | Jul 25 08:21:24 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-f46cbe8e-ef5b-4cd7-ad1a-9fcdcd538e71 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792746713 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.792746713 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2716743173 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 5116193596 ps |
| CPU time | 570.87 seconds |
| Started | Jul 25 08:11:29 PM PDT 24 |
| Finished | Jul 25 08:21:00 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-186491d5-34a0-4c03-8a97-102a796f8651 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716743173 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2716743173 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1442286806 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2756939452 ps |
| CPU time | 182.08 seconds |
| Started | Jul 25 08:15:54 PM PDT 24 |
| Finished | Jul 25 08:18:57 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-32fe36bc-d8e0-4e00-a439-2ed27897c389 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442286806 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1442286806 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.925945422 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 26633554664 ps |
| CPU time | 6185.95 seconds |
| Started | Jul 25 08:07:19 PM PDT 24 |
| Finished | Jul 25 09:50:26 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-a68f75f7-2b72-490b-910c-543fc7eef06f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925945422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.925945422 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.946883907 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 130545776204 ps |
| CPU time | 17994.6 seconds |
| Started | Jul 25 08:17:08 PM PDT 24 |
| Finished | Jul 26 01:17:05 AM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-5a51ef5c-8c94-4c0b-9977-c7ed9ccfb5e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=946883907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.946883907 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.4153334509 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4239551570 ps |
| CPU time | 372.6 seconds |
| Started | Jul 25 08:09:06 PM PDT 24 |
| Finished | Jul 25 08:15:19 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-a8f295f1-7375-4f8d-a82f-68c6ea4ca6f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41533 34509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.4153334509 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3298313433 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3675663382 ps |
| CPU time | 237.32 seconds |
| Started | Jul 25 08:09:06 PM PDT 24 |
| Finished | Jul 25 08:13:04 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-c37f196f-869d-4158-aab4-a660cb30f27c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298313433 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3298313433 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2963764652 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2510391426 ps |
| CPU time | 195.14 seconds |
| Started | Jul 25 08:17:34 PM PDT 24 |
| Finished | Jul 25 08:20:50 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-423ca490-58fb-4754-bcb1-9870553af090 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963764652 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2963764652 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3380426872 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6041373400 ps |
| CPU time | 611.76 seconds |
| Started | Jul 25 08:04:50 PM PDT 24 |
| Finished | Jul 25 08:15:02 PM PDT 24 |
| Peak memory | 611712 kb |
| Host | smart-4d42eeeb-b506-44f2-80c9-f164268e2023 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3380426872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3380426872 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.44022269 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 7348803398 ps |
| CPU time | 2017.16 seconds |
| Started | Jul 25 08:09:31 PM PDT 24 |
| Finished | Jul 25 08:43:09 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-13ea622e-aec9-4512-8710-bb510a363a8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44022269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_au to_mode.44022269 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2991148837 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2934209290 ps |
| CPU time | 600.57 seconds |
| Started | Jul 25 08:07:57 PM PDT 24 |
| Finished | Jul 25 08:17:58 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-1f846839-a62a-459d-84f6-c74c069f88e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991148837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2991148837 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.4281091643 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 7384512024 ps |
| CPU time | 865.77 seconds |
| Started | Jul 25 08:08:44 PM PDT 24 |
| Finished | Jul 25 08:23:10 PM PDT 24 |
| Peak memory | 611616 kb |
| Host | smart-6541bf48-2954-4f39-a591-ae08736f8db1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4281091643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.4281091643 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.519580724 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 7202648685 ps |
| CPU time | 1334.48 seconds |
| Started | Jul 25 08:08:48 PM PDT 24 |
| Finished | Jul 25 08:31:03 PM PDT 24 |
| Peak memory | 611500 kb |
| Host | smart-86bbf3cf-f269-4301-9f62-efb6756da7b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519580724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.519580724 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.939993128 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3418856562 ps |
| CPU time | 674.11 seconds |
| Started | Jul 25 08:09:20 PM PDT 24 |
| Finished | Jul 25 08:20:34 PM PDT 24 |
| Peak memory | 616184 kb |
| Host | smart-c034cab0-2bc2-42db-b749-81f3052eae1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939993128 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_edn_kat.939993128 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1981312680 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 7435183370 ps |
| CPU time | 1586.63 seconds |
| Started | Jul 25 08:08:10 PM PDT 24 |
| Finished | Jul 25 08:34:37 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-9507d47d-df11-409a-93bb-e1269cd89949 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981312680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1981312680 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.507756425 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2692876120 ps |
| CPU time | 253.64 seconds |
| Started | Jul 25 08:08:46 PM PDT 24 |
| Finished | Jul 25 08:13:01 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-38562a4d-f5d4-44c2-a501-b375fac48dbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50 7756425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.507756425 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2845504475 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6891940328 ps |
| CPU time | 1649.17 seconds |
| Started | Jul 25 08:09:05 PM PDT 24 |
| Finished | Jul 25 08:36:35 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-80bf5c03-7906-4764-8e81-e0399c3b437f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2845504475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2845504475 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2898432747 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 3337865576 ps |
| CPU time | 263.1 seconds |
| Started | Jul 25 08:07:59 PM PDT 24 |
| Finished | Jul 25 08:12:22 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-d3e7d69f-10a4-4d61-ae5a-ec71c5bd90fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898432747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2898432747 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.503118597 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2937074446 ps |
| CPU time | 586.11 seconds |
| Started | Jul 25 08:15:46 PM PDT 24 |
| Finished | Jul 25 08:25:33 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-0ca50aa2-1231-4807-8e04-5237194a9d9b |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=503118597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.503118597 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1131733931 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 3064772920 ps |
| CPU time | 258.91 seconds |
| Started | Jul 25 08:05:52 PM PDT 24 |
| Finished | Jul 25 08:10:11 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-ab40f226-739c-4f36-84af-d47653b97602 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131733931 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1131733931 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1162223600 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 2711945452 ps |
| CPU time | 236.27 seconds |
| Started | Jul 25 08:07:22 PM PDT 24 |
| Finished | Jul 25 08:11:19 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-1dbbc434-4c3e-46a7-96c6-c327acb35f04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162223600 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1162223600 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.2674101067 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 2674674688 ps |
| CPU time | 194.22 seconds |
| Started | Jul 25 08:06:24 PM PDT 24 |
| Finished | Jul 25 08:09:39 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-21d22045-68c4-4e31-a6ba-f19c69970caa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674101067 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.2674101067 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.2728014644 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 2490387296 ps |
| CPU time | 118.64 seconds |
| Started | Jul 25 08:04:08 PM PDT 24 |
| Finished | Jul 25 08:06:07 PM PDT 24 |
| Peak memory | 608744 kb |
| Host | smart-c533c455-9139-4e73-9cd3-af739ef4c939 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728014644 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.2728014644 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3777198793 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 58140769476 ps |
| CPU time | 10343.4 seconds |
| Started | Jul 25 08:06:28 PM PDT 24 |
| Finished | Jul 25 10:58:53 PM PDT 24 |
| Peak memory | 625528 kb |
| Host | smart-e02fd259-537e-40cd-a45c-0644ded062aa |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3777198793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3777198793 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.1991341239 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4868751390 ps |
| CPU time | 661.8 seconds |
| Started | Jul 25 08:14:12 PM PDT 24 |
| Finished | Jul 25 08:25:14 PM PDT 24 |
| Peak memory | 611768 kb |
| Host | smart-54570f2d-2b32-4b95-a33e-39b229759a04 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1991341239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1991341239 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.442520179 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 6103163466 ps |
| CPU time | 1173.16 seconds |
| Started | Jul 25 08:08:05 PM PDT 24 |
| Finished | Jul 25 08:27:39 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-98dd591e-1726-442d-bf9b-3f643a72108a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442520179 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.442520179 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3743904518 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 6426184468 ps |
| CPU time | 1159.93 seconds |
| Started | Jul 25 08:06:44 PM PDT 24 |
| Finished | Jul 25 08:26:04 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-7cf9ab82-b8e1-4cf3-9f03-e223e86e43b1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743904518 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.3743904518 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3332164751 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 7568930116 ps |
| CPU time | 1553.61 seconds |
| Started | Jul 25 08:14:15 PM PDT 24 |
| Finished | Jul 25 08:40:08 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-09088d2d-1c5e-4e32-9c0d-3316cff92f05 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332164751 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3332164751 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3372992553 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 6038463457 ps |
| CPU time | 1149.95 seconds |
| Started | Jul 25 08:08:08 PM PDT 24 |
| Finished | Jul 25 08:27:18 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-bf9f41bd-1704-44a4-a271-6e13fbb74d59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372992553 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3372992553 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.564421613 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3501636296 ps |
| CPU time | 346.88 seconds |
| Started | Jul 25 08:07:48 PM PDT 24 |
| Finished | Jul 25 08:13:36 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-3706016e-9475-4793-aa05-f9d53da9fa20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564421613 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.564421613 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2952330631 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 5375322196 ps |
| CPU time | 1198.1 seconds |
| Started | Jul 25 08:18:09 PM PDT 24 |
| Finished | Jul 25 08:38:08 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-1023d2de-bb74-4201-bd85-b7866273a2b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952330631 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2952330631 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2527163099 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3973523656 ps |
| CPU time | 639.74 seconds |
| Started | Jul 25 08:04:40 PM PDT 24 |
| Finished | Jul 25 08:15:20 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-f709fcda-345f-4f5b-9465-ada0daeb9006 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527163099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2527163099 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2763376335 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 4131396651 ps |
| CPU time | 651.58 seconds |
| Started | Jul 25 08:04:52 PM PDT 24 |
| Finished | Jul 25 08:15:45 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-51ec0883-588b-4180-96a3-85c4d71bc40d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2763376335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2763376335 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.639085074 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 4579471531 ps |
| CPU time | 788.61 seconds |
| Started | Jul 25 08:13:59 PM PDT 24 |
| Finished | Jul 25 08:27:07 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-0922285c-2661-4e70-a9bc-d216571610d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=639085074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.639085074 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.188544555 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2782816760 ps |
| CPU time | 326.89 seconds |
| Started | Jul 25 08:12:59 PM PDT 24 |
| Finished | Jul 25 08:18:26 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-0740687c-6380-4581-b49b-8ccdc1984318 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885445 55 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.188544555 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3829017493 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 24051365020 ps |
| CPU time | 2502.38 seconds |
| Started | Jul 25 08:06:12 PM PDT 24 |
| Finished | Jul 25 08:47:56 PM PDT 24 |
| Peak memory | 614060 kb |
| Host | smart-e154a459-b16b-4112-8f89-3f14b3e4c8f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829017493 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3829017493 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2836913048 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2735169112 ps |
| CPU time | 234.15 seconds |
| Started | Jul 25 08:20:28 PM PDT 24 |
| Finished | Jul 25 08:24:23 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-66f52169-31f1-4a17-9c0c-72b6c6970ff9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2836913048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2836913048 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.552847640 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2985035442 ps |
| CPU time | 256.1 seconds |
| Started | Jul 25 08:16:33 PM PDT 24 |
| Finished | Jul 25 08:20:50 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-bb2d9669-27d7-4f5c-83a1-15cdce83c795 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552847640 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_gpio_smoketest.552847640 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.3770602014 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3357280422 ps |
| CPU time | 253.13 seconds |
| Started | Jul 25 08:08:55 PM PDT 24 |
| Finished | Jul 25 08:13:08 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-a81d3237-76e7-4bb5-8866-32cff36b0ce3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770602014 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3770602014 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1648258155 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 2862820880 ps |
| CPU time | 248.77 seconds |
| Started | Jul 25 08:12:16 PM PDT 24 |
| Finished | Jul 25 08:16:24 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-47c34559-553b-448f-94ce-75569bdd3c0e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648258155 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1648258155 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.985457373 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 2632248188 ps |
| CPU time | 176.38 seconds |
| Started | Jul 25 08:10:12 PM PDT 24 |
| Finished | Jul 25 08:13:08 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-009b7dff-739b-48e2-bb44-514d8d6c6187 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985457373 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.985457373 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2668502544 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 3118887314 ps |
| CPU time | 272.1 seconds |
| Started | Jul 25 08:18:34 PM PDT 24 |
| Finished | Jul 25 08:23:07 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-7145bb9a-bd17-4daa-80e4-168b89c6e124 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668502544 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2668502544 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.148255838 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 7022133408 ps |
| CPU time | 1439.88 seconds |
| Started | Jul 25 08:11:59 PM PDT 24 |
| Finished | Jul 25 08:36:00 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-a088b4a1-c7a4-494b-8577-96a2f1e2c41c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148255838 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.148255838 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.358976168 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 3394660174 ps |
| CPU time | 316.03 seconds |
| Started | Jul 25 08:08:39 PM PDT 24 |
| Finished | Jul 25 08:13:55 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-252366c4-79e3-4cb9-b1cf-59a13c96cd9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358976168 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.358976168 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.2306670884 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3185630382 ps |
| CPU time | 379.82 seconds |
| Started | Jul 25 08:16:27 PM PDT 24 |
| Finished | Jul 25 08:22:47 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-a4cd443d-1110-4a90-b83f-8fba66117161 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306670884 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.2306670884 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3199921089 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4039185738 ps |
| CPU time | 420.22 seconds |
| Started | Jul 25 08:06:15 PM PDT 24 |
| Finished | Jul 25 08:13:16 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-7b8fa90e-cbf0-4259-9545-fc279243cd7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199921089 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3199921089 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1212542216 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4932772908 ps |
| CPU time | 749.34 seconds |
| Started | Jul 25 08:05:33 PM PDT 24 |
| Finished | Jul 25 08:18:03 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-296f59eb-6465-4494-8ab6-767fa1ac9641 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212542216 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1212542216 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.410609043 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4952547224 ps |
| CPU time | 831.9 seconds |
| Started | Jul 25 08:03:37 PM PDT 24 |
| Finished | Jul 25 08:17:29 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-f3d0acfb-11fa-43d2-bc3d-d3c90996d18a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410609043 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.410609043 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2577397515 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4184599500 ps |
| CPU time | 729.66 seconds |
| Started | Jul 25 08:03:19 PM PDT 24 |
| Finished | Jul 25 08:15:29 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-e79d38c4-6169-4dd2-9df5-95ed12632964 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577397515 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2577397515 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.451907691 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 65828091565 ps |
| CPU time | 11122.1 seconds |
| Started | Jul 25 08:06:49 PM PDT 24 |
| Finished | Jul 25 11:12:13 PM PDT 24 |
| Peak memory | 625380 kb |
| Host | smart-41eea3e6-516f-4866-9003-c64a71f2f886 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=451907691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.451907691 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1996356509 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 11207359456 ps |
| CPU time | 2177.87 seconds |
| Started | Jul 25 08:09:45 PM PDT 24 |
| Finished | Jul 25 08:46:04 PM PDT 24 |
| Peak memory | 618236 kb |
| Host | smart-709a3448-aad0-4e51-bc42-e77baeda5aac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996 356509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1996356509 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1615437303 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8091917978 ps |
| CPU time | 1435.18 seconds |
| Started | Jul 25 08:08:51 PM PDT 24 |
| Finished | Jul 25 08:32:47 PM PDT 24 |
| Peak memory | 617524 kb |
| Host | smart-d2ace7f4-60d3-43ad-96fd-9905f9e4c6dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1615437303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1615437303 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3424564941 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 12156783027 ps |
| CPU time | 2161.32 seconds |
| Started | Jul 25 08:15:55 PM PDT 24 |
| Finished | Jul 25 08:51:57 PM PDT 24 |
| Peak memory | 618776 kb |
| Host | smart-7df36d3d-6f64-4174-b6ac-a833dcbccc19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3424564941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3424564941 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1812462982 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 10785620318 ps |
| CPU time | 2275.9 seconds |
| Started | Jul 25 08:08:33 PM PDT 24 |
| Finished | Jul 25 08:46:29 PM PDT 24 |
| Peak memory | 618216 kb |
| Host | smart-fe0b2608-3166-465d-8fc3-392001a53c3a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1812462982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1812462982 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1461523758 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 14144254948 ps |
| CPU time | 3516.68 seconds |
| Started | Jul 25 08:09:38 PM PDT 24 |
| Finished | Jul 25 09:08:15 PM PDT 24 |
| Peak memory | 611540 kb |
| Host | smart-262221ac-ddfe-4373-9036-be271d6a4fff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615 23758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1461523758 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2899987362 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3104637104 ps |
| CPU time | 258.89 seconds |
| Started | Jul 25 08:16:17 PM PDT 24 |
| Finished | Jul 25 08:20:37 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-c226f3cb-e7f8-48ae-b951-85d24fbeb3f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899987362 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2899987362 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.4208576379 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 2953305686 ps |
| CPU time | 308.21 seconds |
| Started | Jul 25 08:05:11 PM PDT 24 |
| Finished | Jul 25 08:10:20 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-f718afdc-b183-4e33-b46c-80cf3c6fc5ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208576379 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.4208576379 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1828846351 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2777965812 ps |
| CPU time | 340.29 seconds |
| Started | Jul 25 08:16:18 PM PDT 24 |
| Finished | Jul 25 08:22:00 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-785eb171-5d0c-4e12-979c-682341a38d13 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828846351 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1828846351 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3969796122 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 2752852680 ps |
| CPU time | 227.68 seconds |
| Started | Jul 25 08:09:17 PM PDT 24 |
| Finished | Jul 25 08:13:05 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-370857b6-96cf-4a0a-bf3e-edf2829efcde |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969796122 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3969796122 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2386648327 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3458982622 ps |
| CPU time | 290.16 seconds |
| Started | Jul 25 08:10:34 PM PDT 24 |
| Finished | Jul 25 08:15:24 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-6b09d8a5-9be8-425c-8455-86baa75fceb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386648327 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2386648327 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.560464050 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 2835756670 ps |
| CPU time | 329.41 seconds |
| Started | Jul 25 08:09:58 PM PDT 24 |
| Finished | Jul 25 08:15:28 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-a154dbd5-39e2-4c1d-9c1c-0a15c447d487 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560464050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.560464050 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3513389964 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3642837710 ps |
| CPU time | 308.54 seconds |
| Started | Jul 25 08:16:32 PM PDT 24 |
| Finished | Jul 25 08:21:41 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-37155b5a-ebba-4e10-b027-b6c14500ed7c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35133899 64 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3513389964 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.25799884 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3044894576 ps |
| CPU time | 293.59 seconds |
| Started | Jul 25 08:16:24 PM PDT 24 |
| Finished | Jul 25 08:21:17 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-1761de26-271f-42ec-85d6-5d12afabe2d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25799884 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_smoketest.25799884 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1152667228 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3319163580 ps |
| CPU time | 331 seconds |
| Started | Jul 25 08:06:28 PM PDT 24 |
| Finished | Jul 25 08:11:59 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-1c3b0a4f-815c-4bcd-9518-8c90e16c54f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152667228 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1152667228 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2912234288 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5352689184 ps |
| CPU time | 576.57 seconds |
| Started | Jul 25 08:12:41 PM PDT 24 |
| Finished | Jul 25 08:22:18 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-0b9d7400-dce8-42d5-9675-a9aa4e41ae5e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2912234288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2912234288 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2564642644 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4888043854 ps |
| CPU time | 343.68 seconds |
| Started | Jul 25 08:03:44 PM PDT 24 |
| Finished | Jul 25 08:09:28 PM PDT 24 |
| Peak memory | 621128 kb |
| Host | smart-6507a1bc-cf77-4f97-a60f-e1556a7f3bb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564642644 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.2564642644 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1810902787 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2268587241 ps |
| CPU time | 98.15 seconds |
| Started | Jul 25 08:08:00 PM PDT 24 |
| Finished | Jul 25 08:09:38 PM PDT 24 |
| Peak memory | 618656 kb |
| Host | smart-1d7d6ff7-1337-4f11-8d92-96a818966e56 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1810902787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1810902787 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4072573257 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2681498651 ps |
| CPU time | 105.08 seconds |
| Started | Jul 25 08:11:32 PM PDT 24 |
| Finished | Jul 25 08:13:17 PM PDT 24 |
| Peak memory | 618528 kb |
| Host | smart-a0b6ad9f-9a31-45d6-befc-0b2dac4b1106 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072573257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4072573257 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2530668530 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 48126178318 ps |
| CPU time | 5836.55 seconds |
| Started | Jul 25 08:05:38 PM PDT 24 |
| Finished | Jul 25 09:42:55 PM PDT 24 |
| Peak memory | 619896 kb |
| Host | smart-ce97faeb-6653-4464-9ce8-f07ba02e03fe |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530668530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.2530668530 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.561884555 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 50471885796 ps |
| CPU time | 5646.3 seconds |
| Started | Jul 25 08:08:31 PM PDT 24 |
| Finished | Jul 25 09:42:39 PM PDT 24 |
| Peak memory | 621412 kb |
| Host | smart-90dd192e-354e-4c2d-9a57-99984b0f586e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561884555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.561884555 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.118520160 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 8073446588 ps |
| CPU time | 811.68 seconds |
| Started | Jul 25 08:05:15 PM PDT 24 |
| Finished | Jul 25 08:18:48 PM PDT 24 |
| Peak memory | 621008 kb |
| Host | smart-2c9d45d6-8881-4055-9a5b-54be96cc91a9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=118520160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.118520160 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1143924945 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 45814889300 ps |
| CPU time | 5502.83 seconds |
| Started | Jul 25 08:07:52 PM PDT 24 |
| Finished | Jul 25 09:39:36 PM PDT 24 |
| Peak memory | 620928 kb |
| Host | smart-b43c2f04-115c-4e00-b168-2380d832349e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143924945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1143924945 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3260934131 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 29487525960 ps |
| CPU time | 2538.84 seconds |
| Started | Jul 25 08:06:35 PM PDT 24 |
| Finished | Jul 25 08:48:55 PM PDT 24 |
| Peak memory | 620760 kb |
| Host | smart-51266d82-92ab-4a6e-b3e8-884cc3223b86 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3260934131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3260934131 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1684696037 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 17546699560 ps |
| CPU time | 3509.23 seconds |
| Started | Jul 25 08:09:51 PM PDT 24 |
| Finished | Jul 25 09:08:21 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-6f1b825f-7a95-4bdf-b6ce-6b23eae61991 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1684696037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.1684696037 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2122292303 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 18987654089 ps |
| CPU time | 4167.74 seconds |
| Started | Jul 25 08:10:15 PM PDT 24 |
| Finished | Jul 25 09:19:43 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-b92bb153-d1ed-4506-b673-4c6b180eaed8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2122292303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2122292303 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.353169994 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 24251324000 ps |
| CPU time | 4191.95 seconds |
| Started | Jul 25 08:16:55 PM PDT 24 |
| Finished | Jul 25 09:26:47 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-24dbb058-cd64-4e6e-bfa0-adde2416c702 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353169994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.353169994 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.885218201 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3542454466 ps |
| CPU time | 483.15 seconds |
| Started | Jul 25 08:06:51 PM PDT 24 |
| Finished | Jul 25 08:14:54 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-f9a07e1e-1aee-4005-86f2-378198d9ade0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885218201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.885218201 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2459798731 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 6133587392 ps |
| CPU time | 631.94 seconds |
| Started | Jul 25 08:05:36 PM PDT 24 |
| Finished | Jul 25 08:16:08 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-51dd24e6-31b0-4046-9dc3-b43e47137336 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2459798731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2459798731 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.904606068 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 4976464960 ps |
| CPU time | 1034.64 seconds |
| Started | Jul 25 08:17:45 PM PDT 24 |
| Finished | Jul 25 08:35:00 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-bbe2ee37-34df-4aa5-a446-1c3fa6b59433 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904606068 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_smoketest.904606068 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.322750367 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 3185157244 ps |
| CPU time | 234.09 seconds |
| Started | Jul 25 08:06:52 PM PDT 24 |
| Finished | Jul 25 08:10:46 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-1cde419e-a71f-45ba-9fb1-f30980f84771 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322750367 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.322750367 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2009019684 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 8423110320 ps |
| CPU time | 1380.84 seconds |
| Started | Jul 25 08:05:13 PM PDT 24 |
| Finished | Jul 25 08:28:14 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-4e63dbf7-34ed-4e6e-bc4f-4d90907b5513 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2009019684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2009019684 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.178113199 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 7975328520 ps |
| CPU time | 1415.71 seconds |
| Started | Jul 25 08:07:16 PM PDT 24 |
| Finished | Jul 25 08:30:52 PM PDT 24 |
| Peak memory | 611468 kb |
| Host | smart-202c0656-5648-4847-878b-6b6a7ba7fd0f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=178113199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.178113199 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3861119747 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 8436822632 ps |
| CPU time | 1469.6 seconds |
| Started | Jul 25 08:07:08 PM PDT 24 |
| Finished | Jul 25 08:31:38 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-a701228a-d9e9-47e8-a08a-f3bafafe074c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3861119747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3861119747 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1016525924 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 4030540250 ps |
| CPU time | 829.03 seconds |
| Started | Jul 25 08:07:24 PM PDT 24 |
| Finished | Jul 25 08:21:13 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-054d4225-ec1d-4f80-aa84-ee0779f37605 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1016525924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1016525924 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2397909550 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 3216244548 ps |
| CPU time | 272.85 seconds |
| Started | Jul 25 08:15:38 PM PDT 24 |
| Finished | Jul 25 08:20:11 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-900a9dae-9de5-4ed5-8878-074d7527d233 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397909550 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2397909550 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2156920258 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2376784780 ps |
| CPU time | 268.23 seconds |
| Started | Jul 25 08:03:56 PM PDT 24 |
| Finished | Jul 25 08:08:24 PM PDT 24 |
| Peak memory | 612112 kb |
| Host | smart-c3affd25-3b13-4191-a2e4-ae9fd6e59e64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156920258 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2156920258 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1262984220 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2294664854 ps |
| CPU time | 257.51 seconds |
| Started | Jul 25 08:11:05 PM PDT 24 |
| Finished | Jul 25 08:15:23 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-18044a80-8125-4e1b-85a9-d217c195c95a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262984220 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1262984220 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.1580196342 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 3723223476 ps |
| CPU time | 640.43 seconds |
| Started | Jul 25 08:17:11 PM PDT 24 |
| Finished | Jul 25 08:27:52 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-36adbcd2-2728-424d-923b-3516d6a31a1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580196342 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.1580196342 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.4023359344 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4400230712 ps |
| CPU time | 516.55 seconds |
| Started | Jul 25 08:15:29 PM PDT 24 |
| Finished | Jul 25 08:24:06 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-3d5d6d21-49d9-4330-840a-d46c2e1a8b31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023359344 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.4023359344 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3224198213 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 12875719509 ps |
| CPU time | 1866.46 seconds |
| Started | Jul 25 08:08:35 PM PDT 24 |
| Finished | Jul 25 08:39:42 PM PDT 24 |
| Peak memory | 611836 kb |
| Host | smart-c925379f-050b-4ddf-81ff-d5bc9b6be91e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224 198213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3224198213 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3863366588 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 25882817089 ps |
| CPU time | 2259.49 seconds |
| Started | Jul 25 08:10:15 PM PDT 24 |
| Finished | Jul 25 08:47:55 PM PDT 24 |
| Peak memory | 611892 kb |
| Host | smart-50eb862b-5ce1-46c2-aa3d-10ba015f82be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386 3366588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.3863366588 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1854443514 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 17502065330 ps |
| CPU time | 1419.43 seconds |
| Started | Jul 25 08:05:43 PM PDT 24 |
| Finished | Jul 25 08:29:23 PM PDT 24 |
| Peak memory | 612148 kb |
| Host | smart-eb6194ea-f9b2-453d-a0ce-6f681f597573 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1854443514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1854443514 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768890125 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 23303796440 ps |
| CPU time | 1810.19 seconds |
| Started | Jul 25 08:13:24 PM PDT 24 |
| Finished | Jul 25 08:43:35 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-f7eca6c6-0bfb-413b-8c1d-fa1e88b6e04c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 768890125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768890125 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.400058234 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 9475900110 ps |
| CPU time | 619.18 seconds |
| Started | Jul 25 08:07:22 PM PDT 24 |
| Finished | Jul 25 08:17:42 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-9f47c744-244b-46ed-ad90-c7ed978e705a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400058234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.400058234 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2421196959 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 8112713824 ps |
| CPU time | 676.73 seconds |
| Started | Jul 25 08:07:05 PM PDT 24 |
| Finished | Jul 25 08:18:22 PM PDT 24 |
| Peak memory | 618324 kb |
| Host | smart-ad9d4ec8-1f5b-4f42-ae9b-67bd9e9e152b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2421196959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2421196959 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2112039141 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 6563165335 ps |
| CPU time | 416.07 seconds |
| Started | Jul 25 08:04:56 PM PDT 24 |
| Finished | Jul 25 08:11:52 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-0a5be1dd-33a8-4e18-a9cd-1c5fa4dfb85a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112039141 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2112039141 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1390276915 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 5114650629 ps |
| CPU time | 333.91 seconds |
| Started | Jul 25 08:06:58 PM PDT 24 |
| Finished | Jul 25 08:12:32 PM PDT 24 |
| Peak memory | 618252 kb |
| Host | smart-2faf32f4-8c5d-4e73-90c3-f995409a81bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1390276915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1390276915 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4012969236 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 13370237875 ps |
| CPU time | 1403.66 seconds |
| Started | Jul 25 08:05:37 PM PDT 24 |
| Finished | Jul 25 08:29:01 PM PDT 24 |
| Peak memory | 611948 kb |
| Host | smart-0e131b7d-1e3c-4d0a-ac9d-c2b7486b0d96 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012969236 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4012969236 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1164102782 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 7823520000 ps |
| CPU time | 407.11 seconds |
| Started | Jul 25 08:12:35 PM PDT 24 |
| Finished | Jul 25 08:19:23 PM PDT 24 |
| Peak memory | 611316 kb |
| Host | smart-210e3fe6-5332-44f0-8381-d404d32e5e82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164102782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1164102782 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.946206205 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7755083628 ps |
| CPU time | 711.5 seconds |
| Started | Jul 25 08:05:29 PM PDT 24 |
| Finished | Jul 25 08:17:21 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-5195f90d-a787-4da8-bb53-978b2ea4c636 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946206205 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.946206205 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3142886691 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 19095857868 ps |
| CPU time | 2166.15 seconds |
| Started | Jul 25 08:05:49 PM PDT 24 |
| Finished | Jul 25 08:41:56 PM PDT 24 |
| Peak memory | 611952 kb |
| Host | smart-bf408604-5c95-4ecf-ad53-d4a0b43548c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3142886691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3142886691 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4279355554 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 20812133772 ps |
| CPU time | 1535.49 seconds |
| Started | Jul 25 08:12:29 PM PDT 24 |
| Finished | Jul 25 08:38:05 PM PDT 24 |
| Peak memory | 611448 kb |
| Host | smart-555bf1d7-f98d-466f-9b67-a5cfdbd80cf3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4279355554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4279355554 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2606263486 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 35260062660 ps |
| CPU time | 2555.53 seconds |
| Started | Jul 25 08:06:36 PM PDT 24 |
| Finished | Jul 25 08:49:12 PM PDT 24 |
| Peak memory | 612736 kb |
| Host | smart-28daf2be-efbe-483c-9efd-f6a661b7dbae |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606263486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2606263486 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4023091823 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 6046679856 ps |
| CPU time | 484.74 seconds |
| Started | Jul 25 08:11:38 PM PDT 24 |
| Finished | Jul 25 08:19:43 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-5552bdb6-fca7-456a-99d3-efb600215c15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4023091823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.4023091823 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1899922785 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2918643472 ps |
| CPU time | 347.11 seconds |
| Started | Jul 25 08:07:32 PM PDT 24 |
| Finished | Jul 25 08:13:20 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-34901d31-887c-42a8-bd81-9d79ff407c9a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899922785 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.1899922785 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2678725532 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 5700805512 ps |
| CPU time | 464.92 seconds |
| Started | Jul 25 08:07:53 PM PDT 24 |
| Finished | Jul 25 08:15:38 PM PDT 24 |
| Peak memory | 617476 kb |
| Host | smart-05980d8c-1dd6-415a-9559-4dd915b75366 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2678725532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2678725532 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1662593031 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 6681246790 ps |
| CPU time | 625.9 seconds |
| Started | Jul 25 08:14:43 PM PDT 24 |
| Finished | Jul 25 08:25:09 PM PDT 24 |
| Peak memory | 611412 kb |
| Host | smart-d294ce21-d5f1-4a30-ab7f-64f257f489fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1662593031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1662593031 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1402614395 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5301972080 ps |
| CPU time | 329.01 seconds |
| Started | Jul 25 08:16:04 PM PDT 24 |
| Finished | Jul 25 08:21:33 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-58005de9-f81f-4adb-b2b7-b6c063119f51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402614395 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1402614395 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4134817915 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 7703147592 ps |
| CPU time | 1292.61 seconds |
| Started | Jul 25 08:08:16 PM PDT 24 |
| Finished | Jul 25 08:29:49 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-c2199d52-55f5-4bb7-a8fa-a2104c1c28c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134817915 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.4134817915 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2305122882 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 4647112778 ps |
| CPU time | 500.67 seconds |
| Started | Jul 25 08:06:01 PM PDT 24 |
| Finished | Jul 25 08:14:22 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-b00e473b-eaca-4fd7-bbd2-0ebce2b93caa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305122882 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2305122882 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.7070593 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6023187936 ps |
| CPU time | 395.95 seconds |
| Started | Jul 25 08:16:17 PM PDT 24 |
| Finished | Jul 25 08:22:54 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-1786736e-83ed-4c03-939a-bfb0ae959e48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7070593 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.7070593 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.898611088 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 5547828344 ps |
| CPU time | 497.45 seconds |
| Started | Jul 25 08:07:09 PM PDT 24 |
| Finished | Jul 25 08:15:27 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-12407273-fa1e-44f1-8b01-13ad2ade07e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898 611088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.898611088 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2809710172 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 9729009050 ps |
| CPU time | 527.39 seconds |
| Started | Jul 25 08:08:24 PM PDT 24 |
| Finished | Jul 25 08:17:12 PM PDT 24 |
| Peak memory | 625392 kb |
| Host | smart-e9a13c75-d932-4827-86e0-d58f1c0d5d0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809710172 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2809710172 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1578769492 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 14544202696 ps |
| CPU time | 1505.28 seconds |
| Started | Jul 25 08:05:30 PM PDT 24 |
| Finished | Jul 25 08:30:36 PM PDT 24 |
| Peak memory | 611436 kb |
| Host | smart-d37ce512-6fd3-467d-bdb3-044e77472fb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1578769492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1578769492 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4294638803 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5478137820 ps |
| CPU time | 655.58 seconds |
| Started | Jul 25 08:07:36 PM PDT 24 |
| Finished | Jul 25 08:18:32 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-b0ebd680-8eca-4519-8b97-4df19c85199a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294638803 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.4294638803 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3598937184 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 5724837750 ps |
| CPU time | 673.21 seconds |
| Started | Jul 25 08:03:17 PM PDT 24 |
| Finished | Jul 25 08:14:30 PM PDT 24 |
| Peak memory | 642016 kb |
| Host | smart-b674a14c-a312-46c6-85ac-0a8b90f2a9b7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3598937184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.3598937184 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2906226876 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2895974650 ps |
| CPU time | 296.41 seconds |
| Started | Jul 25 08:17:43 PM PDT 24 |
| Finished | Jul 25 08:22:40 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-071e40a1-de08-4771-a650-81ab3cc34b81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906226876 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.2906226876 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3906764749 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 4774862380 ps |
| CPU time | 566.21 seconds |
| Started | Jul 25 08:07:20 PM PDT 24 |
| Finished | Jul 25 08:16:47 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-9edff9d8-aea8-472c-aff1-e25f55e98327 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906764749 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3906764749 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1463826241 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3521253920 ps |
| CPU time | 217.55 seconds |
| Started | Jul 25 08:04:20 PM PDT 24 |
| Finished | Jul 25 08:07:58 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-1364cdc0-11a8-4f6a-b6b7-f807e0226940 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463826241 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.1463826241 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.181188496 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2905266040 ps |
| CPU time | 320.54 seconds |
| Started | Jul 25 08:12:45 PM PDT 24 |
| Finished | Jul 25 08:18:06 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-4b4391c3-9213-4e9a-9227-be31ef2fbf44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=181188496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.181188496 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1353796166 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2795180823 ps |
| CPU time | 344.68 seconds |
| Started | Jul 25 08:12:46 PM PDT 24 |
| Finished | Jul 25 08:18:31 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-0646b08e-8f31-45a8-93f2-3255adf6a01c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353796166 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1353796166 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4035416681 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2946226780 ps |
| CPU time | 279.98 seconds |
| Started | Jul 25 08:12:57 PM PDT 24 |
| Finished | Jul 25 08:17:38 PM PDT 24 |
| Peak memory | 618108 kb |
| Host | smart-af1c6701-a2be-46fb-9e15-44a9da328566 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035416681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.4035416681 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.200077967 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 4544215908 ps |
| CPU time | 1020.49 seconds |
| Started | Jul 25 08:09:42 PM PDT 24 |
| Finished | Jul 25 08:26:43 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-11c1be39-ded3-42c5-a6c7-ada024fab059 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20007 7967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.200077967 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3158867440 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 5373700850 ps |
| CPU time | 975.67 seconds |
| Started | Jul 25 08:08:03 PM PDT 24 |
| Finished | Jul 25 08:24:19 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-b4f6e625-ef78-42e4-bf8c-f6858aa351fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3158867440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3158867440 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1709348789 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 6126075210 ps |
| CPU time | 596.16 seconds |
| Started | Jul 25 08:12:03 PM PDT 24 |
| Finished | Jul 25 08:22:00 PM PDT 24 |
| Peak memory | 624964 kb |
| Host | smart-7464843d-1348-4b83-bace-cb5e90905380 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709348789 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1709348789 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.937304826 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 6095517440 ps |
| CPU time | 424.8 seconds |
| Started | Jul 25 08:11:56 PM PDT 24 |
| Finished | Jul 25 08:19:01 PM PDT 24 |
| Peak memory | 621156 kb |
| Host | smart-c3aea36b-aa0f-4518-b89d-6619383e2f6d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937304826 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.937304826 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1047064397 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4136901192 ps |
| CPU time | 556.14 seconds |
| Started | Jul 25 08:12:41 PM PDT 24 |
| Finished | Jul 25 08:21:58 PM PDT 24 |
| Peak memory | 619568 kb |
| Host | smart-8bfac47e-d8bf-4a9e-8226-661581451fa0 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104706 4397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1047064397 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.125246836 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2666140664 ps |
| CPU time | 236.24 seconds |
| Started | Jul 25 08:17:55 PM PDT 24 |
| Finished | Jul 25 08:21:52 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-523351b9-311c-4073-8a70-7e1d638b6be1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125246836 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.125246836 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.682717910 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 2776800140 ps |
| CPU time | 222.46 seconds |
| Started | Jul 25 08:06:30 PM PDT 24 |
| Finished | Jul 25 08:10:13 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-b90b2867-6218-49c5-ba68-7359fbd79c70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682717910 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_irq.682717910 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2799009802 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 3432494244 ps |
| CPU time | 227.05 seconds |
| Started | Jul 25 08:17:17 PM PDT 24 |
| Finished | Jul 25 08:21:05 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-588c727f-d8ea-4934-a172-8b849fcb4f59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799009802 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2799009802 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1191395439 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2207577674 ps |
| CPU time | 225.98 seconds |
| Started | Jul 25 08:11:11 PM PDT 24 |
| Finished | Jul 25 08:14:58 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-8f8a4f64-b5c8-4461-aa65-26add3b6d281 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191395 439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1191395439 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.462571727 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3977850480 ps |
| CPU time | 317.47 seconds |
| Started | Jul 25 08:05:55 PM PDT 24 |
| Finished | Jul 25 08:11:13 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-15de0fbd-abfe-4f28-9ded-9578d9b5de1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462571727 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.462571727 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4094546119 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 8297757588 ps |
| CPU time | 1529.52 seconds |
| Started | Jul 25 08:06:21 PM PDT 24 |
| Finished | Jul 25 08:31:51 PM PDT 24 |
| Peak memory | 611392 kb |
| Host | smart-a6d9ff2d-43c5-4137-a8c9-2390b1d4c265 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094546119 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4094546119 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.150561190 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 7426092956 ps |
| CPU time | 746.52 seconds |
| Started | Jul 25 08:17:57 PM PDT 24 |
| Finished | Jul 25 08:30:24 PM PDT 24 |
| Peak memory | 611276 kb |
| Host | smart-d40c432d-6e28-46cf-9404-883554c6bba0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150561190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.150561190 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2467962987 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 8291326870 ps |
| CPU time | 820.11 seconds |
| Started | Jul 25 08:10:20 PM PDT 24 |
| Finished | Jul 25 08:24:01 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-4c3910f2-1c43-4d67-9047-bb06aff22199 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467962987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.2467962987 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2077466399 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5335817646 ps |
| CPU time | 559.06 seconds |
| Started | Jul 25 08:05:49 PM PDT 24 |
| Finished | Jul 25 08:15:08 PM PDT 24 |
| Peak memory | 625560 kb |
| Host | smart-99eb20d7-94c2-4175-b012-6a9ae69b4969 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077466399 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2077466399 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.257106847 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4628171968 ps |
| CPU time | 595.91 seconds |
| Started | Jul 25 08:05:13 PM PDT 24 |
| Finished | Jul 25 08:15:09 PM PDT 24 |
| Peak memory | 625532 kb |
| Host | smart-efe48c89-4d8d-42bd-ace0-004d91133ea4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257106847 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.257106847 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1792145818 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3827972410 ps |
| CPU time | 439.22 seconds |
| Started | Jul 25 08:07:14 PM PDT 24 |
| Finished | Jul 25 08:14:33 PM PDT 24 |
| Peak memory | 620308 kb |
| Host | smart-c9e05a12-e017-4064-9de5-f648317fb271 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792145818 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1792145818 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2718984780 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3405076456 ps |
| CPU time | 306.06 seconds |
| Started | Jul 25 08:05:13 PM PDT 24 |
| Finished | Jul 25 08:10:19 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-46b35deb-8da0-49f3-ab27-3c39edb7ea17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718984780 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2718984780 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3986524140 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 6265604236 ps |
| CPU time | 704.1 seconds |
| Started | Jul 25 08:12:04 PM PDT 24 |
| Finished | Jul 25 08:23:49 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-3651e148-ead9-4f2d-a1d6-0126799e6159 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986524140 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3986524140 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1363776129 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 4951191812 ps |
| CPU time | 836.75 seconds |
| Started | Jul 25 08:16:19 PM PDT 24 |
| Finished | Jul 25 08:30:17 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-fd054a0f-7bd6-4522-92b6-1644f9a10e58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363776129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1363776129 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219503727 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4444429337 ps |
| CPU time | 746.2 seconds |
| Started | Jul 25 08:16:30 PM PDT 24 |
| Finished | Jul 25 08:28:59 PM PDT 24 |
| Peak memory | 611648 kb |
| Host | smart-02bc7c4a-45bd-4bbc-9886-94085f0c6c38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219503727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219503727 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2194833045 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4722547199 ps |
| CPU time | 631.45 seconds |
| Started | Jul 25 08:15:39 PM PDT 24 |
| Finished | Jul 25 08:26:10 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-93b0c01f-49ee-43ff-855f-e0320b408488 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194833045 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2194833045 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4055235852 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 3341764612 ps |
| CPU time | 285.77 seconds |
| Started | Jul 25 08:15:55 PM PDT 24 |
| Finished | Jul 25 08:20:41 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-d012f2b3-b432-4a72-ba4a-5da072a106e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055235852 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.4055235852 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4030150378 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 20070347511 ps |
| CPU time | 4239.73 seconds |
| Started | Jul 25 08:07:59 PM PDT 24 |
| Finished | Jul 25 09:18:40 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-2963051f-ffb9-478e-a0f5-8ffe986bbb41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030150378 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.4030150378 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.524100850 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 4890499863 ps |
| CPU time | 690.31 seconds |
| Started | Jul 25 08:09:37 PM PDT 24 |
| Finished | Jul 25 08:21:10 PM PDT 24 |
| Peak memory | 614528 kb |
| Host | smart-5091fa26-0a25-4255-b4ad-dbda813798f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524100850 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.524100850 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3611860640 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2906874558 ps |
| CPU time | 326.54 seconds |
| Started | Jul 25 08:07:39 PM PDT 24 |
| Finished | Jul 25 08:13:07 PM PDT 24 |
| Peak memory | 614112 kb |
| Host | smart-ab7bacb9-166d-4d64-9251-1fe4074e17e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611860640 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3611860640 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.36128806 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 21936315636 ps |
| CPU time | 1755.25 seconds |
| Started | Jul 25 08:08:53 PM PDT 24 |
| Finished | Jul 25 08:38:09 PM PDT 24 |
| Peak memory | 615616 kb |
| Host | smart-95ccd10d-715c-450c-9d10-a1c5896acbd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36128806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.36128806 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2403162268 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6621218598 ps |
| CPU time | 521.05 seconds |
| Started | Jul 25 08:06:34 PM PDT 24 |
| Finished | Jul 25 08:15:15 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-16e6d1d0-048b-4a0d-b37a-b9e809876565 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403162268 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2403162268 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3843540050 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 7986529604 ps |
| CPU time | 1673.47 seconds |
| Started | Jul 25 08:04:11 PM PDT 24 |
| Finished | Jul 25 08:32:05 PM PDT 24 |
| Peak memory | 619568 kb |
| Host | smart-e6a60485-badb-4809-8ced-716c96a2d375 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3843540050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.3843540050 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.2672045376 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 3031570600 ps |
| CPU time | 337.92 seconds |
| Started | Jul 25 08:18:19 PM PDT 24 |
| Finished | Jul 25 08:23:57 PM PDT 24 |
| Peak memory | 617732 kb |
| Host | smart-aefb94d8-bdf4-4c8e-8b49-669250f35ff7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672045376 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.2672045376 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.539472843 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4272427368 ps |
| CPU time | 615.45 seconds |
| Started | Jul 25 08:05:17 PM PDT 24 |
| Finished | Jul 25 08:15:33 PM PDT 24 |
| Peak memory | 625408 kb |
| Host | smart-ce09a899-a90a-439b-afce-527058a7a9ae |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539472843 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.539472843 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2897003159 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 8756382252 ps |
| CPU time | 1992.78 seconds |
| Started | Jul 25 08:06:56 PM PDT 24 |
| Finished | Jul 25 08:40:10 PM PDT 24 |
| Peak memory | 624000 kb |
| Host | smart-17fd17bd-8f17-439a-813b-e7b1927b70dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897003159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2897003159 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1622656816 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 4866147577 ps |
| CPU time | 479.02 seconds |
| Started | Jul 25 08:05:15 PM PDT 24 |
| Finished | Jul 25 08:13:14 PM PDT 24 |
| Peak memory | 619540 kb |
| Host | smart-9c55f12c-97d4-4052-aa2e-e95aa8ade1f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622656816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1622656816 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3659165086 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 78212814537 ps |
| CPU time | 14424.1 seconds |
| Started | Jul 25 08:04:43 PM PDT 24 |
| Finished | Jul 26 12:05:09 AM PDT 24 |
| Peak memory | 636692 kb |
| Host | smart-295d16dd-b778-4841-9ab7-eed635ffe004 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3659165086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3659165086 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2238718464 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 4642981816 ps |
| CPU time | 663.35 seconds |
| Started | Jul 25 08:04:57 PM PDT 24 |
| Finished | Jul 25 08:16:01 PM PDT 24 |
| Peak memory | 625388 kb |
| Host | smart-c6236617-cb09-407d-a18f-64d83c8587a7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238718464 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2238718464 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1898522660 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 4358195520 ps |
| CPU time | 644.42 seconds |
| Started | Jul 25 08:02:34 PM PDT 24 |
| Finished | Jul 25 08:13:20 PM PDT 24 |
| Peak memory | 625428 kb |
| Host | smart-812dd867-106f-40bf-bc98-e1a209e31804 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898522660 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1898522660 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1393225100 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 4108099176 ps |
| CPU time | 643.64 seconds |
| Started | Jul 25 08:04:27 PM PDT 24 |
| Finished | Jul 25 08:15:11 PM PDT 24 |
| Peak memory | 625404 kb |
| Host | smart-a1f19fbb-8e92-4027-89cb-af515cbfb2d0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393225100 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1393225100 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.2542766826 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 6860760767 ps |
| CPU time | 660.89 seconds |
| Started | Jul 25 08:13:32 PM PDT 24 |
| Finished | Jul 25 08:24:33 PM PDT 24 |
| Peak memory | 621708 kb |
| Host | smart-ddd2ce47-8ed4-4f71-b55f-3c396ec80772 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2542766826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.2542766826 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1672884191 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2691132559 ps |
| CPU time | 153.25 seconds |
| Started | Jul 25 08:11:53 PM PDT 24 |
| Finished | Jul 25 08:14:26 PM PDT 24 |
| Peak memory | 622244 kb |
| Host | smart-13b1becd-b8b8-47a7-94ff-fac8af036266 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672884191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1672884191 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.2655868256 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4807671270 ps |
| CPU time | 495.2 seconds |
| Started | Jul 25 08:13:04 PM PDT 24 |
| Finished | Jul 25 08:21:20 PM PDT 24 |
| Peak memory | 624996 kb |
| Host | smart-a5524cf0-2132-4eb3-a305-830b2ed27e24 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655868256 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.2655868256 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.4289697576 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 10004479980 ps |
| CPU time | 1206.76 seconds |
| Started | Jul 25 08:11:31 PM PDT 24 |
| Finished | Jul 25 08:31:38 PM PDT 24 |
| Peak memory | 624964 kb |
| Host | smart-053e263f-950f-4c28-9576-327b91b4be18 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289697576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.4289697576 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.207095409 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 14835115515 ps |
| CPU time | 3399.68 seconds |
| Started | Jul 25 08:21:40 PM PDT 24 |
| Finished | Jul 25 09:18:20 PM PDT 24 |
| Peak memory | 611544 kb |
| Host | smart-66d66251-0185-46d6-8f0e-999601626aee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207095409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.207095409 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.142978205 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 15700601588 ps |
| CPU time | 3498.97 seconds |
| Started | Jul 25 08:20:15 PM PDT 24 |
| Finished | Jul 25 09:18:35 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-b2cbc729-f679-48cc-9a4a-d04665ded00f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142978205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.142978205 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.3669358993 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 15443236101 ps |
| CPU time | 3290.83 seconds |
| Started | Jul 25 08:19:44 PM PDT 24 |
| Finished | Jul 25 09:14:36 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-3257a23e-a6d3-4b7c-b9d7-3cb6e7c5a1cc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669358993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.3669358993 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1377743967 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 11150676988 ps |
| CPU time | 2534.27 seconds |
| Started | Jul 25 08:22:01 PM PDT 24 |
| Finished | Jul 25 09:04:16 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-1fc96f07-fa05-4b2d-8015-468554f26d1d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377743967 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1377743967 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1863746132 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 15148770182 ps |
| CPU time | 3722.49 seconds |
| Started | Jul 25 08:20:19 PM PDT 24 |
| Finished | Jul 25 09:22:22 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-f1589bac-261d-44dc-8c39-6bbc30bd1fe5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863746132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1863746132 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3202541765 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 14975601300 ps |
| CPU time | 4169.82 seconds |
| Started | Jul 25 08:21:09 PM PDT 24 |
| Finished | Jul 25 09:30:39 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-6b21ea6e-855b-4339-971d-21ac9f8e2333 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202541765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.3202541765 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.510719065 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 15351977380 ps |
| CPU time | 4033.44 seconds |
| Started | Jul 25 08:22:18 PM PDT 24 |
| Finished | Jul 25 09:29:32 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-6e528308-4b63-4ada-9500-deb90f44edc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510719065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.510719065 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.1122971279 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 26732181712 ps |
| CPU time | 6006.28 seconds |
| Started | Jul 25 08:19:18 PM PDT 24 |
| Finished | Jul 25 09:59:25 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-3b854a3d-f231-46e9-8389-7d0b68ea979c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122971279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.1122971279 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2715127118 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15160044026 ps |
| CPU time | 3169.87 seconds |
| Started | Jul 25 08:20:25 PM PDT 24 |
| Finished | Jul 25 09:13:15 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-9078683b-82c4-4259-86fd-64789faa982f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715127118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2715127118 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.4074667974 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 28356788243 ps |
| CPU time | 5282.74 seconds |
| Started | Jul 25 08:21:43 PM PDT 24 |
| Finished | Jul 25 09:49:47 PM PDT 24 |
| Peak memory | 612648 kb |
| Host | smart-9064fea5-0f85-435d-837b-ed6793336ff3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074667974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.4074667974 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.1709579819 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 14907152042 ps |
| CPU time | 4208.95 seconds |
| Started | Jul 25 08:22:00 PM PDT 24 |
| Finished | Jul 25 09:32:09 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-6641d0f7-ec58-48b3-8ac0-2442b9b0cb35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1709579819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.1709579819 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.564126612 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 16634231480 ps |
| CPU time | 3931.25 seconds |
| Started | Jul 25 08:20:50 PM PDT 24 |
| Finished | Jul 25 09:26:22 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-bc304ce2-9a8b-4a87-98f0-0a38ca61367b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564126612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.564126612 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.639139655 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 4889255176 ps |
| CPU time | 463.55 seconds |
| Started | Jul 25 08:15:42 PM PDT 24 |
| Finished | Jul 25 08:23:25 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-92d43699-6b43-4fd7-89b3-f0053b291134 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639139655 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.639139655 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.10730444 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 6172223273 ps |
| CPU time | 307.05 seconds |
| Started | Jul 25 08:17:00 PM PDT 24 |
| Finished | Jul 25 08:22:08 PM PDT 24 |
| Peak memory | 623860 kb |
| Host | smart-e5960ba4-ab03-4175-920b-879d9bd7e15e |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=10730444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.10730444 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.1153758600 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 3247174504 ps |
| CPU time | 123.6 seconds |
| Started | Jul 25 08:16:01 PM PDT 24 |
| Finished | Jul 25 08:18:04 PM PDT 24 |
| Peak memory | 618700 kb |
| Host | smart-b93dd304-6016-4f6b-9dc0-383ed764618c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153758600 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1153758600 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.127077591 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 12348104642 ps |
| CPU time | 951.47 seconds |
| Started | Jul 25 08:30:10 PM PDT 24 |
| Finished | Jul 25 08:46:02 PM PDT 24 |
| Peak memory | 621544 kb |
| Host | smart-8c03bd7d-fb66-472f-958c-e441227f8783 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127077591 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.127077591 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3805681117 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 8494633336 ps |
| CPU time | 1186.22 seconds |
| Started | Jul 25 08:29:11 PM PDT 24 |
| Finished | Jul 25 08:48:57 PM PDT 24 |
| Peak memory | 619832 kb |
| Host | smart-90db5171-564e-4c8d-8f4d-bac7e3c77389 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3805681117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3805681117 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.735477911 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3232429640 ps |
| CPU time | 362.39 seconds |
| Started | Jul 25 08:29:50 PM PDT 24 |
| Finished | Jul 25 08:35:52 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-05a903b0-8523-423a-88d9-94c9fb27f8d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735477911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.735477911 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.2739813975 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5373404472 ps |
| CPU time | 692.81 seconds |
| Started | Jul 25 08:30:38 PM PDT 24 |
| Finished | Jul 25 08:42:11 PM PDT 24 |
| Peak memory | 620400 kb |
| Host | smart-5f626e84-41e8-4a7c-bed9-f398205b5b9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2739813975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.2739813975 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2073668154 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 8972731825 ps |
| CPU time | 913.29 seconds |
| Started | Jul 25 08:29:28 PM PDT 24 |
| Finished | Jul 25 08:44:42 PM PDT 24 |
| Peak memory | 621120 kb |
| Host | smart-3130c9d7-a10f-4991-9464-1efbd227afd4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073668154 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2073668154 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1809470267 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 13012209074 ps |
| CPU time | 2761.67 seconds |
| Started | Jul 25 08:29:14 PM PDT 24 |
| Finished | Jul 25 09:15:16 PM PDT 24 |
| Peak memory | 619648 kb |
| Host | smart-0c1c9b1c-d1db-408a-9065-f0502b3bee05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1809470267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1809470267 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2651008810 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 12908452880 ps |
| CPU time | 713.99 seconds |
| Started | Jul 25 08:30:25 PM PDT 24 |
| Finished | Jul 25 08:42:19 PM PDT 24 |
| Peak memory | 621952 kb |
| Host | smart-02951f50-6264-4b36-b14f-72cc9b20821e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651008810 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2651008810 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2613200895 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4285568888 ps |
| CPU time | 608.72 seconds |
| Started | Jul 25 08:31:08 PM PDT 24 |
| Finished | Jul 25 08:41:17 PM PDT 24 |
| Peak memory | 619528 kb |
| Host | smart-4de5b668-7acf-4da6-8f3f-827da7cfd136 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2613200895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.2613200895 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1600833766 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 11325815513 ps |
| CPU time | 752.71 seconds |
| Started | Jul 25 08:29:12 PM PDT 24 |
| Finished | Jul 25 08:41:45 PM PDT 24 |
| Peak memory | 621504 kb |
| Host | smart-a628e804-c074-42c2-9993-ebffe5d1c281 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600833766 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.1600833766 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.674678352 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 4721176054 ps |
| CPU time | 710.27 seconds |
| Started | Jul 25 08:30:23 PM PDT 24 |
| Finished | Jul 25 08:42:14 PM PDT 24 |
| Peak memory | 623820 kb |
| Host | smart-40b77162-812d-4cdb-845c-a0fbde0a82b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=674678352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.674678352 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3823073845 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3979519944 ps |
| CPU time | 376.81 seconds |
| Started | Jul 25 08:30:13 PM PDT 24 |
| Finished | Jul 25 08:36:30 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-4e87afa4-89f9-4914-b3ef-4d84fbbf1d9f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823073845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3823073845 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3111908041 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 7279356247 ps |
| CPU time | 546.96 seconds |
| Started | Jul 25 08:30:06 PM PDT 24 |
| Finished | Jul 25 08:39:14 PM PDT 24 |
| Peak memory | 621136 kb |
| Host | smart-5de2faf0-76ad-423e-888a-2b4b1508c119 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111908041 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3111908041 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1163761383 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 8274115190 ps |
| CPU time | 1406.9 seconds |
| Started | Jul 25 08:31:25 PM PDT 24 |
| Finished | Jul 25 08:54:53 PM PDT 24 |
| Peak memory | 619544 kb |
| Host | smart-1e696148-3fde-4698-9c08-cc89e3e78020 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1163761383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1163761383 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3913159029 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 3257184984 ps |
| CPU time | 501.34 seconds |
| Started | Jul 25 08:29:39 PM PDT 24 |
| Finished | Jul 25 08:38:00 PM PDT 24 |
| Peak memory | 619536 kb |
| Host | smart-17705afe-d7d4-430a-b7b0-71389b0146e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3913159029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3913159029 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2457745755 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 3754529350 ps |
| CPU time | 429.81 seconds |
| Started | Jul 25 08:31:33 PM PDT 24 |
| Finished | Jul 25 08:38:43 PM PDT 24 |
| Peak memory | 619312 kb |
| Host | smart-12fd5973-98b4-47a6-894b-9d095b0d7854 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457745755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2457745755 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3067671050 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5713373176 ps |
| CPU time | 681.46 seconds |
| Started | Jul 25 08:31:29 PM PDT 24 |
| Finished | Jul 25 08:42:51 PM PDT 24 |
| Peak memory | 650668 kb |
| Host | smart-55aa2a49-a633-431b-8f4d-419867393945 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3067671050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3067671050 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1408988755 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4471003560 ps |
| CPU time | 621.8 seconds |
| Started | Jul 25 08:30:21 PM PDT 24 |
| Finished | Jul 25 08:40:43 PM PDT 24 |
| Peak memory | 619824 kb |
| Host | smart-696aac3f-2502-4857-b68b-e85982b5544e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1408988755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1408988755 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3795850232 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 13171310750 ps |
| CPU time | 2560.45 seconds |
| Started | Jul 25 08:32:13 PM PDT 24 |
| Finished | Jul 25 09:14:54 PM PDT 24 |
| Peak memory | 619576 kb |
| Host | smart-3c2b5bd5-4a90-49dc-9618-26869e09e240 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3795850232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3795850232 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069334111 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3843811480 ps |
| CPU time | 493.48 seconds |
| Started | Jul 25 08:30:32 PM PDT 24 |
| Finished | Jul 25 08:38:45 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-835e3eba-d65e-47f3-ad20-32b66b9c2815 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069334111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4069334111 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.523154701 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 4796548136 ps |
| CPU time | 627.02 seconds |
| Started | Jul 25 08:30:21 PM PDT 24 |
| Finished | Jul 25 08:40:49 PM PDT 24 |
| Peak memory | 650632 kb |
| Host | smart-9324e6b5-03f1-46ce-af75-62578bf1acf8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 523154701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.523154701 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4211882970 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 4818447450 ps |
| CPU time | 760.45 seconds |
| Started | Jul 25 08:32:04 PM PDT 24 |
| Finished | Jul 25 08:44:45 PM PDT 24 |
| Peak memory | 619804 kb |
| Host | smart-eca511f5-75b9-4b51-9369-6c33ad8efa6e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4211882970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.4211882970 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1588924135 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13642895532 ps |
| CPU time | 1671.5 seconds |
| Started | Jul 25 08:15:46 PM PDT 24 |
| Finished | Jul 25 08:43:38 PM PDT 24 |
| Peak memory | 608432 kb |
| Host | smart-b6a5ad7e-75fd-45b2-9cf3-6139f9f27e4a |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588924135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 588924135 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1553061746 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 4499049174 ps |
| CPU time | 405.85 seconds |
| Started | Jul 25 08:26:49 PM PDT 24 |
| Finished | Jul 25 08:33:36 PM PDT 24 |
| Peak memory | 621384 kb |
| Host | smart-c480def9-b1fc-4abb-9ca9-fe667ed74bbb |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 553061746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.1553061746 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1681985203 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 2861914328 ps |
| CPU time | 326.85 seconds |
| Started | Jul 25 08:17:41 PM PDT 24 |
| Finished | Jul 25 08:23:08 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-17909107-ac6a-419f-a797-bf5fce8f1f6b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1681985203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1681985203 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2099567834 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 18687993080 ps |
| CPU time | 479.03 seconds |
| Started | Jul 25 08:20:08 PM PDT 24 |
| Finished | Jul 25 08:28:07 PM PDT 24 |
| Peak memory | 619828 kb |
| Host | smart-24e34782-8fb9-46ec-ba76-192fad3125fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2099567834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2099567834 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.2539114188 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2993047460 ps |
| CPU time | 248.24 seconds |
| Started | Jul 25 08:19:35 PM PDT 24 |
| Finished | Jul 25 08:23:43 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-2476fc55-743d-4fa1-ae9e-5cfee14b9430 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539114188 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2539114188 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1178027439 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 3182031683 ps |
| CPU time | 330.08 seconds |
| Started | Jul 25 08:18:52 PM PDT 24 |
| Finished | Jul 25 08:24:22 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-47df9472-599f-4621-9c02-23534ca82f13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178 027439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1178027439 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3720262090 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2856703618 ps |
| CPU time | 271.32 seconds |
| Started | Jul 25 08:24:04 PM PDT 24 |
| Finished | Jul 25 08:28:35 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-1a38a25a-0e2d-4fb4-9279-bbe42dbf6642 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720262090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3720262090 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3262773252 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3076788956 ps |
| CPU time | 329.64 seconds |
| Started | Jul 25 08:21:14 PM PDT 24 |
| Finished | Jul 25 08:26:44 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-4dc459bb-3e4f-4564-9ebb-ec1f535bd33e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262773252 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3262773252 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.4097596810 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 2716349856 ps |
| CPU time | 191.45 seconds |
| Started | Jul 25 08:20:11 PM PDT 24 |
| Finished | Jul 25 08:23:22 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-2007ac72-dc39-458e-bd72-15fbcd1278c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097596810 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.4097596810 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.2580536038 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 2882866879 ps |
| CPU time | 288.02 seconds |
| Started | Jul 25 08:20:26 PM PDT 24 |
| Finished | Jul 25 08:25:14 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-e537334f-461a-406e-848e-fd13ddf13854 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580536038 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2580536038 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.2202442832 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 3604348650 ps |
| CPU time | 304.97 seconds |
| Started | Jul 25 08:24:23 PM PDT 24 |
| Finished | Jul 25 08:29:28 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-ae20eaf0-11c6-4e90-8f4c-310e74faeac7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202442832 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.2202442832 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1764535702 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2820129977 ps |
| CPU time | 372 seconds |
| Started | Jul 25 08:19:26 PM PDT 24 |
| Finished | Jul 25 08:25:39 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-f35e97bf-a064-421f-bfa1-c192949015fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1764535702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1764535702 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.535726722 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6087027098 ps |
| CPU time | 753.17 seconds |
| Started | Jul 25 08:20:15 PM PDT 24 |
| Finished | Jul 25 08:32:48 PM PDT 24 |
| Peak memory | 624372 kb |
| Host | smart-9a96dd04-fa2b-425c-8d3d-2c66456273e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=535726722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.535726722 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.252935744 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 8511334362 ps |
| CPU time | 1862.48 seconds |
| Started | Jul 25 08:20:46 PM PDT 24 |
| Finished | Jul 25 08:51:49 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-017be51a-6ad0-4bca-b802-23f2a6a61e87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=252935744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.252935744 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3518794270 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8445132050 ps |
| CPU time | 1772.75 seconds |
| Started | Jul 25 08:21:08 PM PDT 24 |
| Finished | Jul 25 08:50:41 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-ba2378c3-83bc-4726-b776-a9a492866697 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518794270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.3518794270 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3764658432 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 11881712396 ps |
| CPU time | 1454.65 seconds |
| Started | Jul 25 08:21:33 PM PDT 24 |
| Finished | Jul 25 08:45:48 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-921cf410-fa6d-4864-845e-eb14ca63623d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764658432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3764658432 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.4177868894 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 8387279518 ps |
| CPU time | 1531.03 seconds |
| Started | Jul 25 08:22:02 PM PDT 24 |
| Finished | Jul 25 08:47:34 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-81f7ce6f-c802-43fc-858e-91ea6a22127a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4177868894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.4177868894 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3862862308 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4571620576 ps |
| CPU time | 599.24 seconds |
| Started | Jul 25 08:21:08 PM PDT 24 |
| Finished | Jul 25 08:31:07 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-e5162c74-70e4-42a9-88c5-1274c1269a02 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3862862308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3862862308 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1197427862 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 256373631706 ps |
| CPU time | 11213.6 seconds |
| Started | Jul 25 08:20:14 PM PDT 24 |
| Finished | Jul 25 11:27:09 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-3b7d4245-8c0e-462c-99c5-e9faeb089dcc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197427862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1197427862 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.1964834066 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3063585496 ps |
| CPU time | 354.72 seconds |
| Started | Jul 25 08:24:02 PM PDT 24 |
| Finished | Jul 25 08:29:57 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-e1c02ae9-4053-48ce-b048-579f19936116 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964834066 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.1964834066 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.1797482449 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3951993372 ps |
| CPU time | 445.73 seconds |
| Started | Jul 25 08:18:59 PM PDT 24 |
| Finished | Jul 25 08:26:26 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-6f53adcf-ab71-4eae-b7f9-d157a830451f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797482449 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1797482449 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3342200926 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 7697693116 ps |
| CPU time | 649.27 seconds |
| Started | Jul 25 08:20:14 PM PDT 24 |
| Finished | Jul 25 08:31:04 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-cea37bb3-39b7-4712-ab3e-f7e8a7cd2d81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3342200926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3342200926 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3581161423 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 2858398832 ps |
| CPU time | 308.04 seconds |
| Started | Jul 25 08:25:00 PM PDT 24 |
| Finished | Jul 25 08:30:08 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-89ca4520-def7-471b-8d49-9bf72f9dfb5f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581161423 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3581161423 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1012979951 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 8643036712 ps |
| CPU time | 905.25 seconds |
| Started | Jul 25 08:21:28 PM PDT 24 |
| Finished | Jul 25 08:36:33 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-881de495-806d-4940-8192-fcaa8ab56d75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1012979951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1012979951 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.244700040 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 5177850600 ps |
| CPU time | 781.26 seconds |
| Started | Jul 25 08:18:56 PM PDT 24 |
| Finished | Jul 25 08:31:57 PM PDT 24 |
| Peak memory | 611232 kb |
| Host | smart-fe75f150-db14-48c5-b706-3efb4465a8a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =244700040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.244700040 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1919246599 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 7909213516 ps |
| CPU time | 972.63 seconds |
| Started | Jul 25 08:23:48 PM PDT 24 |
| Finished | Jul 25 08:40:01 PM PDT 24 |
| Peak memory | 617900 kb |
| Host | smart-c43847f3-2af5-460d-8f4f-153c73631966 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919246599 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1919246599 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4255307055 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 27112151795 ps |
| CPU time | 4032.47 seconds |
| Started | Jul 25 08:25:03 PM PDT 24 |
| Finished | Jul 25 09:32:16 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-34f2d1b5-ff5f-4391-9d92-3e85b869fac2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255307055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.4255307055 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1555992600 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 12696650036 ps |
| CPU time | 1003.14 seconds |
| Started | Jul 25 08:22:55 PM PDT 24 |
| Finished | Jul 25 08:39:39 PM PDT 24 |
| Peak memory | 621904 kb |
| Host | smart-29e8a718-cc53-44af-a4a2-a579c109b616 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1555992600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1555992600 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3027146143 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4254865392 ps |
| CPU time | 600.05 seconds |
| Started | Jul 25 08:23:43 PM PDT 24 |
| Finished | Jul 25 08:33:43 PM PDT 24 |
| Peak memory | 612712 kb |
| Host | smart-eca4868b-c477-4217-a92d-51cdd386fffc |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027146143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3027146143 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1368102834 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4176619114 ps |
| CPU time | 690.88 seconds |
| Started | Jul 25 08:22:38 PM PDT 24 |
| Finished | Jul 25 08:34:09 PM PDT 24 |
| Peak memory | 612704 kb |
| Host | smart-5d7daaa2-b970-4a9e-b272-75e2b3c99b9e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368102834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1368102834 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1058719140 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 4101448664 ps |
| CPU time | 720.38 seconds |
| Started | Jul 25 08:23:20 PM PDT 24 |
| Finished | Jul 25 08:35:21 PM PDT 24 |
| Peak memory | 613560 kb |
| Host | smart-02920447-3800-402c-88f8-3f82ed197b91 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058719140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1058719140 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1222649045 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4451275590 ps |
| CPU time | 602.06 seconds |
| Started | Jul 25 08:23:15 PM PDT 24 |
| Finished | Jul 25 08:33:18 PM PDT 24 |
| Peak memory | 613464 kb |
| Host | smart-26eedc17-85ea-4db5-b94b-ec9f4e9d0650 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222649045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1222649045 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1070972227 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 4538487690 ps |
| CPU time | 594.44 seconds |
| Started | Jul 25 08:21:53 PM PDT 24 |
| Finished | Jul 25 08:31:48 PM PDT 24 |
| Peak memory | 612804 kb |
| Host | smart-bba7ac52-ac5b-4cea-ad13-22ee2b533c2f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070972227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1070972227 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.531496346 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4163340628 ps |
| CPU time | 757.3 seconds |
| Started | Jul 25 08:22:38 PM PDT 24 |
| Finished | Jul 25 08:35:15 PM PDT 24 |
| Peak memory | 613832 kb |
| Host | smart-62d9932c-357d-4bcc-8d61-c9bb86c8b0ab |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531496346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.531496346 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.340107758 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 3099362490 ps |
| CPU time | 190.27 seconds |
| Started | Jul 25 08:25:36 PM PDT 24 |
| Finished | Jul 25 08:28:47 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-45cc2e98-4a20-4dda-aa29-3f0431f5ebf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340107758 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_clkmgr_jitter.340107758 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3179703620 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 2985614188 ps |
| CPU time | 458.17 seconds |
| Started | Jul 25 08:27:56 PM PDT 24 |
| Finished | Jul 25 08:35:36 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-0bb32a84-1685-4a53-b430-4663c798ed80 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179703620 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3179703620 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.217422567 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3542096336 ps |
| CPU time | 241.47 seconds |
| Started | Jul 25 08:23:19 PM PDT 24 |
| Finished | Jul 25 08:27:21 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-91a1eb77-6dca-459b-8113-a2699c17f6fd |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217422567 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.217422567 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3300269027 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 4749344940 ps |
| CPU time | 465.84 seconds |
| Started | Jul 25 08:25:20 PM PDT 24 |
| Finished | Jul 25 08:33:07 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-a6cf8d6a-e23d-4ec3-b6c5-656fef843da9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300269027 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3300269027 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.914283000 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 4504890552 ps |
| CPU time | 543.47 seconds |
| Started | Jul 25 08:26:05 PM PDT 24 |
| Finished | Jul 25 08:35:10 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-e00da3ba-40b4-4d0c-9408-b713112b707d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914283000 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.914283000 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4018843904 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 4302865056 ps |
| CPU time | 692.34 seconds |
| Started | Jul 25 08:28:40 PM PDT 24 |
| Finished | Jul 25 08:40:13 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-157cdba3-6db2-46f6-bea7-b84ae3d3d622 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018843904 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.4018843904 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2671085424 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4703193640 ps |
| CPU time | 488.63 seconds |
| Started | Jul 25 08:25:13 PM PDT 24 |
| Finished | Jul 25 08:33:22 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-0dc646c8-954b-4aa9-bd1c-9c0ccb57f9de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671085424 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.2671085424 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3362558481 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 11008030552 ps |
| CPU time | 1045.06 seconds |
| Started | Jul 25 08:24:11 PM PDT 24 |
| Finished | Jul 25 08:41:36 PM PDT 24 |
| Peak memory | 611256 kb |
| Host | smart-2a7d0513-d556-4d54-b8dc-7850d98a4bf9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362558481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3362558481 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1574031167 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 3439155142 ps |
| CPU time | 484.48 seconds |
| Started | Jul 25 08:22:16 PM PDT 24 |
| Finished | Jul 25 08:30:21 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-033536ff-9edd-41ff-96c5-66fefb3375d0 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574031167 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1574031167 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2692298305 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 4469180116 ps |
| CPU time | 761.05 seconds |
| Started | Jul 25 08:25:07 PM PDT 24 |
| Finished | Jul 25 08:37:49 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-4361f0b3-a56c-4f43-9901-b2237c850b0b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692298305 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2692298305 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3138563395 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3047263650 ps |
| CPU time | 341.71 seconds |
| Started | Jul 25 08:26:33 PM PDT 24 |
| Finished | Jul 25 08:32:15 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-16cba732-9538-43dc-9b9c-7ed1efb4e151 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138563395 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.3138563395 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1506011922 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 26635183960 ps |
| CPU time | 7537.28 seconds |
| Started | Jul 25 08:20:44 PM PDT 24 |
| Finished | Jul 25 10:26:22 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-e68c528c-8839-40c2-b2ee-b869cf560b68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506011922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1506011922 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2303776647 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5341413680 ps |
| CPU time | 474.31 seconds |
| Started | Jul 25 08:20:28 PM PDT 24 |
| Finished | Jul 25 08:28:23 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-8bfcc5c7-0e4f-4703-bac8-7d0517c3c384 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037 76647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2303776647 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1666623725 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 2945140432 ps |
| CPU time | 174.97 seconds |
| Started | Jul 25 08:19:50 PM PDT 24 |
| Finished | Jul 25 08:22:45 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-5e3e1ad3-1217-41f3-b249-7686764303c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666623725 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1666623725 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3464198587 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 7069678138 ps |
| CPU time | 671.87 seconds |
| Started | Jul 25 08:20:28 PM PDT 24 |
| Finished | Jul 25 08:31:40 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-c10216ec-65ba-4854-9bd5-763758946217 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464198587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3464198587 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.3783723506 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2959002576 ps |
| CPU time | 231.5 seconds |
| Started | Jul 25 08:24:59 PM PDT 24 |
| Finished | Jul 25 08:28:51 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-ff335989-65fb-4253-873e-184399a6c84a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783723506 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3783723506 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3555696777 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4977464344 ps |
| CPU time | 1024.59 seconds |
| Started | Jul 25 08:19:45 PM PDT 24 |
| Finished | Jul 25 08:36:50 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-3b32e45c-867c-4d15-bcbe-b1401ad26552 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555696777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3555696777 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2684525124 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 3366839026 ps |
| CPU time | 539.45 seconds |
| Started | Jul 25 08:20:04 PM PDT 24 |
| Finished | Jul 25 08:29:04 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-35524aef-e13b-4b6e-b16b-f30f15e17268 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684525124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2684525124 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3791643646 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 6919596394 ps |
| CPU time | 1202.32 seconds |
| Started | Jul 25 08:23:08 PM PDT 24 |
| Finished | Jul 25 08:43:11 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-6283851c-6541-4b4b-a420-df92afb0070d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3791643646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.3791643646 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4028770129 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 7106013368 ps |
| CPU time | 865.69 seconds |
| Started | Jul 25 08:20:10 PM PDT 24 |
| Finished | Jul 25 08:34:36 PM PDT 24 |
| Peak memory | 611344 kb |
| Host | smart-6eaf7800-0291-456b-bede-dbf867161879 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028770129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.4028770129 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.225694329 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3920354150 ps |
| CPU time | 778.77 seconds |
| Started | Jul 25 08:21:27 PM PDT 24 |
| Finished | Jul 25 08:34:26 PM PDT 24 |
| Peak memory | 616096 kb |
| Host | smart-3bdb9555-457d-4c97-9ed7-39341868ccb6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225694329 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.225694329 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2743845864 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 7193572840 ps |
| CPU time | 1379.9 seconds |
| Started | Jul 25 08:21:52 PM PDT 24 |
| Finished | Jul 25 08:44:52 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-4963f2be-9169-41c3-8bfc-d32d72207cbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743845864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2743845864 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1162317377 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 2883834942 ps |
| CPU time | 213.75 seconds |
| Started | Jul 25 08:20:21 PM PDT 24 |
| Finished | Jul 25 08:23:55 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-5d4c8c1a-2bfb-454f-9fb3-921e71785111 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11 62317377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1162317377 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4005567993 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 7454968520 ps |
| CPU time | 1564.93 seconds |
| Started | Jul 25 08:21:11 PM PDT 24 |
| Finished | Jul 25 08:47:16 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-2506ed74-cbab-4178-a4fb-8af5bd3acc30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4005567993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4005567993 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2170440612 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2993430968 ps |
| CPU time | 288.74 seconds |
| Started | Jul 25 08:21:06 PM PDT 24 |
| Finished | Jul 25 08:25:55 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-1ca8e562-3772-4e92-ab63-43ef2a2d2ead |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170440612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2170440612 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2472979254 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 3590321560 ps |
| CPU time | 502.02 seconds |
| Started | Jul 25 08:25:35 PM PDT 24 |
| Finished | Jul 25 08:33:58 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-b606a5f3-abc9-4dc0-89ca-1bb7bd245cb3 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2472979254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2472979254 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.3367724413 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2787508168 ps |
| CPU time | 239.72 seconds |
| Started | Jul 25 08:17:33 PM PDT 24 |
| Finished | Jul 25 08:21:33 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-89ff81da-e7a8-48cf-a8df-eca665555bb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367724413 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.3367724413 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.4132564599 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2894603784 ps |
| CPU time | 278.59 seconds |
| Started | Jul 25 08:16:31 PM PDT 24 |
| Finished | Jul 25 08:21:11 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-78a1321f-d0a4-4c95-b921-fb0afe94958e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132564599 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.4132564599 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.1087958500 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3016576128 ps |
| CPU time | 192.17 seconds |
| Started | Jul 25 08:16:54 PM PDT 24 |
| Finished | Jul 25 08:20:06 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-1e71c84c-2f31-49da-952f-6c0adc68d758 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087958500 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1087958500 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.4131196529 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1786631944 ps |
| CPU time | 111.58 seconds |
| Started | Jul 25 08:16:44 PM PDT 24 |
| Finished | Jul 25 08:18:36 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-3edffe19-ee6c-4d45-a2a7-66f1f814f2f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131196529 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.4131196529 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1698391410 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 58154685184 ps |
| CPU time | 9987.71 seconds |
| Started | Jul 25 08:20:10 PM PDT 24 |
| Finished | Jul 25 11:06:40 PM PDT 24 |
| Peak memory | 625452 kb |
| Host | smart-4ec95c56-4a98-4af9-b710-cffa7fd210eb |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1698391410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1698391410 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.305201137 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 6019366760 ps |
| CPU time | 619.87 seconds |
| Started | Jul 25 08:30:43 PM PDT 24 |
| Finished | Jul 25 08:41:03 PM PDT 24 |
| Peak memory | 611720 kb |
| Host | smart-6cbec914-7a28-4946-8b74-08b021c1384a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=305201137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.305201137 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4213511109 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 5485048548 ps |
| CPU time | 903.09 seconds |
| Started | Jul 25 08:21:31 PM PDT 24 |
| Finished | Jul 25 08:36:35 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-a4ba5748-eefe-414f-ac46-0e222ed64187 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213511109 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.4213511109 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2904021852 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 5495496060 ps |
| CPU time | 1170.72 seconds |
| Started | Jul 25 08:21:29 PM PDT 24 |
| Finished | Jul 25 08:41:01 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-4afd2b62-3046-4fea-9279-db1a84e501fd |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904021852 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2904021852 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1254395345 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 7806413454 ps |
| CPU time | 1341.31 seconds |
| Started | Jul 25 08:24:56 PM PDT 24 |
| Finished | Jul 25 08:47:18 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-4e101229-0233-490c-8a3b-953cdb537e33 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254395345 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1254395345 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.900824537 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 5586814888 ps |
| CPU time | 888.65 seconds |
| Started | Jul 25 08:17:50 PM PDT 24 |
| Finished | Jul 25 08:32:39 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-f312c92b-75d8-4324-9780-fb889bc06430 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900824537 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.900824537 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.525905057 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 3484409618 ps |
| CPU time | 391.7 seconds |
| Started | Jul 25 08:17:58 PM PDT 24 |
| Finished | Jul 25 08:24:30 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-82d40e80-ea25-48fc-ba5c-197bad85c5d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525905057 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.525905057 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1062455225 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 5008003630 ps |
| CPU time | 756.15 seconds |
| Started | Jul 25 08:19:14 PM PDT 24 |
| Finished | Jul 25 08:31:51 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-e8ec80c0-17ed-4e1e-b155-3280120482e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 62455225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1062455225 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2900126907 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 5576294744 ps |
| CPU time | 843.61 seconds |
| Started | Jul 25 08:30:43 PM PDT 24 |
| Finished | Jul 25 08:44:47 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-99295195-4935-4f9f-80ed-4119a84eda39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900126907 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2900126907 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.570454555 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 3905301592 ps |
| CPU time | 682.3 seconds |
| Started | Jul 25 08:18:41 PM PDT 24 |
| Finished | Jul 25 08:30:04 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-026fa6c6-3f3e-49fc-a9ff-944f23b8466d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570454555 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.570454555 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.841243155 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5384923777 ps |
| CPU time | 771.44 seconds |
| Started | Jul 25 08:26:02 PM PDT 24 |
| Finished | Jul 25 08:38:55 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-29632914-e7e2-45bd-85ce-3c50db121ea8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=841243155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.841243155 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.561272254 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3337692904 ps |
| CPU time | 316.63 seconds |
| Started | Jul 25 08:24:05 PM PDT 24 |
| Finished | Jul 25 08:29:21 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-24cc4577-b1ba-4f2c-a976-858660a36f30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5612722 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.561272254 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3920598116 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 22144818070 ps |
| CPU time | 1912.7 seconds |
| Started | Jul 25 08:17:16 PM PDT 24 |
| Finished | Jul 25 08:49:09 PM PDT 24 |
| Peak memory | 614352 kb |
| Host | smart-159472e9-0c67-4df4-92fd-d0d5f4c305ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920598116 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3920598116 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1844476244 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 22043228411 ps |
| CPU time | 1594.23 seconds |
| Started | Jul 25 08:23:47 PM PDT 24 |
| Finished | Jul 25 08:50:22 PM PDT 24 |
| Peak memory | 616224 kb |
| Host | smart-0711374d-702f-47c8-add3-c93579e1c12a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1844476244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.1844476244 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1446934245 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2292147712 ps |
| CPU time | 178.53 seconds |
| Started | Jul 25 08:27:15 PM PDT 24 |
| Finished | Jul 25 08:30:14 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-beb7b9cb-cb78-4b42-ac2f-b91c1d62f4dc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1446934245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1446934245 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.3958234846 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3272772083 ps |
| CPU time | 229.1 seconds |
| Started | Jul 25 08:32:29 PM PDT 24 |
| Finished | Jul 25 08:36:19 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-f9ac20a5-43f1-43cf-859f-2892fdce50af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958234846 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.3958234846 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3358769726 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 2466915380 ps |
| CPU time | 216.07 seconds |
| Started | Jul 25 08:21:44 PM PDT 24 |
| Finished | Jul 25 08:25:20 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-63460d0a-3b4e-4752-9b10-f569f84e4b31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358769726 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3358769726 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3964535505 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 3252955184 ps |
| CPU time | 232.58 seconds |
| Started | Jul 25 08:24:05 PM PDT 24 |
| Finished | Jul 25 08:27:58 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-d9d6bb12-e91a-4859-974e-b938705c9d55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964535505 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.3964535505 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1207422852 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 2597785167 ps |
| CPU time | 201.47 seconds |
| Started | Jul 25 08:22:23 PM PDT 24 |
| Finished | Jul 25 08:25:44 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-8c3d1ed7-f4f2-43aa-a30a-a02605be6c9e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207422852 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1207422852 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2267068339 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2932189112 ps |
| CPU time | 319.67 seconds |
| Started | Jul 25 08:29:59 PM PDT 24 |
| Finished | Jul 25 08:35:20 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-3d4196b0-76c5-4623-98b4-cb58a075693a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267068339 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2267068339 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1499017837 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 6608963016 ps |
| CPU time | 1355.32 seconds |
| Started | Jul 25 08:21:59 PM PDT 24 |
| Finished | Jul 25 08:44:35 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-ca772947-bbb6-4806-abf9-699c27121758 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499017837 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1499017837 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2118450930 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 3820390800 ps |
| CPU time | 305.83 seconds |
| Started | Jul 25 08:23:12 PM PDT 24 |
| Finished | Jul 25 08:28:18 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-655b59ca-0939-454b-b38e-522becc9686d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118450930 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2118450930 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2282407281 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3309532352 ps |
| CPU time | 477.75 seconds |
| Started | Jul 25 08:25:03 PM PDT 24 |
| Finished | Jul 25 08:33:01 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-4d25f1b2-e545-4023-ad5e-36523022d2b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282407281 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2282407281 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1541179875 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4931511884 ps |
| CPU time | 686.18 seconds |
| Started | Jul 25 08:18:39 PM PDT 24 |
| Finished | Jul 25 08:30:06 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-84115f74-88a2-4c03-9dbd-817b827f6550 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541179875 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1541179875 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3335173602 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 5596329036 ps |
| CPU time | 783.76 seconds |
| Started | Jul 25 08:19:05 PM PDT 24 |
| Finished | Jul 25 08:32:10 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-fb2cda93-e504-4eb8-b1b7-5c1b73973d12 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335173602 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3335173602 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.838433231 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 4445199550 ps |
| CPU time | 946.87 seconds |
| Started | Jul 25 08:18:58 PM PDT 24 |
| Finished | Jul 25 08:34:46 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-c0bac359-e210-4319-8282-94f6e4212360 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838433231 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.838433231 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.806062165 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4992330158 ps |
| CPU time | 716.94 seconds |
| Started | Jul 25 08:21:39 PM PDT 24 |
| Finished | Jul 25 08:33:37 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-a5d1f84f-82fb-42f9-acb6-03bacced1101 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806062165 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.806062165 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3387689793 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 63450412597 ps |
| CPU time | 11721.7 seconds |
| Started | Jul 25 08:18:24 PM PDT 24 |
| Finished | Jul 25 11:33:47 PM PDT 24 |
| Peak memory | 625380 kb |
| Host | smart-ad0b629e-bd03-4744-bfdb-9b3126c93f66 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3387689793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3387689793 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2561099846 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 7859293348 ps |
| CPU time | 1472.25 seconds |
| Started | Jul 25 08:21:34 PM PDT 24 |
| Finished | Jul 25 08:46:07 PM PDT 24 |
| Peak memory | 618512 kb |
| Host | smart-2a71c706-17a2-4736-ace2-98c13cf55a36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561 099846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2561099846 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1824781970 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 7959358767 ps |
| CPU time | 1668.8 seconds |
| Started | Jul 25 08:21:28 PM PDT 24 |
| Finished | Jul 25 08:49:17 PM PDT 24 |
| Peak memory | 618524 kb |
| Host | smart-b09505ff-002a-4992-a803-2e83f644e7f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1824781970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1824781970 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.131518048 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 11988360417 ps |
| CPU time | 2065.36 seconds |
| Started | Jul 25 08:24:21 PM PDT 24 |
| Finished | Jul 25 08:58:46 PM PDT 24 |
| Peak memory | 618832 kb |
| Host | smart-6376f9d4-93a9-473a-9008-2d0f0c419e09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=131518048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.131518048 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1944814649 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 8115914154 ps |
| CPU time | 1733.35 seconds |
| Started | Jul 25 08:21:19 PM PDT 24 |
| Finished | Jul 25 08:50:12 PM PDT 24 |
| Peak memory | 617244 kb |
| Host | smart-3bbdfac3-b7d5-417d-972f-e5662d82f4d6 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1944814649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1944814649 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2197712988 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 13693034920 ps |
| CPU time | 2404.12 seconds |
| Started | Jul 25 08:21:44 PM PDT 24 |
| Finished | Jul 25 09:01:48 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-3821eb87-e337-423a-b7c0-0b2321b06281 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219771 2988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2197712988 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.287026449 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 8362551160 ps |
| CPU time | 1413.7 seconds |
| Started | Jul 25 08:21:37 PM PDT 24 |
| Finished | Jul 25 08:45:11 PM PDT 24 |
| Peak memory | 611692 kb |
| Host | smart-e1db991e-7550-48e0-91ee-1d489f7f51fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28702 6449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.287026449 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2469681617 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 16930365170 ps |
| CPU time | 3643.31 seconds |
| Started | Jul 25 08:21:05 PM PDT 24 |
| Finished | Jul 25 09:21:49 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-d802b4ba-c938-4f25-a2ea-dd52c00489ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24696 81617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2469681617 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.2021422785 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2429715828 ps |
| CPU time | 239.45 seconds |
| Started | Jul 25 08:24:20 PM PDT 24 |
| Finished | Jul 25 08:28:20 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-68204c44-ff02-4769-99d5-4829878ce05e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021422785 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.2021422785 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.634378225 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2620489600 ps |
| CPU time | 205.76 seconds |
| Started | Jul 25 08:16:47 PM PDT 24 |
| Finished | Jul 25 08:20:13 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-8d54e45c-9721-4a36-9dfa-ca97c18035ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634378225 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.634378225 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2793990974 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2763982150 ps |
| CPU time | 226.59 seconds |
| Started | Jul 25 08:24:01 PM PDT 24 |
| Finished | Jul 25 08:27:47 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-d615a3aa-946b-4f39-9124-385f0d95a1de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793990974 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2793990974 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2738663765 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 2582436576 ps |
| CPU time | 246.94 seconds |
| Started | Jul 25 08:23:51 PM PDT 24 |
| Finished | Jul 25 08:27:59 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-a5d85e36-2da3-462d-8f90-71c14e309f00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738663765 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2738663765 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3220362433 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 3682379902 ps |
| CPU time | 296.62 seconds |
| Started | Jul 25 08:24:22 PM PDT 24 |
| Finished | Jul 25 08:29:19 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-5ac2b620-6f8f-4d60-a1fc-125a5781e379 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220362433 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3220362433 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1644999694 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 3076565212 ps |
| CPU time | 285.26 seconds |
| Started | Jul 25 08:21:29 PM PDT 24 |
| Finished | Jul 25 08:26:15 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-7c10f787-e2cb-4aab-a876-9cdaaf1caa71 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644999694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1644999694 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.54325616 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 3395379108 ps |
| CPU time | 315.79 seconds |
| Started | Jul 25 08:23:39 PM PDT 24 |
| Finished | Jul 25 08:28:55 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-1e5b3a64-a14e-4150-b709-02ffb6737193 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54325616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.54325616 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.3527672266 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3317495088 ps |
| CPU time | 277.09 seconds |
| Started | Jul 25 08:25:20 PM PDT 24 |
| Finished | Jul 25 08:29:57 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-fa3fc978-85ba-48f6-b5ef-25944d0b6576 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527672266 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.3527672266 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.849338140 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 3243666056 ps |
| CPU time | 273.59 seconds |
| Started | Jul 25 08:18:39 PM PDT 24 |
| Finished | Jul 25 08:23:13 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-6ae65202-8ba2-415e-b07c-0d7f2cc53ab5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849338140 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.849338140 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.265768389 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4911090264 ps |
| CPU time | 463.66 seconds |
| Started | Jul 25 08:23:18 PM PDT 24 |
| Finished | Jul 25 08:31:02 PM PDT 24 |
| Peak memory | 611656 kb |
| Host | smart-a6df3a3f-19e3-4255-8458-bba3a8b5c57a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=265768389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.265768389 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3822357813 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2953688690 ps |
| CPU time | 137.82 seconds |
| Started | Jul 25 08:19:22 PM PDT 24 |
| Finished | Jul 25 08:21:40 PM PDT 24 |
| Peak memory | 620332 kb |
| Host | smart-254b597b-ac7b-48d5-8861-5f1288b7208a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38223578 13 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3822357813 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.4223454781 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 11365877005 ps |
| CPU time | 1004.65 seconds |
| Started | Jul 25 08:18:44 PM PDT 24 |
| Finished | Jul 25 08:35:29 PM PDT 24 |
| Peak memory | 625456 kb |
| Host | smart-44b797e1-a954-4a74-b02f-f83110939d83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223454781 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.4223454781 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.620683534 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 1957729302 ps |
| CPU time | 120.55 seconds |
| Started | Jul 25 08:20:04 PM PDT 24 |
| Finished | Jul 25 08:22:05 PM PDT 24 |
| Peak memory | 618580 kb |
| Host | smart-d502bfef-0982-4f2d-99b7-797cb32cb4b4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=620683534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.620683534 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2700922020 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 2311834382 ps |
| CPU time | 111.65 seconds |
| Started | Jul 25 08:18:56 PM PDT 24 |
| Finished | Jul 25 08:20:48 PM PDT 24 |
| Peak memory | 623704 kb |
| Host | smart-03f8d806-962d-447b-b708-687146d7b36f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700922020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2700922020 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4248868142 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 49711882830 ps |
| CPU time | 5357.45 seconds |
| Started | Jul 25 08:18:02 PM PDT 24 |
| Finished | Jul 25 09:47:20 PM PDT 24 |
| Peak memory | 621404 kb |
| Host | smart-56591d81-79d0-4155-87e7-b7c9f4a0e53c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248868142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.4248868142 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1562782829 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 48541455868 ps |
| CPU time | 5931.18 seconds |
| Started | Jul 25 08:18:43 PM PDT 24 |
| Finished | Jul 25 09:57:35 PM PDT 24 |
| Peak memory | 621100 kb |
| Host | smart-832958dd-8177-4b04-9a89-cbc4c24fa763 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562782829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1562782829 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3479278463 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 8830700049 ps |
| CPU time | 1014.52 seconds |
| Started | Jul 25 08:18:51 PM PDT 24 |
| Finished | Jul 25 08:35:46 PM PDT 24 |
| Peak memory | 620860 kb |
| Host | smart-745a5fec-ace7-4a39-9b14-12e45345dd64 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479278463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3479278463 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2243984879 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 48056118218 ps |
| CPU time | 5080.67 seconds |
| Started | Jul 25 08:18:46 PM PDT 24 |
| Finished | Jul 25 09:43:28 PM PDT 24 |
| Peak memory | 621140 kb |
| Host | smart-6e2ed523-f8c6-44d4-be85-938e281f193e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243984879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.2243984879 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3220126812 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 29740413725 ps |
| CPU time | 2062.27 seconds |
| Started | Jul 25 08:18:31 PM PDT 24 |
| Finished | Jul 25 08:52:54 PM PDT 24 |
| Peak memory | 623032 kb |
| Host | smart-6a076bc5-23d7-4508-83e7-9190bc397f7d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3220126812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3220126812 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1838440386 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 16983639240 ps |
| CPU time | 3747.09 seconds |
| Started | Jul 25 08:19:15 PM PDT 24 |
| Finished | Jul 25 09:21:43 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-c1486fd1-4fbe-4fce-8e02-baa1c58dfc28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1838440386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1838440386 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1178732308 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 18936342132 ps |
| CPU time | 3813.81 seconds |
| Started | Jul 25 08:21:23 PM PDT 24 |
| Finished | Jul 25 09:24:57 PM PDT 24 |
| Peak memory | 611036 kb |
| Host | smart-10269b50-4a20-4822-9621-b305c88eec25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1178732308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1178732308 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4070443605 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 24709764937 ps |
| CPU time | 4075.12 seconds |
| Started | Jul 25 08:24:11 PM PDT 24 |
| Finished | Jul 25 09:32:06 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-8431cf3b-ac7f-4e93-96e3-0931106db3e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070443605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4070443605 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3823223900 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2842223046 ps |
| CPU time | 481.22 seconds |
| Started | Jul 25 08:19:44 PM PDT 24 |
| Finished | Jul 25 08:27:46 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-5ff4927c-2d4a-44ed-9b60-2d020e39b091 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823223900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.3823223900 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1215904249 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6077849278 ps |
| CPU time | 1023.61 seconds |
| Started | Jul 25 08:21:39 PM PDT 24 |
| Finished | Jul 25 08:38:42 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-89fc9cf2-2f47-40af-9ac8-70ff2c0dd89f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1215904249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1215904249 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.622510808 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5620326008 ps |
| CPU time | 1248.49 seconds |
| Started | Jul 25 08:25:50 PM PDT 24 |
| Finished | Jul 25 08:46:39 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-b145228d-5325-4778-8c87-3b858fbafaa7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622510808 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.622510808 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.90798808 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 2875310921 ps |
| CPU time | 424.19 seconds |
| Started | Jul 25 08:17:35 PM PDT 24 |
| Finished | Jul 25 08:24:40 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-4c2a5e20-9d0e-4aa2-9e44-1aa4c311e813 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90798808 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.90798808 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2450113392 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 8322960120 ps |
| CPU time | 1317.21 seconds |
| Started | Jul 25 08:17:09 PM PDT 24 |
| Finished | Jul 25 08:39:07 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-d407822e-f6ce-467d-a9b2-21392fe7cd2c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2450113392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2450113392 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2686458110 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 7404470868 ps |
| CPU time | 1309.27 seconds |
| Started | Jul 25 08:18:46 PM PDT 24 |
| Finished | Jul 25 08:40:36 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-e1e899df-d74f-4b53-9e7c-757d541a1e66 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2686458110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2686458110 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.44566781 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 4270927736 ps |
| CPU time | 954.46 seconds |
| Started | Jul 25 08:19:54 PM PDT 24 |
| Finished | Jul 25 08:35:49 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-9b216f3c-0624-4f8b-bb22-a880e89de1aa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=44566781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.44566781 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1065709290 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2381771364 ps |
| CPU time | 378.76 seconds |
| Started | Jul 25 08:26:11 PM PDT 24 |
| Finished | Jul 25 08:32:30 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-c96d31f5-0df1-4c4c-8732-cced6d0f9945 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065709290 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1065709290 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.2523935281 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2189683050 ps |
| CPU time | 262.77 seconds |
| Started | Jul 25 08:18:25 PM PDT 24 |
| Finished | Jul 25 08:22:49 PM PDT 24 |
| Peak memory | 612084 kb |
| Host | smart-2abe8714-5e35-4734-afb9-98f0ea570507 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523935281 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2523935281 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1659935420 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3197979120 ps |
| CPU time | 278.83 seconds |
| Started | Jul 25 08:28:49 PM PDT 24 |
| Finished | Jul 25 08:33:28 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-fbb6eba4-84fa-473d-9ec7-d95915fea51a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659935420 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1659935420 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.4117949733 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 4681162712 ps |
| CPU time | 747.06 seconds |
| Started | Jul 25 08:24:29 PM PDT 24 |
| Finished | Jul 25 08:36:57 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-cf7812f6-7381-4c16-9133-9a92bd90967f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117949733 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.4117949733 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.2129630794 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4550867768 ps |
| CPU time | 432.36 seconds |
| Started | Jul 25 08:30:44 PM PDT 24 |
| Finished | Jul 25 08:37:57 PM PDT 24 |
| Peak memory | 611192 kb |
| Host | smart-62bd4f76-0ec8-4e35-b609-3b168a56147f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129630794 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2129630794 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.1012433945 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 5815359148 ps |
| CPU time | 1257.88 seconds |
| Started | Jul 25 08:28:20 PM PDT 24 |
| Finished | Jul 25 08:49:18 PM PDT 24 |
| Peak memory | 625604 kb |
| Host | smart-0acd0ffd-6789-44c0-bea9-4186fd5a581a |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1012433945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.1012433945 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1534849761 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 12541210723 ps |
| CPU time | 1522.35 seconds |
| Started | Jul 25 08:21:19 PM PDT 24 |
| Finished | Jul 25 08:46:42 PM PDT 24 |
| Peak memory | 612076 kb |
| Host | smart-381cacef-574a-4afc-8656-309b088f3fac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534 849761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1534849761 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2620579447 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 29733662435 ps |
| CPU time | 2050.71 seconds |
| Started | Jul 25 08:23:30 PM PDT 24 |
| Finished | Jul 25 08:57:42 PM PDT 24 |
| Peak memory | 611836 kb |
| Host | smart-1705fb41-41e8-4b50-bf29-cbadf618cce5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262 0579447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2620579447 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1566376530 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 15319449538 ps |
| CPU time | 1560.76 seconds |
| Started | Jul 25 08:18:33 PM PDT 24 |
| Finished | Jul 25 08:44:36 PM PDT 24 |
| Peak memory | 612100 kb |
| Host | smart-8c08fe78-db8c-41d3-a96d-6fbef67c0d2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1566376530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1566376530 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3076166312 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 25685277936 ps |
| CPU time | 1624.63 seconds |
| Started | Jul 25 08:31:10 PM PDT 24 |
| Finished | Jul 25 08:58:15 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-67fd9607-7584-4d4d-a249-b14e9a57dc57 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3076166312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3076166312 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3400820956 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 7875536632 ps |
| CPU time | 527.16 seconds |
| Started | Jul 25 08:17:58 PM PDT 24 |
| Finished | Jul 25 08:26:46 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-05dc5030-d6d8-4838-a758-e3077956bd72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400820956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3400820956 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3485464719 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 6068523400 ps |
| CPU time | 608.47 seconds |
| Started | Jul 25 08:20:29 PM PDT 24 |
| Finished | Jul 25 08:30:38 PM PDT 24 |
| Peak memory | 617040 kb |
| Host | smart-e52ffa24-5e32-4e82-936f-2e992e830ca3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3485464719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3485464719 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2358062047 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 8194915595 ps |
| CPU time | 631.99 seconds |
| Started | Jul 25 08:20:36 PM PDT 24 |
| Finished | Jul 25 08:31:08 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-36ac4d52-637f-475a-8350-912b9beed7ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358062047 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2358062047 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1449938392 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3454069224 ps |
| CPU time | 433.76 seconds |
| Started | Jul 25 08:23:14 PM PDT 24 |
| Finished | Jul 25 08:30:28 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-eb97ebf5-8601-4311-a7d9-30ae027c22b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449938392 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1449938392 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.924203841 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 4082111328 ps |
| CPU time | 333.79 seconds |
| Started | Jul 25 08:20:12 PM PDT 24 |
| Finished | Jul 25 08:25:46 PM PDT 24 |
| Peak memory | 616928 kb |
| Host | smart-89f27775-3cbf-4edb-a3b2-3910af655af4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=924203841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.924203841 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1676035702 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 13211047944 ps |
| CPU time | 1520.14 seconds |
| Started | Jul 25 08:18:32 PM PDT 24 |
| Finished | Jul 25 08:43:54 PM PDT 24 |
| Peak memory | 612148 kb |
| Host | smart-f84141ca-e190-4617-ad3a-8d691a3ae937 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676035702 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1676035702 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1302951034 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 7560413564 ps |
| CPU time | 473.08 seconds |
| Started | Jul 25 08:23:54 PM PDT 24 |
| Finished | Jul 25 08:31:47 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-26152399-cfc5-4807-9e89-595c2a280c67 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302951034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1302951034 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3275563168 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 5261847617 ps |
| CPU time | 490.5 seconds |
| Started | Jul 25 08:18:27 PM PDT 24 |
| Finished | Jul 25 08:26:38 PM PDT 24 |
| Peak memory | 611644 kb |
| Host | smart-3d5cf813-203b-4c0e-9f96-8a0699bd021d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275563168 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3275563168 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.652873522 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 23398047416 ps |
| CPU time | 2040.61 seconds |
| Started | Jul 25 08:19:09 PM PDT 24 |
| Finished | Jul 25 08:53:10 PM PDT 24 |
| Peak memory | 612172 kb |
| Host | smart-cc1c1eca-9804-441c-9e7c-8a3487f2be10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=652873522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.652873522 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2212127993 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6703055128 ps |
| CPU time | 587.7 seconds |
| Started | Jul 25 08:24:52 PM PDT 24 |
| Finished | Jul 25 08:34:40 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-7ac2d9ce-77ec-483a-9152-2826fc24cdde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2212127993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2212127993 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2752210430 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2921817290 ps |
| CPU time | 275.94 seconds |
| Started | Jul 25 08:18:33 PM PDT 24 |
| Finished | Jul 25 08:23:09 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-db9a44f4-34e0-4386-845b-270c9875414e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752210430 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2752210430 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3616465810 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4825573689 ps |
| CPU time | 443.75 seconds |
| Started | Jul 25 08:19:24 PM PDT 24 |
| Finished | Jul 25 08:26:48 PM PDT 24 |
| Peak memory | 618484 kb |
| Host | smart-2b726515-abb8-4396-b5e5-480753bf01ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3616465810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3616465810 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3462003958 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5491491656 ps |
| CPU time | 568.18 seconds |
| Started | Jul 25 08:28:06 PM PDT 24 |
| Finished | Jul 25 08:37:36 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-1ac04d97-9271-4f8e-ae80-f7b61d6cdaa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620039 58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3462003958 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.340778419 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 6315032594 ps |
| CPU time | 501.74 seconds |
| Started | Jul 25 08:30:19 PM PDT 24 |
| Finished | Jul 25 08:38:41 PM PDT 24 |
| Peak memory | 611024 kb |
| Host | smart-0b394873-a199-443c-8b55-35d5650259b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=340778419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.340778419 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1663967172 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 5279528532 ps |
| CPU time | 427.55 seconds |
| Started | Jul 25 08:25:43 PM PDT 24 |
| Finished | Jul 25 08:32:51 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-19187f7c-6853-4dfe-8a9a-69038988928a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663967172 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1663967172 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2957115382 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 6175418176 ps |
| CPU time | 804.26 seconds |
| Started | Jul 25 08:18:32 PM PDT 24 |
| Finished | Jul 25 08:31:57 PM PDT 24 |
| Peak memory | 611316 kb |
| Host | smart-f2d4dd6d-5cb8-44da-81d8-9089334248f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957115382 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2957115382 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1640221248 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5324827456 ps |
| CPU time | 566.4 seconds |
| Started | Jul 25 08:18:25 PM PDT 24 |
| Finished | Jul 25 08:27:51 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-7ef251cb-3ebe-466d-b299-b8bc1d063a32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640221248 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1640221248 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.62407866 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 6893028408 ps |
| CPU time | 614.29 seconds |
| Started | Jul 25 08:26:14 PM PDT 24 |
| Finished | Jul 25 08:36:29 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-4d18f434-b29f-4234-9aec-752d855595b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62407866 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.62407866 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4039561632 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3597668656 ps |
| CPU time | 331.2 seconds |
| Started | Jul 25 08:18:19 PM PDT 24 |
| Finished | Jul 25 08:23:50 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-914788a2-b6a3-4e6e-a67a-2cc3fc7440e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403 9561632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.4039561632 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2720837928 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 8614169909 ps |
| CPU time | 696.22 seconds |
| Started | Jul 25 08:23:37 PM PDT 24 |
| Finished | Jul 25 08:35:14 PM PDT 24 |
| Peak memory | 625476 kb |
| Host | smart-24d889e4-3087-447e-9cd9-9399a790513c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720837928 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2720837928 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.188925993 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 11767000848 ps |
| CPU time | 1905.71 seconds |
| Started | Jul 25 08:19:14 PM PDT 24 |
| Finished | Jul 25 08:51:00 PM PDT 24 |
| Peak memory | 611544 kb |
| Host | smart-4674cd04-1610-4a90-b4e5-d4f2f27a8760 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=188925993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.188925993 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1180649697 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5151805386 ps |
| CPU time | 820.48 seconds |
| Started | Jul 25 08:20:40 PM PDT 24 |
| Finished | Jul 25 08:34:21 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-aa0f6424-cb6a-4cb3-9b7f-cb71813a7600 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180649697 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1180649697 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1235283656 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5345937548 ps |
| CPU time | 849.64 seconds |
| Started | Jul 25 08:17:57 PM PDT 24 |
| Finished | Jul 25 08:32:07 PM PDT 24 |
| Peak memory | 642000 kb |
| Host | smart-c49f91f7-b7ff-49f6-b359-12a705900322 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1235283656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1235283656 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2248652959 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3071467186 ps |
| CPU time | 289.52 seconds |
| Started | Jul 25 08:25:29 PM PDT 24 |
| Finished | Jul 25 08:30:19 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-7dba74fb-679f-4789-a131-6fc15de0be39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248652959 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2248652959 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2147850284 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3629999162 ps |
| CPU time | 510.79 seconds |
| Started | Jul 25 08:17:57 PM PDT 24 |
| Finished | Jul 25 08:26:28 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-582239ce-bbbd-4a07-b29e-9efc395cb93a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147850284 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2147850284 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.834095048 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 2699524600 ps |
| CPU time | 278.29 seconds |
| Started | Jul 25 08:18:51 PM PDT 24 |
| Finished | Jul 25 08:23:29 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-cb5bc0b4-97c8-4ed8-8dd7-9c2f1265f5c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834095048 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.834095048 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.800073455 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2928669811 ps |
| CPU time | 336.28 seconds |
| Started | Jul 25 08:25:23 PM PDT 24 |
| Finished | Jul 25 08:31:01 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-4732f07a-0000-44b0-b368-a11371229f38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800073455 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.800073455 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4211467037 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 4724713330 ps |
| CPU time | 795.73 seconds |
| Started | Jul 25 08:19:47 PM PDT 24 |
| Finished | Jul 25 08:33:03 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-14f852ec-5a1e-4784-8aca-0cda09f0151a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42114 67037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.4211467037 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3608834493 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 5732301376 ps |
| CPU time | 1151.17 seconds |
| Started | Jul 25 08:20:30 PM PDT 24 |
| Finished | Jul 25 08:39:42 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-c897de45-7dc8-416b-9669-277414cfaa14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3608834493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3608834493 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1278857756 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4649571876 ps |
| CPU time | 397.45 seconds |
| Started | Jul 25 08:22:10 PM PDT 24 |
| Finished | Jul 25 08:28:48 PM PDT 24 |
| Peak memory | 621248 kb |
| Host | smart-d7e02a8d-142e-423f-97ec-355989a45941 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278857756 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1278857756 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2425124645 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 6734841096 ps |
| CPU time | 487.57 seconds |
| Started | Jul 25 08:24:46 PM PDT 24 |
| Finished | Jul 25 08:32:54 PM PDT 24 |
| Peak memory | 621108 kb |
| Host | smart-54e92077-60e3-4d91-880c-283044431e55 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425124645 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2425124645 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2649377206 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5558042916 ps |
| CPU time | 585.39 seconds |
| Started | Jul 25 08:29:59 PM PDT 24 |
| Finished | Jul 25 08:39:45 PM PDT 24 |
| Peak memory | 622108 kb |
| Host | smart-08eff6ac-1e5d-46f2-9ea3-b7de522d61d2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264937 7206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2649377206 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2670318975 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2577880312 ps |
| CPU time | 238.23 seconds |
| Started | Jul 25 08:25:46 PM PDT 24 |
| Finished | Jul 25 08:29:45 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-e5262f17-7431-43a1-a90f-1e51e226c13e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670318975 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.2670318975 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.936992083 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 3009149200 ps |
| CPU time | 223 seconds |
| Started | Jul 25 08:19:42 PM PDT 24 |
| Finished | Jul 25 08:23:26 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-d1484e8e-0bda-44ba-bfc9-4e5e3787725a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936992083 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.936992083 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.161040506 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2973733704 ps |
| CPU time | 277.24 seconds |
| Started | Jul 25 08:25:15 PM PDT 24 |
| Finished | Jul 25 08:29:53 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-17b7721b-0fe1-4d10-bdff-42808c74be1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161040506 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_smoketest.161040506 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.691916315 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 5859323940 ps |
| CPU time | 965.45 seconds |
| Started | Jul 25 08:23:10 PM PDT 24 |
| Finished | Jul 25 08:39:15 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-36938aa3-d0c9-484a-947f-481f2b72bde1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69191631 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.691916315 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3238231131 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3366668414 ps |
| CPU time | 313.72 seconds |
| Started | Jul 25 08:21:57 PM PDT 24 |
| Finished | Jul 25 08:27:11 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-3c7362b0-17f7-47d9-a3f6-68bf538fdf0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238231 131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3238231131 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2010827886 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3734551090 ps |
| CPU time | 322.32 seconds |
| Started | Jul 25 08:18:06 PM PDT 24 |
| Finished | Jul 25 08:23:29 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-a7632b4b-351f-4d12-980d-67c631a48908 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010827886 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2010827886 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2354191048 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 8943859000 ps |
| CPU time | 1166.02 seconds |
| Started | Jul 25 08:17:03 PM PDT 24 |
| Finished | Jul 25 08:36:29 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-5f3f705f-2bb1-4cc7-9343-546a8430373c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354191048 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2354191048 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3673121706 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 8149224232 ps |
| CPU time | 769.23 seconds |
| Started | Jul 25 08:22:40 PM PDT 24 |
| Finished | Jul 25 08:35:29 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-df49b280-b586-402c-9722-2172fd3ce81f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673121706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3673121706 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1990222314 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 9403485540 ps |
| CPU time | 976.59 seconds |
| Started | Jul 25 08:21:51 PM PDT 24 |
| Finished | Jul 25 08:38:08 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-201d9d77-2dff-4ff7-b091-5630114dc046 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990222314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.1990222314 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1241296919 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6019678435 ps |
| CPU time | 751.87 seconds |
| Started | Jul 25 08:17:58 PM PDT 24 |
| Finished | Jul 25 08:30:30 PM PDT 24 |
| Peak memory | 625564 kb |
| Host | smart-3becd778-5d74-4762-a097-a70d24b0677b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241296919 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1241296919 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.454391171 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4685674272 ps |
| CPU time | 548.43 seconds |
| Started | Jul 25 08:18:39 PM PDT 24 |
| Finished | Jul 25 08:27:48 PM PDT 24 |
| Peak memory | 625556 kb |
| Host | smart-ad691d9a-aa0b-446c-ae24-08c2822904dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454391171 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.454391171 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2570198276 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3775347813 ps |
| CPU time | 381.01 seconds |
| Started | Jul 25 08:18:33 PM PDT 24 |
| Finished | Jul 25 08:24:54 PM PDT 24 |
| Peak memory | 619740 kb |
| Host | smart-ce7ba9a3-e95b-49fe-929e-54820d7fbc26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570198276 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2570198276 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3076542541 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3581369719 ps |
| CPU time | 399.5 seconds |
| Started | Jul 25 08:17:43 PM PDT 24 |
| Finished | Jul 25 08:24:24 PM PDT 24 |
| Peak memory | 620080 kb |
| Host | smart-200e48d1-ef28-48a4-ac7f-cceb2c2e9ac2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076542541 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3076542541 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3469467249 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2909602786 ps |
| CPU time | 235.86 seconds |
| Started | Jul 25 08:17:53 PM PDT 24 |
| Finished | Jul 25 08:21:49 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-61ebe652-89a0-44d3-b752-09e990b30669 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469467249 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3469467249 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2519670278 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 8626576970 ps |
| CPU time | 1277.38 seconds |
| Started | Jul 25 08:22:43 PM PDT 24 |
| Finished | Jul 25 08:44:01 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-6cc3248c-20db-4dd8-bf86-090ca5ee5972 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519670278 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2519670278 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.139690178 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5516128240 ps |
| CPU time | 716.04 seconds |
| Started | Jul 25 08:22:11 PM PDT 24 |
| Finished | Jul 25 08:34:07 PM PDT 24 |
| Peak memory | 611384 kb |
| Host | smart-1d02959a-ad3c-405b-8559-32bbbaf08983 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139690178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.139690178 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2084029918 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5005113828 ps |
| CPU time | 544.42 seconds |
| Started | Jul 25 08:22:22 PM PDT 24 |
| Finished | Jul 25 08:31:27 PM PDT 24 |
| Peak memory | 611696 kb |
| Host | smart-65a0b723-0474-41e1-a057-a389dd458986 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084029918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2084029918 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.399890871 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5230884994 ps |
| CPU time | 631.18 seconds |
| Started | Jul 25 08:24:12 PM PDT 24 |
| Finished | Jul 25 08:34:44 PM PDT 24 |
| Peak memory | 611660 kb |
| Host | smart-f7021f40-9d13-40de-9516-3279a781f8e8 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399890871 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.399890871 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1341276284 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2482923630 ps |
| CPU time | 225.79 seconds |
| Started | Jul 25 08:26:37 PM PDT 24 |
| Finished | Jul 25 08:30:23 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-54f418eb-ba3f-4327-beff-0c7b645427e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341276284 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1341276284 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1983914944 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 20730621200 ps |
| CPU time | 3163.58 seconds |
| Started | Jul 25 08:18:46 PM PDT 24 |
| Finished | Jul 25 09:11:30 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-e2c311bc-30ee-4645-8fc9-192cf5b50dff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983914944 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1983914944 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1958766141 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 4689385805 ps |
| CPU time | 548.52 seconds |
| Started | Jul 25 08:19:03 PM PDT 24 |
| Finished | Jul 25 08:28:13 PM PDT 24 |
| Peak memory | 614172 kb |
| Host | smart-adcd3d1d-d49a-4d32-9b2b-7fd42293da52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958766141 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1958766141 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3714797748 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2474980045 ps |
| CPU time | 285.3 seconds |
| Started | Jul 25 08:19:06 PM PDT 24 |
| Finished | Jul 25 08:23:53 PM PDT 24 |
| Peak memory | 613816 kb |
| Host | smart-7980af81-6331-4f0f-a651-bbc3384dc8f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714797748 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.3714797748 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.321907087 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3897400684 ps |
| CPU time | 400.87 seconds |
| Started | Jul 25 08:20:47 PM PDT 24 |
| Finished | Jul 25 08:27:28 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-38ee6474-bfd3-45ee-b683-c27713ba32a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321907087 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.321907087 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1292088623 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 23210263038 ps |
| CPU time | 1770.97 seconds |
| Started | Jul 25 08:21:13 PM PDT 24 |
| Finished | Jul 25 08:50:44 PM PDT 24 |
| Peak memory | 615424 kb |
| Host | smart-017ef6dc-eaa0-4b65-8bfc-967e421f2914 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12920886 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1292088623 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1837853610 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5478271000 ps |
| CPU time | 503.04 seconds |
| Started | Jul 25 08:21:16 PM PDT 24 |
| Finished | Jul 25 08:29:40 PM PDT 24 |
| Peak memory | 611608 kb |
| Host | smart-117b28c2-d959-423e-92d2-0feedafaeb05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837853610 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1837853610 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1713421201 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 13602382390 ps |
| CPU time | 2695.71 seconds |
| Started | Jul 25 08:17:14 PM PDT 24 |
| Finished | Jul 25 09:02:10 PM PDT 24 |
| Peak memory | 623876 kb |
| Host | smart-3ca3dedd-d860-4d05-81fb-8e0027451479 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1713421201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1713421201 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1267025983 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 2693309786 ps |
| CPU time | 273.39 seconds |
| Started | Jul 25 08:25:32 PM PDT 24 |
| Finished | Jul 25 08:30:06 PM PDT 24 |
| Peak memory | 617836 kb |
| Host | smart-44afc193-8351-4502-b50c-077e0f8a3667 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267025983 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1267025983 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.100886453 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4724747560 ps |
| CPU time | 704.76 seconds |
| Started | Jul 25 08:17:36 PM PDT 24 |
| Finished | Jul 25 08:29:21 PM PDT 24 |
| Peak memory | 625404 kb |
| Host | smart-dd52f41a-2e8a-4da3-ad16-f0e952e869ea |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100886453 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.100886453 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3616680978 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 8336113333 ps |
| CPU time | 2206.34 seconds |
| Started | Jul 25 08:17:57 PM PDT 24 |
| Finished | Jul 25 08:54:44 PM PDT 24 |
| Peak memory | 623976 kb |
| Host | smart-550cb05a-3ebb-47d6-a84e-3e7f7df7dedc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616680978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3616680978 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3140368587 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 5285976050 ps |
| CPU time | 601.57 seconds |
| Started | Jul 25 08:18:24 PM PDT 24 |
| Finished | Jul 25 08:28:26 PM PDT 24 |
| Peak memory | 625396 kb |
| Host | smart-d98f283f-dae8-4539-801c-8de8114bb49f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140368587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3140368587 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2821981715 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 78670985544 ps |
| CPU time | 13351.6 seconds |
| Started | Jul 25 08:17:33 PM PDT 24 |
| Finished | Jul 26 12:00:07 AM PDT 24 |
| Peak memory | 634648 kb |
| Host | smart-c7917b4a-0211-4e8e-a3b2-233d2323ca45 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2821981715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2821981715 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.428678292 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 4134406956 ps |
| CPU time | 610.43 seconds |
| Started | Jul 25 08:17:10 PM PDT 24 |
| Finished | Jul 25 08:27:22 PM PDT 24 |
| Peak memory | 625400 kb |
| Host | smart-1d99e926-de80-4c5f-bbe8-3107b481d334 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428678292 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.428678292 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2720077536 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 4631875016 ps |
| CPU time | 690.47 seconds |
| Started | Jul 25 08:19:48 PM PDT 24 |
| Finished | Jul 25 08:31:20 PM PDT 24 |
| Peak memory | 625412 kb |
| Host | smart-1f55a30b-993b-432a-a62f-e155bfb4f46e |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720077536 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2720077536 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.638690551 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 4214656194 ps |
| CPU time | 569.66 seconds |
| Started | Jul 25 08:17:21 PM PDT 24 |
| Finished | Jul 25 08:26:51 PM PDT 24 |
| Peak memory | 625372 kb |
| Host | smart-b599b7e9-69ed-488e-8e33-f2a09434d19a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638690551 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.638690551 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.4241558236 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2507958859 ps |
| CPU time | 169.31 seconds |
| Started | Jul 25 08:22:26 PM PDT 24 |
| Finished | Jul 25 08:25:15 PM PDT 24 |
| Peak memory | 623000 kb |
| Host | smart-6848211c-aa21-4d0e-b6c5-ce507539c813 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4241558236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.4241558236 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.2754845416 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 8141943585 ps |
| CPU time | 873.32 seconds |
| Started | Jul 25 08:23:48 PM PDT 24 |
| Finished | Jul 25 08:38:22 PM PDT 24 |
| Peak memory | 623104 kb |
| Host | smart-3d3959fe-5db9-48ce-9927-f6bc807eeeec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754845416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2754845416 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.1129155864 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 6159088527 ps |
| CPU time | 544.43 seconds |
| Started | Jul 25 08:22:01 PM PDT 24 |
| Finished | Jul 25 08:31:05 PM PDT 24 |
| Peak memory | 633120 kb |
| Host | smart-2bcec2fb-c4da-44b5-9ec6-d88e8d6d2cae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129155864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.1129155864 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1404023762 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 15075554545 ps |
| CPU time | 4306.23 seconds |
| Started | Jul 25 08:34:34 PM PDT 24 |
| Finished | Jul 25 09:46:21 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-9f4c8305-e345-442f-97a6-87f11fcaca5e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404023762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1404023762 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.815681589 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 15364043086 ps |
| CPU time | 3630.24 seconds |
| Started | Jul 25 08:28:26 PM PDT 24 |
| Finished | Jul 25 09:28:57 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-079058ee-f82e-4bd1-b52f-985e3cd68ecc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815681589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.815681589 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2375784538 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 15259178428 ps |
| CPU time | 3128.78 seconds |
| Started | Jul 25 08:29:02 PM PDT 24 |
| Finished | Jul 25 09:21:12 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-47b35317-f30c-459b-802d-619d93a98318 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375784538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2375784538 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.926969333 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 14933801578 ps |
| CPU time | 4432.93 seconds |
| Started | Jul 25 08:35:32 PM PDT 24 |
| Finished | Jul 25 09:49:26 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-136b028a-8652-4a85-a912-99e944056af1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926969333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.926969333 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2721655895 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 11397764631 ps |
| CPU time | 2832.62 seconds |
| Started | Jul 25 08:28:02 PM PDT 24 |
| Finished | Jul 25 09:15:15 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-d19e08c5-4e21-4bfa-80bd-64ffe53483cd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721655895 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2721655895 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2640384525 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 15212137156 ps |
| CPU time | 4394.49 seconds |
| Started | Jul 25 08:36:57 PM PDT 24 |
| Finished | Jul 25 09:50:12 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-2b6deb3f-080b-406e-892d-a5002a922e7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640384525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2640384525 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4175108734 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 14980295200 ps |
| CPU time | 2855.53 seconds |
| Started | Jul 25 08:36:59 PM PDT 24 |
| Finished | Jul 25 09:24:35 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-d5a0ba55-a5d6-4048-9fd2-5f88bb617e29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175108734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.4175108734 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1740721756 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 14741227196 ps |
| CPU time | 2943.44 seconds |
| Started | Jul 25 08:29:39 PM PDT 24 |
| Finished | Jul 25 09:18:43 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-77da61f7-474a-4cf8-aa93-81465624db51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740721756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1740721756 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.1971394359 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 26256885600 ps |
| CPU time | 5369.72 seconds |
| Started | Jul 25 08:31:30 PM PDT 24 |
| Finished | Jul 25 10:01:00 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-2e270ca7-0861-42a1-a027-0c4b3f4e5e3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971394359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1971394359 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1921103520 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 14398741442 ps |
| CPU time | 3530.39 seconds |
| Started | Jul 25 08:27:45 PM PDT 24 |
| Finished | Jul 25 09:26:36 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-d8b6f820-bb65-4feb-b32f-821ea0e92f50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921103520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.1921103520 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2704240814 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 26545954617 ps |
| CPU time | 2964.86 seconds |
| Started | Jul 25 08:35:25 PM PDT 24 |
| Finished | Jul 25 09:24:50 PM PDT 24 |
| Peak memory | 612272 kb |
| Host | smart-0557ae21-0f78-49e7-bcb9-2dabb070d373 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704240814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2704240814 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1244493387 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 14942798304 ps |
| CPU time | 3823.63 seconds |
| Started | Jul 25 08:28:27 PM PDT 24 |
| Finished | Jul 25 09:32:11 PM PDT 24 |
| Peak memory | 611492 kb |
| Host | smart-bcbbcd9f-3318-4da2-a59d-7557e854fa27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1244493387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1244493387 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2708876369 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 17463466792 ps |
| CPU time | 4796.52 seconds |
| Started | Jul 25 08:36:29 PM PDT 24 |
| Finished | Jul 25 09:56:26 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-634bdc49-2f7b-49e9-b438-69c341e5a059 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708876369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2708876369 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.1377356817 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 4435353408 ps |
| CPU time | 482.92 seconds |
| Started | Jul 25 08:25:27 PM PDT 24 |
| Finished | Jul 25 08:33:31 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-51eadafb-43e4-4f8e-80f3-a114f9eb8a77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377356817 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1377356817 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.1858102070 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 5138487650 ps |
| CPU time | 269.84 seconds |
| Started | Jul 25 08:31:27 PM PDT 24 |
| Finished | Jul 25 08:35:58 PM PDT 24 |
| Peak memory | 619368 kb |
| Host | smart-27f880d2-cbcd-4119-b661-5345fefa9332 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1858102070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1858102070 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.1723182199 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 2554466590 ps |
| CPU time | 114.81 seconds |
| Started | Jul 25 08:24:36 PM PDT 24 |
| Finished | Jul 25 08:26:31 PM PDT 24 |
| Peak memory | 618400 kb |
| Host | smart-02b6ae54-3e1c-43e6-b44a-3becac3db8b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723182199 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1723182199 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3631206156 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 5552245900 ps |
| CPU time | 704.55 seconds |
| Started | Jul 25 08:30:38 PM PDT 24 |
| Finished | Jul 25 08:42:23 PM PDT 24 |
| Peak memory | 650548 kb |
| Host | smart-227d0fa2-a60e-46e0-9812-8c6bfce3dcbe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3631206156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3631206156 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.214135546 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3304700696 ps |
| CPU time | 360.34 seconds |
| Started | Jul 25 08:30:21 PM PDT 24 |
| Finished | Jul 25 08:36:22 PM PDT 24 |
| Peak memory | 649180 kb |
| Host | smart-72e6e70c-0877-4eb5-b369-3a3b4564c967 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214135546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_s w_alert_handler_lpg_sleep_mode_alerts.214135546 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.3584919873 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5080398422 ps |
| CPU time | 656.31 seconds |
| Started | Jul 25 08:32:09 PM PDT 24 |
| Finished | Jul 25 08:43:05 PM PDT 24 |
| Peak memory | 650564 kb |
| Host | smart-c9973fb0-1e46-4111-ac9d-86b63bf09a9e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3584919873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3584919873 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407759345 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3856610712 ps |
| CPU time | 536.22 seconds |
| Started | Jul 25 08:32:03 PM PDT 24 |
| Finished | Jul 25 08:41:00 PM PDT 24 |
| Peak memory | 649772 kb |
| Host | smart-393c3b57-e33e-4abb-83bf-2b4b3b97641b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407759345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2407759345 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860247432 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3769126532 ps |
| CPU time | 483.77 seconds |
| Started | Jul 25 08:31:38 PM PDT 24 |
| Finished | Jul 25 08:39:42 PM PDT 24 |
| Peak memory | 650068 kb |
| Host | smart-dd26db07-7bcd-484e-a921-0b6ad3752b09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860247432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2860247432 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1948861377 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4672337488 ps |
| CPU time | 609.6 seconds |
| Started | Jul 25 08:31:07 PM PDT 24 |
| Finished | Jul 25 08:41:17 PM PDT 24 |
| Peak memory | 650912 kb |
| Host | smart-1cff5d61-d2fb-4e38-978d-78b62c1d336e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1948861377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1948861377 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.2225528050 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 5361958180 ps |
| CPU time | 689.3 seconds |
| Started | Jul 25 08:31:19 PM PDT 24 |
| Finished | Jul 25 08:42:49 PM PDT 24 |
| Peak memory | 650356 kb |
| Host | smart-8cb4a0db-7b03-4b88-9622-98edff42f9dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2225528050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2225528050 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1283959140 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6222356138 ps |
| CPU time | 676.73 seconds |
| Started | Jul 25 08:31:55 PM PDT 24 |
| Finished | Jul 25 08:43:12 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-62bf6fdf-7250-4ffe-a0cb-ebc7388b7a09 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1283959140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.1283959140 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2297858685 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3315342516 ps |
| CPU time | 400.6 seconds |
| Started | Jul 25 08:33:36 PM PDT 24 |
| Finished | Jul 25 08:40:17 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-a5bf4555-e013-4ecc-8ca9-f651384d485f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297858685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2297858685 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4010385225 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3485079298 ps |
| CPU time | 392.23 seconds |
| Started | Jul 25 08:27:14 PM PDT 24 |
| Finished | Jul 25 08:33:46 PM PDT 24 |
| Peak memory | 619552 kb |
| Host | smart-7ed38d53-7904-4163-8656-e12cde7f25df |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010385225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.4010385225 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.188485259 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4984732376 ps |
| CPU time | 655.64 seconds |
| Started | Jul 25 08:26:49 PM PDT 24 |
| Finished | Jul 25 08:37:45 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-ff5f0219-5361-4e89-a81c-29a77be134b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 188485259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.188485259 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1610332107 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 6085095920 ps |
| CPU time | 342.62 seconds |
| Started | Jul 25 08:26:22 PM PDT 24 |
| Finished | Jul 25 08:32:05 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-cc6aca7b-778d-4bae-ab3a-141f7c419972 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1610332107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1610332107 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1904589167 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 26983338636 ps |
| CPU time | 6394.45 seconds |
| Started | Jul 25 08:27:44 PM PDT 24 |
| Finished | Jul 25 10:14:19 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-715f640e-6095-416e-a283-c5a48aa8df02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904589167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1904589167 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.418572025 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4523838768 ps |
| CPU time | 629.14 seconds |
| Started | Jul 25 08:28:07 PM PDT 24 |
| Finished | Jul 25 08:38:37 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-00fc9d0f-9276-47a2-b020-3eced07593dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=418572025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.418572025 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1997868467 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 6307977280 ps |
| CPU time | 697.79 seconds |
| Started | Jul 25 08:26:18 PM PDT 24 |
| Finished | Jul 25 08:37:56 PM PDT 24 |
| Peak memory | 621140 kb |
| Host | smart-8da97d59-dce9-441f-8e9e-badd64686ada |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997868467 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1997868467 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.557735214 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 8260670712 ps |
| CPU time | 1031.04 seconds |
| Started | Jul 25 08:26:20 PM PDT 24 |
| Finished | Jul 25 08:43:31 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-293e3ead-13fd-47b1-8c39-b93297104d3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55773521 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.557735214 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.66769627 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 8182962360 ps |
| CPU time | 1643.03 seconds |
| Started | Jul 25 08:26:48 PM PDT 24 |
| Finished | Jul 25 08:54:11 PM PDT 24 |
| Peak memory | 619536 kb |
| Host | smart-73679355-73f4-48d0-bcbd-dd332d60bf06 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=66769627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.66769627 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.3854082938 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 3791320348 ps |
| CPU time | 634.21 seconds |
| Started | Jul 25 08:25:52 PM PDT 24 |
| Finished | Jul 25 08:36:26 PM PDT 24 |
| Peak memory | 625400 kb |
| Host | smart-7175c75d-bc2d-4ba3-a81c-3cbdf0d48c8c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854082938 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3854082938 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3501112200 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 8984560170 ps |
| CPU time | 2056.22 seconds |
| Started | Jul 25 08:26:55 PM PDT 24 |
| Finished | Jul 25 09:01:11 PM PDT 24 |
| Peak memory | 625404 kb |
| Host | smart-fdaa7e00-d2b3-47dd-8ca1-61cd2f3bee00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501112200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.3501112200 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4148185625 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4383847412 ps |
| CPU time | 640.06 seconds |
| Started | Jul 25 08:26:34 PM PDT 24 |
| Finished | Jul 25 08:37:14 PM PDT 24 |
| Peak memory | 619264 kb |
| Host | smart-22debe79-245f-46af-8470-5cb84deb5d1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148185625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4148185625 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2844817540 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 4667576768 ps |
| CPU time | 597.9 seconds |
| Started | Jul 25 08:25:28 PM PDT 24 |
| Finished | Jul 25 08:35:26 PM PDT 24 |
| Peak memory | 625388 kb |
| Host | smart-c315097d-671d-4f85-b1d7-63a70fd60bea |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844817540 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2844817540 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2870469903 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4536394732 ps |
| CPU time | 495.76 seconds |
| Started | Jul 25 08:25:12 PM PDT 24 |
| Finished | Jul 25 08:33:28 PM PDT 24 |
| Peak memory | 625448 kb |
| Host | smart-b7b2afe5-3629-4c75-9e4f-d442daf2855c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870469903 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2870469903 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1865832749 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 4981403592 ps |
| CPU time | 748.54 seconds |
| Started | Jul 25 08:29:08 PM PDT 24 |
| Finished | Jul 25 08:41:37 PM PDT 24 |
| Peak memory | 625428 kb |
| Host | smart-99ff8922-e9e8-466d-9846-f5b1cb5e614a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865832749 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1865832749 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1389577466 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 15825442800 ps |
| CPU time | 1478.86 seconds |
| Started | Jul 25 08:26:49 PM PDT 24 |
| Finished | Jul 25 08:51:28 PM PDT 24 |
| Peak memory | 623080 kb |
| Host | smart-8caee419-b670-4c7f-b4c2-5621349b8d0d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1389577466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1389577466 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3296017731 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 2907253408 ps |
| CPU time | 165.45 seconds |
| Started | Jul 25 08:26:37 PM PDT 24 |
| Finished | Jul 25 08:29:23 PM PDT 24 |
| Peak memory | 623672 kb |
| Host | smart-81298468-a75f-43da-abb1-8f518a85c06d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296017731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3296017731 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.4153339456 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3229491037 ps |
| CPU time | 211.05 seconds |
| Started | Jul 25 08:26:56 PM PDT 24 |
| Finished | Jul 25 08:30:27 PM PDT 24 |
| Peak memory | 624640 kb |
| Host | smart-e955532f-5039-4915-936c-0872525c7bcc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153339456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.4153339456 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.45563260 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4625763940 ps |
| CPU time | 386.74 seconds |
| Started | Jul 25 08:32:20 PM PDT 24 |
| Finished | Jul 25 08:38:48 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-c04997a1-dea1-4ef6-bb95-9ab7cbd6bf03 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45563260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw _alert_handler_lpg_sleep_mode_alerts.45563260 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3175224059 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 5441970674 ps |
| CPU time | 514.7 seconds |
| Started | Jul 25 08:34:04 PM PDT 24 |
| Finished | Jul 25 08:42:39 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-866f3b00-3882-4481-8b93-33ba9361401b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3175224059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3175224059 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1518517416 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3678348040 ps |
| CPU time | 341.84 seconds |
| Started | Jul 25 08:33:04 PM PDT 24 |
| Finished | Jul 25 08:38:47 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-43c59195-fcd0-4aca-b48e-95ad2fb53207 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518517416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1518517416 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2277069319 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 5363175032 ps |
| CPU time | 1031.38 seconds |
| Started | Jul 25 08:32:15 PM PDT 24 |
| Finished | Jul 25 08:49:27 PM PDT 24 |
| Peak memory | 650284 kb |
| Host | smart-ca79272c-8421-4858-a745-45ef6ad26ea7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2277069319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2277069319 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760101928 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4045050856 ps |
| CPU time | 542.19 seconds |
| Started | Jul 25 08:32:29 PM PDT 24 |
| Finished | Jul 25 08:41:31 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-d6a546f1-0acf-486b-9915-a4c9a166d7e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760101928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1760101928 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444357605 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4491733880 ps |
| CPU time | 333.42 seconds |
| Started | Jul 25 08:33:38 PM PDT 24 |
| Finished | Jul 25 08:39:12 PM PDT 24 |
| Peak memory | 649836 kb |
| Host | smart-28ad3ba7-b04a-4a3d-bb55-5149c217d207 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444357605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1444357605 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.1150382897 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4864114320 ps |
| CPU time | 513.34 seconds |
| Started | Jul 25 08:31:59 PM PDT 24 |
| Finished | Jul 25 08:40:33 PM PDT 24 |
| Peak memory | 650572 kb |
| Host | smart-7a0ef97c-3346-4bb5-8cc3-b5bd9f6da8cf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1150382897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1150382897 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.515523497 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3478012660 ps |
| CPU time | 518.53 seconds |
| Started | Jul 25 08:33:13 PM PDT 24 |
| Finished | Jul 25 08:41:52 PM PDT 24 |
| Peak memory | 649584 kb |
| Host | smart-005891ef-5ea6-4089-9260-db12c29bbc53 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515523497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.515523497 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3998691204 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4227729252 ps |
| CPU time | 390.12 seconds |
| Started | Jul 25 08:36:47 PM PDT 24 |
| Finished | Jul 25 08:43:18 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-b4599f47-f382-40b8-b885-e16207aea532 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998691204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3998691204 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1221137610 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 6144406258 ps |
| CPU time | 536 seconds |
| Started | Jul 25 08:32:18 PM PDT 24 |
| Finished | Jul 25 08:41:14 PM PDT 24 |
| Peak memory | 650780 kb |
| Host | smart-73045a47-46a8-4cc9-8f7f-327d6c154a26 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1221137610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1221137610 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3528135645 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3471632624 ps |
| CPU time | 523.06 seconds |
| Started | Jul 25 08:28:29 PM PDT 24 |
| Finished | Jul 25 08:37:12 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-33f10cfa-22b2-4464-94b8-291ec2fd87cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528135645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3528135645 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1847136433 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 7202595686 ps |
| CPU time | 593.46 seconds |
| Started | Jul 25 08:28:46 PM PDT 24 |
| Finished | Jul 25 08:38:40 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-6200f347-dbde-4bcb-a0a5-5830bce8e6d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1847136433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1847136433 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3543322559 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 14566714566 ps |
| CPU time | 3607.1 seconds |
| Started | Jul 25 08:27:45 PM PDT 24 |
| Finished | Jul 25 09:27:53 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-80a964d3-a6f4-4901-b4f7-0ff69bfb058c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543322559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3543322559 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.4199320772 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5954002796 ps |
| CPU time | 685.11 seconds |
| Started | Jul 25 08:30:06 PM PDT 24 |
| Finished | Jul 25 08:41:31 PM PDT 24 |
| Peak memory | 611756 kb |
| Host | smart-b52d6c99-2cc6-43f8-b8f1-b1cee6a6bfc0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4199320772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.4199320772 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3370346825 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 7096929233 ps |
| CPU time | 576.18 seconds |
| Started | Jul 25 08:29:19 PM PDT 24 |
| Finished | Jul 25 08:38:56 PM PDT 24 |
| Peak memory | 621148 kb |
| Host | smart-ed633539-a834-4b7e-9ac7-4b54e1058078 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370346825 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3370346825 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3951592474 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6375951322 ps |
| CPU time | 714.18 seconds |
| Started | Jul 25 08:27:57 PM PDT 24 |
| Finished | Jul 25 08:39:51 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-8646ae91-dc83-4691-a508-804ded339432 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515924 74 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3951592474 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.254481978 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 3820473936 ps |
| CPU time | 695.29 seconds |
| Started | Jul 25 08:27:02 PM PDT 24 |
| Finished | Jul 25 08:38:38 PM PDT 24 |
| Peak memory | 619580 kb |
| Host | smart-1ef147eb-9c1d-4849-897d-1d0eae87e764 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=254481978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.254481978 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.2615839775 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3945596408 ps |
| CPU time | 621.61 seconds |
| Started | Jul 25 08:27:31 PM PDT 24 |
| Finished | Jul 25 08:37:53 PM PDT 24 |
| Peak memory | 625344 kb |
| Host | smart-6f36b32c-ee72-4e29-a39a-951907182cc9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615839775 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2615839775 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.287663978 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 8317837069 ps |
| CPU time | 1341.41 seconds |
| Started | Jul 25 08:28:45 PM PDT 24 |
| Finished | Jul 25 08:51:07 PM PDT 24 |
| Peak memory | 625376 kb |
| Host | smart-babd2d07-eab5-4406-89db-0e66cc6dcc96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287663978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq.287663978 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.907582918 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 4488561085 ps |
| CPU time | 534.18 seconds |
| Started | Jul 25 08:28:21 PM PDT 24 |
| Finished | Jul 25 08:37:16 PM PDT 24 |
| Peak memory | 625384 kb |
| Host | smart-7cd286be-cfad-43d2-bc9a-4a12a9f6321c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907582918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.907582918 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.601623306 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3945885800 ps |
| CPU time | 577.88 seconds |
| Started | Jul 25 08:27:08 PM PDT 24 |
| Finished | Jul 25 08:36:46 PM PDT 24 |
| Peak memory | 625372 kb |
| Host | smart-491af912-a379-4e6d-8913-159e15ff418e |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601623306 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.601623306 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.978153431 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4206575560 ps |
| CPU time | 603.89 seconds |
| Started | Jul 25 08:26:14 PM PDT 24 |
| Finished | Jul 25 08:36:18 PM PDT 24 |
| Peak memory | 625372 kb |
| Host | smart-3e2609d4-4601-4c20-b71f-a23b7c6ba70c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978153431 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.978153431 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1543589759 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 3710138936 ps |
| CPU time | 614.87 seconds |
| Started | Jul 25 08:28:23 PM PDT 24 |
| Finished | Jul 25 08:38:38 PM PDT 24 |
| Peak memory | 625428 kb |
| Host | smart-2ee6aac8-4df2-449a-b6d0-d0d8c64e5fbf |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543589759 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1543589759 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.496910849 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2431917620 ps |
| CPU time | 180.17 seconds |
| Started | Jul 25 08:27:37 PM PDT 24 |
| Finished | Jul 25 08:30:38 PM PDT 24 |
| Peak memory | 622248 kb |
| Host | smart-750f6913-2570-48bd-bc0d-9118fb76f05d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=496910849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.496910849 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.1707394333 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 11553433697 ps |
| CPU time | 1017.34 seconds |
| Started | Jul 25 08:26:49 PM PDT 24 |
| Finished | Jul 25 08:43:46 PM PDT 24 |
| Peak memory | 621724 kb |
| Host | smart-c4884d63-be4b-4f8d-bf57-1eaf91515b4e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707394333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1707394333 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.755164935 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 5360885920 ps |
| CPU time | 500.53 seconds |
| Started | Jul 25 08:26:44 PM PDT 24 |
| Finished | Jul 25 08:35:05 PM PDT 24 |
| Peak memory | 624208 kb |
| Host | smart-6fc0a357-9ae0-4f2f-a89b-7b17a386ff19 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755164935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.755164935 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.765178586 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5090171800 ps |
| CPU time | 592.32 seconds |
| Started | Jul 25 08:32:47 PM PDT 24 |
| Finished | Jul 25 08:42:40 PM PDT 24 |
| Peak memory | 650700 kb |
| Host | smart-bf4c2c72-7490-4eb4-b50e-55a9e7ee636c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 765178586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.765178586 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4264888329 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3139764756 ps |
| CPU time | 373.3 seconds |
| Started | Jul 25 08:36:43 PM PDT 24 |
| Finished | Jul 25 08:42:57 PM PDT 24 |
| Peak memory | 649564 kb |
| Host | smart-19f9e736-6752-48cd-8325-8ddb1788e362 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264888329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4264888329 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2475102581 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4814602016 ps |
| CPU time | 712.77 seconds |
| Started | Jul 25 08:35:04 PM PDT 24 |
| Finished | Jul 25 08:46:58 PM PDT 24 |
| Peak memory | 650592 kb |
| Host | smart-cbf721ff-7f7a-4dbb-9fff-ca3d7a72b751 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2475102581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2475102581 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215354224 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3772617792 ps |
| CPU time | 461.74 seconds |
| Started | Jul 25 08:33:26 PM PDT 24 |
| Finished | Jul 25 08:41:08 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-17e42514-9d7e-4caf-af50-347f5a974e6d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215354224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1215354224 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1140892219 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3485820522 ps |
| CPU time | 355.3 seconds |
| Started | Jul 25 08:33:23 PM PDT 24 |
| Finished | Jul 25 08:39:18 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-47d94706-9216-45ef-b46c-92d0786de468 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140892219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1140892219 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.1034595740 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5430765156 ps |
| CPU time | 658.67 seconds |
| Started | Jul 25 08:32:39 PM PDT 24 |
| Finished | Jul 25 08:43:38 PM PDT 24 |
| Peak memory | 620404 kb |
| Host | smart-77cbc504-6569-4ffc-8ce4-892c21b27cab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1034595740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1034595740 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1756633113 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 3437435000 ps |
| CPU time | 378.26 seconds |
| Started | Jul 25 08:32:54 PM PDT 24 |
| Finished | Jul 25 08:39:12 PM PDT 24 |
| Peak memory | 649316 kb |
| Host | smart-50b39528-a3b9-4daa-8044-dd338d4ad180 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756633113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1756633113 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1355288509 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3546805842 ps |
| CPU time | 419.01 seconds |
| Started | Jul 25 08:34:19 PM PDT 24 |
| Finished | Jul 25 08:41:18 PM PDT 24 |
| Peak memory | 649472 kb |
| Host | smart-176e19e2-9f0f-4a5b-be6f-b07d3a9b83ff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355288509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1355288509 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.1554450905 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4821990926 ps |
| CPU time | 598.23 seconds |
| Started | Jul 25 08:35:39 PM PDT 24 |
| Finished | Jul 25 08:45:38 PM PDT 24 |
| Peak memory | 650672 kb |
| Host | smart-851f27b6-e4d4-43f9-a0f9-ee3fa61c3541 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1554450905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.1554450905 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3235843817 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5141826612 ps |
| CPU time | 884.94 seconds |
| Started | Jul 25 08:33:54 PM PDT 24 |
| Finished | Jul 25 08:48:39 PM PDT 24 |
| Peak memory | 650556 kb |
| Host | smart-0a8c3b86-0aca-4a7b-abbc-e9e3923527c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3235843817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3235843817 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.103665512 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 5122379288 ps |
| CPU time | 561.23 seconds |
| Started | Jul 25 08:36:10 PM PDT 24 |
| Finished | Jul 25 08:45:31 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-9144eecb-4800-48ac-a92e-11188c9847fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 103665512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.103665512 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872558892 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3817792560 ps |
| CPU time | 399.51 seconds |
| Started | Jul 25 08:37:17 PM PDT 24 |
| Finished | Jul 25 08:43:57 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-1966c7a6-e69d-47eb-bfc1-20e5b4b461b9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872558892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1872558892 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.2356573030 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4894913662 ps |
| CPU time | 629.23 seconds |
| Started | Jul 25 08:37:03 PM PDT 24 |
| Finished | Jul 25 08:47:33 PM PDT 24 |
| Peak memory | 650916 kb |
| Host | smart-4515856f-07a2-4175-a9b7-cd613a482842 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2356573030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2356573030 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.433753910 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 3099790452 ps |
| CPU time | 449.29 seconds |
| Started | Jul 25 08:34:25 PM PDT 24 |
| Finished | Jul 25 08:41:55 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-4adff27f-cfa7-430f-85fa-7a094d010c6f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433753910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_s w_alert_handler_lpg_sleep_mode_alerts.433753910 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.4228237997 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5458084468 ps |
| CPU time | 471.32 seconds |
| Started | Jul 25 08:34:05 PM PDT 24 |
| Finished | Jul 25 08:41:57 PM PDT 24 |
| Peak memory | 620516 kb |
| Host | smart-1644dd18-1a8d-42ef-a854-562281e3c5bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4228237997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.4228237997 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.90287463 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4918863798 ps |
| CPU time | 532.12 seconds |
| Started | Jul 25 08:27:34 PM PDT 24 |
| Finished | Jul 25 08:36:26 PM PDT 24 |
| Peak memory | 650676 kb |
| Host | smart-b26a9b4d-9cea-4766-a6be-0a73dddede0b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 90287463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.90287463 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3011216668 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 18079555376 ps |
| CPU time | 3529.33 seconds |
| Started | Jul 25 08:29:32 PM PDT 24 |
| Finished | Jul 25 09:28:22 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-f062c871-719d-4c5c-97ce-266183b8a8e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011216668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3011216668 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2091030455 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 6345015900 ps |
| CPU time | 821.87 seconds |
| Started | Jul 25 08:28:10 PM PDT 24 |
| Finished | Jul 25 08:41:52 PM PDT 24 |
| Peak memory | 611452 kb |
| Host | smart-80d5d1b3-b383-47af-875d-4d5473724fde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2091030455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2091030455 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1918585074 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 5110535310 ps |
| CPU time | 457.98 seconds |
| Started | Jul 25 08:28:36 PM PDT 24 |
| Finished | Jul 25 08:36:14 PM PDT 24 |
| Peak memory | 621108 kb |
| Host | smart-e63ff018-58fe-4050-9159-b43aaed294d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918585074 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1918585074 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.663747725 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 8359759326 ps |
| CPU time | 1334.34 seconds |
| Started | Jul 25 08:29:52 PM PDT 24 |
| Finished | Jul 25 08:52:07 PM PDT 24 |
| Peak memory | 619584 kb |
| Host | smart-efc40e2a-6d75-4882-9e75-b1cbbec94b53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=663747725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.663747725 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.634695754 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3283738562 ps |
| CPU time | 384.78 seconds |
| Started | Jul 25 08:34:05 PM PDT 24 |
| Finished | Jul 25 08:40:30 PM PDT 24 |
| Peak memory | 649460 kb |
| Host | smart-27b781bc-3894-4193-9c5a-f3c5c8abb07e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634695754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s w_alert_handler_lpg_sleep_mode_alerts.634695754 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.3300927824 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5339333438 ps |
| CPU time | 654.57 seconds |
| Started | Jul 25 08:34:42 PM PDT 24 |
| Finished | Jul 25 08:45:37 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-6797c1c5-f0ca-48d1-807d-1047a4354513 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3300927824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3300927824 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124833428 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3839359998 ps |
| CPU time | 449.98 seconds |
| Started | Jul 25 08:33:43 PM PDT 24 |
| Finished | Jul 25 08:41:13 PM PDT 24 |
| Peak memory | 649152 kb |
| Host | smart-d754835b-27dd-4b33-9735-0cbb7e73125b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124833428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2124833428 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.318137 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5429258264 ps |
| CPU time | 449.13 seconds |
| Started | Jul 25 08:34:34 PM PDT 24 |
| Finished | Jul 25 08:42:03 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-8356d4f8-e6b1-4331-bdc3-879a987bf461 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 318137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.318137 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697453125 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3747889280 ps |
| CPU time | 329.65 seconds |
| Started | Jul 25 08:34:42 PM PDT 24 |
| Finished | Jul 25 08:40:11 PM PDT 24 |
| Peak memory | 649316 kb |
| Host | smart-a2c7a399-be79-45a2-b0b7-67882333e3a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697453125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2697453125 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.4029714492 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 4825756160 ps |
| CPU time | 455.59 seconds |
| Started | Jul 25 08:33:21 PM PDT 24 |
| Finished | Jul 25 08:40:57 PM PDT 24 |
| Peak memory | 650656 kb |
| Host | smart-b38f28c0-e90e-410d-8fbb-3ac5a564dc2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4029714492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.4029714492 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2669794384 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4271468180 ps |
| CPU time | 566.67 seconds |
| Started | Jul 25 08:33:56 PM PDT 24 |
| Finished | Jul 25 08:43:23 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-616b5534-0622-43cf-b826-e5aeb0824e28 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669794384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2669794384 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.2108487161 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5704650400 ps |
| CPU time | 667.66 seconds |
| Started | Jul 25 08:33:55 PM PDT 24 |
| Finished | Jul 25 08:45:03 PM PDT 24 |
| Peak memory | 650356 kb |
| Host | smart-3594b34d-703a-4018-b216-7efa38d4731b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2108487161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2108487161 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.3226059516 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 4638178912 ps |
| CPU time | 613.69 seconds |
| Started | Jul 25 08:34:41 PM PDT 24 |
| Finished | Jul 25 08:44:54 PM PDT 24 |
| Peak memory | 620508 kb |
| Host | smart-7c39985b-5411-483e-8c6f-74d195b10f57 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3226059516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3226059516 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1522259028 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3643415820 ps |
| CPU time | 426.99 seconds |
| Started | Jul 25 08:34:38 PM PDT 24 |
| Finished | Jul 25 08:41:45 PM PDT 24 |
| Peak memory | 649452 kb |
| Host | smart-c5d8a9d4-a593-45f3-9a64-2af323acf507 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522259028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1522259028 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.1316471273 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4686444364 ps |
| CPU time | 688.65 seconds |
| Started | Jul 25 08:33:52 PM PDT 24 |
| Finished | Jul 25 08:45:21 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-3cf70fa6-f760-418f-8428-5ec30c7cabfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1316471273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1316471273 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879000365 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 3402987360 ps |
| CPU time | 375.43 seconds |
| Started | Jul 25 08:28:20 PM PDT 24 |
| Finished | Jul 25 08:34:35 PM PDT 24 |
| Peak memory | 649304 kb |
| Host | smart-7c6d06c1-1e1b-4ca2-b2e8-43f3c2ed6e48 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879000365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3879000365 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.878876263 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4484878836 ps |
| CPU time | 521.51 seconds |
| Started | Jul 25 08:27:59 PM PDT 24 |
| Finished | Jul 25 08:36:41 PM PDT 24 |
| Peak memory | 650596 kb |
| Host | smart-b8079a25-0de1-4da6-98e4-73bbe9f192dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 878876263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.878876263 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.860141985 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 18015863200 ps |
| CPU time | 3717.01 seconds |
| Started | Jul 25 08:28:04 PM PDT 24 |
| Finished | Jul 25 09:30:02 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-0a1c3a9c-48f5-40a3-89cc-6205f85590a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860141985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.860141985 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3179915402 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 12348993325 ps |
| CPU time | 882.64 seconds |
| Started | Jul 25 08:27:50 PM PDT 24 |
| Finished | Jul 25 08:42:33 PM PDT 24 |
| Peak memory | 621100 kb |
| Host | smart-d3f891a4-94b6-4b3d-a9e6-b6133ca86d94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179915402 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3179915402 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2285837377 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 13445007480 ps |
| CPU time | 2817.41 seconds |
| Started | Jul 25 08:27:45 PM PDT 24 |
| Finished | Jul 25 09:14:43 PM PDT 24 |
| Peak memory | 623880 kb |
| Host | smart-4f01aeea-dc2b-4cd6-b34c-97f2281f013d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2285837377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2285837377 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2220286689 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 3902797000 ps |
| CPU time | 416.25 seconds |
| Started | Jul 25 08:34:08 PM PDT 24 |
| Finished | Jul 25 08:41:05 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-eb49379c-e063-4c3a-a492-7aa0a2ad94e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220286689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2220286689 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.45879402 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4985078128 ps |
| CPU time | 824.61 seconds |
| Started | Jul 25 08:34:09 PM PDT 24 |
| Finished | Jul 25 08:47:54 PM PDT 24 |
| Peak memory | 651052 kb |
| Host | smart-a6be9bb9-7260-49ba-9413-a582e162e0bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 45879402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.45879402 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2945268872 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3816928950 ps |
| CPU time | 338.33 seconds |
| Started | Jul 25 08:35:03 PM PDT 24 |
| Finished | Jul 25 08:40:42 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-694259a7-7bcf-48b0-8286-e5312f80329c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945268872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2945268872 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1640617423 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 6492072060 ps |
| CPU time | 628.86 seconds |
| Started | Jul 25 08:35:07 PM PDT 24 |
| Finished | Jul 25 08:45:36 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-66c547b7-7ab2-466a-82c0-1feb91b2cb95 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1640617423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1640617423 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.694852664 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3499710412 ps |
| CPU time | 456.06 seconds |
| Started | Jul 25 08:34:47 PM PDT 24 |
| Finished | Jul 25 08:42:23 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-896e35e0-b08e-47ca-9776-3e39da144cf7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694852664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_s w_alert_handler_lpg_sleep_mode_alerts.694852664 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.2265755383 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4419513684 ps |
| CPU time | 588.55 seconds |
| Started | Jul 25 08:34:12 PM PDT 24 |
| Finished | Jul 25 08:44:01 PM PDT 24 |
| Peak memory | 650576 kb |
| Host | smart-62d7794f-377a-4d27-b278-bce70ef4b491 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2265755383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2265755383 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3291803312 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5622840042 ps |
| CPU time | 500.08 seconds |
| Started | Jul 25 08:34:23 PM PDT 24 |
| Finished | Jul 25 08:42:43 PM PDT 24 |
| Peak memory | 651004 kb |
| Host | smart-00e0f19e-d711-4717-9a87-46c645a634da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3291803312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3291803312 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458890264 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 4096875384 ps |
| CPU time | 510.92 seconds |
| Started | Jul 25 08:35:16 PM PDT 24 |
| Finished | Jul 25 08:43:47 PM PDT 24 |
| Peak memory | 649252 kb |
| Host | smart-0ee103c3-0e9f-4b5f-a82e-fdebaceded7f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458890264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1458890264 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.2454534696 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 4120970184 ps |
| CPU time | 509.3 seconds |
| Started | Jul 25 08:34:50 PM PDT 24 |
| Finished | Jul 25 08:43:20 PM PDT 24 |
| Peak memory | 620220 kb |
| Host | smart-f20f060f-6f0c-411d-8bd2-eac7535e3e6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2454534696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2454534696 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2493161017 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 6071750564 ps |
| CPU time | 628.92 seconds |
| Started | Jul 25 08:34:56 PM PDT 24 |
| Finished | Jul 25 08:45:26 PM PDT 24 |
| Peak memory | 650656 kb |
| Host | smart-03850f35-4789-4a16-9d9d-3dfbc82da5cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2493161017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2493161017 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.4116345064 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5464189930 ps |
| CPU time | 583.49 seconds |
| Started | Jul 25 08:34:44 PM PDT 24 |
| Finished | Jul 25 08:44:28 PM PDT 24 |
| Peak memory | 650728 kb |
| Host | smart-01dd2b30-633a-4c26-b577-533682ce64d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4116345064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.4116345064 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.355557894 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4953213400 ps |
| CPU time | 548.88 seconds |
| Started | Jul 25 08:34:59 PM PDT 24 |
| Finished | Jul 25 08:44:08 PM PDT 24 |
| Peak memory | 651020 kb |
| Host | smart-76934053-8525-4025-bbea-75bc9b637ed8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 355557894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.355557894 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.166104792 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4299829260 ps |
| CPU time | 491.71 seconds |
| Started | Jul 25 08:31:41 PM PDT 24 |
| Finished | Jul 25 08:39:53 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-c9e040cf-364b-4d52-8cf8-241beafd6e2a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166104792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw _alert_handler_lpg_sleep_mode_alerts.166104792 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.754820028 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 4849506248 ps |
| CPU time | 723.66 seconds |
| Started | Jul 25 08:29:17 PM PDT 24 |
| Finished | Jul 25 08:41:21 PM PDT 24 |
| Peak memory | 650656 kb |
| Host | smart-9c8a2be8-4fde-4e07-b0ea-0d1bc50b85f0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 754820028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.754820028 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4075467642 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 14167025000 ps |
| CPU time | 2811.19 seconds |
| Started | Jul 25 08:29:37 PM PDT 24 |
| Finished | Jul 25 09:16:29 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-143ab0ba-1000-46a7-8721-df62d605f010 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075467642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.4075467642 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4120117050 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 6328457972 ps |
| CPU time | 494.34 seconds |
| Started | Jul 25 08:29:59 PM PDT 24 |
| Finished | Jul 25 08:38:13 PM PDT 24 |
| Peak memory | 621144 kb |
| Host | smart-fc38b7cc-fa41-4ee3-a038-77e602330763 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120117050 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.4120117050 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2400254843 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8382192608 ps |
| CPU time | 1253.84 seconds |
| Started | Jul 25 08:29:56 PM PDT 24 |
| Finished | Jul 25 08:50:51 PM PDT 24 |
| Peak memory | 623860 kb |
| Host | smart-190b0377-a547-43e9-92da-a2d646929d30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2400254843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2400254843 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1933620005 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 4393775600 ps |
| CPU time | 406.45 seconds |
| Started | Jul 25 08:36:43 PM PDT 24 |
| Finished | Jul 25 08:43:29 PM PDT 24 |
| Peak memory | 649596 kb |
| Host | smart-ee4c65a1-ae17-4d09-9189-287275f74aef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933620005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1933620005 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.2831254836 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5262554294 ps |
| CPU time | 477.62 seconds |
| Started | Jul 25 08:36:23 PM PDT 24 |
| Finished | Jul 25 08:44:21 PM PDT 24 |
| Peak memory | 650904 kb |
| Host | smart-a575bb43-f09d-4852-96ad-7374c1d21511 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2831254836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2831254836 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1051913849 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4159682028 ps |
| CPU time | 389.24 seconds |
| Started | Jul 25 08:36:24 PM PDT 24 |
| Finished | Jul 25 08:42:53 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-d5c818ce-f9fb-4c3a-9ac4-94063ad02f69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051913849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1051913849 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2107454688 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5296203154 ps |
| CPU time | 635.1 seconds |
| Started | Jul 25 08:36:53 PM PDT 24 |
| Finished | Jul 25 08:47:28 PM PDT 24 |
| Peak memory | 650600 kb |
| Host | smart-7bbe1ddb-a986-4d5d-ab74-6d0121665a4a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2107454688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2107454688 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749649662 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 4149144768 ps |
| CPU time | 386.22 seconds |
| Started | Jul 25 08:36:01 PM PDT 24 |
| Finished | Jul 25 08:42:27 PM PDT 24 |
| Peak memory | 649588 kb |
| Host | smart-84436f5c-41b9-437f-8ea7-bf798e9627ee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749649662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1749649662 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.325701059 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 6086643780 ps |
| CPU time | 609.03 seconds |
| Started | Jul 25 08:36:55 PM PDT 24 |
| Finished | Jul 25 08:47:05 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-9eb7e4e3-c57b-4ce5-a8c8-99789a85b99b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 325701059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.325701059 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033006936 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3429376500 ps |
| CPU time | 302.73 seconds |
| Started | Jul 25 08:37:05 PM PDT 24 |
| Finished | Jul 25 08:42:08 PM PDT 24 |
| Peak memory | 649280 kb |
| Host | smart-9e431d62-f0b8-4c67-8676-940b955974af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033006936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3033006936 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.105071953 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4957024892 ps |
| CPU time | 684.84 seconds |
| Started | Jul 25 08:36:53 PM PDT 24 |
| Finished | Jul 25 08:48:18 PM PDT 24 |
| Peak memory | 650596 kb |
| Host | smart-41304899-7a28-4e4a-b196-2860e974b846 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 105071953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.105071953 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965728673 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3552422536 ps |
| CPU time | 368.98 seconds |
| Started | Jul 25 08:35:40 PM PDT 24 |
| Finished | Jul 25 08:41:50 PM PDT 24 |
| Peak memory | 649160 kb |
| Host | smart-201b497d-a910-4fd7-b37f-e220206c859a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965728673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3965728673 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2370952426 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4707266092 ps |
| CPU time | 724.97 seconds |
| Started | Jul 25 08:36:34 PM PDT 24 |
| Finished | Jul 25 08:48:39 PM PDT 24 |
| Peak memory | 650352 kb |
| Host | smart-042c6457-4c7b-4e0a-873b-13113e310b09 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2370952426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2370952426 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2497511487 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 4158836928 ps |
| CPU time | 393.55 seconds |
| Started | Jul 25 08:41:11 PM PDT 24 |
| Finished | Jul 25 08:47:45 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-5da95a65-7e59-444e-a059-2bdefaf3aa5f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497511487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2497511487 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2591456505 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5370413506 ps |
| CPU time | 713.62 seconds |
| Started | Jul 25 08:36:57 PM PDT 24 |
| Finished | Jul 25 08:48:51 PM PDT 24 |
| Peak memory | 650564 kb |
| Host | smart-8bead6eb-b8a6-407d-b698-0ce45e65e1a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2591456505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2591456505 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.248161496 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 4248593458 ps |
| CPU time | 413.99 seconds |
| Started | Jul 25 08:41:00 PM PDT 24 |
| Finished | Jul 25 08:47:54 PM PDT 24 |
| Peak memory | 649616 kb |
| Host | smart-06e37adf-75e3-4724-8038-59e3f70c936f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248161496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_s w_alert_handler_lpg_sleep_mode_alerts.248161496 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1858454029 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4271215180 ps |
| CPU time | 603.09 seconds |
| Started | Jul 25 08:36:28 PM PDT 24 |
| Finished | Jul 25 08:46:32 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-660d6903-b78f-4ced-bab6-db039b366008 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1858454029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1858454029 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2308240286 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3972504390 ps |
| CPU time | 386.28 seconds |
| Started | Jul 25 08:37:45 PM PDT 24 |
| Finished | Jul 25 08:44:12 PM PDT 24 |
| Peak memory | 649640 kb |
| Host | smart-ae29e6ab-4ad5-470e-89c0-2f0c1a6fa880 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308240286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2308240286 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.2622293870 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4439749804 ps |
| CPU time | 383.53 seconds |
| Started | Jul 25 08:36:31 PM PDT 24 |
| Finished | Jul 25 08:42:55 PM PDT 24 |
| Peak memory | 650356 kb |
| Host | smart-a0c0061e-ee1e-4caa-a818-974288955ffc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2622293870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2622293870 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413777053 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3924473952 ps |
| CPU time | 288.98 seconds |
| Started | Jul 25 08:35:52 PM PDT 24 |
| Finished | Jul 25 08:40:41 PM PDT 24 |
| Peak memory | 650028 kb |
| Host | smart-19b5d74f-09b6-4085-9c6a-8e5cfc33dc2e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413777053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3413777053 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1957819846 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5918617352 ps |
| CPU time | 534.99 seconds |
| Started | Jul 25 08:36:07 PM PDT 24 |
| Finished | Jul 25 08:45:02 PM PDT 24 |
| Peak memory | 650696 kb |
| Host | smart-1d8ec4bb-04cb-414b-8b54-69bf8fbcd391 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1957819846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1957819846 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3254826995 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3677467432 ps |
| CPU time | 361.7 seconds |
| Started | Jul 25 08:37:46 PM PDT 24 |
| Finished | Jul 25 08:43:48 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-e964df68-7010-441f-8baa-55e619c0b12b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254826995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3254826995 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.2351635385 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 6115592800 ps |
| CPU time | 524.86 seconds |
| Started | Jul 25 08:37:31 PM PDT 24 |
| Finished | Jul 25 08:46:16 PM PDT 24 |
| Peak memory | 650540 kb |
| Host | smart-f8128adb-7c35-4fd7-9f5f-40a96be12a63 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2351635385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2351635385 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.827605943 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 21342088760 ps |
| CPU time | 3888.43 seconds |
| Started | Jul 25 08:28:54 PM PDT 24 |
| Finished | Jul 25 09:33:43 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-0d11f5f1-a3ba-4e85-bc8f-ccc8897490d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827605943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.827605943 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2193480137 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 12496610200 ps |
| CPU time | 749.22 seconds |
| Started | Jul 25 08:29:12 PM PDT 24 |
| Finished | Jul 25 08:41:41 PM PDT 24 |
| Peak memory | 621624 kb |
| Host | smart-10b7061e-6377-487e-9064-6ead96af0dbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193480137 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.2193480137 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1327453278 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 8655862644 ps |
| CPU time | 1835.67 seconds |
| Started | Jul 25 08:29:34 PM PDT 24 |
| Finished | Jul 25 09:00:11 PM PDT 24 |
| Peak memory | 619576 kb |
| Host | smart-d41d661e-9f73-4808-9a99-9abd3f54142d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1327453278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.1327453278 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.791086172 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 4027322850 ps |
| CPU time | 374.61 seconds |
| Started | Jul 25 08:36:38 PM PDT 24 |
| Finished | Jul 25 08:42:53 PM PDT 24 |
| Peak memory | 649152 kb |
| Host | smart-f717424f-0e13-4e94-97eb-dd9e869ee8ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791086172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.791086172 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.572127961 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3829823996 ps |
| CPU time | 308.57 seconds |
| Started | Jul 25 08:37:43 PM PDT 24 |
| Finished | Jul 25 08:42:52 PM PDT 24 |
| Peak memory | 649612 kb |
| Host | smart-10433a49-c211-48b1-809e-060d14f01b30 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572127961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_s w_alert_handler_lpg_sleep_mode_alerts.572127961 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.2023942208 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5022288958 ps |
| CPU time | 646.11 seconds |
| Started | Jul 25 08:37:36 PM PDT 24 |
| Finished | Jul 25 08:48:23 PM PDT 24 |
| Peak memory | 620304 kb |
| Host | smart-ef5e678d-fee4-45b4-a7ca-fea9cad28ab3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2023942208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2023942208 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383145178 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3631165964 ps |
| CPU time | 406.72 seconds |
| Started | Jul 25 08:37:58 PM PDT 24 |
| Finished | Jul 25 08:44:45 PM PDT 24 |
| Peak memory | 649568 kb |
| Host | smart-b4b02b02-2d06-40df-af6e-030e6f097640 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383145178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2383145178 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.9851308 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4596853848 ps |
| CPU time | 554.57 seconds |
| Started | Jul 25 08:37:36 PM PDT 24 |
| Finished | Jul 25 08:46:51 PM PDT 24 |
| Peak memory | 651964 kb |
| Host | smart-acba85b6-4672-4ac3-aff6-16b3db25796f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 9851308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.9851308 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396168806 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3630680888 ps |
| CPU time | 283.28 seconds |
| Started | Jul 25 08:36:19 PM PDT 24 |
| Finished | Jul 25 08:41:03 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-e56c5195-95f5-49dc-9d82-4c003fd1a1b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396168806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3396168806 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1633194432 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3839100952 ps |
| CPU time | 409.62 seconds |
| Started | Jul 25 08:36:29 PM PDT 24 |
| Finished | Jul 25 08:43:18 PM PDT 24 |
| Peak memory | 649688 kb |
| Host | smart-090d98ec-1482-4e00-b7f8-f98f181d3822 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633194432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1633194432 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.649365129 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5328059330 ps |
| CPU time | 534.95 seconds |
| Started | Jul 25 08:36:33 PM PDT 24 |
| Finished | Jul 25 08:45:28 PM PDT 24 |
| Peak memory | 650648 kb |
| Host | smart-ecfbe2c0-4869-4b36-992d-f4e2d7bbca37 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 649365129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.649365129 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4290874560 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3560622288 ps |
| CPU time | 384.15 seconds |
| Started | Jul 25 08:37:17 PM PDT 24 |
| Finished | Jul 25 08:43:42 PM PDT 24 |
| Peak memory | 649704 kb |
| Host | smart-aa2ab697-5a0d-4cca-a6e1-aa487ed95761 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290874560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4290874560 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.3888264917 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 4916144200 ps |
| CPU time | 581.02 seconds |
| Started | Jul 25 08:38:24 PM PDT 24 |
| Finished | Jul 25 08:48:05 PM PDT 24 |
| Peak memory | 620464 kb |
| Host | smart-1ad5541d-63c2-474f-b7f0-7d888a8a15b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3888264917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.3888264917 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1309420591 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4296399928 ps |
| CPU time | 346.83 seconds |
| Started | Jul 25 08:37:07 PM PDT 24 |
| Finished | Jul 25 08:42:54 PM PDT 24 |
| Peak memory | 649740 kb |
| Host | smart-dffb337c-cd1f-4c14-8c05-2f56b3de7d87 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309420591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1309420591 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1585840039 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5273916700 ps |
| CPU time | 412.42 seconds |
| Started | Jul 25 08:36:38 PM PDT 24 |
| Finished | Jul 25 08:43:31 PM PDT 24 |
| Peak memory | 650644 kb |
| Host | smart-4648e087-2f24-41ef-88b4-0e0bad59c8f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1585840039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1585840039 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411184619 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 4373640434 ps |
| CPU time | 456.31 seconds |
| Started | Jul 25 08:37:36 PM PDT 24 |
| Finished | Jul 25 08:45:12 PM PDT 24 |
| Peak memory | 649480 kb |
| Host | smart-f03d8aa6-fb82-4cc8-831f-52ef1b222d39 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411184619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1411184619 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.3556596011 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4931796908 ps |
| CPU time | 554.28 seconds |
| Started | Jul 25 08:38:33 PM PDT 24 |
| Finished | Jul 25 08:47:48 PM PDT 24 |
| Peak memory | 650632 kb |
| Host | smart-242a50c3-364b-4480-93ad-add25b25f349 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3556596011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3556596011 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.314772729 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 5494790648 ps |
| CPU time | 615.88 seconds |
| Started | Jul 25 08:37:10 PM PDT 24 |
| Finished | Jul 25 08:47:27 PM PDT 24 |
| Peak memory | 650552 kb |
| Host | smart-dec2f654-266f-426d-9fd0-3f6a3bed25df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 314772729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.314772729 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3600914862 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3223463612 ps |
| CPU time | 304.45 seconds |
| Started | Jul 25 08:28:56 PM PDT 24 |
| Finished | Jul 25 08:34:01 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-708ff951-56f0-4872-aa17-2efb7629bad7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600914862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.3600914862 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.617833300 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 6039807384 ps |
| CPU time | 687.7 seconds |
| Started | Jul 25 08:28:07 PM PDT 24 |
| Finished | Jul 25 08:39:35 PM PDT 24 |
| Peak memory | 650612 kb |
| Host | smart-cd76d4bc-37f1-41d0-b3e2-f85628569ed6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 617833300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.617833300 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1368741770 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 20255616894 ps |
| CPU time | 4252.91 seconds |
| Started | Jul 25 08:29:17 PM PDT 24 |
| Finished | Jul 25 09:40:10 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-67ab5f59-9e96-480b-86b4-e9afe7d76f19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368741770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1368741770 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1431682011 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3496229434 ps |
| CPU time | 458.88 seconds |
| Started | Jul 25 08:31:04 PM PDT 24 |
| Finished | Jul 25 08:38:43 PM PDT 24 |
| Peak memory | 619556 kb |
| Host | smart-43c2e3c8-ee5a-48a6-91cd-16d4c2779910 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1431682011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1431682011 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3435897808 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 6081208396 ps |
| CPU time | 457.42 seconds |
| Started | Jul 25 08:37:29 PM PDT 24 |
| Finished | Jul 25 08:45:07 PM PDT 24 |
| Peak memory | 650624 kb |
| Host | smart-21c77678-9582-4736-80c7-07ccfbff339d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3435897808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3435897808 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3674568620 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4318068682 ps |
| CPU time | 573.49 seconds |
| Started | Jul 25 08:36:56 PM PDT 24 |
| Finished | Jul 25 08:46:30 PM PDT 24 |
| Peak memory | 650624 kb |
| Host | smart-d95f18fd-f9da-41da-9359-7fc12cd6f2a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3674568620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3674568620 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.65539851 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4917663728 ps |
| CPU time | 534.01 seconds |
| Started | Jul 25 08:37:24 PM PDT 24 |
| Finished | Jul 25 08:46:19 PM PDT 24 |
| Peak memory | 650388 kb |
| Host | smart-3cc0ca33-b231-49b0-b969-ce81889c6aa4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 65539851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.65539851 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1568891083 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 6498064060 ps |
| CPU time | 619.33 seconds |
| Started | Jul 25 08:41:45 PM PDT 24 |
| Finished | Jul 25 08:52:04 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-c8d59450-d2a2-48e2-89bd-d4449da0d664 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1568891083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1568891083 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.1206089411 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4978003260 ps |
| CPU time | 603.21 seconds |
| Started | Jul 25 08:37:16 PM PDT 24 |
| Finished | Jul 25 08:47:19 PM PDT 24 |
| Peak memory | 650560 kb |
| Host | smart-aaf7c5df-7952-4310-8588-48796dc69fec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1206089411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1206089411 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.3222453662 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 4962573820 ps |
| CPU time | 438.8 seconds |
| Started | Jul 25 08:38:15 PM PDT 24 |
| Finished | Jul 25 08:45:34 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-d036cbb7-f7f7-4842-8be5-6c690c9f7e3a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3222453662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.3222453662 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.4069155680 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5734943968 ps |
| CPU time | 604.1 seconds |
| Started | Jul 25 08:38:27 PM PDT 24 |
| Finished | Jul 25 08:48:32 PM PDT 24 |
| Peak memory | 650360 kb |
| Host | smart-b5bc8a12-d033-4f81-90f0-302bc3efc060 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4069155680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.4069155680 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4115801926 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4546432004 ps |
| CPU time | 298.73 seconds |
| Started | Jul 25 08:30:47 PM PDT 24 |
| Finished | Jul 25 08:35:46 PM PDT 24 |
| Peak memory | 657864 kb |
| Host | smart-3bcaaf66-b574-47fc-b85d-472c98db4e17 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115801926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.4115801926 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3705948219 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5873162310 ps |
| CPU time | 280.84 seconds |
| Started | Jul 25 08:31:02 PM PDT 24 |
| Finished | Jul 25 08:35:43 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-b285a02c-43c3-4e0b-a350-c5253378822e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705948219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3705948219 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1150904826 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4352824320 ps |
| CPU time | 229.68 seconds |
| Started | Jul 25 08:31:17 PM PDT 24 |
| Finished | Jul 25 08:35:07 PM PDT 24 |
| Peak memory | 641496 kb |
| Host | smart-101f81a9-39f3-4f32-b44d-bc10d2fdd98a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150904826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1150904826 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2082634224 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5202929364 ps |
| CPU time | 306.4 seconds |
| Started | Jul 25 08:31:04 PM PDT 24 |
| Finished | Jul 25 08:36:11 PM PDT 24 |
| Peak memory | 654412 kb |
| Host | smart-1f41f508-b55a-4291-bc30-c5ba9ec14921 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082634224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.2082634224 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.242727893 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6005704998 ps |
| CPU time | 317.68 seconds |
| Started | Jul 25 08:31:13 PM PDT 24 |
| Finished | Jul 25 08:36:31 PM PDT 24 |
| Peak memory | 641492 kb |
| Host | smart-079a43cc-be5d-46fb-8de5-555737812d14 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242727893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 6.chip_padctrl_attributes.242727893 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.65676072 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4944049292 ps |
| CPU time | 261.56 seconds |
| Started | Jul 25 08:31:07 PM PDT 24 |
| Finished | Jul 25 08:35:29 PM PDT 24 |
| Peak memory | 657364 kb |
| Host | smart-65f85f6f-f313-402d-8362-4295f31354c2 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65676072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 7.chip_padctrl_attributes.65676072 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2480218275 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5945794116 ps |
| CPU time | 353.03 seconds |
| Started | Jul 25 08:31:04 PM PDT 24 |
| Finished | Jul 25 08:36:57 PM PDT 24 |
| Peak memory | 657848 kb |
| Host | smart-d52d6a1e-eb16-4677-a60a-9e5d644ff1d6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480218275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2480218275 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.791700569 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5684102042 ps |
| CPU time | 273.91 seconds |
| Started | Jul 25 08:31:15 PM PDT 24 |
| Finished | Jul 25 08:35:49 PM PDT 24 |
| Peak memory | 649752 kb |
| Host | smart-2eb1ed13-c8d1-4168-9b72-e1f508210baf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791700569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 9.chip_padctrl_attributes.791700569 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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