| T1032 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3249693439 |
|
|
Jul 25 08:10:58 PM PDT 24 |
Jul 25 08:23:01 PM PDT 24 |
4764528520 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3616680978 |
|
|
Jul 25 08:17:57 PM PDT 24 |
Jul 25 08:54:44 PM PDT 24 |
8336113333 ps |
| T777 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.90287463 |
|
|
Jul 25 08:27:34 PM PDT 24 |
Jul 25 08:36:26 PM PDT 24 |
4918863798 ps |
| T668 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1899922785 |
|
|
Jul 25 08:07:32 PM PDT 24 |
Jul 25 08:13:20 PM PDT 24 |
2918643472 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2751199759 |
|
|
Jul 25 08:02:13 PM PDT 24 |
Jul 25 08:20:34 PM PDT 24 |
10710779806 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.410609043 |
|
|
Jul 25 08:03:37 PM PDT 24 |
Jul 25 08:17:29 PM PDT 24 |
4952547224 ps |
| T725 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.199425081 |
|
|
Jul 25 08:32:22 PM PDT 24 |
Jul 25 08:44:21 PM PDT 24 |
4573034100 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_edn_kat.225694329 |
|
|
Jul 25 08:21:27 PM PDT 24 |
Jul 25 08:34:26 PM PDT 24 |
3920354150 ps |
| T1036 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1904589167 |
|
|
Jul 25 08:27:44 PM PDT 24 |
Jul 25 10:14:19 PM PDT 24 |
26983338636 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1016525924 |
|
|
Jul 25 08:07:24 PM PDT 24 |
Jul 25 08:21:13 PM PDT 24 |
4030540250 ps |
| T1038 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4211882970 |
|
|
Jul 25 08:32:04 PM PDT 24 |
Jul 25 08:44:45 PM PDT 24 |
4818447450 ps |
| T1039 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2799009802 |
|
|
Jul 25 08:17:17 PM PDT 24 |
Jul 25 08:21:05 PM PDT 24 |
3432494244 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1895774033 |
|
|
Jul 25 08:01:48 PM PDT 24 |
Jul 25 08:09:57 PM PDT 24 |
19247572190 ps |
| T1041 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.1404023762 |
|
|
Jul 25 08:34:34 PM PDT 24 |
Jul 25 09:46:21 PM PDT 24 |
15075554545 ps |
| T1042 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.127077591 |
|
|
Jul 25 08:30:10 PM PDT 24 |
Jul 25 08:46:02 PM PDT 24 |
12348104642 ps |
| T765 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.4069155680 |
|
|
Jul 25 08:38:27 PM PDT 24 |
Jul 25 08:48:32 PM PDT 24 |
5734943968 ps |
| T1043 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2225528050 |
|
|
Jul 25 08:31:19 PM PDT 24 |
Jul 25 08:42:49 PM PDT 24 |
5361958180 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.131518048 |
|
|
Jul 25 08:24:21 PM PDT 24 |
Jul 25 08:58:46 PM PDT 24 |
11988360417 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2845504475 |
|
|
Jul 25 08:09:05 PM PDT 24 |
Jul 25 08:36:35 PM PDT 24 |
6891940328 ps |
| T1045 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3249011727 |
|
|
Jul 25 08:06:18 PM PDT 24 |
Jul 25 08:11:55 PM PDT 24 |
2664036912 ps |
| T1046 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.1897877165 |
|
|
Jul 25 08:01:14 PM PDT 24 |
Jul 25 08:07:20 PM PDT 24 |
2753927695 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.36128806 |
|
|
Jul 25 08:08:53 PM PDT 24 |
Jul 25 08:38:09 PM PDT 24 |
21936315636 ps |
| T1047 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1723182199 |
|
|
Jul 25 08:24:36 PM PDT 24 |
Jul 25 08:26:31 PM PDT 24 |
2554466590 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2897003159 |
|
|
Jul 25 08:06:56 PM PDT 24 |
Jul 25 08:40:10 PM PDT 24 |
8756382252 ps |
| T1049 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2147506957 |
|
|
Jul 25 08:09:04 PM PDT 24 |
Jul 25 08:56:29 PM PDT 24 |
11422493441 ps |
| T1050 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3372992553 |
|
|
Jul 25 08:08:08 PM PDT 24 |
Jul 25 08:27:18 PM PDT 24 |
6038463457 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1288542454 |
|
|
Jul 25 08:02:29 PM PDT 24 |
Jul 25 08:12:52 PM PDT 24 |
5457676948 ps |
| T786 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739453657 |
|
|
Jul 25 08:34:58 PM PDT 24 |
Jul 25 08:40:24 PM PDT 24 |
3805142000 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2519670278 |
|
|
Jul 25 08:22:43 PM PDT 24 |
Jul 25 08:44:01 PM PDT 24 |
8626576970 ps |
| T339 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3130220274 |
|
|
Jul 25 08:03:15 PM PDT 24 |
Jul 25 08:13:32 PM PDT 24 |
4709614914 ps |
| T168 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3170814555 |
|
|
Jul 25 08:04:08 PM PDT 24 |
Jul 25 08:09:17 PM PDT 24 |
2986432969 ps |
| T1052 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.325701059 |
|
|
Jul 25 08:36:55 PM PDT 24 |
Jul 25 08:47:05 PM PDT 24 |
6086643780 ps |
| T1053 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.118520160 |
|
|
Jul 25 08:05:15 PM PDT 24 |
Jul 25 08:18:48 PM PDT 24 |
8073446588 ps |
| T444 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.519580724 |
|
|
Jul 25 08:08:48 PM PDT 24 |
Jul 25 08:31:03 PM PDT 24 |
7202648685 ps |
| T766 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1341178986 |
|
|
Jul 25 08:06:36 PM PDT 24 |
Jul 25 08:18:30 PM PDT 24 |
5909517890 ps |
| T776 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.900750089 |
|
|
Jul 25 08:35:16 PM PDT 24 |
Jul 25 08:41:24 PM PDT 24 |
3724011080 ps |
| T340 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2470417850 |
|
|
Jul 25 08:02:52 PM PDT 24 |
Jul 25 08:13:38 PM PDT 24 |
4536579686 ps |
| T1054 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.1267025983 |
|
|
Jul 25 08:25:32 PM PDT 24 |
Jul 25 08:30:06 PM PDT 24 |
2693309786 ps |
| T1055 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.442520179 |
|
|
Jul 25 08:08:05 PM PDT 24 |
Jul 25 08:27:39 PM PDT 24 |
6103163466 ps |
| T66 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3076166312 |
|
|
Jul 25 08:31:10 PM PDT 24 |
Jul 25 08:58:15 PM PDT 24 |
25685277936 ps |
| T757 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407759345 |
|
|
Jul 25 08:32:03 PM PDT 24 |
Jul 25 08:41:00 PM PDT 24 |
3856610712 ps |
| T1056 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2308240286 |
|
|
Jul 25 08:37:45 PM PDT 24 |
Jul 25 08:44:12 PM PDT 24 |
3972504390 ps |
| T1057 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.907582918 |
|
|
Jul 25 08:28:21 PM PDT 24 |
Jul 25 08:37:16 PM PDT 24 |
4488561085 ps |
| T1058 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.620683534 |
|
|
Jul 25 08:20:04 PM PDT 24 |
Jul 25 08:22:05 PM PDT 24 |
1957729302 ps |
| T1059 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4018843904 |
|
|
Jul 25 08:28:40 PM PDT 24 |
Jul 25 08:40:13 PM PDT 24 |
4302865056 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_aes_idle.3205127851 |
|
|
Jul 25 08:01:11 PM PDT 24 |
Jul 25 08:04:53 PM PDT 24 |
2695842400 ps |
| T1061 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.864897407 |
|
|
Jul 25 08:01:49 PM PDT 24 |
Jul 25 08:10:25 PM PDT 24 |
7271234104 ps |
| T726 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2031459171 |
|
|
Jul 25 08:39:19 PM PDT 24 |
Jul 25 08:49:21 PM PDT 24 |
5341285820 ps |
| T1062 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2669724935 |
|
|
Jul 25 08:12:21 PM PDT 24 |
Jul 25 09:17:25 PM PDT 24 |
16033252704 ps |
| T1063 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.358976168 |
|
|
Jul 25 08:08:39 PM PDT 24 |
Jul 25 08:13:55 PM PDT 24 |
3394660174 ps |
| T1064 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2467962987 |
|
|
Jul 25 08:10:20 PM PDT 24 |
Jul 25 08:24:01 PM PDT 24 |
8291326870 ps |
| T225 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4030150378 |
|
|
Jul 25 08:07:59 PM PDT 24 |
Jul 25 09:18:40 PM PDT 24 |
20070347511 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.217422567 |
|
|
Jul 25 08:23:19 PM PDT 24 |
Jul 25 08:27:21 PM PDT 24 |
3542096336 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3500067940 |
|
|
Jul 25 08:18:06 PM PDT 24 |
Jul 25 08:31:00 PM PDT 24 |
5964164768 ps |
| T277 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.728824127 |
|
|
Jul 25 08:08:08 PM PDT 24 |
Jul 25 08:34:13 PM PDT 24 |
14397745900 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.321907087 |
|
|
Jul 25 08:20:47 PM PDT 24 |
Jul 25 08:27:28 PM PDT 24 |
3897400684 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.2899987362 |
|
|
Jul 25 08:16:17 PM PDT 24 |
Jul 25 08:20:37 PM PDT 24 |
3104637104 ps |
| T45 |
/workspace/coverage/default/1.chip_sw_power_virus.2121545292 |
|
|
Jul 25 08:20:55 PM PDT 24 |
Jul 25 08:43:11 PM PDT 24 |
5803400338 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2603269909 |
|
|
Jul 25 08:02:47 PM PDT 24 |
Jul 25 08:14:39 PM PDT 24 |
4513551680 ps |
| T280 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.139690178 |
|
|
Jul 25 08:22:11 PM PDT 24 |
Jul 25 08:34:07 PM PDT 24 |
5516128240 ps |
| T281 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1402614395 |
|
|
Jul 25 08:16:04 PM PDT 24 |
Jul 25 08:21:33 PM PDT 24 |
5301972080 ps |
| T282 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2190637151 |
|
|
Jul 25 07:58:26 PM PDT 24 |
Jul 25 08:08:45 PM PDT 24 |
4612514704 ps |
| T283 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4271900163 |
|
|
Jul 25 08:08:56 PM PDT 24 |
Jul 25 08:59:40 PM PDT 24 |
11542573884 ps |
| T1066 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2429044104 |
|
|
Jul 25 08:09:18 PM PDT 24 |
Jul 25 09:21:05 PM PDT 24 |
17742054600 ps |
| T795 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936784776 |
|
|
Jul 25 08:34:40 PM PDT 24 |
Jul 25 08:40:21 PM PDT 24 |
4069480784 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4035416681 |
|
|
Jul 25 08:12:57 PM PDT 24 |
Jul 25 08:17:38 PM PDT 24 |
2946226780 ps |
| T1068 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1057609898 |
|
|
Jul 25 08:11:28 PM PDT 24 |
Jul 25 08:25:07 PM PDT 24 |
3838620480 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.454045070 |
|
|
Jul 25 07:59:38 PM PDT 24 |
Jul 25 08:01:15 PM PDT 24 |
2072077539 ps |
| T789 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3998691204 |
|
|
Jul 25 08:36:47 PM PDT 24 |
Jul 25 08:43:18 PM PDT 24 |
4227729252 ps |
| T760 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1113902292 |
|
|
Jul 25 08:31:23 PM PDT 24 |
Jul 25 08:42:08 PM PDT 24 |
5277594350 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4248868142 |
|
|
Jul 25 08:18:02 PM PDT 24 |
Jul 25 09:47:20 PM PDT 24 |
49711882830 ps |
| T1070 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1736440270 |
|
|
Jul 25 08:04:24 PM PDT 24 |
Jul 25 08:08:35 PM PDT 24 |
2713327240 ps |
| T762 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1283959140 |
|
|
Jul 25 08:31:55 PM PDT 24 |
Jul 25 08:43:12 PM PDT 24 |
6222356138 ps |
| T1071 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1828846351 |
|
|
Jul 25 08:16:18 PM PDT 24 |
Jul 25 08:22:00 PM PDT 24 |
2777965812 ps |
| T157 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1698391410 |
|
|
Jul 25 08:20:10 PM PDT 24 |
Jul 25 11:06:40 PM PDT 24 |
58154685184 ps |
| T778 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1568891083 |
|
|
Jul 25 08:41:45 PM PDT 24 |
Jul 25 08:52:04 PM PDT 24 |
6498064060 ps |
| T801 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1554450905 |
|
|
Jul 25 08:35:39 PM PDT 24 |
Jul 25 08:45:38 PM PDT 24 |
4821990926 ps |
| T172 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2023942208 |
|
|
Jul 25 08:37:36 PM PDT 24 |
Jul 25 08:48:23 PM PDT 24 |
5022288958 ps |
| T747 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396168806 |
|
|
Jul 25 08:36:19 PM PDT 24 |
Jul 25 08:41:03 PM PDT 24 |
3630680888 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.44022269 |
|
|
Jul 25 08:09:31 PM PDT 24 |
Jul 25 08:43:09 PM PDT 24 |
7348803398 ps |
| T711 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.524100850 |
|
|
Jul 25 08:09:37 PM PDT 24 |
Jul 25 08:21:10 PM PDT 24 |
4890499863 ps |
| T1073 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2713827842 |
|
|
Jul 25 08:04:46 PM PDT 24 |
Jul 25 08:10:49 PM PDT 24 |
3496319384 ps |
| T783 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697453125 |
|
|
Jul 25 08:34:42 PM PDT 24 |
Jul 25 08:40:11 PM PDT 24 |
3747889280 ps |
| T1074 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.673808443 |
|
|
Jul 25 08:08:02 PM PDT 24 |
Jul 25 09:42:12 PM PDT 24 |
24493651750 ps |
| T1075 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2073668154 |
|
|
Jul 25 08:29:28 PM PDT 24 |
Jul 25 08:44:42 PM PDT 24 |
8972731825 ps |
| T1076 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4120117050 |
|
|
Jul 25 08:29:59 PM PDT 24 |
Jul 25 08:38:13 PM PDT 24 |
6328457972 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1648258155 |
|
|
Jul 25 08:12:16 PM PDT 24 |
Jul 25 08:16:24 PM PDT 24 |
2862820880 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3424564941 |
|
|
Jul 25 08:15:55 PM PDT 24 |
Jul 25 08:51:57 PM PDT 24 |
12156783027 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3262773252 |
|
|
Jul 25 08:21:14 PM PDT 24 |
Jul 25 08:26:44 PM PDT 24 |
3076788956 ps |
| T1080 |
/workspace/coverage/default/2.chip_tap_straps_dev.4241558236 |
|
|
Jul 25 08:22:26 PM PDT 24 |
Jul 25 08:25:15 PM PDT 24 |
2507958859 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768890125 |
|
|
Jul 25 08:13:24 PM PDT 24 |
Jul 25 08:43:35 PM PDT 24 |
23303796440 ps |
| T1081 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.840270819 |
|
|
Jul 25 08:10:03 PM PDT 24 |
Jul 25 09:07:10 PM PDT 24 |
15410092079 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3400820956 |
|
|
Jul 25 08:17:58 PM PDT 24 |
Jul 25 08:26:46 PM PDT 24 |
7875536632 ps |
| T1083 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1178027439 |
|
|
Jul 25 08:18:52 PM PDT 24 |
Jul 25 08:24:22 PM PDT 24 |
3182031683 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3116726883 |
|
|
Jul 25 08:00:46 PM PDT 24 |
Jul 25 08:07:31 PM PDT 24 |
4388074414 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2077405223 |
|
|
Jul 25 08:02:10 PM PDT 24 |
Jul 25 08:08:53 PM PDT 24 |
7458564112 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.557410763 |
|
|
Jul 25 08:09:25 PM PDT 24 |
Jul 25 09:16:04 PM PDT 24 |
24613373918 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1031817577 |
|
|
Jul 25 08:08:10 PM PDT 24 |
Jul 25 08:51:12 PM PDT 24 |
22770228407 ps |
| T1087 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3370346825 |
|
|
Jul 25 08:29:19 PM PDT 24 |
Jul 25 08:38:56 PM PDT 24 |
7096929233 ps |
| T211 |
/workspace/coverage/default/0.chip_jtag_mem_access.2193392126 |
|
|
Jul 25 07:53:41 PM PDT 24 |
Jul 25 08:19:43 PM PDT 24 |
13599388684 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2422482172 |
|
|
Jul 25 08:06:22 PM PDT 24 |
Jul 25 08:17:08 PM PDT 24 |
4690544059 ps |
| T1088 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3111908041 |
|
|
Jul 25 08:30:06 PM PDT 24 |
Jul 25 08:39:14 PM PDT 24 |
7279356247 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.44566781 |
|
|
Jul 25 08:19:54 PM PDT 24 |
Jul 25 08:35:49 PM PDT 24 |
4270927736 ps |
| T1090 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1756633113 |
|
|
Jul 25 08:32:54 PM PDT 24 |
Jul 25 08:39:12 PM PDT 24 |
3437435000 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.985457373 |
|
|
Jul 25 08:10:12 PM PDT 24 |
Jul 25 08:13:08 PM PDT 24 |
2632248188 ps |
| T1092 |
/workspace/coverage/default/1.chip_sw_aes_enc.3289659051 |
|
|
Jul 25 08:09:46 PM PDT 24 |
Jul 25 08:13:33 PM PDT 24 |
2821341096 ps |
| T1093 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2986173248 |
|
|
Jul 25 08:01:53 PM PDT 24 |
Jul 25 08:06:30 PM PDT 24 |
2800954396 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_gpio.2142111502 |
|
|
Jul 25 08:17:01 PM PDT 24 |
Jul 25 08:25:28 PM PDT 24 |
3950784512 ps |
| T1094 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.4074667974 |
|
|
Jul 25 08:21:43 PM PDT 24 |
Jul 25 09:49:47 PM PDT 24 |
28356788243 ps |
| T722 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.985995564 |
|
|
Jul 25 08:32:37 PM PDT 24 |
Jul 25 08:40:23 PM PDT 24 |
3852017356 ps |
| T1095 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1592390204 |
|
|
Jul 25 08:08:07 PM PDT 24 |
Jul 25 09:06:26 PM PDT 24 |
14230887910 ps |
| T1096 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2497511487 |
|
|
Jul 25 08:41:11 PM PDT 24 |
Jul 25 08:47:45 PM PDT 24 |
4158836928 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1958766141 |
|
|
Jul 25 08:19:03 PM PDT 24 |
Jul 25 08:28:13 PM PDT 24 |
4689385805 ps |
| T1098 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3581161423 |
|
|
Jul 25 08:25:00 PM PDT 24 |
Jul 25 08:30:08 PM PDT 24 |
2858398832 ps |
| T190 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.784682145 |
|
|
Jul 25 08:17:45 PM PDT 24 |
Jul 25 09:32:40 PM PDT 24 |
44968346034 ps |
| T240 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2469681617 |
|
|
Jul 25 08:21:05 PM PDT 24 |
Jul 25 09:21:49 PM PDT 24 |
16930365170 ps |
| T1099 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.747238315 |
|
|
Jul 25 08:03:04 PM PDT 24 |
Jul 25 08:15:29 PM PDT 24 |
3932720980 ps |
| T1100 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3300269027 |
|
|
Jul 25 08:25:20 PM PDT 24 |
Jul 25 08:33:07 PM PDT 24 |
4749344940 ps |
| T1101 |
/workspace/coverage/default/2.chip_sw_aes_idle.4097596810 |
|
|
Jul 25 08:20:11 PM PDT 24 |
Jul 25 08:23:22 PM PDT 24 |
2716349856 ps |
| T1102 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2110806929 |
|
|
Jul 25 08:03:11 PM PDT 24 |
Jul 25 08:12:10 PM PDT 24 |
4646548894 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_aes_enc.4062010133 |
|
|
Jul 25 08:01:50 PM PDT 24 |
Jul 25 08:07:41 PM PDT 24 |
3165489552 ps |
| T1104 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1207422852 |
|
|
Jul 25 08:22:23 PM PDT 24 |
Jul 25 08:25:44 PM PDT 24 |
2597785167 ps |
| T1105 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2853289093 |
|
|
Jul 25 08:14:06 PM PDT 24 |
Jul 25 08:17:08 PM PDT 24 |
1970505190 ps |
| T161 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.768822178 |
|
|
Jul 25 08:01:27 PM PDT 24 |
Jul 25 08:10:10 PM PDT 24 |
3608908310 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.838433231 |
|
|
Jul 25 08:18:58 PM PDT 24 |
Jul 25 08:34:46 PM PDT 24 |
4445199550 ps |
| T643 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3109737977 |
|
|
Jul 25 08:02:54 PM PDT 24 |
Jul 25 11:27:45 PM PDT 24 |
83477673353 ps |
| T1107 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3499568759 |
|
|
Jul 25 08:02:32 PM PDT 24 |
Jul 25 08:08:00 PM PDT 24 |
2637240850 ps |
| T1108 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.62407866 |
|
|
Jul 25 08:26:14 PM PDT 24 |
Jul 25 08:36:29 PM PDT 24 |
6893028408 ps |
| T1109 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2454534696 |
|
|
Jul 25 08:34:50 PM PDT 24 |
Jul 25 08:43:20 PM PDT 24 |
4120970184 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3858073908 |
|
|
Jul 25 08:00:07 PM PDT 24 |
Jul 25 08:41:07 PM PDT 24 |
7314292604 ps |
| T1111 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.161040506 |
|
|
Jul 25 08:25:15 PM PDT 24 |
Jul 25 08:29:53 PM PDT 24 |
2973733704 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2821981715 |
|
|
Jul 25 08:17:33 PM PDT 24 |
Jul 26 12:00:07 AM PDT 24 |
78670985544 ps |
| T1113 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1376440196 |
|
|
Jul 25 08:10:06 PM PDT 24 |
Jul 25 10:09:38 PM PDT 24 |
23611884256 ps |
| T1114 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3854082938 |
|
|
Jul 25 08:25:52 PM PDT 24 |
Jul 25 08:36:26 PM PDT 24 |
3791320348 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1931188010 |
|
|
Jul 25 08:00:45 PM PDT 24 |
Jul 25 08:30:46 PM PDT 24 |
8483350640 ps |
| T720 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.649365129 |
|
|
Jul 25 08:36:33 PM PDT 24 |
Jul 25 08:45:28 PM PDT 24 |
5328059330 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.5325982 |
|
|
Jul 25 08:11:15 PM PDT 24 |
Jul 25 08:17:35 PM PDT 24 |
5427631120 ps |
| T1117 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2049727519 |
|
|
Jul 25 08:04:53 PM PDT 24 |
Jul 25 08:11:56 PM PDT 24 |
3292923622 ps |
| T744 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124833428 |
|
|
Jul 25 08:33:43 PM PDT 24 |
Jul 25 08:41:13 PM PDT 24 |
3839359998 ps |
| T1118 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219503727 |
|
|
Jul 25 08:16:30 PM PDT 24 |
Jul 25 08:28:59 PM PDT 24 |
4444429337 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1943943880 |
|
|
Jul 25 08:00:27 PM PDT 24 |
Jul 25 10:53:33 PM PDT 24 |
58741944449 ps |
| T1120 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.148255838 |
|
|
Jul 25 08:11:59 PM PDT 24 |
Jul 25 08:36:00 PM PDT 24 |
7022133408 ps |
| T1121 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.786605792 |
|
|
Jul 25 08:02:28 PM PDT 24 |
Jul 25 08:13:52 PM PDT 24 |
4154587932 ps |
| T1122 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1026392304 |
|
|
Jul 25 08:03:57 PM PDT 24 |
Jul 25 08:14:51 PM PDT 24 |
3545625280 ps |
| T1123 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1316471273 |
|
|
Jul 25 08:33:52 PM PDT 24 |
Jul 25 08:45:21 PM PDT 24 |
4686444364 ps |
| T306 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3986524140 |
|
|
Jul 25 08:12:04 PM PDT 24 |
Jul 25 08:23:49 PM PDT 24 |
6265604236 ps |
| T110 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.251675652 |
|
|
Jul 25 08:03:54 PM PDT 24 |
Jul 25 08:09:51 PM PDT 24 |
4273081388 ps |
| T649 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1709348789 |
|
|
Jul 25 08:12:03 PM PDT 24 |
Jul 25 08:22:00 PM PDT 24 |
6126075210 ps |
| T690 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1824781970 |
|
|
Jul 25 08:21:28 PM PDT 24 |
Jul 25 08:49:17 PM PDT 24 |
7959358767 ps |
| T691 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4264888329 |
|
|
Jul 25 08:36:43 PM PDT 24 |
Jul 25 08:42:57 PM PDT 24 |
3139764756 ps |
| T692 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.539472843 |
|
|
Jul 25 08:05:17 PM PDT 24 |
Jul 25 08:15:33 PM PDT 24 |
4272427368 ps |
| T693 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3246549052 |
|
|
Jul 25 08:01:21 PM PDT 24 |
Jul 25 08:19:32 PM PDT 24 |
5793890080 ps |
| T445 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4028770129 |
|
|
Jul 25 08:20:10 PM PDT 24 |
Jul 25 08:34:36 PM PDT 24 |
7106013368 ps |
| T694 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2704240814 |
|
|
Jul 25 08:35:25 PM PDT 24 |
Jul 25 09:24:50 PM PDT 24 |
26545954617 ps |
| T695 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3578255834 |
|
|
Jul 25 08:01:30 PM PDT 24 |
Jul 25 08:25:03 PM PDT 24 |
6738792488 ps |
| T696 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1395222409 |
|
|
Jul 25 08:11:40 PM PDT 24 |
Jul 25 08:23:19 PM PDT 24 |
4922992300 ps |
| T738 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1197427862 |
|
|
Jul 25 08:20:14 PM PDT 24 |
Jul 25 11:27:09 PM PDT 24 |
256373631706 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2758427334 |
|
|
Jul 25 08:21:28 PM PDT 24 |
Jul 25 08:29:17 PM PDT 24 |
4854628648 ps |
| T1125 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3367724413 |
|
|
Jul 25 08:17:33 PM PDT 24 |
Jul 25 08:21:33 PM PDT 24 |
2787508168 ps |
| T1126 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.456382868 |
|
|
Jul 25 08:04:50 PM PDT 24 |
Jul 25 08:50:04 PM PDT 24 |
8728287660 ps |
| T1127 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.925945422 |
|
|
Jul 25 08:07:19 PM PDT 24 |
Jul 25 09:50:26 PM PDT 24 |
26633554664 ps |
| T385 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.4067659525 |
|
|
Jul 25 08:00:41 PM PDT 24 |
Jul 25 08:04:51 PM PDT 24 |
2741880720 ps |
| T1128 |
/workspace/coverage/default/0.chip_tap_straps_prod.1157543109 |
|
|
Jul 25 08:02:39 PM PDT 24 |
Jul 25 08:05:17 PM PDT 24 |
2332959444 ps |
| T1129 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.1991341239 |
|
|
Jul 25 08:14:12 PM PDT 24 |
Jul 25 08:25:14 PM PDT 24 |
4868751390 ps |
| T1130 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.931866897 |
|
|
Jul 25 08:06:14 PM PDT 24 |
Jul 25 08:14:05 PM PDT 24 |
3934203480 ps |
| T254 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.9851308 |
|
|
Jul 25 08:37:36 PM PDT 24 |
Jul 25 08:46:51 PM PDT 24 |
4596853848 ps |
| T794 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1144727601 |
|
|
Jul 25 08:35:08 PM PDT 24 |
Jul 25 08:45:56 PM PDT 24 |
5630095840 ps |
| T1131 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3743904518 |
|
|
Jul 25 08:06:44 PM PDT 24 |
Jul 25 08:26:04 PM PDT 24 |
6426184468 ps |
| T1132 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3913159029 |
|
|
Jul 25 08:29:39 PM PDT 24 |
Jul 25 08:38:00 PM PDT 24 |
3257184984 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_flash_init.3829017493 |
|
|
Jul 25 08:06:12 PM PDT 24 |
Jul 25 08:47:56 PM PDT 24 |
24051365020 ps |
| T250 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1305107495 |
|
|
Jul 25 07:58:59 PM PDT 24 |
Jul 25 08:07:14 PM PDT 24 |
5162410698 ps |
| T1133 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.4281091643 |
|
|
Jul 25 08:08:44 PM PDT 24 |
Jul 25 08:23:10 PM PDT 24 |
7384512024 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3616465810 |
|
|
Jul 25 08:19:24 PM PDT 24 |
Jul 25 08:26:48 PM PDT 24 |
4825573689 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3229650655 |
|
|
Jul 25 08:00:38 PM PDT 24 |
Jul 25 08:13:49 PM PDT 24 |
5296774790 ps |
| T1136 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1996356509 |
|
|
Jul 25 08:09:45 PM PDT 24 |
Jul 25 08:46:04 PM PDT 24 |
11207359456 ps |
| T808 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.4139311586 |
|
|
Jul 25 08:31:24 PM PDT 24 |
Jul 25 08:43:20 PM PDT 24 |
4542767780 ps |
| T1137 |
/workspace/coverage/default/0.rom_e2e_static_critical.2485139098 |
|
|
Jul 25 08:07:02 PM PDT 24 |
Jul 25 09:10:10 PM PDT 24 |
17557148108 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2249341881 |
|
|
Jul 25 08:02:17 PM PDT 24 |
Jul 25 08:10:11 PM PDT 24 |
7806252736 ps |
| T38 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3469467249 |
|
|
Jul 25 08:17:53 PM PDT 24 |
Jul 25 08:21:49 PM PDT 24 |
2909602786 ps |
| T173 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3407888732 |
|
|
Jul 25 08:00:48 PM PDT 24 |
Jul 25 08:11:03 PM PDT 24 |
4908281544 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1449938392 |
|
|
Jul 25 08:23:14 PM PDT 24 |
Jul 25 08:30:28 PM PDT 24 |
3454069224 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.4177868894 |
|
|
Jul 25 08:22:02 PM PDT 24 |
Jul 25 08:47:34 PM PDT 24 |
8387279518 ps |
| T669 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2752210430 |
|
|
Jul 25 08:18:33 PM PDT 24 |
Jul 25 08:23:09 PM PDT 24 |
2921817290 ps |
| T1140 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.878478844 |
|
|
Jul 25 08:05:45 PM PDT 24 |
Jul 25 08:35:51 PM PDT 24 |
10439899628 ps |
| T101 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.378138802 |
|
|
Jul 25 08:04:01 PM PDT 24 |
Jul 25 08:08:16 PM PDT 24 |
3309564880 ps |
| T422 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.4155618240 |
|
|
Jul 25 08:06:17 PM PDT 24 |
Jul 25 08:11:08 PM PDT 24 |
3041726108 ps |
| T423 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.268451027 |
|
|
Jul 25 08:00:52 PM PDT 24 |
Jul 25 08:18:04 PM PDT 24 |
5337297126 ps |
| T424 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2827239838 |
|
|
Jul 25 08:04:18 PM PDT 24 |
Jul 25 08:13:18 PM PDT 24 |
4087441619 ps |
| T425 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1863746132 |
|
|
Jul 25 08:20:19 PM PDT 24 |
Jul 25 09:22:22 PM PDT 24 |
15148770182 ps |
| T426 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2613200895 |
|
|
Jul 25 08:31:08 PM PDT 24 |
Jul 25 08:41:17 PM PDT 24 |
4285568888 ps |
| T330 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2698123735 |
|
|
Jul 25 07:59:50 PM PDT 24 |
Jul 25 08:07:59 PM PDT 24 |
3905995640 ps |
| T427 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2963862044 |
|
|
Jul 25 08:02:42 PM PDT 24 |
Jul 25 08:37:45 PM PDT 24 |
24700248943 ps |
| T428 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.634695754 |
|
|
Jul 25 08:34:05 PM PDT 24 |
Jul 25 08:40:30 PM PDT 24 |
3283738562 ps |
| T429 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.561272254 |
|
|
Jul 25 08:24:05 PM PDT 24 |
Jul 25 08:29:21 PM PDT 24 |
3337692904 ps |
| T1141 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.303330990 |
|
|
Jul 25 08:05:41 PM PDT 24 |
Jul 25 08:09:35 PM PDT 24 |
3133079751 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3873549477 |
|
|
Jul 25 08:11:54 PM PDT 24 |
Jul 25 08:22:02 PM PDT 24 |
4649645504 ps |
| T1143 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2459798731 |
|
|
Jul 25 08:05:36 PM PDT 24 |
Jul 25 08:16:08 PM PDT 24 |
6133587392 ps |
| T321 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1563324193 |
|
|
Jul 25 08:20:10 PM PDT 24 |
Jul 25 08:38:38 PM PDT 24 |
6043741036 ps |
| T1144 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749649662 |
|
|
Jul 25 08:36:01 PM PDT 24 |
Jul 25 08:42:27 PM PDT 24 |
4149144768 ps |
| T1145 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1903084543 |
|
|
Jul 25 08:07:34 PM PDT 24 |
Jul 25 09:17:37 PM PDT 24 |
15262745980 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1684088604 |
|
|
Jul 25 08:00:56 PM PDT 24 |
Jul 25 08:12:54 PM PDT 24 |
6398237922 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1928323710 |
|
|
Jul 25 08:13:18 PM PDT 24 |
Jul 25 08:32:44 PM PDT 24 |
8886404576 ps |
| T1147 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3585872610 |
|
|
Jul 25 08:09:49 PM PDT 24 |
Jul 25 09:21:33 PM PDT 24 |
14514041408 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4294638803 |
|
|
Jul 25 08:07:36 PM PDT 24 |
Jul 25 08:18:32 PM PDT 24 |
5478137820 ps |
| T1148 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1070972227 |
|
|
Jul 25 08:21:53 PM PDT 24 |
Jul 25 08:31:48 PM PDT 24 |
4538487690 ps |
| T93 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1483859076 |
|
|
Jul 25 08:39:23 PM PDT 24 |
Jul 25 08:48:47 PM PDT 24 |
4875687600 ps |
| T1149 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2195293395 |
|
|
Jul 25 08:08:31 PM PDT 24 |
Jul 25 09:09:54 PM PDT 24 |
15737969340 ps |
| T746 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965728673 |
|
|
Jul 25 08:35:40 PM PDT 24 |
Jul 25 08:41:50 PM PDT 24 |
3552422536 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1893666583 |
|
|
Jul 25 08:04:36 PM PDT 24 |
Jul 25 08:08:48 PM PDT 24 |
2866465286 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_power_idle_load.4117949733 |
|
|
Jul 25 08:24:29 PM PDT 24 |
Jul 25 08:36:57 PM PDT 24 |
4681162712 ps |
| T309 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1633194432 |
|
|
Jul 25 08:36:29 PM PDT 24 |
Jul 25 08:43:18 PM PDT 24 |
3839100952 ps |
| T264 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2056251464 |
|
|
Jul 25 08:03:59 PM PDT 24 |
Jul 25 08:44:55 PM PDT 24 |
10418399228 ps |
| T372 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1692465809 |
|
|
Jul 25 08:12:26 PM PDT 24 |
Jul 25 10:07:33 PM PDT 24 |
23790340954 ps |
| T1152 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1463826241 |
|
|
Jul 25 08:04:20 PM PDT 24 |
Jul 25 08:07:58 PM PDT 24 |
3521253920 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2457294793 |
|
|
Jul 25 08:01:58 PM PDT 24 |
Jul 25 08:09:11 PM PDT 24 |
3029473416 ps |
| T373 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3333121685 |
|
|
Jul 25 08:08:25 PM PDT 24 |
Jul 25 10:00:54 PM PDT 24 |
24501401090 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2686458110 |
|
|
Jul 25 08:18:46 PM PDT 24 |
Jul 25 08:40:36 PM PDT 24 |
7404470868 ps |
| T1155 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1431682011 |
|
|
Jul 25 08:31:04 PM PDT 24 |
Jul 25 08:38:43 PM PDT 24 |
3496229434 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2674101067 |
|
|
Jul 25 08:06:24 PM PDT 24 |
Jul 25 08:09:39 PM PDT 24 |
2674674688 ps |
| T1157 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2244859738 |
|
|
Jul 25 08:31:13 PM PDT 24 |
Jul 25 08:37:30 PM PDT 24 |
3365352964 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3710959719 |
|
|
Jul 25 08:02:39 PM PDT 24 |
Jul 25 08:25:13 PM PDT 24 |
7522222829 ps |
| T1159 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1647937725 |
|
|
Jul 25 08:04:52 PM PDT 24 |
Jul 25 09:09:01 PM PDT 24 |
25385459840 ps |
| T784 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.3067671050 |
|
|
Jul 25 08:31:29 PM PDT 24 |
Jul 25 08:42:51 PM PDT 24 |
5713373176 ps |
| T1160 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1566376530 |
|
|
Jul 25 08:18:33 PM PDT 24 |
Jul 25 08:44:36 PM PDT 24 |
15319449538 ps |
| T1161 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.4029714492 |
|
|
Jul 25 08:33:21 PM PDT 24 |
Jul 25 08:40:57 PM PDT 24 |
4825756160 ps |
| T1162 |
/workspace/coverage/default/2.rom_e2e_self_hash.1971394359 |
|
|
Jul 25 08:31:30 PM PDT 24 |
Jul 25 10:01:00 PM PDT 24 |
26256885600 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2099567834 |
|
|
Jul 25 08:20:08 PM PDT 24 |
Jul 25 08:28:07 PM PDT 24 |
18687993080 ps |
| T1164 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.1362406014 |
|
|
Jul 25 08:00:47 PM PDT 24 |
Jul 25 08:05:09 PM PDT 24 |
2845252520 ps |
| T749 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1365245972 |
|
|
Jul 25 08:33:10 PM PDT 24 |
Jul 25 08:42:48 PM PDT 24 |
5107682814 ps |
| T1165 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3175224059 |
|
|
Jul 25 08:34:04 PM PDT 24 |
Jul 25 08:42:39 PM PDT 24 |
5441970674 ps |
| T1166 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1580196342 |
|
|
Jul 25 08:17:11 PM PDT 24 |
Jul 25 08:27:52 PM PDT 24 |
3723223476 ps |
| T1167 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1062455225 |
|
|
Jul 25 08:19:14 PM PDT 24 |
Jul 25 08:31:51 PM PDT 24 |
5008003630 ps |
| T775 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3022702284 |
|
|
Jul 25 08:35:11 PM PDT 24 |
Jul 25 08:41:39 PM PDT 24 |
3832665020 ps |
| T1168 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1534849761 |
|
|
Jul 25 08:21:19 PM PDT 24 |
Jul 25 08:46:42 PM PDT 24 |
12541210723 ps |
| T1169 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1676035702 |
|
|
Jul 25 08:18:32 PM PDT 24 |
Jul 25 08:43:54 PM PDT 24 |
13211047944 ps |
| T1170 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2898826983 |
|
|
Jul 25 08:07:37 PM PDT 24 |
Jul 25 09:06:18 PM PDT 24 |
14505387578 ps |
| T94 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413777053 |
|
|
Jul 25 08:35:52 PM PDT 24 |
Jul 25 08:40:41 PM PDT 24 |
3924473952 ps |
| T1171 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2812416578 |
|
|
Jul 25 08:09:11 PM PDT 24 |
Jul 25 08:17:37 PM PDT 24 |
4872443204 ps |
| T1172 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1515696407 |
|
|
Jul 25 08:01:14 PM PDT 24 |
Jul 25 08:08:56 PM PDT 24 |
4035105080 ps |
| T804 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2475102581 |
|
|
Jul 25 08:35:04 PM PDT 24 |
Jul 25 08:46:58 PM PDT 24 |
4814602016 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1103464692 |
|
|
Jul 25 08:03:41 PM PDT 24 |
Jul 25 08:09:25 PM PDT 24 |
2679336045 ps |
| T1174 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.639085074 |
|
|
Jul 25 08:13:59 PM PDT 24 |
Jul 25 08:27:07 PM PDT 24 |
4579471531 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1931488573 |
|
|
Jul 25 08:01:25 PM PDT 24 |
Jul 25 08:06:35 PM PDT 24 |
3224917938 ps |
| T1176 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455791626 |
|
|
Jul 25 08:29:03 PM PDT 24 |
Jul 25 08:36:05 PM PDT 24 |
3835155340 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2421196959 |
|
|
Jul 25 08:07:05 PM PDT 24 |
Jul 25 08:18:22 PM PDT 24 |
8112713824 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1837853610 |
|
|
Jul 25 08:21:16 PM PDT 24 |
Jul 25 08:29:40 PM PDT 24 |
5478271000 ps |
| T1178 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.4103794877 |
|
|
Jul 25 08:09:57 PM PDT 24 |
Jul 25 08:33:20 PM PDT 24 |
11681339652 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3863366588 |
|
|
Jul 25 08:10:15 PM PDT 24 |
Jul 25 08:47:55 PM PDT 24 |
25882817089 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1578769492 |
|
|
Jul 25 08:05:30 PM PDT 24 |
Jul 25 08:30:36 PM PDT 24 |
14544202696 ps |
| T356 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2212127993 |
|
|
Jul 25 08:24:52 PM PDT 24 |
Jul 25 08:34:40 PM PDT 24 |
6703055128 ps |