| T705 |
/workspace/coverage/default/2.rom_raw_unlock.1858102070 |
|
|
Jul 25 08:31:27 PM PDT 24 |
Jul 25 08:35:58 PM PDT 24 |
5138487650 ps |
| T206 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3711072190 |
|
|
Jul 25 07:58:21 PM PDT 24 |
Jul 25 08:08:11 PM PDT 24 |
6754109843 ps |
| T1180 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1079900154 |
|
|
Jul 25 08:06:48 PM PDT 24 |
Jul 25 09:10:11 PM PDT 24 |
14840350030 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_flash_init.2074547166 |
|
|
Jul 25 08:00:54 PM PDT 24 |
Jul 25 08:42:17 PM PDT 24 |
23625572114 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1768307702 |
|
|
Jul 25 08:03:50 PM PDT 24 |
Jul 25 08:08:52 PM PDT 24 |
3024900260 ps |
| T310 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.756274494 |
|
|
Jul 25 08:29:37 PM PDT 24 |
Jul 25 08:40:25 PM PDT 24 |
4823531500 ps |
| T1183 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1905331144 |
|
|
Jul 25 08:07:26 PM PDT 24 |
Jul 25 09:02:06 PM PDT 24 |
10730204424 ps |
| T268 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1266021928 |
|
|
Jul 25 08:37:34 PM PDT 24 |
Jul 25 08:46:50 PM PDT 24 |
5685455820 ps |
| T1184 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.254481978 |
|
|
Jul 25 08:27:02 PM PDT 24 |
Jul 25 08:38:38 PM PDT 24 |
3820473936 ps |
| T1185 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.926969333 |
|
|
Jul 25 08:35:32 PM PDT 24 |
Jul 25 09:49:26 PM PDT 24 |
14933801578 ps |
| T275 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2091030455 |
|
|
Jul 25 08:28:10 PM PDT 24 |
Jul 25 08:41:52 PM PDT 24 |
6345015900 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1644999694 |
|
|
Jul 25 08:21:29 PM PDT 24 |
Jul 25 08:26:15 PM PDT 24 |
3076565212 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_hmac_enc.3358769726 |
|
|
Jul 25 08:21:44 PM PDT 24 |
Jul 25 08:25:20 PM PDT 24 |
2466915380 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2281470881 |
|
|
Jul 25 08:03:08 PM PDT 24 |
Jul 25 08:43:42 PM PDT 24 |
18459043912 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2810828783 |
|
|
Jul 25 08:08:07 PM PDT 24 |
Jul 25 08:23:33 PM PDT 24 |
8710350296 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.90798808 |
|
|
Jul 25 08:17:35 PM PDT 24 |
Jul 25 08:24:40 PM PDT 24 |
2875310921 ps |
| T351 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.105071953 |
|
|
Jul 25 08:36:53 PM PDT 24 |
Jul 25 08:48:18 PM PDT 24 |
4957024892 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_example_flash.1162223600 |
|
|
Jul 25 08:07:22 PM PDT 24 |
Jul 25 08:11:19 PM PDT 24 |
2711945452 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2425124645 |
|
|
Jul 25 08:24:46 PM PDT 24 |
Jul 25 08:32:54 PM PDT 24 |
6734841096 ps |
| T361 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1206089411 |
|
|
Jul 25 08:37:16 PM PDT 24 |
Jul 25 08:47:19 PM PDT 24 |
4978003260 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1344351043 |
|
|
Jul 25 08:09:10 PM PDT 24 |
Jul 25 11:32:47 PM PDT 24 |
255409386380 ps |
| T810 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2351635385 |
|
|
Jul 25 08:37:31 PM PDT 24 |
Jul 25 08:46:16 PM PDT 24 |
6115592800 ps |
| T802 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1140892219 |
|
|
Jul 25 08:33:23 PM PDT 24 |
Jul 25 08:39:18 PM PDT 24 |
3485820522 ps |
| T322 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.4240893016 |
|
|
Jul 25 08:22:05 PM PDT 24 |
Jul 25 08:34:50 PM PDT 24 |
5337888784 ps |
| T73 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.4153339456 |
|
|
Jul 25 08:26:56 PM PDT 24 |
Jul 25 08:30:27 PM PDT 24 |
3229491037 ps |
| T342 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1212542216 |
|
|
Jul 25 08:05:33 PM PDT 24 |
Jul 25 08:18:03 PM PDT 24 |
4932772908 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.900824537 |
|
|
Jul 25 08:17:50 PM PDT 24 |
Jul 25 08:32:39 PM PDT 24 |
5586814888 ps |
| T1195 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.755164935 |
|
|
Jul 25 08:26:44 PM PDT 24 |
Jul 25 08:35:05 PM PDT 24 |
5360885920 ps |
| T1196 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1508493494 |
|
|
Jul 25 08:09:36 PM PDT 24 |
Jul 25 09:09:09 PM PDT 24 |
15371424904 ps |
| T57 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.462571727 |
|
|
Jul 25 08:05:55 PM PDT 24 |
Jul 25 08:11:13 PM PDT 24 |
3977850480 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.42987334 |
|
|
Jul 25 08:07:36 PM PDT 24 |
Jul 25 08:17:58 PM PDT 24 |
5406002080 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1363776129 |
|
|
Jul 25 08:16:19 PM PDT 24 |
Jul 25 08:30:17 PM PDT 24 |
4951191812 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1178732308 |
|
|
Jul 25 08:21:23 PM PDT 24 |
Jul 25 09:24:57 PM PDT 24 |
18936342132 ps |
| T374 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1604429889 |
|
|
Jul 25 08:11:21 PM PDT 24 |
Jul 25 09:28:26 PM PDT 24 |
18432028200 ps |
| T805 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3224366065 |
|
|
Jul 25 08:30:50 PM PDT 24 |
Jul 25 08:40:34 PM PDT 24 |
5009951106 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2272803546 |
|
|
Jul 25 08:02:47 PM PDT 24 |
Jul 25 08:06:54 PM PDT 24 |
2504508062 ps |
| T1201 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2285837377 |
|
|
Jul 25 08:27:45 PM PDT 24 |
Jul 25 09:14:43 PM PDT 24 |
13445007480 ps |
| T1202 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3764658432 |
|
|
Jul 25 08:21:33 PM PDT 24 |
Jul 25 08:45:48 PM PDT 24 |
11881712396 ps |
| T769 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134283558 |
|
|
Jul 25 08:29:52 PM PDT 24 |
Jul 25 08:36:38 PM PDT 24 |
3763000776 ps |
| T392 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3243450465 |
|
|
Jul 25 08:09:33 PM PDT 24 |
Jul 25 08:17:10 PM PDT 24 |
6677080150 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_aes_entropy.233759841 |
|
|
Jul 25 08:01:40 PM PDT 24 |
Jul 25 08:05:58 PM PDT 24 |
3008623784 ps |
| T1204 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.1153758600 |
|
|
Jul 25 08:16:01 PM PDT 24 |
Jul 25 08:18:04 PM PDT 24 |
3247174504 ps |
| T1205 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3179915402 |
|
|
Jul 25 08:27:50 PM PDT 24 |
Jul 25 08:42:33 PM PDT 24 |
12348993325 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1269879463 |
|
|
Jul 25 08:05:21 PM PDT 24 |
Jul 25 08:14:12 PM PDT 24 |
5156703032 ps |
| T1206 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1600675996 |
|
|
Jul 25 08:06:11 PM PDT 24 |
Jul 25 09:09:03 PM PDT 24 |
14841740438 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2952330631 |
|
|
Jul 25 08:18:09 PM PDT 24 |
Jul 25 08:38:08 PM PDT 24 |
5375322196 ps |
| T257 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1518517416 |
|
|
Jul 25 08:33:04 PM PDT 24 |
Jul 25 08:38:47 PM PDT 24 |
3678348040 ps |
| T750 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1169116061 |
|
|
Jul 25 08:33:11 PM PDT 24 |
Jul 25 08:41:42 PM PDT 24 |
5591654620 ps |
| T1208 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4160866120 |
|
|
Jul 25 08:02:26 PM PDT 24 |
Jul 25 11:33:52 PM PDT 24 |
254427711624 ps |
| T1209 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1355288509 |
|
|
Jul 25 08:34:19 PM PDT 24 |
Jul 25 08:41:18 PM PDT 24 |
3546805842 ps |
| T1210 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.669060709 |
|
|
Jul 25 07:59:56 PM PDT 24 |
Jul 25 08:12:36 PM PDT 24 |
4130701106 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2716743173 |
|
|
Jul 25 08:11:29 PM PDT 24 |
Jul 25 08:21:00 PM PDT 24 |
5116193596 ps |
| T1212 |
/workspace/coverage/default/2.rom_e2e_static_critical.2708876369 |
|
|
Jul 25 08:36:29 PM PDT 24 |
Jul 25 09:56:26 PM PDT 24 |
17463466792 ps |
| T1213 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1377743967 |
|
|
Jul 25 08:22:01 PM PDT 24 |
Jul 25 09:04:16 PM PDT 24 |
11150676988 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2443980905 |
|
|
Jul 25 08:03:08 PM PDT 24 |
Jul 25 08:31:24 PM PDT 24 |
22249729850 ps |
| T1214 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2580536038 |
|
|
Jul 25 08:20:26 PM PDT 24 |
Jul 25 08:25:14 PM PDT 24 |
2882866879 ps |
| T1215 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2238718464 |
|
|
Jul 25 08:04:57 PM PDT 24 |
Jul 25 08:16:01 PM PDT 24 |
4642981816 ps |
| T1216 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2421539984 |
|
|
Jul 25 08:05:03 PM PDT 24 |
Jul 25 08:53:29 PM PDT 24 |
10899287202 ps |
| T62 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2570198276 |
|
|
Jul 25 08:18:33 PM PDT 24 |
Jul 25 08:24:54 PM PDT 24 |
3775347813 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_coremark.3352201188 |
|
|
Jul 25 08:00:37 PM PDT 24 |
Jul 25 11:53:14 PM PDT 24 |
71318519384 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.193190176 |
|
|
Jul 25 07:58:54 PM PDT 24 |
Jul 25 08:03:46 PM PDT 24 |
2829162460 ps |
| T1218 |
/workspace/coverage/default/0.chip_tap_straps_dev.2887049416 |
|
|
Jul 25 08:00:02 PM PDT 24 |
Jul 25 08:05:15 PM PDT 24 |
4471233607 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2670318975 |
|
|
Jul 25 08:25:46 PM PDT 24 |
Jul 25 08:29:45 PM PDT 24 |
2577880312 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.123125300 |
|
|
Jul 25 07:59:11 PM PDT 24 |
Jul 25 08:11:55 PM PDT 24 |
5577856984 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2606263486 |
|
|
Jul 25 08:06:36 PM PDT 24 |
Jul 25 08:49:12 PM PDT 24 |
35260062660 ps |
| T1222 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.697871479 |
|
|
Jul 25 08:01:27 PM PDT 24 |
Jul 25 08:12:42 PM PDT 24 |
3795256387 ps |
| T1223 |
/workspace/coverage/default/1.chip_sw_example_rom.2728014644 |
|
|
Jul 25 08:04:08 PM PDT 24 |
Jul 25 08:06:07 PM PDT 24 |
2490387296 ps |
| T320 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3370210229 |
|
|
Jul 25 08:00:53 PM PDT 24 |
Jul 25 08:13:56 PM PDT 24 |
4086323480 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.21812596 |
|
|
Jul 25 08:04:23 PM PDT 24 |
Jul 25 09:08:25 PM PDT 24 |
20028868439 ps |
| T1225 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3226059516 |
|
|
Jul 25 08:34:41 PM PDT 24 |
Jul 25 08:44:54 PM PDT 24 |
4638178912 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4038786957 |
|
|
Jul 25 08:01:52 PM PDT 24 |
Jul 25 08:07:47 PM PDT 24 |
2838382840 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.726345456 |
|
|
Jul 25 08:02:30 PM PDT 24 |
Jul 25 08:09:50 PM PDT 24 |
3985872900 ps |
| T296 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1984468443 |
|
|
Jul 25 08:30:22 PM PDT 24 |
Jul 25 08:36:13 PM PDT 24 |
3231289580 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3833582456 |
|
|
Jul 25 08:02:20 PM PDT 24 |
Jul 25 09:20:52 PM PDT 24 |
15704545356 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.3527672266 |
|
|
Jul 25 08:25:20 PM PDT 24 |
Jul 25 08:29:57 PM PDT 24 |
3317495088 ps |
| T1228 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.674678352 |
|
|
Jul 25 08:30:23 PM PDT 24 |
Jul 25 08:42:14 PM PDT 24 |
4721176054 ps |
| T1229 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2193480137 |
|
|
Jul 25 08:29:12 PM PDT 24 |
Jul 25 08:41:41 PM PDT 24 |
12496610200 ps |
| T793 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.960344260 |
|
|
Jul 25 08:37:05 PM PDT 24 |
Jul 25 08:45:15 PM PDT 24 |
3593533898 ps |
| T1230 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.914283000 |
|
|
Jul 25 08:26:05 PM PDT 24 |
Jul 25 08:35:10 PM PDT 24 |
4504890552 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.570454555 |
|
|
Jul 25 08:18:41 PM PDT 24 |
Jul 25 08:30:04 PM PDT 24 |
3905301592 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1254395345 |
|
|
Jul 25 08:24:56 PM PDT 24 |
Jul 25 08:47:18 PM PDT 24 |
7806413454 ps |
| T743 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4290874560 |
|
|
Jul 25 08:37:17 PM PDT 24 |
Jul 25 08:43:42 PM PDT 24 |
3560622288 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1555992600 |
|
|
Jul 25 08:22:55 PM PDT 24 |
Jul 25 08:39:39 PM PDT 24 |
12696650036 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4039561632 |
|
|
Jul 25 08:18:19 PM PDT 24 |
Jul 25 08:23:50 PM PDT 24 |
3597668656 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1977215335 |
|
|
Jul 25 08:01:02 PM PDT 24 |
Jul 25 08:08:17 PM PDT 24 |
4253304184 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1466554853 |
|
|
Jul 25 08:03:54 PM PDT 24 |
Jul 25 08:15:29 PM PDT 24 |
4751913148 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.622674513 |
|
|
Jul 25 08:02:46 PM PDT 24 |
Jul 25 08:06:37 PM PDT 24 |
3015762320 ps |
| T1238 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2651008810 |
|
|
Jul 25 08:30:25 PM PDT 24 |
Jul 25 08:42:19 PM PDT 24 |
12908452880 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3630130495 |
|
|
Jul 25 08:11:18 PM PDT 24 |
Jul 25 08:34:36 PM PDT 24 |
8002116330 ps |
| T1239 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.350570401 |
|
|
Jul 25 08:30:34 PM PDT 24 |
Jul 25 08:43:16 PM PDT 24 |
6144653944 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3142886691 |
|
|
Jul 25 08:05:49 PM PDT 24 |
Jul 25 08:41:56 PM PDT 24 |
19095857868 ps |
| T812 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2242849169 |
|
|
Jul 25 08:28:31 PM PDT 24 |
Jul 25 08:35:20 PM PDT 24 |
5303953240 ps |
| T1241 |
/workspace/coverage/default/2.chip_sival_flash_info_access.1681985203 |
|
|
Jul 25 08:17:41 PM PDT 24 |
Jul 25 08:23:08 PM PDT 24 |
2861914328 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.587312415 |
|
|
Jul 25 07:59:05 PM PDT 24 |
Jul 25 08:34:21 PM PDT 24 |
8044640200 ps |
| T1242 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2757976374 |
|
|
Jul 25 08:00:16 PM PDT 24 |
Jul 25 08:09:41 PM PDT 24 |
4461565738 ps |
| T41 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2403162268 |
|
|
Jul 25 08:06:34 PM PDT 24 |
Jul 25 08:15:15 PM PDT 24 |
6621218598 ps |
| T78 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1611276040 |
|
|
Jul 25 07:59:55 PM PDT 24 |
Jul 25 08:08:08 PM PDT 24 |
3876966288 ps |
| T1243 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.314772729 |
|
|
Jul 25 08:37:10 PM PDT 24 |
Jul 25 08:47:27 PM PDT 24 |
5494790648 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3701746520 |
|
|
Jul 25 08:01:02 PM PDT 24 |
Jul 25 08:06:48 PM PDT 24 |
3495621868 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2305122882 |
|
|
Jul 25 08:06:01 PM PDT 24 |
Jul 25 08:14:22 PM PDT 24 |
4647112778 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3224198213 |
|
|
Jul 25 08:08:35 PM PDT 24 |
Jul 25 08:39:42 PM PDT 24 |
12875719509 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3199921089 |
|
|
Jul 25 08:06:15 PM PDT 24 |
Jul 25 08:13:16 PM PDT 24 |
4039185738 ps |
| T772 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2109403520 |
|
|
Jul 25 08:36:20 PM PDT 24 |
Jul 25 08:46:53 PM PDT 24 |
5656928208 ps |
| T803 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.572127961 |
|
|
Jul 25 08:37:43 PM PDT 24 |
Jul 25 08:42:52 PM PDT 24 |
3829823996 ps |
| T641 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.2684525124 |
|
|
Jul 25 08:20:04 PM PDT 24 |
Jul 25 08:29:04 PM PDT 24 |
3366839026 ps |
| T1246 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2133457990 |
|
|
Jul 25 08:31:02 PM PDT 24 |
Jul 25 08:43:10 PM PDT 24 |
5285564154 ps |
| T60 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1478762598 |
|
|
Jul 25 08:02:04 PM PDT 24 |
Jul 25 08:08:23 PM PDT 24 |
4536651838 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2252025378 |
|
|
Jul 25 08:01:53 PM PDT 24 |
Jul 25 08:14:56 PM PDT 24 |
5380777596 ps |
| T207 |
/workspace/coverage/default/0.chip_sw_power_virus.4051473597 |
|
|
Jul 25 08:08:39 PM PDT 24 |
Jul 25 08:34:20 PM PDT 24 |
5709609296 ps |
| T1248 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.340778419 |
|
|
Jul 25 08:30:19 PM PDT 24 |
Jul 25 08:38:41 PM PDT 24 |
6315032594 ps |
| T1249 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2530668530 |
|
|
Jul 25 08:05:38 PM PDT 24 |
Jul 25 09:42:55 PM PDT 24 |
48126178318 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4252098576 |
|
|
Jul 25 08:00:56 PM PDT 24 |
Jul 25 08:08:28 PM PDT 24 |
7239770165 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.265768389 |
|
|
Jul 25 08:23:18 PM PDT 24 |
Jul 25 08:31:02 PM PDT 24 |
4911090264 ps |
| T1251 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.178113199 |
|
|
Jul 25 08:07:16 PM PDT 24 |
Jul 25 08:30:52 PM PDT 24 |
7975328520 ps |
| T788 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3013533306 |
|
|
Jul 25 08:37:27 PM PDT 24 |
Jul 25 08:47:45 PM PDT 24 |
6529623956 ps |
| T276 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3380426872 |
|
|
Jul 25 08:04:50 PM PDT 24 |
Jul 25 08:15:02 PM PDT 24 |
6041373400 ps |
| T1252 |
/workspace/coverage/default/2.rom_e2e_smoke.1244493387 |
|
|
Jul 25 08:28:27 PM PDT 24 |
Jul 25 09:32:11 PM PDT 24 |
14942798304 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4055235852 |
|
|
Jul 25 08:15:55 PM PDT 24 |
Jul 25 08:20:41 PM PDT 24 |
3341764612 ps |
| T752 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.870161801 |
|
|
Jul 25 08:37:59 PM PDT 24 |
Jul 25 08:49:45 PM PDT 24 |
5342656240 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2652594013 |
|
|
Jul 25 08:01:43 PM PDT 24 |
Jul 25 09:18:21 PM PDT 24 |
17616142574 ps |
| T1255 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3342200926 |
|
|
Jul 25 08:20:14 PM PDT 24 |
Jul 25 08:31:04 PM PDT 24 |
7697693116 ps |
| T1256 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.55262344 |
|
|
Jul 25 08:01:28 PM PDT 24 |
Jul 25 08:13:20 PM PDT 24 |
5763629014 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1713421201 |
|
|
Jul 25 08:17:14 PM PDT 24 |
Jul 25 09:02:10 PM PDT 24 |
13602382390 ps |
| T798 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118753591 |
|
|
Jul 25 08:03:35 PM PDT 24 |
Jul 25 08:09:56 PM PDT 24 |
3566028318 ps |
| T1258 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2493161017 |
|
|
Jul 25 08:34:56 PM PDT 24 |
Jul 25 08:45:26 PM PDT 24 |
6071750564 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1393225100 |
|
|
Jul 25 08:04:27 PM PDT 24 |
Jul 25 08:15:11 PM PDT 24 |
4108099176 ps |
| T1260 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.1129155864 |
|
|
Jul 25 08:22:01 PM PDT 24 |
Jul 25 08:31:05 PM PDT 24 |
6159088527 ps |
| T1261 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2472979254 |
|
|
Jul 25 08:25:35 PM PDT 24 |
Jul 25 08:33:58 PM PDT 24 |
3590321560 ps |
| T1262 |
/workspace/coverage/default/3.chip_tap_straps_prod.3296017731 |
|
|
Jul 25 08:26:37 PM PDT 24 |
Jul 25 08:29:23 PM PDT 24 |
2907253408 ps |
| T150 |
/workspace/coverage/default/1.chip_jtag_csr_rw.4014742299 |
|
|
Jul 25 08:04:59 PM PDT 24 |
Jul 25 08:33:44 PM PDT 24 |
12431280300 ps |
| T1263 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2898432747 |
|
|
Jul 25 08:07:59 PM PDT 24 |
Jul 25 08:12:22 PM PDT 24 |
3337865576 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3298944484 |
|
|
Jul 25 08:00:51 PM PDT 24 |
Jul 25 08:09:01 PM PDT 24 |
7466058962 ps |
| T1265 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3791643646 |
|
|
Jul 25 08:23:08 PM PDT 24 |
Jul 25 08:43:11 PM PDT 24 |
6919596394 ps |
| T773 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2107454688 |
|
|
Jul 25 08:36:53 PM PDT 24 |
Jul 25 08:47:28 PM PDT 24 |
5296203154 ps |
| T650 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1278857756 |
|
|
Jul 25 08:22:10 PM PDT 24 |
Jul 25 08:28:48 PM PDT 24 |
4649571876 ps |
| T362 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1585840039 |
|
|
Jul 25 08:36:38 PM PDT 24 |
Jul 25 08:43:31 PM PDT 24 |
5273916700 ps |
| T790 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3254826995 |
|
|
Jul 25 08:37:46 PM PDT 24 |
Jul 25 08:43:48 PM PDT 24 |
3677467432 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1087958500 |
|
|
Jul 25 08:16:54 PM PDT 24 |
Jul 25 08:20:06 PM PDT 24 |
3016576128 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1292088623 |
|
|
Jul 25 08:21:13 PM PDT 24 |
Jul 25 08:50:44 PM PDT 24 |
23210263038 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.493764748 |
|
|
Jul 25 08:04:55 PM PDT 24 |
Jul 25 08:10:22 PM PDT 24 |
3093782700 ps |
| T1269 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1327453278 |
|
|
Jul 25 08:29:34 PM PDT 24 |
Jul 25 09:00:11 PM PDT 24 |
8655862644 ps |
| T311 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2831254836 |
|
|
Jul 25 08:36:23 PM PDT 24 |
Jul 25 08:44:21 PM PDT 24 |
5262554294 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2354191048 |
|
|
Jul 25 08:17:03 PM PDT 24 |
Jul 25 08:36:29 PM PDT 24 |
8943859000 ps |
| T312 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3253035439 |
|
|
Jul 25 08:34:09 PM PDT 24 |
Jul 25 08:39:09 PM PDT 24 |
3097092600 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.4208576379 |
|
|
Jul 25 08:05:11 PM PDT 24 |
Jul 25 08:10:20 PM PDT 24 |
2953305686 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.252935744 |
|
|
Jul 25 08:20:46 PM PDT 24 |
Jul 25 08:51:49 PM PDT 24 |
8511334362 ps |
| T269 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4116345064 |
|
|
Jul 25 08:34:44 PM PDT 24 |
Jul 25 08:44:28 PM PDT 24 |
5464189930 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2533701824 |
|
|
Jul 25 08:01:28 PM PDT 24 |
Jul 25 08:28:02 PM PDT 24 |
7286582962 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2305333267 |
|
|
Jul 25 08:10:24 PM PDT 24 |
Jul 25 08:22:01 PM PDT 24 |
19620024256 ps |
| T706 |
/workspace/coverage/default/0.rom_raw_unlock.1770455586 |
|
|
Jul 25 08:02:11 PM PDT 24 |
Jul 25 08:05:47 PM PDT 24 |
4997794913 ps |
| T751 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2669794384 |
|
|
Jul 25 08:33:56 PM PDT 24 |
Jul 25 08:43:23 PM PDT 24 |
4271468180 ps |
| T1275 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.863677326 |
|
|
Jul 25 08:01:51 PM PDT 24 |
Jul 25 08:07:19 PM PDT 24 |
3410972606 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2800884547 |
|
|
Jul 25 08:03:04 PM PDT 24 |
Jul 25 08:23:43 PM PDT 24 |
12228017630 ps |
| T811 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1522259028 |
|
|
Jul 25 08:34:38 PM PDT 24 |
Jul 25 08:41:45 PM PDT 24 |
3643415820 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_example_concurrency.1131733931 |
|
|
Jul 25 08:05:52 PM PDT 24 |
Jul 25 08:10:11 PM PDT 24 |
3064772920 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4039837746 |
|
|
Jul 25 08:02:54 PM PDT 24 |
Jul 25 08:20:54 PM PDT 24 |
6696256584 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2672045376 |
|
|
Jul 25 08:18:19 PM PDT 24 |
Jul 25 08:23:57 PM PDT 24 |
3031570600 ps |
| T1280 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.691896312 |
|
|
Jul 25 08:10:02 PM PDT 24 |
Jul 25 09:37:47 PM PDT 24 |
16019618440 ps |
| T1281 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.1981312680 |
|
|
Jul 25 08:08:10 PM PDT 24 |
Jul 25 08:34:37 PM PDT 24 |
7435183370 ps |
| T754 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.45563260 |
|
|
Jul 25 08:32:20 PM PDT 24 |
Jul 25 08:38:48 PM PDT 24 |
4625763940 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.870487843 |
|
|
Jul 25 08:07:12 PM PDT 24 |
Jul 25 08:12:00 PM PDT 24 |
3087230822 ps |
| T1283 |
/workspace/coverage/default/0.chip_sw_example_rom.99368936 |
|
|
Jul 25 07:58:51 PM PDT 24 |
Jul 25 08:00:54 PM PDT 24 |
2068964376 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2202442832 |
|
|
Jul 25 08:24:23 PM PDT 24 |
Jul 25 08:29:28 PM PDT 24 |
3604348650 ps |
| T1285 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3140368587 |
|
|
Jul 25 08:18:24 PM PDT 24 |
Jul 25 08:28:26 PM PDT 24 |
5285976050 ps |
| T1286 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3275563168 |
|
|
Jul 25 08:18:27 PM PDT 24 |
Jul 25 08:26:38 PM PDT 24 |
5261847617 ps |
| T1287 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.248161496 |
|
|
Jul 25 08:41:00 PM PDT 24 |
Jul 25 08:47:54 PM PDT 24 |
4248593458 ps |
| T405 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1302951034 |
|
|
Jul 25 08:23:54 PM PDT 24 |
Jul 25 08:31:47 PM PDT 24 |
7560413564 ps |
| T1288 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3888264917 |
|
|
Jul 25 08:38:24 PM PDT 24 |
Jul 25 08:48:05 PM PDT 24 |
4916144200 ps |
| T56 |
/workspace/coverage/default/2.chip_sw_alert_test.1964834066 |
|
|
Jul 25 08:24:02 PM PDT 24 |
Jul 25 08:29:57 PM PDT 24 |
3063585496 ps |
| T1289 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.754820028 |
|
|
Jul 25 08:29:17 PM PDT 24 |
Jul 25 08:41:21 PM PDT 24 |
4849506248 ps |
| T670 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1337313995 |
|
|
Jul 25 08:02:49 PM PDT 24 |
Jul 25 08:07:35 PM PDT 24 |
2588865456 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2057640550 |
|
|
Jul 25 08:00:35 PM PDT 24 |
Jul 25 08:10:21 PM PDT 24 |
4156356040 ps |
| T1291 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1981787575 |
|
|
Jul 25 08:02:38 PM PDT 24 |
Jul 25 08:29:30 PM PDT 24 |
7533747366 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2798055206 |
|
|
Jul 25 08:15:50 PM PDT 24 |
Jul 25 08:20:21 PM PDT 24 |
3627197901 ps |
| T763 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1051913849 |
|
|
Jul 25 08:36:24 PM PDT 24 |
Jul 25 08:42:53 PM PDT 24 |
4159682028 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2743845864 |
|
|
Jul 25 08:21:52 PM PDT 24 |
Jul 25 08:44:52 PM PDT 24 |
7193572840 ps |
| T113 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4279355554 |
|
|
Jul 25 08:12:29 PM PDT 24 |
Jul 25 08:38:05 PM PDT 24 |
20812133772 ps |
| T1294 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.207095409 |
|
|
Jul 25 08:21:40 PM PDT 24 |
Jul 25 09:18:20 PM PDT 24 |
14835115515 ps |
| T1295 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4134817915 |
|
|
Jul 25 08:08:16 PM PDT 24 |
Jul 25 08:29:49 PM PDT 24 |
7703147592 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3123443493 |
|
|
Jul 25 08:03:22 PM PDT 24 |
Jul 25 08:19:46 PM PDT 24 |
5840351962 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.834095048 |
|
|
Jul 25 08:18:51 PM PDT 24 |
Jul 25 08:23:29 PM PDT 24 |
2699524600 ps |
| T813 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.578421974 |
|
|
Jul 25 08:33:57 PM PDT 24 |
Jul 25 08:40:59 PM PDT 24 |
3841588824 ps |
| T787 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.617833300 |
|
|
Jul 25 08:28:07 PM PDT 24 |
Jul 25 08:39:35 PM PDT 24 |
6039807384 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1663967172 |
|
|
Jul 25 08:25:43 PM PDT 24 |
Jul 25 08:32:51 PM PDT 24 |
5279528532 ps |
| T208 |
/workspace/coverage/default/2.chip_sw_power_virus.1012433945 |
|
|
Jul 25 08:28:20 PM PDT 24 |
Jul 25 08:49:18 PM PDT 24 |
5815359148 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.2118450930 |
|
|
Jul 25 08:23:12 PM PDT 24 |
Jul 25 08:28:18 PM PDT 24 |
3820390800 ps |
| T1300 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.3835217723 |
|
|
Jul 25 08:04:00 PM PDT 24 |
Jul 25 08:15:01 PM PDT 24 |
10680207680 ps |
| T779 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1823953167 |
|
|
Jul 25 08:31:03 PM PDT 24 |
Jul 25 08:41:15 PM PDT 24 |
5118649464 ps |
| T1301 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.434149200 |
|
|
Jul 25 08:11:20 PM PDT 24 |
Jul 25 09:50:31 PM PDT 24 |
24174330530 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1110304435 |
|
|
Jul 25 08:05:28 PM PDT 24 |
Jul 25 08:09:59 PM PDT 24 |
2764789428 ps |
| T1303 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.287026449 |
|
|
Jul 25 08:21:37 PM PDT 24 |
Jul 25 08:45:11 PM PDT 24 |
8362551160 ps |
| T1304 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.4289697576 |
|
|
Jul 25 08:11:31 PM PDT 24 |
Jul 25 08:31:38 PM PDT 24 |
10004479980 ps |
| T748 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2575275138 |
|
|
Jul 25 08:31:59 PM PDT 24 |
Jul 25 08:38:45 PM PDT 24 |
4217513448 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1081431872 |
|
|
Jul 25 08:02:21 PM PDT 24 |
Jul 25 08:16:53 PM PDT 24 |
8412243540 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1919246599 |
|
|
Jul 25 08:23:48 PM PDT 24 |
Jul 25 08:40:01 PM PDT 24 |
7909213516 ps |
| T1307 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.792746713 |
|
|
Jul 25 08:11:18 PM PDT 24 |
Jul 25 08:21:24 PM PDT 24 |
3387633100 ps |
| T1308 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2720077536 |
|
|
Jul 25 08:19:48 PM PDT 24 |
Jul 25 08:31:20 PM PDT 24 |
4631875016 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.454391171 |
|
|
Jul 25 08:18:39 PM PDT 24 |
Jul 25 08:27:48 PM PDT 24 |
4685674272 ps |
| T1309 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3969796122 |
|
|
Jul 25 08:09:17 PM PDT 24 |
Jul 25 08:13:05 PM PDT 24 |
2752852680 ps |
| T1310 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2220286689 |
|
|
Jul 25 08:34:08 PM PDT 24 |
Jul 25 08:41:05 PM PDT 24 |
3902797000 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3964535505 |
|
|
Jul 25 08:24:05 PM PDT 24 |
Jul 25 08:27:58 PM PDT 24 |
3252955184 ps |
| T1312 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1162317377 |
|
|
Jul 25 08:20:21 PM PDT 24 |
Jul 25 08:23:55 PM PDT 24 |
2883834942 ps |
| T1313 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3179703620 |
|
|
Jul 25 08:27:56 PM PDT 24 |
Jul 25 08:35:36 PM PDT 24 |
2985614188 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1574031167 |
|
|
Jul 25 08:22:16 PM PDT 24 |
Jul 25 08:30:21 PM PDT 24 |
3439155142 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1887016022 |
|
|
Jul 25 08:18:11 PM PDT 24 |
Jul 25 08:22:54 PM PDT 24 |
3136629766 ps |
| T1315 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.76398019 |
|
|
Jul 25 08:12:27 PM PDT 24 |
Jul 25 10:14:41 PM PDT 24 |
23697908728 ps |
| T1316 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.4079074310 |
|
|
Jul 25 08:09:38 PM PDT 24 |
Jul 25 09:09:08 PM PDT 24 |
14807533200 ps |
| T1317 |
/workspace/coverage/default/1.rom_raw_unlock.10730444 |
|
|
Jul 25 08:17:00 PM PDT 24 |
Jul 25 08:22:08 PM PDT 24 |
6172223273 ps |
| T1318 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2147850284 |
|
|
Jul 25 08:17:57 PM PDT 24 |
Jul 25 08:26:28 PM PDT 24 |
3629999162 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2197712988 |
|
|
Jul 25 08:21:44 PM PDT 24 |
Jul 25 09:01:48 PM PDT 24 |
13693034920 ps |
| T791 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2782209424 |
|
|
Jul 25 08:34:26 PM PDT 24 |
Jul 25 08:40:44 PM PDT 24 |
4561223084 ps |
| T1319 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.395424427 |
|
|
Jul 25 08:03:57 PM PDT 24 |
Jul 25 08:45:58 PM PDT 24 |
11836308150 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2303776647 |
|
|
Jul 25 08:20:28 PM PDT 24 |
Jul 25 08:28:23 PM PDT 24 |
5341413680 ps |
| T1320 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1466194399 |
|
|
Jul 25 08:00:22 PM PDT 24 |
Jul 25 08:11:05 PM PDT 24 |
3799599400 ps |
| T1321 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4190253298 |
|
|
Jul 25 08:10:14 PM PDT 24 |
Jul 25 08:32:02 PM PDT 24 |
5907887534 ps |
| T1322 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.815681589 |
|
|
Jul 25 08:28:26 PM PDT 24 |
Jul 25 09:28:57 PM PDT 24 |
15364043086 ps |
| T1323 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458890264 |
|
|
Jul 25 08:35:16 PM PDT 24 |
Jul 25 08:43:47 PM PDT 24 |
4096875384 ps |
| T721 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.188485259 |
|
|
Jul 25 08:26:49 PM PDT 24 |
Jul 25 08:37:45 PM PDT 24 |
4984732376 ps |
| T1324 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2375784538 |
|
|
Jul 25 08:29:02 PM PDT 24 |
Jul 25 09:21:12 PM PDT 24 |
15259178428 ps |
| T799 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.166104792 |
|
|
Jul 25 08:31:41 PM PDT 24 |
Jul 25 08:39:53 PM PDT 24 |
4299829260 ps |
| T755 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1150382897 |
|
|
Jul 25 08:31:59 PM PDT 24 |
Jul 25 08:40:33 PM PDT 24 |
4864114320 ps |
| T1325 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879000365 |
|
|
Jul 25 08:28:20 PM PDT 24 |
Jul 25 08:34:35 PM PDT 24 |
3402987360 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.340107758 |
|
|
Jul 25 08:25:36 PM PDT 24 |
Jul 25 08:28:47 PM PDT 24 |
3099362490 ps |
| T1327 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3102159658 |
|
|
Jul 25 08:02:47 PM PDT 24 |
Jul 25 08:13:18 PM PDT 24 |
3489184126 ps |
| T1328 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.944840207 |
|
|
Jul 25 08:00:06 PM PDT 24 |
Jul 25 08:05:27 PM PDT 24 |
3367088242 ps |
| T1329 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3496948790 |
|
|
Jul 25 08:09:32 PM PDT 24 |
Jul 25 09:17:19 PM PDT 24 |
15100079300 ps |
| T406 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3684269326 |
|
|
Jul 25 08:02:53 PM PDT 24 |
Jul 25 08:31:46 PM PDT 24 |
21927556544 ps |
| T1330 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2678725532 |
|
|
Jul 25 08:07:53 PM PDT 24 |
Jul 25 08:15:38 PM PDT 24 |
5700805512 ps |
| T1331 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2844817540 |
|
|
Jul 25 08:25:28 PM PDT 24 |
Jul 25 08:35:26 PM PDT 24 |
4667576768 ps |
| T1332 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1143924945 |
|
|
Jul 25 08:07:52 PM PDT 24 |
Jul 25 09:39:36 PM PDT 24 |
45814889300 ps |
| T1333 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.856564263 |
|
|
Jul 25 08:01:20 PM PDT 24 |
Jul 25 08:07:42 PM PDT 24 |
3329058795 ps |
| T1334 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2397909550 |
|
|
Jul 25 08:15:38 PM PDT 24 |
Jul 25 08:20:11 PM PDT 24 |
3216244548 ps |
| T782 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.878876263 |
|
|
Jul 25 08:27:59 PM PDT 24 |
Jul 25 08:36:41 PM PDT 24 |
4484878836 ps |
| T61 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2010827886 |
|
|
Jul 25 08:18:06 PM PDT 24 |
Jul 25 08:23:29 PM PDT 24 |
3734551090 ps |
| T806 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2277069319 |
|
|
Jul 25 08:32:15 PM PDT 24 |
Jul 25 08:49:27 PM PDT 24 |
5363175032 ps |
| T1335 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.136288467 |
|
|
Jul 25 08:08:52 PM PDT 24 |
Jul 25 08:14:44 PM PDT 24 |
3063800258 ps |
| T1336 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2700922020 |
|
|
Jul 25 08:18:56 PM PDT 24 |
Jul 25 08:20:48 PM PDT 24 |
2311834382 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.800073455 |
|
|
Jul 25 08:25:23 PM PDT 24 |
Jul 25 08:31:01 PM PDT 24 |
2928669811 ps |
| T1337 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1562782829 |
|
|
Jul 25 08:18:43 PM PDT 24 |
Jul 25 09:57:35 PM PDT 24 |
48541455868 ps |
| T1338 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1600833766 |
|
|
Jul 25 08:29:12 PM PDT 24 |
Jul 25 08:41:45 PM PDT 24 |
11325815513 ps |
| T111 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1553061746 |
|
|
Jul 25 08:26:49 PM PDT 24 |
Jul 25 08:33:36 PM PDT 24 |
4499049174 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1854443514 |
|
|
Jul 25 08:05:43 PM PDT 24 |
Jul 25 08:29:23 PM PDT 24 |
17502065330 ps |
| T1340 |
/workspace/coverage/default/1.chip_sw_aes_idle.341087960 |
|
|
Jul 25 08:08:25 PM PDT 24 |
Jul 25 08:11:10 PM PDT 24 |
2120066936 ps |
| T729 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411184619 |
|
|
Jul 25 08:37:36 PM PDT 24 |
Jul 25 08:45:12 PM PDT 24 |
4373640434 ps |
| T1341 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.860141985 |
|
|
Jul 25 08:28:04 PM PDT 24 |
Jul 25 09:30:02 PM PDT 24 |
18015863200 ps |
| T1342 |
/workspace/coverage/default/1.chip_sw_aes_entropy.734855189 |
|
|
Jul 25 08:09:09 PM PDT 24 |
Jul 25 08:13:11 PM PDT 24 |
3101072560 ps |
| T1343 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3087139755 |
|
|
Jul 25 08:00:42 PM PDT 24 |
Jul 25 08:17:02 PM PDT 24 |
6598841660 ps |
| T29 |
/workspace/coverage/default/0.chip_sw_gpio.246094972 |
|
|
Jul 25 07:58:36 PM PDT 24 |
Jul 25 08:06:45 PM PDT 24 |
3800090242 ps |
| T1344 |
/workspace/coverage/default/1.rom_e2e_smoke.1709579819 |
|
|
Jul 25 08:22:00 PM PDT 24 |
Jul 25 09:32:09 PM PDT 24 |
14907152042 ps |
| T1345 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3485464719 |
|
|
Jul 25 08:20:29 PM PDT 24 |
Jul 25 08:30:38 PM PDT 24 |
6068523400 ps |