| T202 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4109100725 |
|
|
Jul 27 08:02:02 PM PDT 24 |
Jul 27 08:14:49 PM PDT 24 |
4526157110 ps |
| T965 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.278131303 |
|
|
Jul 27 08:15:22 PM PDT 24 |
Jul 27 09:26:37 PM PDT 24 |
14525880301 ps |
| T243 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1850560184 |
|
|
Jul 27 08:24:55 PM PDT 24 |
Jul 27 08:38:11 PM PDT 24 |
6609866566 ps |
| T251 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3054658447 |
|
|
Jul 27 08:00:02 PM PDT 24 |
Jul 27 08:05:58 PM PDT 24 |
3413253030 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.562231688 |
|
|
Jul 27 07:52:53 PM PDT 24 |
Jul 27 09:27:36 PM PDT 24 |
26899245440 ps |
| T967 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2747070862 |
|
|
Jul 27 08:22:38 PM PDT 24 |
Jul 27 08:34:55 PM PDT 24 |
11140375073 ps |
| T461 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2432629986 |
|
|
Jul 27 07:54:42 PM PDT 24 |
Jul 27 08:12:01 PM PDT 24 |
5770921024 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1533252984 |
|
|
Jul 27 08:15:28 PM PDT 24 |
Jul 27 08:21:12 PM PDT 24 |
2993848966 ps |
| T969 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3170529256 |
|
|
Jul 27 08:17:49 PM PDT 24 |
Jul 27 08:24:57 PM PDT 24 |
3950571116 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_example_flash.1136625811 |
|
|
Jul 27 07:55:51 PM PDT 24 |
Jul 27 07:59:33 PM PDT 24 |
2790202564 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1577294368 |
|
|
Jul 27 08:11:47 PM PDT 24 |
Jul 27 08:20:21 PM PDT 24 |
3542764822 ps |
| T254 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3242105864 |
|
|
Jul 27 07:55:34 PM PDT 24 |
Jul 27 08:31:16 PM PDT 24 |
11584228273 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3305086690 |
|
|
Jul 27 07:51:28 PM PDT 24 |
Jul 27 07:55:51 PM PDT 24 |
3053648292 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1766403224 |
|
|
Jul 27 07:53:26 PM PDT 24 |
Jul 27 08:02:15 PM PDT 24 |
5759590032 ps |
| T455 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4119738629 |
|
|
Jul 27 07:54:30 PM PDT 24 |
Jul 27 08:56:04 PM PDT 24 |
24408957016 ps |
| T149 |
/workspace/coverage/default/2.rom_raw_unlock.121910276 |
|
|
Jul 27 08:16:52 PM PDT 24 |
Jul 27 08:21:11 PM PDT 24 |
5713753198 ps |
| T114 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2203919147 |
|
|
Jul 27 07:53:18 PM PDT 24 |
Jul 27 08:11:54 PM PDT 24 |
6920746875 ps |
| T378 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1576509934 |
|
|
Jul 27 08:26:10 PM PDT 24 |
Jul 27 08:37:44 PM PDT 24 |
5528283218 ps |
| T432 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.776130585 |
|
|
Jul 27 08:17:08 PM PDT 24 |
Jul 27 08:23:32 PM PDT 24 |
3607698754 ps |
| T449 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3855087630 |
|
|
Jul 27 08:33:25 PM PDT 24 |
Jul 27 08:45:48 PM PDT 24 |
5772148540 ps |
| T450 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1446175338 |
|
|
Jul 27 08:28:10 PM PDT 24 |
Jul 27 08:39:23 PM PDT 24 |
6168515896 ps |
| T451 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3257072098 |
|
|
Jul 27 08:08:10 PM PDT 24 |
Jul 27 08:13:48 PM PDT 24 |
2971447690 ps |
| T23 |
/workspace/coverage/default/1.chip_sw_gpio.2798664309 |
|
|
Jul 27 07:55:09 PM PDT 24 |
Jul 27 08:02:52 PM PDT 24 |
3929878638 ps |
| T452 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3441308602 |
|
|
Jul 27 08:11:27 PM PDT 24 |
Jul 27 08:41:07 PM PDT 24 |
8106420918 ps |
| T90 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2820170106 |
|
|
Jul 27 07:51:39 PM PDT 24 |
Jul 27 08:11:22 PM PDT 24 |
12481949320 ps |
| T274 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3023505059 |
|
|
Jul 27 08:08:49 PM PDT 24 |
Jul 27 09:30:22 PM PDT 24 |
15067149640 ps |
| T453 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2434236345 |
|
|
Jul 27 08:05:33 PM PDT 24 |
Jul 27 08:14:39 PM PDT 24 |
5123847340 ps |
| T222 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1683785726 |
|
|
Jul 27 07:56:41 PM PDT 24 |
Jul 27 09:16:32 PM PDT 24 |
15453075436 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.895864415 |
|
|
Jul 27 07:51:48 PM PDT 24 |
Jul 27 07:58:05 PM PDT 24 |
3933762140 ps |
| T972 |
/workspace/coverage/default/2.rom_e2e_smoke.366303815 |
|
|
Jul 27 08:20:25 PM PDT 24 |
Jul 27 09:20:44 PM PDT 24 |
15284159956 ps |
| T244 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1650997135 |
|
|
Jul 27 08:24:48 PM PDT 24 |
Jul 27 08:35:54 PM PDT 24 |
4534211614 ps |
| T232 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.681167518 |
|
|
Jul 27 07:55:20 PM PDT 24 |
Jul 27 09:19:59 PM PDT 24 |
51090269762 ps |
| T353 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.5372366 |
|
|
Jul 27 08:03:15 PM PDT 24 |
Jul 27 08:24:13 PM PDT 24 |
5970915908 ps |
| T180 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.800288241 |
|
|
Jul 27 08:02:39 PM PDT 24 |
Jul 27 08:10:41 PM PDT 24 |
4539124300 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2609469950 |
|
|
Jul 27 08:09:46 PM PDT 24 |
Jul 27 09:40:47 PM PDT 24 |
43315658937 ps |
| T347 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1854109000 |
|
|
Jul 27 08:05:20 PM PDT 24 |
Jul 27 08:20:41 PM PDT 24 |
5251034792 ps |
| T20 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2932684541 |
|
|
Jul 27 08:00:13 PM PDT 24 |
Jul 27 09:16:36 PM PDT 24 |
20016318103 ps |
| T227 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2836103594 |
|
|
Jul 27 08:04:45 PM PDT 24 |
Jul 27 08:46:58 PM PDT 24 |
10429864288 ps |
| T780 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.870402001 |
|
|
Jul 27 08:06:08 PM PDT 24 |
Jul 27 08:14:46 PM PDT 24 |
3787917138 ps |
| T111 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4171478421 |
|
|
Jul 27 08:16:43 PM PDT 24 |
Jul 27 09:16:55 PM PDT 24 |
22837470064 ps |
| T275 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.763411449 |
|
|
Jul 27 07:59:36 PM PDT 24 |
Jul 27 09:22:03 PM PDT 24 |
17534865430 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1728386939 |
|
|
Jul 27 08:14:18 PM PDT 24 |
Jul 27 08:21:31 PM PDT 24 |
5144055114 ps |
| T738 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1921321237 |
|
|
Jul 27 08:10:53 PM PDT 24 |
Jul 27 08:15:14 PM PDT 24 |
3365333322 ps |
| T974 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3448583793 |
|
|
Jul 27 07:54:31 PM PDT 24 |
Jul 27 08:08:32 PM PDT 24 |
8155664894 ps |
| T373 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.117138972 |
|
|
Jul 27 07:53:02 PM PDT 24 |
Jul 27 08:02:58 PM PDT 24 |
4566138529 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.125620956 |
|
|
Jul 27 08:03:17 PM PDT 24 |
Jul 27 08:09:29 PM PDT 24 |
3450568846 ps |
| T174 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3926470107 |
|
|
Jul 27 08:13:58 PM PDT 24 |
Jul 27 08:28:38 PM PDT 24 |
8542789349 ps |
| T317 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3675042461 |
|
|
Jul 27 08:29:40 PM PDT 24 |
Jul 27 08:38:32 PM PDT 24 |
4685594260 ps |
| T318 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.470528804 |
|
|
Jul 27 08:28:55 PM PDT 24 |
Jul 27 08:41:07 PM PDT 24 |
5450530472 ps |
| T319 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1149353842 |
|
|
Jul 27 08:05:14 PM PDT 24 |
Jul 27 08:16:14 PM PDT 24 |
5219771080 ps |
| T320 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2564942218 |
|
|
Jul 27 08:04:38 PM PDT 24 |
Jul 27 09:19:06 PM PDT 24 |
14049723479 ps |
| T88 |
/workspace/coverage/default/2.chip_jtag_mem_access.1890652593 |
|
|
Jul 27 08:07:11 PM PDT 24 |
Jul 27 08:32:31 PM PDT 24 |
13412137800 ps |
| T321 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3140994228 |
|
|
Jul 27 08:06:26 PM PDT 24 |
Jul 27 08:19:51 PM PDT 24 |
4275141182 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.626796379 |
|
|
Jul 27 07:53:11 PM PDT 24 |
Jul 27 08:11:08 PM PDT 24 |
13488915523 ps |
| T323 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2812385685 |
|
|
Jul 27 07:57:30 PM PDT 24 |
Jul 27 09:12:13 PM PDT 24 |
14124539472 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.2482959228 |
|
|
Jul 27 07:52:58 PM PDT 24 |
Jul 27 08:24:07 PM PDT 24 |
8122766400 ps |
| T976 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.3191633063 |
|
|
Jul 27 07:58:54 PM PDT 24 |
Jul 27 09:11:59 PM PDT 24 |
15847677524 ps |
| T810 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.220289893 |
|
|
Jul 27 08:26:37 PM PDT 24 |
Jul 27 08:38:22 PM PDT 24 |
4365444656 ps |
| T822 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.770187161 |
|
|
Jul 27 08:24:23 PM PDT 24 |
Jul 27 08:37:06 PM PDT 24 |
5200962236 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1328471570 |
|
|
Jul 27 08:14:56 PM PDT 24 |
Jul 27 08:19:38 PM PDT 24 |
2819722319 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4157454381 |
|
|
Jul 27 08:02:45 PM PDT 24 |
Jul 27 08:15:06 PM PDT 24 |
5264656820 ps |
| T398 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.361401958 |
|
|
Jul 27 08:14:07 PM PDT 24 |
Jul 27 08:24:19 PM PDT 24 |
5301913780 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1207546853 |
|
|
Jul 27 08:07:36 PM PDT 24 |
Jul 27 08:11:00 PM PDT 24 |
2902497935 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2743408372 |
|
|
Jul 27 07:52:24 PM PDT 24 |
Jul 27 07:57:58 PM PDT 24 |
7033108377 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3262260800 |
|
|
Jul 27 07:54:35 PM PDT 24 |
Jul 27 08:04:49 PM PDT 24 |
6227660004 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2780029463 |
|
|
Jul 27 08:09:49 PM PDT 24 |
Jul 27 11:06:08 PM PDT 24 |
57372397544 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1234130134 |
|
|
Jul 27 08:11:20 PM PDT 24 |
Jul 27 08:25:03 PM PDT 24 |
7405806766 ps |
| T379 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1505860469 |
|
|
Jul 27 08:28:42 PM PDT 24 |
Jul 27 08:37:35 PM PDT 24 |
4673696508 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2963701810 |
|
|
Jul 27 08:13:48 PM PDT 24 |
Jul 27 08:23:45 PM PDT 24 |
7259827367 ps |
| T982 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.433837898 |
|
|
Jul 27 08:13:09 PM PDT 24 |
Jul 27 09:19:20 PM PDT 24 |
14551123405 ps |
| T776 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3431680873 |
|
|
Jul 27 08:23:19 PM PDT 24 |
Jul 27 08:33:14 PM PDT 24 |
5885729736 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2048152777 |
|
|
Jul 27 08:15:46 PM PDT 24 |
Jul 27 08:19:33 PM PDT 24 |
2441178231 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2803094628 |
|
|
Jul 27 08:10:40 PM PDT 24 |
Jul 27 08:23:18 PM PDT 24 |
4470378234 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1873712759 |
|
|
Jul 27 08:07:14 PM PDT 24 |
Jul 27 08:44:31 PM PDT 24 |
18233875463 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1606768226 |
|
|
Jul 27 08:08:36 PM PDT 24 |
Jul 27 08:13:32 PM PDT 24 |
3017656460 ps |
| T986 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1441202612 |
|
|
Jul 27 07:57:02 PM PDT 24 |
Jul 27 08:00:56 PM PDT 24 |
2069684110 ps |
| T374 |
/workspace/coverage/default/2.chip_sw_hmac_enc.4117248127 |
|
|
Jul 27 08:13:54 PM PDT 24 |
Jul 27 08:17:53 PM PDT 24 |
2496913936 ps |
| T711 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.159123687 |
|
|
Jul 27 08:17:18 PM PDT 24 |
Jul 28 02:33:15 AM PDT 24 |
157106643658 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.943403484 |
|
|
Jul 27 08:05:15 PM PDT 24 |
Jul 27 08:10:59 PM PDT 24 |
3690926920 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.1129582079 |
|
|
Jul 27 08:12:43 PM PDT 24 |
Jul 27 08:36:58 PM PDT 24 |
7500575512 ps |
| T989 |
/workspace/coverage/default/0.chip_sw_aes_enc.3660306978 |
|
|
Jul 27 07:52:16 PM PDT 24 |
Jul 27 07:56:39 PM PDT 24 |
2223947640 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_kmac_idle.3808121460 |
|
|
Jul 27 08:08:19 PM PDT 24 |
Jul 27 08:12:45 PM PDT 24 |
2966386620 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.785057977 |
|
|
Jul 27 08:14:07 PM PDT 24 |
Jul 27 08:51:40 PM PDT 24 |
24584465480 ps |
| T462 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.860246 |
|
|
Jul 27 08:12:41 PM PDT 24 |
Jul 27 08:31:45 PM PDT 24 |
7346024689 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.203322121 |
|
|
Jul 27 07:53:09 PM PDT 24 |
Jul 27 08:11:17 PM PDT 24 |
9758875409 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_flash_init.3648292028 |
|
|
Jul 27 07:51:29 PM PDT 24 |
Jul 27 08:27:54 PM PDT 24 |
23726780968 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3627958279 |
|
|
Jul 27 08:11:43 PM PDT 24 |
Jul 27 08:15:17 PM PDT 24 |
3143188200 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2863950941 |
|
|
Jul 27 07:52:53 PM PDT 24 |
Jul 27 09:57:41 PM PDT 24 |
31737616566 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1469141502 |
|
|
Jul 27 08:10:28 PM PDT 24 |
Jul 27 08:17:20 PM PDT 24 |
6128452950 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_example_flash.1662279529 |
|
|
Jul 27 07:52:07 PM PDT 24 |
Jul 27 07:54:34 PM PDT 24 |
2803010140 ps |
| T996 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.298985044 |
|
|
Jul 27 08:21:26 PM PDT 24 |
Jul 27 09:33:14 PM PDT 24 |
15675577920 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1896636844 |
|
|
Jul 27 08:00:37 PM PDT 24 |
Jul 27 09:02:51 PM PDT 24 |
17944978140 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3054681991 |
|
|
Jul 27 08:10:53 PM PDT 24 |
Jul 27 08:25:22 PM PDT 24 |
9554542003 ps |
| T848 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.265820525 |
|
|
Jul 27 08:29:29 PM PDT 24 |
Jul 27 08:38:05 PM PDT 24 |
4635073326 ps |
| T384 |
/workspace/coverage/default/0.chip_sival_flash_info_access.774075186 |
|
|
Jul 27 07:52:13 PM PDT 24 |
Jul 27 07:56:36 PM PDT 24 |
3082048484 ps |
| T755 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1221125741 |
|
|
Jul 27 08:16:52 PM PDT 24 |
Jul 27 08:30:26 PM PDT 24 |
10759908764 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_edn_kat.3132381745 |
|
|
Jul 27 08:01:22 PM PDT 24 |
Jul 27 08:11:08 PM PDT 24 |
2956000568 ps |
| T819 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.573612892 |
|
|
Jul 27 08:23:13 PM PDT 24 |
Jul 27 08:34:19 PM PDT 24 |
5610993952 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2560077454 |
|
|
Jul 27 07:56:48 PM PDT 24 |
Jul 27 08:05:02 PM PDT 24 |
3996021304 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1699654054 |
|
|
Jul 27 08:07:44 PM PDT 24 |
Jul 27 08:43:39 PM PDT 24 |
8854773280 ps |
| T1001 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.866393932 |
|
|
Jul 27 08:14:22 PM PDT 24 |
Jul 27 08:25:42 PM PDT 24 |
4321812560 ps |
| T1002 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3457260011 |
|
|
Jul 27 08:22:54 PM PDT 24 |
Jul 27 08:33:43 PM PDT 24 |
6461242706 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1881186316 |
|
|
Jul 27 08:17:28 PM PDT 24 |
Jul 27 08:22:46 PM PDT 24 |
3498911984 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2588550434 |
|
|
Jul 27 07:57:10 PM PDT 24 |
Jul 27 08:11:51 PM PDT 24 |
6294821898 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_edn_kat.1934171934 |
|
|
Jul 27 08:11:40 PM PDT 24 |
Jul 27 08:20:59 PM PDT 24 |
3562771624 ps |
| T847 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1164924023 |
|
|
Jul 27 08:27:41 PM PDT 24 |
Jul 27 08:35:29 PM PDT 24 |
3560235760 ps |
| T725 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.363099011 |
|
|
Jul 27 08:08:07 PM PDT 24 |
Jul 27 08:10:00 PM PDT 24 |
3127724410 ps |
| T342 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2636130449 |
|
|
Jul 27 08:13:46 PM PDT 24 |
Jul 27 08:27:27 PM PDT 24 |
5045413288 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2860444868 |
|
|
Jul 27 08:13:49 PM PDT 24 |
Jul 27 08:19:53 PM PDT 24 |
3270448779 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2003155194 |
|
|
Jul 27 07:53:32 PM PDT 24 |
Jul 27 07:59:38 PM PDT 24 |
7164589736 ps |
| T785 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.4068686563 |
|
|
Jul 27 08:22:42 PM PDT 24 |
Jul 27 08:32:49 PM PDT 24 |
4863203872 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.913376735 |
|
|
Jul 27 08:14:29 PM PDT 24 |
Jul 27 08:21:43 PM PDT 24 |
5822147732 ps |
| T834 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.836926734 |
|
|
Jul 27 08:19:20 PM PDT 24 |
Jul 27 08:27:14 PM PDT 24 |
4641903008 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4265660892 |
|
|
Jul 27 08:16:48 PM PDT 24 |
Jul 27 08:21:13 PM PDT 24 |
3355971924 ps |
| T824 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964293014 |
|
|
Jul 27 08:29:05 PM PDT 24 |
Jul 27 08:37:24 PM PDT 24 |
3596811616 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.685692780 |
|
|
Jul 27 07:54:25 PM PDT 24 |
Jul 27 09:25:49 PM PDT 24 |
47345916584 ps |
| T1010 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3051949329 |
|
|
Jul 27 08:02:10 PM PDT 24 |
Jul 27 09:07:19 PM PDT 24 |
14679158120 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1635257449 |
|
|
Jul 27 08:15:33 PM PDT 24 |
Jul 27 08:35:54 PM PDT 24 |
7645966526 ps |
| T1011 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3914524208 |
|
|
Jul 27 08:26:02 PM PDT 24 |
Jul 27 09:06:49 PM PDT 24 |
12954398574 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1701598045 |
|
|
Jul 27 08:05:32 PM PDT 24 |
Jul 27 08:14:04 PM PDT 24 |
5880928789 ps |
| T1012 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.415821717 |
|
|
Jul 27 07:57:16 PM PDT 24 |
Jul 27 08:09:14 PM PDT 24 |
3391156642 ps |
| T1013 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3499360994 |
|
|
Jul 27 08:20:16 PM PDT 24 |
Jul 27 08:31:22 PM PDT 24 |
4414794892 ps |
| T50 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3620425405 |
|
|
Jul 27 07:52:33 PM PDT 24 |
Jul 27 08:00:44 PM PDT 24 |
4115752348 ps |
| T429 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.246140677 |
|
|
Jul 27 07:54:08 PM PDT 24 |
Jul 27 07:56:45 PM PDT 24 |
2000600216 ps |
| T72 |
/workspace/coverage/default/1.chip_tap_straps_rma.1404994457 |
|
|
Jul 27 08:05:34 PM PDT 24 |
Jul 27 08:13:59 PM PDT 24 |
5604014074 ps |
| T454 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1774329001 |
|
|
Jul 27 08:28:16 PM PDT 24 |
Jul 27 08:39:47 PM PDT 24 |
5817163552 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.916785011 |
|
|
Jul 27 08:06:35 PM PDT 24 |
Jul 27 08:09:51 PM PDT 24 |
2603061971 ps |
| T308 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4241183062 |
|
|
Jul 27 07:53:23 PM PDT 24 |
Jul 27 08:07:10 PM PDT 24 |
5115635250 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3535986095 |
|
|
Jul 27 07:52:28 PM PDT 24 |
Jul 27 08:02:38 PM PDT 24 |
5003596952 ps |
| T310 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345945698 |
|
|
Jul 27 08:25:41 PM PDT 24 |
Jul 27 08:32:15 PM PDT 24 |
3342504328 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.847085343 |
|
|
Jul 27 07:56:10 PM PDT 24 |
Jul 27 09:20:50 PM PDT 24 |
45210379364 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1506524508 |
|
|
Jul 27 07:56:17 PM PDT 24 |
Jul 27 08:30:01 PM PDT 24 |
8830633940 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.898830765 |
|
|
Jul 27 08:14:36 PM PDT 24 |
Jul 27 08:20:11 PM PDT 24 |
3329228588 ps |
| T314 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1467980798 |
|
|
Jul 27 08:27:19 PM PDT 24 |
Jul 27 08:40:08 PM PDT 24 |
4939184560 ps |
| T132 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1025277811 |
|
|
Jul 27 08:05:36 PM PDT 24 |
Jul 27 08:14:41 PM PDT 24 |
7243043418 ps |
| T315 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.235178519 |
|
|
Jul 27 08:33:29 PM PDT 24 |
Jul 27 08:45:50 PM PDT 24 |
6143042942 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1059330533 |
|
|
Jul 27 07:59:08 PM PDT 24 |
Jul 27 08:04:24 PM PDT 24 |
3084707820 ps |
| T1015 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.1668917134 |
|
|
Jul 27 08:13:51 PM PDT 24 |
Jul 27 09:16:06 PM PDT 24 |
31343808055 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.127528185 |
|
|
Jul 27 08:07:21 PM PDT 24 |
Jul 27 08:25:35 PM PDT 24 |
6747232574 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3023593464 |
|
|
Jul 27 08:11:05 PM PDT 24 |
Jul 27 09:51:57 PM PDT 24 |
48853653590 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3262870534 |
|
|
Jul 27 07:55:00 PM PDT 24 |
Jul 27 08:11:17 PM PDT 24 |
7515784212 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2130078616 |
|
|
Jul 27 07:56:35 PM PDT 24 |
Jul 27 08:24:16 PM PDT 24 |
9332089384 ps |
| T1018 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3906436992 |
|
|
Jul 27 07:53:20 PM PDT 24 |
Jul 27 08:11:59 PM PDT 24 |
5453879280 ps |
| T138 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3669148316 |
|
|
Jul 27 08:19:25 PM PDT 24 |
Jul 27 08:29:47 PM PDT 24 |
4370279512 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.401556469 |
|
|
Jul 27 07:55:08 PM PDT 24 |
Jul 27 07:58:58 PM PDT 24 |
2663189428 ps |
| T809 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2922460113 |
|
|
Jul 27 08:22:28 PM PDT 24 |
Jul 27 08:30:15 PM PDT 24 |
3711990680 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1117749272 |
|
|
Jul 27 08:09:29 PM PDT 24 |
Jul 27 09:49:51 PM PDT 24 |
47491821220 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_aes_idle.785731362 |
|
|
Jul 27 07:55:31 PM PDT 24 |
Jul 27 07:59:48 PM PDT 24 |
3443299026 ps |
| T425 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.461806896 |
|
|
Jul 27 07:53:34 PM PDT 24 |
Jul 27 07:58:50 PM PDT 24 |
5386895256 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.322916400 |
|
|
Jul 27 08:17:30 PM PDT 24 |
Jul 27 08:20:20 PM PDT 24 |
2836161700 ps |
| T798 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.4155428474 |
|
|
Jul 27 08:19:17 PM PDT 24 |
Jul 27 08:32:13 PM PDT 24 |
6113816110 ps |
| T1022 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2448593730 |
|
|
Jul 27 08:05:44 PM PDT 24 |
Jul 27 08:09:01 PM PDT 24 |
2509043171 ps |
| T343 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.288230208 |
|
|
Jul 27 08:06:10 PM PDT 24 |
Jul 27 08:29:10 PM PDT 24 |
5671483336 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.77543897 |
|
|
Jul 27 08:07:05 PM PDT 24 |
Jul 27 08:17:22 PM PDT 24 |
9728059658 ps |
| T389 |
/workspace/coverage/default/2.chip_tap_straps_dev.611816596 |
|
|
Jul 27 08:14:41 PM PDT 24 |
Jul 27 08:19:50 PM PDT 24 |
4326136329 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3381377109 |
|
|
Jul 27 07:59:25 PM PDT 24 |
Jul 27 08:07:48 PM PDT 24 |
3869985352 ps |
| T463 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3162845316 |
|
|
Jul 27 08:02:58 PM PDT 24 |
Jul 27 08:26:56 PM PDT 24 |
6299049496 ps |
| T862 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.918874576 |
|
|
Jul 27 08:20:48 PM PDT 24 |
Jul 27 08:28:34 PM PDT 24 |
3727124920 ps |
| T731 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.935632181 |
|
|
Jul 27 08:28:20 PM PDT 24 |
Jul 27 08:36:10 PM PDT 24 |
5736874424 ps |
| T1024 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1683332381 |
|
|
Jul 27 07:55:36 PM PDT 24 |
Jul 27 08:03:41 PM PDT 24 |
4468754536 ps |
| T1025 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1225500564 |
|
|
Jul 27 08:01:09 PM PDT 24 |
Jul 27 09:12:33 PM PDT 24 |
15393496500 ps |
| T805 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3292681612 |
|
|
Jul 27 08:27:05 PM PDT 24 |
Jul 27 08:34:20 PM PDT 24 |
3512507918 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_example_rom.2670482243 |
|
|
Jul 27 08:08:27 PM PDT 24 |
Jul 27 08:11:09 PM PDT 24 |
2570296144 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3656304073 |
|
|
Jul 27 08:09:28 PM PDT 24 |
Jul 27 08:23:48 PM PDT 24 |
5226838774 ps |
| T1027 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3667544074 |
|
|
Jul 27 08:12:07 PM PDT 24 |
Jul 27 09:17:16 PM PDT 24 |
14983765873 ps |
| T172 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2032803003 |
|
|
Jul 27 07:56:10 PM PDT 24 |
Jul 27 07:59:12 PM PDT 24 |
3258394848 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3584958330 |
|
|
Jul 27 07:54:50 PM PDT 24 |
Jul 27 08:13:27 PM PDT 24 |
11792526410 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2515173178 |
|
|
Jul 27 08:14:21 PM PDT 24 |
Jul 27 08:26:36 PM PDT 24 |
3965494390 ps |
| T1030 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.806882245 |
|
|
Jul 27 08:10:39 PM PDT 24 |
Jul 27 08:27:51 PM PDT 24 |
7180184750 ps |
| T1031 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3545617122 |
|
|
Jul 27 08:21:32 PM PDT 24 |
Jul 27 09:37:29 PM PDT 24 |
15336074248 ps |
| T825 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3208341464 |
|
|
Jul 27 08:24:32 PM PDT 24 |
Jul 27 08:32:55 PM PDT 24 |
3922134836 ps |
| T203 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.407281443 |
|
|
Jul 27 08:11:59 PM PDT 24 |
Jul 27 08:38:49 PM PDT 24 |
23361425560 ps |
| T845 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531055575 |
|
|
Jul 27 08:25:57 PM PDT 24 |
Jul 27 08:32:52 PM PDT 24 |
3666466736 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.966781897 |
|
|
Jul 27 07:58:42 PM PDT 24 |
Jul 27 08:05:39 PM PDT 24 |
9563843974 ps |
| T800 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848684805 |
|
|
Jul 27 08:28:25 PM PDT 24 |
Jul 27 08:34:26 PM PDT 24 |
3310691110 ps |
| T828 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1034522258 |
|
|
Jul 27 08:28:25 PM PDT 24 |
Jul 27 08:37:35 PM PDT 24 |
5292198820 ps |
| T804 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.838064290 |
|
|
Jul 27 08:26:54 PM PDT 24 |
Jul 27 08:35:26 PM PDT 24 |
5047523488 ps |
| T758 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1155495763 |
|
|
Jul 27 08:29:14 PM PDT 24 |
Jul 27 08:42:04 PM PDT 24 |
6585228360 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.720856307 |
|
|
Jul 27 07:55:21 PM PDT 24 |
Jul 27 08:47:30 PM PDT 24 |
28515547593 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2368313130 |
|
|
Jul 27 08:17:26 PM PDT 24 |
Jul 27 08:21:55 PM PDT 24 |
3091303056 ps |
| T1034 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4045503775 |
|
|
Jul 27 07:58:55 PM PDT 24 |
Jul 27 08:53:11 PM PDT 24 |
11088136570 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2808592313 |
|
|
Jul 27 08:12:32 PM PDT 24 |
Jul 27 08:18:20 PM PDT 24 |
3128312388 ps |
| T1036 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1506364637 |
|
|
Jul 27 08:12:23 PM PDT 24 |
Jul 27 08:22:07 PM PDT 24 |
4333792736 ps |
| T390 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2415142742 |
|
|
Jul 27 08:21:59 PM PDT 24 |
Jul 27 08:28:07 PM PDT 24 |
3666957740 ps |
| T400 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1457508883 |
|
|
Jul 27 08:20:52 PM PDT 24 |
Jul 27 10:16:13 PM PDT 24 |
26781530412 ps |
| T401 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.1542725507 |
|
|
Jul 27 08:21:00 PM PDT 24 |
Jul 27 09:17:08 PM PDT 24 |
26133197585 ps |
| T402 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.453670031 |
|
|
Jul 27 08:25:14 PM PDT 24 |
Jul 27 08:33:51 PM PDT 24 |
4814751064 ps |
| T403 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1913014141 |
|
|
Jul 27 08:23:42 PM PDT 24 |
Jul 27 08:33:44 PM PDT 24 |
8336315928 ps |
| T387 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2619274441 |
|
|
Jul 27 07:53:18 PM PDT 24 |
Jul 27 07:57:33 PM PDT 24 |
2741266719 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4221800302 |
|
|
Jul 27 07:53:16 PM PDT 24 |
Jul 27 08:00:10 PM PDT 24 |
3724092910 ps |
| T404 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.404445936 |
|
|
Jul 27 07:55:51 PM PDT 24 |
Jul 27 09:10:41 PM PDT 24 |
15165620280 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_power_virus.3121878940 |
|
|
Jul 27 08:12:12 PM PDT 24 |
Jul 27 08:40:52 PM PDT 24 |
5883926472 ps |
| T151 |
/workspace/coverage/default/1.rom_raw_unlock.1780045667 |
|
|
Jul 27 08:08:01 PM PDT 24 |
Jul 27 08:11:30 PM PDT 24 |
4418049350 ps |
| T1037 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3641533376 |
|
|
Jul 27 08:10:22 PM PDT 24 |
Jul 27 08:17:26 PM PDT 24 |
6304571867 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3015113620 |
|
|
Jul 27 08:10:41 PM PDT 24 |
Jul 27 08:15:34 PM PDT 24 |
2566445883 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4262184011 |
|
|
Jul 27 08:12:36 PM PDT 24 |
Jul 27 08:16:02 PM PDT 24 |
2994366200 ps |
| T329 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.501754251 |
|
|
Jul 27 08:23:55 PM PDT 24 |
Jul 27 08:36:34 PM PDT 24 |
5730592868 ps |
| T331 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3920362134 |
|
|
Jul 27 08:05:22 PM PDT 24 |
Jul 27 08:28:03 PM PDT 24 |
10248458008 ps |
| T332 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2909451762 |
|
|
Jul 27 08:09:25 PM PDT 24 |
Jul 27 08:14:23 PM PDT 24 |
3089779754 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1904819999 |
|
|
Jul 27 07:59:05 PM PDT 24 |
Jul 27 08:09:01 PM PDT 24 |
6871487784 ps |
| T334 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.750814766 |
|
|
Jul 27 07:56:04 PM PDT 24 |
Jul 27 08:28:16 PM PDT 24 |
8442065342 ps |
| T335 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.450250865 |
|
|
Jul 27 08:02:55 PM PDT 24 |
Jul 27 08:41:49 PM PDT 24 |
8686439516 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1084113391 |
|
|
Jul 27 08:11:38 PM PDT 24 |
Jul 27 08:20:03 PM PDT 24 |
17981594396 ps |
| T337 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.508175255 |
|
|
Jul 27 08:12:34 PM PDT 24 |
Jul 27 08:43:46 PM PDT 24 |
10569465038 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1316640905 |
|
|
Jul 27 07:51:05 PM PDT 24 |
Jul 27 08:23:46 PM PDT 24 |
8406258648 ps |
| T339 |
/workspace/coverage/default/0.chip_sw_edn_kat.267685326 |
|
|
Jul 27 07:53:35 PM PDT 24 |
Jul 27 08:03:38 PM PDT 24 |
3455394392 ps |
| T1039 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1914032336 |
|
|
Jul 27 08:21:14 PM PDT 24 |
Jul 27 09:15:51 PM PDT 24 |
14591597336 ps |
| T228 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2273175648 |
|
|
Jul 27 07:53:39 PM PDT 24 |
Jul 27 08:16:59 PM PDT 24 |
6710507640 ps |
| T1040 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1222256419 |
|
|
Jul 27 08:09:24 PM PDT 24 |
Jul 27 08:13:09 PM PDT 24 |
2113196000 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1978335141 |
|
|
Jul 27 08:10:03 PM PDT 24 |
Jul 27 08:24:08 PM PDT 24 |
5402496960 ps |
| T430 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1753750032 |
|
|
Jul 27 08:04:14 PM PDT 24 |
Jul 27 08:11:26 PM PDT 24 |
8994044405 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.625312629 |
|
|
Jul 27 08:12:20 PM PDT 24 |
Jul 27 09:06:22 PM PDT 24 |
26006764104 ps |
| T1042 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2193031929 |
|
|
Jul 27 08:18:16 PM PDT 24 |
Jul 27 08:23:26 PM PDT 24 |
3262563405 ps |
| T324 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.238795854 |
|
|
Jul 27 07:59:02 PM PDT 24 |
Jul 27 08:06:41 PM PDT 24 |
3692404020 ps |
| T1043 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4214818659 |
|
|
Jul 27 08:15:25 PM PDT 24 |
Jul 27 08:19:08 PM PDT 24 |
3048350754 ps |
| T854 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2900482271 |
|
|
Jul 27 08:24:20 PM PDT 24 |
Jul 27 08:31:27 PM PDT 24 |
3756314450 ps |
| T855 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3049490498 |
|
|
Jul 27 08:27:06 PM PDT 24 |
Jul 27 08:34:58 PM PDT 24 |
4553024582 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1120468266 |
|
|
Jul 27 08:15:42 PM PDT 24 |
Jul 27 08:44:28 PM PDT 24 |
6896158424 ps |
| T1044 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2991056519 |
|
|
Jul 27 08:24:05 PM PDT 24 |
Jul 27 08:31:41 PM PDT 24 |
4146055672 ps |
| T1045 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.915473112 |
|
|
Jul 27 08:27:43 PM PDT 24 |
Jul 27 08:36:28 PM PDT 24 |
4148351232 ps |
| T1046 |
/workspace/coverage/default/0.rom_keymgr_functest.4232791118 |
|
|
Jul 27 07:52:00 PM PDT 24 |
Jul 27 08:00:32 PM PDT 24 |
4039283256 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2634581706 |
|
|
Jul 27 07:59:37 PM PDT 24 |
Jul 27 08:19:23 PM PDT 24 |
8522036554 ps |
| T1048 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1162656254 |
|
|
Jul 27 08:21:48 PM PDT 24 |
Jul 27 09:43:41 PM PDT 24 |
22604257336 ps |
| T829 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599925417 |
|
|
Jul 27 08:23:11 PM PDT 24 |
Jul 27 08:29:08 PM PDT 24 |
3722653920 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.4211054278 |
|
|
Jul 27 08:09:02 PM PDT 24 |
Jul 27 08:13:53 PM PDT 24 |
2803188262 ps |
| T1050 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.127568994 |
|
|
Jul 27 08:03:26 PM PDT 24 |
Jul 27 08:07:34 PM PDT 24 |
2948498602 ps |
| T777 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.146029385 |
|
|
Jul 27 08:27:42 PM PDT 24 |
Jul 27 08:35:33 PM PDT 24 |
3898023660 ps |
| T846 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3567098224 |
|
|
Jul 27 08:26:17 PM PDT 24 |
Jul 27 08:36:49 PM PDT 24 |
6136432648 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.536627938 |
|
|
Jul 27 07:52:00 PM PDT 24 |
Jul 27 08:01:05 PM PDT 24 |
7534265860 ps |
| T773 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187663959 |
|
|
Jul 27 08:21:42 PM PDT 24 |
Jul 27 08:28:34 PM PDT 24 |
4148899658 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3037100399 |
|
|
Jul 27 08:11:24 PM PDT 24 |
Jul 27 09:19:57 PM PDT 24 |
18315294713 ps |
| T1053 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1702818550 |
|
|
Jul 27 08:07:45 PM PDT 24 |
Jul 27 09:12:11 PM PDT 24 |
24611276183 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2583976612 |
|
|
Jul 27 08:04:28 PM PDT 24 |
Jul 27 08:09:02 PM PDT 24 |
2832035960 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4224268287 |
|
|
Jul 27 07:53:24 PM PDT 24 |
Jul 27 08:03:01 PM PDT 24 |
4669492726 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.3568046888 |
|
|
Jul 27 08:18:02 PM PDT 24 |
Jul 27 08:54:33 PM PDT 24 |
10464751868 ps |
| T237 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.788523251 |
|
|
Jul 27 07:54:52 PM PDT 24 |
Jul 27 09:36:35 PM PDT 24 |
49786609504 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.422121363 |
|
|
Jul 27 07:53:22 PM PDT 24 |
Jul 27 08:01:59 PM PDT 24 |
4915426609 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.257826588 |
|
|
Jul 27 08:01:50 PM PDT 24 |
Jul 27 09:14:34 PM PDT 24 |
17686811240 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2545439185 |
|
|
Jul 27 08:01:57 PM PDT 24 |
Jul 27 08:18:33 PM PDT 24 |
4792909688 ps |
| T83 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.1573951726 |
|
|
Jul 27 07:52:37 PM PDT 24 |
Jul 27 07:56:52 PM PDT 24 |
2340312208 ps |
| T325 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3929976098 |
|
|
Jul 27 08:14:58 PM PDT 24 |
Jul 27 08:23:25 PM PDT 24 |
3429371880 ps |
| T1059 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2892385201 |
|
|
Jul 27 08:10:43 PM PDT 24 |
Jul 27 08:48:19 PM PDT 24 |
34000078490 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.59219412 |
|
|
Jul 27 07:51:28 PM PDT 24 |
Jul 27 08:00:18 PM PDT 24 |
4181158440 ps |
| T752 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.420527758 |
|
|
Jul 27 08:24:33 PM PDT 24 |
Jul 27 08:29:53 PM PDT 24 |
3761988892 ps |
| T795 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.928722166 |
|
|
Jul 27 08:27:17 PM PDT 24 |
Jul 27 08:33:56 PM PDT 24 |
3933673252 ps |
| T60 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3070746667 |
|
|
Jul 27 07:52:26 PM PDT 24 |
Jul 27 08:15:34 PM PDT 24 |
21125101720 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3301376580 |
|
|
Jul 27 08:04:05 PM PDT 24 |
Jul 27 08:07:47 PM PDT 24 |
2307490568 ps |
| T1062 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1721110122 |
|
|
Jul 27 07:55:22 PM PDT 24 |
Jul 27 08:04:24 PM PDT 24 |
4567125196 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1289428246 |
|
|
Jul 27 07:54:26 PM PDT 24 |
Jul 27 08:00:12 PM PDT 24 |
3071868380 ps |
| T141 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1730633328 |
|
|
Jul 27 08:04:01 PM PDT 24 |
Jul 27 08:09:22 PM PDT 24 |
3522006642 ps |