| T32 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4193660060 |
|
|
Jul 27 08:10:49 PM PDT 24 |
Jul 27 08:20:05 PM PDT 24 |
6393668740 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.898461559 |
|
|
Jul 27 07:56:44 PM PDT 24 |
Jul 27 08:12:04 PM PDT 24 |
5702777032 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2873138870 |
|
|
Jul 27 07:53:32 PM PDT 24 |
Jul 27 08:19:23 PM PDT 24 |
12408437806 ps |
| T1065 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2267626610 |
|
|
Jul 27 08:06:44 PM PDT 24 |
Jul 27 08:39:32 PM PDT 24 |
10100094975 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3722358711 |
|
|
Jul 27 07:53:17 PM PDT 24 |
Jul 27 07:59:52 PM PDT 24 |
3909699016 ps |
| T1066 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.933469524 |
|
|
Jul 27 08:22:25 PM PDT 24 |
Jul 27 08:34:47 PM PDT 24 |
9635354849 ps |
| T1067 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.837939794 |
|
|
Jul 27 08:28:02 PM PDT 24 |
Jul 27 08:34:53 PM PDT 24 |
3994286776 ps |
| T200 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.547183730 |
|
|
Jul 27 07:56:07 PM PDT 24 |
Jul 27 10:52:01 PM PDT 24 |
60094482984 ps |
| T821 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592265249 |
|
|
Jul 27 08:28:55 PM PDT 24 |
Jul 27 08:35:00 PM PDT 24 |
3160274206 ps |
| T1068 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.290020731 |
|
|
Jul 27 08:21:04 PM PDT 24 |
Jul 27 09:26:16 PM PDT 24 |
18712148528 ps |
| T1069 |
/workspace/coverage/default/0.rom_e2e_smoke.3534321368 |
|
|
Jul 27 07:56:43 PM PDT 24 |
Jul 27 09:04:22 PM PDT 24 |
14450679498 ps |
| T1070 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.659149327 |
|
|
Jul 27 08:24:48 PM PDT 24 |
Jul 27 09:22:43 PM PDT 24 |
12514296624 ps |
| T1071 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.258380578 |
|
|
Jul 27 07:53:33 PM PDT 24 |
Jul 27 08:03:35 PM PDT 24 |
3833244014 ps |
| T778 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.822732704 |
|
|
Jul 27 07:55:25 PM PDT 24 |
Jul 27 08:03:40 PM PDT 24 |
5286502936 ps |
| T56 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.632602916 |
|
|
Jul 27 07:51:47 PM PDT 24 |
Jul 27 08:22:13 PM PDT 24 |
23471490322 ps |
| T1072 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4143106550 |
|
|
Jul 27 08:13:43 PM PDT 24 |
Jul 27 08:23:36 PM PDT 24 |
4246834582 ps |
| T51 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1849884320 |
|
|
Jul 27 07:44:38 PM PDT 24 |
Jul 27 08:05:17 PM PDT 24 |
12634227480 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.399462595 |
|
|
Jul 27 07:54:52 PM PDT 24 |
Jul 27 09:33:30 PM PDT 24 |
44436118920 ps |
| T289 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2819399020 |
|
|
Jul 27 08:04:17 PM PDT 24 |
Jul 27 08:15:13 PM PDT 24 |
4362524640 ps |
| T434 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.288450195 |
|
|
Jul 27 08:28:44 PM PDT 24 |
Jul 27 08:35:31 PM PDT 24 |
3496193980 ps |
| T435 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.141310021 |
|
|
Jul 27 08:12:04 PM PDT 24 |
Jul 27 08:34:31 PM PDT 24 |
5825852250 ps |
| T436 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4102675286 |
|
|
Jul 27 07:53:14 PM PDT 24 |
Jul 27 07:57:09 PM PDT 24 |
2063708422 ps |
| T437 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3400176528 |
|
|
Jul 27 08:24:34 PM PDT 24 |
Jul 27 08:33:49 PM PDT 24 |
5041541356 ps |
| T438 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1226009081 |
|
|
Jul 27 08:09:25 PM PDT 24 |
Jul 27 08:18:01 PM PDT 24 |
4752722344 ps |
| T439 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2035742629 |
|
|
Jul 27 08:05:47 PM PDT 24 |
Jul 27 08:17:31 PM PDT 24 |
3654118940 ps |
| T440 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1300370554 |
|
|
Jul 27 08:10:57 PM PDT 24 |
Jul 27 09:18:32 PM PDT 24 |
17031835534 ps |
| T255 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.240825481 |
|
|
Jul 27 07:56:28 PM PDT 24 |
Jul 27 08:29:38 PM PDT 24 |
10791162455 ps |
| T1073 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3027012773 |
|
|
Jul 27 07:53:39 PM PDT 24 |
Jul 27 08:02:12 PM PDT 24 |
5314996456 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_kmac_idle.820014939 |
|
|
Jul 27 07:53:08 PM PDT 24 |
Jul 27 07:56:04 PM PDT 24 |
2648053736 ps |
| T1075 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1543674556 |
|
|
Jul 27 07:57:00 PM PDT 24 |
Jul 27 08:17:06 PM PDT 24 |
7569310668 ps |
| T247 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.525101389 |
|
|
Jul 27 08:24:48 PM PDT 24 |
Jul 27 08:33:05 PM PDT 24 |
3377332840 ps |
| T1076 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.578118912 |
|
|
Jul 27 08:15:41 PM PDT 24 |
Jul 27 08:24:44 PM PDT 24 |
9535672113 ps |
| T350 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1312145060 |
|
|
Jul 27 07:53:54 PM PDT 24 |
Jul 27 08:07:01 PM PDT 24 |
5900194360 ps |
| T409 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.128352759 |
|
|
Jul 27 07:58:58 PM PDT 24 |
Jul 27 09:47:24 PM PDT 24 |
24102405230 ps |
| T1077 |
/workspace/coverage/default/0.chip_tap_straps_prod.3416886046 |
|
|
Jul 27 07:52:14 PM PDT 24 |
Jul 27 07:55:04 PM PDT 24 |
3132994911 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2344826749 |
|
|
Jul 27 07:58:09 PM PDT 24 |
Jul 27 08:17:37 PM PDT 24 |
7364291560 ps |
| T1079 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1493535846 |
|
|
Jul 27 08:21:38 PM PDT 24 |
Jul 27 08:49:05 PM PDT 24 |
7907332360 ps |
| T1080 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1869113748 |
|
|
Jul 27 08:11:53 PM PDT 24 |
Jul 27 08:23:25 PM PDT 24 |
5412164836 ps |
| T1081 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2808247080 |
|
|
Jul 27 07:55:43 PM PDT 24 |
Jul 27 09:06:27 PM PDT 24 |
15574287450 ps |
| T1082 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3204368724 |
|
|
Jul 27 08:09:10 PM PDT 24 |
Jul 27 08:11:50 PM PDT 24 |
2809844666 ps |
| T348 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3734805263 |
|
|
Jul 27 07:53:00 PM PDT 24 |
Jul 27 08:05:20 PM PDT 24 |
4595970372 ps |
| T1083 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.325173911 |
|
|
Jul 27 07:54:13 PM PDT 24 |
Jul 27 08:44:56 PM PDT 24 |
26447555996 ps |
| T793 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2943267613 |
|
|
Jul 27 08:26:40 PM PDT 24 |
Jul 27 08:32:05 PM PDT 24 |
3660983650 ps |
| T1084 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4041316334 |
|
|
Jul 27 08:14:33 PM PDT 24 |
Jul 27 08:20:57 PM PDT 24 |
4255849304 ps |
| T1085 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.7621039 |
|
|
Jul 27 08:01:49 PM PDT 24 |
Jul 27 08:15:15 PM PDT 24 |
8098454044 ps |
| T1086 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3216765743 |
|
|
Jul 27 08:22:03 PM PDT 24 |
Jul 27 08:33:00 PM PDT 24 |
8861304694 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1418349659 |
|
|
Jul 27 07:58:52 PM PDT 24 |
Jul 27 08:10:54 PM PDT 24 |
19736852198 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1920516083 |
|
|
Jul 27 07:53:13 PM PDT 24 |
Jul 27 08:32:49 PM PDT 24 |
21472571336 ps |
| T1089 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3575381136 |
|
|
Jul 27 08:24:55 PM PDT 24 |
Jul 27 08:51:53 PM PDT 24 |
8458392902 ps |
| T426 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.3293489935 |
|
|
Jul 27 07:53:03 PM PDT 24 |
Jul 27 09:16:56 PM PDT 24 |
18254379608 ps |
| T832 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3752614319 |
|
|
Jul 27 08:25:44 PM PDT 24 |
Jul 27 08:39:13 PM PDT 24 |
5499029400 ps |
| T766 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2397335387 |
|
|
Jul 27 08:33:46 PM PDT 24 |
Jul 27 08:44:15 PM PDT 24 |
4727654986 ps |
| T128 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3234057114 |
|
|
Jul 27 08:16:35 PM PDT 24 |
Jul 27 08:25:26 PM PDT 24 |
6583597832 ps |
| T410 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2896551583 |
|
|
Jul 27 08:01:54 PM PDT 24 |
Jul 27 09:22:37 PM PDT 24 |
18829407976 ps |
| T1090 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.390810160 |
|
|
Jul 27 07:53:11 PM PDT 24 |
Jul 27 08:01:46 PM PDT 24 |
6005460446 ps |
| T1091 |
/workspace/coverage/default/4.chip_tap_straps_dev.3754448605 |
|
|
Jul 27 08:22:39 PM PDT 24 |
Jul 27 08:28:14 PM PDT 24 |
3933665967 ps |
| T1092 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.921669294 |
|
|
Jul 27 08:05:02 PM PDT 24 |
Jul 27 08:49:00 PM PDT 24 |
27898847840 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1796508440 |
|
|
Jul 27 08:17:55 PM PDT 24 |
Jul 27 08:27:26 PM PDT 24 |
7022086252 ps |
| T1094 |
/workspace/coverage/default/2.chip_sw_aes_idle.680697632 |
|
|
Jul 27 08:11:39 PM PDT 24 |
Jul 27 08:17:11 PM PDT 24 |
2694097368 ps |
| T1095 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.38230675 |
|
|
Jul 27 07:57:42 PM PDT 24 |
Jul 27 08:01:24 PM PDT 24 |
2541216611 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2299119016 |
|
|
Jul 27 08:12:12 PM PDT 24 |
Jul 27 08:30:08 PM PDT 24 |
5776776008 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3039026581 |
|
|
Jul 27 08:11:08 PM PDT 24 |
Jul 27 08:20:16 PM PDT 24 |
4121493074 ps |
| T1098 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.647607652 |
|
|
Jul 27 07:55:51 PM PDT 24 |
Jul 27 08:02:27 PM PDT 24 |
3097326750 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_kmac_idle.3203761876 |
|
|
Jul 27 08:13:41 PM PDT 24 |
Jul 27 08:17:51 PM PDT 24 |
2838013200 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.605010145 |
|
|
Jul 27 08:00:10 PM PDT 24 |
Jul 27 09:10:06 PM PDT 24 |
19398017679 ps |
| T252 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3409047589 |
|
|
Jul 27 08:18:07 PM PDT 24 |
Jul 27 08:23:51 PM PDT 24 |
2919568466 ps |
| T708 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.3415401240 |
|
|
Jul 27 08:01:22 PM PDT 24 |
Jul 27 08:11:57 PM PDT 24 |
3236408190 ps |
| T63 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1605056982 |
|
|
Jul 27 08:10:16 PM PDT 24 |
Jul 27 08:15:48 PM PDT 24 |
3380518412 ps |
| T783 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.2765841014 |
|
|
Jul 27 08:29:12 PM PDT 24 |
Jul 27 08:39:26 PM PDT 24 |
5217909260 ps |
| T1101 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.3281625812 |
|
|
Jul 27 08:10:32 PM PDT 24 |
Jul 27 08:28:33 PM PDT 24 |
6206090734 ps |
| T1102 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2950798441 |
|
|
Jul 27 07:59:12 PM PDT 24 |
Jul 27 08:03:53 PM PDT 24 |
2793768648 ps |
| T261 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1074020937 |
|
|
Jul 27 08:26:31 PM PDT 24 |
Jul 27 08:39:29 PM PDT 24 |
5730964096 ps |
| T787 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208632833 |
|
|
Jul 27 08:22:54 PM PDT 24 |
Jul 27 08:29:17 PM PDT 24 |
4247372340 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2177119099 |
|
|
Jul 27 07:59:17 PM PDT 24 |
Jul 27 08:04:40 PM PDT 24 |
3556293428 ps |
| T1104 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2001299838 |
|
|
Jul 27 08:18:25 PM PDT 24 |
Jul 27 08:23:14 PM PDT 24 |
4352971060 ps |
| T814 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.698719958 |
|
|
Jul 27 08:23:24 PM PDT 24 |
Jul 27 08:30:37 PM PDT 24 |
3798906666 ps |
| T1105 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3143374839 |
|
|
Jul 27 08:28:44 PM PDT 24 |
Jul 27 08:38:44 PM PDT 24 |
5954199266 ps |
| T1106 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4089521361 |
|
|
Jul 27 08:06:16 PM PDT 24 |
Jul 27 08:14:45 PM PDT 24 |
5915782774 ps |
| T1107 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.108261042 |
|
|
Jul 27 08:15:13 PM PDT 24 |
Jul 27 08:22:28 PM PDT 24 |
3436365306 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3793052398 |
|
|
Jul 27 08:01:16 PM PDT 24 |
Jul 27 08:04:58 PM PDT 24 |
2902748249 ps |
| T1108 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3727078945 |
|
|
Jul 27 08:21:21 PM PDT 24 |
Jul 27 09:15:15 PM PDT 24 |
11757316030 ps |
| T370 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3799380375 |
|
|
Jul 27 08:28:36 PM PDT 24 |
Jul 27 08:38:16 PM PDT 24 |
4607508682 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4065454458 |
|
|
Jul 27 08:05:23 PM PDT 24 |
Jul 27 08:12:33 PM PDT 24 |
5262564312 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1947307873 |
|
|
Jul 27 08:12:26 PM PDT 24 |
Jul 27 08:54:45 PM PDT 24 |
11231775192 ps |
| T1110 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2210786321 |
|
|
Jul 27 08:08:35 PM PDT 24 |
Jul 27 08:20:08 PM PDT 24 |
4274177880 ps |
| T1111 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.300972893 |
|
|
Jul 27 07:56:36 PM PDT 24 |
Jul 27 08:07:03 PM PDT 24 |
4452056850 ps |
| T836 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.800712355 |
|
|
Jul 27 08:26:39 PM PDT 24 |
Jul 27 08:32:51 PM PDT 24 |
3251036088 ps |
| T1112 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.236260139 |
|
|
Jul 27 07:59:08 PM PDT 24 |
Jul 27 08:32:03 PM PDT 24 |
24078792730 ps |
| T849 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2633612530 |
|
|
Jul 27 08:32:08 PM PDT 24 |
Jul 27 08:43:09 PM PDT 24 |
4893949620 ps |
| T1113 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3013464679 |
|
|
Jul 27 08:20:35 PM PDT 24 |
Jul 27 09:22:12 PM PDT 24 |
15407509280 ps |
| T91 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4052014556 |
|
|
Jul 27 07:55:31 PM PDT 24 |
Jul 27 11:35:38 PM PDT 24 |
255957460752 ps |
| T784 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3139493282 |
|
|
Jul 27 08:18:53 PM PDT 24 |
Jul 27 08:28:34 PM PDT 24 |
5320790680 ps |
| T1114 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.617288915 |
|
|
Jul 27 08:02:26 PM PDT 24 |
Jul 27 08:53:49 PM PDT 24 |
11091484903 ps |
| T1115 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2289886656 |
|
|
Jul 27 08:15:22 PM PDT 24 |
Jul 27 09:19:22 PM PDT 24 |
24504116197 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_power_virus.1066714236 |
|
|
Jul 27 07:58:03 PM PDT 24 |
Jul 27 08:28:30 PM PDT 24 |
6158974506 ps |
| T1116 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2955597489 |
|
|
Jul 27 08:16:57 PM PDT 24 |
Jul 27 08:36:14 PM PDT 24 |
5835216018 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.889891023 |
|
|
Jul 27 07:55:52 PM PDT 24 |
Jul 27 08:30:32 PM PDT 24 |
13274254930 ps |
| T385 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1788563877 |
|
|
Jul 27 07:57:20 PM PDT 24 |
Jul 27 08:09:33 PM PDT 24 |
5557618271 ps |
| T1117 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.4140257248 |
|
|
Jul 27 07:59:01 PM PDT 24 |
Jul 27 09:07:33 PM PDT 24 |
15178036882 ps |
| T1118 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.112144836 |
|
|
Jul 27 08:11:26 PM PDT 24 |
Jul 27 09:00:32 PM PDT 24 |
24198663530 ps |
| T238 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3795698302 |
|
|
Jul 27 07:52:20 PM PDT 24 |
Jul 27 09:33:06 PM PDT 24 |
47891857140 ps |
| T345 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.110331953 |
|
|
Jul 27 07:57:30 PM PDT 24 |
Jul 27 08:21:40 PM PDT 24 |
6497807760 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2936853043 |
|
|
Jul 27 07:51:30 PM PDT 24 |
Jul 27 07:59:54 PM PDT 24 |
6083240704 ps |
| T1120 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4000149264 |
|
|
Jul 27 08:10:45 PM PDT 24 |
Jul 27 08:15:06 PM PDT 24 |
2803294468 ps |
| T1121 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3136154503 |
|
|
Jul 27 08:10:12 PM PDT 24 |
Jul 28 12:05:11 AM PDT 24 |
79148406399 ps |
| T61 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1297547776 |
|
|
Jul 27 08:14:54 PM PDT 24 |
Jul 27 08:36:46 PM PDT 24 |
23542780202 ps |
| T1122 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1072227344 |
|
|
Jul 27 08:24:35 PM PDT 24 |
Jul 27 08:34:48 PM PDT 24 |
3172142513 ps |
| T81 |
/workspace/coverage/default/1.chip_tap_straps_dev.1489792075 |
|
|
Jul 27 08:06:35 PM PDT 24 |
Jul 27 08:31:41 PM PDT 24 |
13820417966 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2916526552 |
|
|
Jul 27 08:10:29 PM PDT 24 |
Jul 27 08:22:14 PM PDT 24 |
4694136168 ps |
| T1123 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1476973884 |
|
|
Jul 27 07:56:52 PM PDT 24 |
Jul 27 09:09:20 PM PDT 24 |
15080934296 ps |
| T796 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489578711 |
|
|
Jul 27 08:25:24 PM PDT 24 |
Jul 27 08:31:05 PM PDT 24 |
3425641530 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3197533733 |
|
|
Jul 27 07:53:07 PM PDT 24 |
Jul 27 08:00:49 PM PDT 24 |
3457690936 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3103633948 |
|
|
Jul 27 08:08:33 PM PDT 24 |
Jul 27 08:13:13 PM PDT 24 |
3238925526 ps |
| T1125 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1545132447 |
|
|
Jul 27 08:18:27 PM PDT 24 |
Jul 27 08:23:18 PM PDT 24 |
2791978720 ps |
| T775 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1244842118 |
|
|
Jul 27 08:24:25 PM PDT 24 |
Jul 27 08:36:32 PM PDT 24 |
4616819048 ps |
| T1126 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3158670468 |
|
|
Jul 27 07:58:28 PM PDT 24 |
Jul 27 08:36:40 PM PDT 24 |
10682786612 ps |
| T842 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.173934336 |
|
|
Jul 27 08:25:24 PM PDT 24 |
Jul 27 08:33:48 PM PDT 24 |
4003512208 ps |
| T726 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3991588991 |
|
|
Jul 27 08:11:07 PM PDT 24 |
Jul 27 08:14:08 PM PDT 24 |
3608191879 ps |
| T1127 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3657750418 |
|
|
Jul 27 08:10:43 PM PDT 24 |
Jul 27 09:31:18 PM PDT 24 |
14861771224 ps |
| T1128 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2170120867 |
|
|
Jul 27 07:53:37 PM PDT 24 |
Jul 27 08:07:35 PM PDT 24 |
6145988166 ps |
| T833 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2705729541 |
|
|
Jul 27 08:25:29 PM PDT 24 |
Jul 27 08:34:13 PM PDT 24 |
3936630824 ps |
| T1129 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1320597920 |
|
|
Jul 27 08:11:47 PM PDT 24 |
Jul 27 08:16:04 PM PDT 24 |
3366585329 ps |
| T1130 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.3765505915 |
|
|
Jul 27 07:57:34 PM PDT 24 |
Jul 27 08:02:58 PM PDT 24 |
2734557850 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2036522937 |
|
|
Jul 27 08:11:02 PM PDT 24 |
Jul 27 08:21:43 PM PDT 24 |
6687693288 ps |
| T1132 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2680752855 |
|
|
Jul 27 07:51:46 PM PDT 24 |
Jul 27 08:05:06 PM PDT 24 |
5045645896 ps |
| T1133 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.331130575 |
|
|
Jul 27 08:05:56 PM PDT 24 |
Jul 27 08:16:01 PM PDT 24 |
6873942696 ps |
| T1134 |
/workspace/coverage/default/0.chip_sw_example_rom.3770157373 |
|
|
Jul 27 07:54:13 PM PDT 24 |
Jul 27 07:56:52 PM PDT 24 |
2308077902 ps |
| T351 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1506769989 |
|
|
Jul 27 08:14:39 PM PDT 24 |
Jul 27 08:35:41 PM PDT 24 |
6273126806 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2386368639 |
|
|
Jul 27 07:56:14 PM PDT 24 |
Jul 27 08:08:20 PM PDT 24 |
4149377757 ps |
| T1135 |
/workspace/coverage/default/2.chip_sw_aes_enc.3765922199 |
|
|
Jul 27 08:12:33 PM PDT 24 |
Jul 27 08:17:17 PM PDT 24 |
3619567348 ps |
| T108 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3746277487 |
|
|
Jul 27 08:15:22 PM PDT 24 |
Jul 27 08:33:36 PM PDT 24 |
20257016580 ps |
| T1136 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.169909530 |
|
|
Jul 27 08:08:46 PM PDT 24 |
Jul 27 08:15:58 PM PDT 24 |
3147946168 ps |
| T1137 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1849052216 |
|
|
Jul 27 08:00:33 PM PDT 24 |
Jul 27 08:16:43 PM PDT 24 |
5966828140 ps |
| T262 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1658058801 |
|
|
Jul 27 08:25:45 PM PDT 24 |
Jul 27 08:34:45 PM PDT 24 |
6207706282 ps |
| T1138 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.469332192 |
|
|
Jul 27 08:14:42 PM PDT 24 |
Jul 27 08:20:24 PM PDT 24 |
3400734611 ps |
| T1139 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.835016092 |
|
|
Jul 27 07:59:04 PM PDT 24 |
Jul 27 08:23:51 PM PDT 24 |
11537185600 ps |
| T292 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2217015140 |
|
|
Jul 27 08:19:09 PM PDT 24 |
Jul 27 08:29:49 PM PDT 24 |
5896343370 ps |
| T1140 |
/workspace/coverage/default/2.rom_keymgr_functest.4123756843 |
|
|
Jul 27 08:17:06 PM PDT 24 |
Jul 27 08:25:04 PM PDT 24 |
4518719580 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1897608547 |
|
|
Jul 27 08:14:31 PM PDT 24 |
Jul 27 09:22:08 PM PDT 24 |
14938910312 ps |
| T1141 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.688460412 |
|
|
Jul 27 08:12:29 PM PDT 24 |
Jul 27 08:42:16 PM PDT 24 |
7491867760 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2029402060 |
|
|
Jul 27 08:07:11 PM PDT 24 |
Jul 27 08:16:45 PM PDT 24 |
5587825610 ps |
| T815 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2580754117 |
|
|
Jul 27 08:23:22 PM PDT 24 |
Jul 27 08:34:30 PM PDT 24 |
5215098940 ps |
| T1142 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1587444952 |
|
|
Jul 27 07:54:03 PM PDT 24 |
Jul 27 08:06:05 PM PDT 24 |
8530756712 ps |
| T802 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2464770891 |
|
|
Jul 27 08:23:24 PM PDT 24 |
Jul 27 08:30:17 PM PDT 24 |
3103708468 ps |
| T844 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2625414694 |
|
|
Jul 27 08:21:35 PM PDT 24 |
Jul 27 08:28:31 PM PDT 24 |
3515629392 ps |
| T857 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.585382326 |
|
|
Jul 27 08:29:27 PM PDT 24 |
Jul 27 08:38:44 PM PDT 24 |
5758541720 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.84218960 |
|
|
Jul 27 07:51:33 PM PDT 24 |
Jul 27 08:01:34 PM PDT 24 |
4018660300 ps |
| T727 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1655887270 |
|
|
Jul 27 08:09:40 PM PDT 24 |
Jul 27 08:11:29 PM PDT 24 |
2250360820 ps |
| T728 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3115648032 |
|
|
Jul 27 07:57:47 PM PDT 24 |
Jul 27 07:59:44 PM PDT 24 |
2248993732 ps |
| T1144 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1362342289 |
|
|
Jul 27 08:00:35 PM PDT 24 |
Jul 27 08:10:12 PM PDT 24 |
7743463728 ps |
| T1145 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.452815136 |
|
|
Jul 27 08:22:37 PM PDT 24 |
Jul 27 08:53:23 PM PDT 24 |
7981760668 ps |
| T831 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.4178594505 |
|
|
Jul 27 08:21:32 PM PDT 24 |
Jul 27 08:33:12 PM PDT 24 |
6018651052 ps |
| T1146 |
/workspace/coverage/default/2.chip_tap_straps_prod.2596300882 |
|
|
Jul 27 08:14:52 PM PDT 24 |
Jul 27 08:51:07 PM PDT 24 |
18113378667 ps |
| T723 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2938856826 |
|
|
Jul 27 08:15:01 PM PDT 24 |
Jul 27 08:26:10 PM PDT 24 |
5743147769 ps |
| T1147 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1183224063 |
|
|
Jul 27 08:28:46 PM PDT 24 |
Jul 27 08:37:54 PM PDT 24 |
4069648984 ps |
| T391 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3485708318 |
|
|
Jul 27 08:29:07 PM PDT 24 |
Jul 27 08:36:19 PM PDT 24 |
4045842400 ps |
| T789 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2675214580 |
|
|
Jul 27 08:26:10 PM PDT 24 |
Jul 27 08:34:30 PM PDT 24 |
3883787188 ps |
| T1148 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3306577575 |
|
|
Jul 27 08:26:10 PM PDT 24 |
Jul 27 09:28:14 PM PDT 24 |
17242820076 ps |
| T779 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1400045856 |
|
|
Jul 27 08:25:50 PM PDT 24 |
Jul 27 08:35:48 PM PDT 24 |
5159990000 ps |
| T760 |
/workspace/coverage/default/0.rom_raw_unlock.2231105905 |
|
|
Jul 27 07:54:08 PM PDT 24 |
Jul 27 07:57:52 PM PDT 24 |
5982867073 ps |
| T1149 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.730122646 |
|
|
Jul 27 07:54:54 PM PDT 24 |
Jul 27 08:00:56 PM PDT 24 |
5011213170 ps |
| T1150 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1289627755 |
|
|
Jul 27 08:11:24 PM PDT 24 |
Jul 27 08:19:06 PM PDT 24 |
7105148160 ps |
| T1151 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2511403486 |
|
|
Jul 27 07:56:44 PM PDT 24 |
Jul 27 08:01:17 PM PDT 24 |
3067833432 ps |
| T1152 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3389958162 |
|
|
Jul 27 08:19:37 PM PDT 24 |
Jul 27 08:27:42 PM PDT 24 |
4628169769 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3906968217 |
|
|
Jul 27 07:52:43 PM PDT 24 |
Jul 27 08:15:07 PM PDT 24 |
8281385912 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4147331701 |
|
|
Jul 27 07:54:42 PM PDT 24 |
Jul 27 08:20:10 PM PDT 24 |
11708692473 ps |
| T712 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4247071407 |
|
|
Jul 27 08:08:22 PM PDT 24 |
Jul 28 03:25:23 AM PDT 24 |
194594143208 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749822168 |
|
|
Jul 27 07:55:19 PM PDT 24 |
Jul 27 08:03:41 PM PDT 24 |
3476358924 ps |
| T62 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2334207293 |
|
|
Jul 27 08:07:07 PM PDT 24 |
Jul 27 08:33:17 PM PDT 24 |
23966555868 ps |
| T1156 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1594364746 |
|
|
Jul 27 08:10:28 PM PDT 24 |
Jul 27 10:10:27 PM PDT 24 |
23596307729 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2237306667 |
|
|
Jul 27 07:53:02 PM PDT 24 |
Jul 27 08:04:11 PM PDT 24 |
6379500569 ps |
| T856 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890938157 |
|
|
Jul 27 08:24:19 PM PDT 24 |
Jul 27 08:32:12 PM PDT 24 |
3500824134 ps |
| T826 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066733362 |
|
|
Jul 27 08:23:58 PM PDT 24 |
Jul 27 08:30:09 PM PDT 24 |
3245672142 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2983466672 |
|
|
Jul 27 08:14:40 PM PDT 24 |
Jul 27 08:23:05 PM PDT 24 |
5278459417 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2785285732 |
|
|
Jul 27 07:52:52 PM PDT 24 |
Jul 27 08:05:34 PM PDT 24 |
10309981332 ps |
| T790 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.889164347 |
|
|
Jul 27 08:27:18 PM PDT 24 |
Jul 27 08:38:31 PM PDT 24 |
5664446086 ps |
| T372 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1353587136 |
|
|
Jul 27 07:55:17 PM PDT 24 |
Jul 27 07:58:28 PM PDT 24 |
2486704738 ps |
| T1159 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3098339212 |
|
|
Jul 27 08:12:48 PM PDT 24 |
Jul 27 08:22:12 PM PDT 24 |
4834985848 ps |
| T1160 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1339357605 |
|
|
Jul 27 07:59:01 PM PDT 24 |
Jul 27 09:08:20 PM PDT 24 |
14913426552 ps |
| T803 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2112262491 |
|
|
Jul 27 08:24:47 PM PDT 24 |
Jul 27 08:30:42 PM PDT 24 |
3520846688 ps |
| T1161 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1996750182 |
|
|
Jul 27 08:12:29 PM PDT 24 |
Jul 27 08:28:36 PM PDT 24 |
5723408350 ps |
| T1162 |
/workspace/coverage/default/0.rom_e2e_self_hash.1737179698 |
|
|
Jul 27 08:02:34 PM PDT 24 |
Jul 27 09:42:29 PM PDT 24 |
26040171306 ps |
| T1163 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.775486969 |
|
|
Jul 27 08:29:51 PM PDT 24 |
Jul 27 08:41:54 PM PDT 24 |
5310619176 ps |
| T1164 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.1635046640 |
|
|
Jul 27 07:52:24 PM PDT 24 |
Jul 27 07:57:51 PM PDT 24 |
2884360794 ps |
| T133 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1268424963 |
|
|
Jul 27 08:24:32 PM PDT 24 |
Jul 27 08:35:01 PM PDT 24 |
6320786512 ps |
| T1165 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.4050874927 |
|
|
Jul 27 07:58:06 PM PDT 24 |
Jul 27 08:03:11 PM PDT 24 |
2935090502 ps |
| T781 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1942120073 |
|
|
Jul 27 08:15:26 PM PDT 24 |
Jul 27 08:31:47 PM PDT 24 |
8606929248 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.4136866672 |
|
|
Jul 27 08:18:03 PM PDT 24 |
Jul 27 08:22:22 PM PDT 24 |
2370994856 ps |
| T1167 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1206813947 |
|
|
Jul 27 08:22:20 PM PDT 24 |
Jul 27 08:33:09 PM PDT 24 |
4036034112 ps |
| T1168 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.3788183632 |
|
|
Jul 27 08:11:43 PM PDT 24 |
Jul 27 08:16:24 PM PDT 24 |
2541118560 ps |
| T1169 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3100528874 |
|
|
Jul 27 08:12:04 PM PDT 24 |
Jul 27 08:18:40 PM PDT 24 |
6489023260 ps |
| T1170 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.121536833 |
|
|
Jul 27 08:20:14 PM PDT 24 |
Jul 27 08:35:46 PM PDT 24 |
12692424808 ps |
| T109 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2034766986 |
|
|
Jul 27 08:07:33 PM PDT 24 |
Jul 27 08:12:46 PM PDT 24 |
7782085986 ps |
| T448 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2114117455 |
|
|
Jul 27 08:06:52 PM PDT 24 |
Jul 27 08:14:22 PM PDT 24 |
4503169378 ps |
| T1171 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.3158687128 |
|
|
Jul 27 07:59:17 PM PDT 24 |
Jul 27 08:05:30 PM PDT 24 |
3572379681 ps |
| T1172 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2744550931 |
|
|
Jul 27 08:00:49 PM PDT 24 |
Jul 27 08:09:02 PM PDT 24 |
4986807616 ps |
| T1173 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.145711599 |
|
|
Jul 27 08:27:01 PM PDT 24 |
Jul 27 08:33:25 PM PDT 24 |
3243078790 ps |
| T129 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3065735923 |
|
|
Jul 27 08:16:22 PM PDT 24 |
Jul 27 08:22:52 PM PDT 24 |
5403812614 ps |
| T134 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4252932154 |
|
|
Jul 27 07:58:39 PM PDT 24 |
Jul 27 08:12:22 PM PDT 24 |
6864534560 ps |
| T97 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2796006103 |
|
|
Jul 27 08:29:39 PM PDT 24 |
Jul 27 08:35:49 PM PDT 24 |
3623047120 ps |
| T100 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1154513993 |
|
|
Jul 27 07:51:57 PM PDT 24 |
Jul 27 08:00:25 PM PDT 24 |
4502130303 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.754233730 |
|
|
Jul 27 08:09:03 PM PDT 24 |
Jul 27 08:15:11 PM PDT 24 |
3594229088 ps |
| T101 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2152129212 |
|
|
Jul 27 08:10:55 PM PDT 24 |
Jul 27 09:04:36 PM PDT 24 |
20009755268 ps |
| T102 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1057451156 |
|
|
Jul 27 08:29:47 PM PDT 24 |
Jul 27 08:36:46 PM PDT 24 |
3411782830 ps |
| T103 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2995518494 |
|
|
Jul 27 08:22:19 PM PDT 24 |
Jul 27 08:35:52 PM PDT 24 |
6039271928 ps |
| T104 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1153287781 |
|
|
Jul 27 08:25:05 PM PDT 24 |
Jul 27 08:35:39 PM PDT 24 |
5416551372 ps |
| T105 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1430471589 |
|
|
Jul 27 08:09:38 PM PDT 24 |
Jul 27 08:22:14 PM PDT 24 |
4830791538 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.44529359 |
|
|
Jul 27 08:14:42 PM PDT 24 |
Jul 27 08:40:17 PM PDT 24 |
10472542890 ps |
| T107 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3561786709 |
|
|
Jul 27 07:57:29 PM PDT 24 |
Jul 27 08:13:11 PM PDT 24 |
5163199852 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.511777571 |
|
|
Jul 27 07:56:17 PM PDT 24 |
Jul 27 08:01:44 PM PDT 24 |
2575222145 ps |
| T330 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3207531644 |
|
|
Jul 27 08:30:16 PM PDT 24 |
Jul 27 08:40:52 PM PDT 24 |
4917131688 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.4144545135 |
|
|
Jul 27 07:54:09 PM PDT 24 |
Jul 27 11:18:17 PM PDT 24 |
57983844214 ps |
| T729 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3834387344 |
|
|
Jul 27 07:59:34 PM PDT 24 |
Jul 27 08:01:27 PM PDT 24 |
2361544204 ps |
| T1175 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1937045006 |
|
|
Jul 27 08:00:06 PM PDT 24 |
Jul 27 08:08:09 PM PDT 24 |
5795540118 ps |
| T158 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1948125453 |
|
|
Jul 27 08:00:09 PM PDT 24 |
Jul 27 08:34:37 PM PDT 24 |
14272749768 ps |
| T399 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4117572777 |
|
|
Jul 27 07:53:24 PM PDT 24 |
Jul 27 07:59:25 PM PDT 24 |
5202400104 ps |
| T811 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285811724 |
|
|
Jul 27 08:27:49 PM PDT 24 |
Jul 27 08:34:03 PM PDT 24 |
3809274840 ps |
| T550 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.93946370 |
|
|
Jul 27 08:12:26 PM PDT 24 |
Jul 27 08:25:07 PM PDT 24 |
4670704160 ps |
| T1176 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2294583590 |
|
|
Jul 27 08:16:36 PM PDT 24 |
Jul 27 08:21:09 PM PDT 24 |
2336290532 ps |
| T786 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.335774523 |
|
|
Jul 27 08:23:28 PM PDT 24 |
Jul 27 08:35:53 PM PDT 24 |
5569165500 ps |
| T791 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2369805676 |
|
|
Jul 27 08:25:53 PM PDT 24 |
Jul 27 08:34:03 PM PDT 24 |
3202868070 ps |
| T1177 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2146090778 |
|
|
Jul 27 07:57:01 PM PDT 24 |
Jul 27 08:30:46 PM PDT 24 |
21912185217 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3022626090 |
|
|
Jul 27 07:53:34 PM PDT 24 |
Jul 27 08:17:41 PM PDT 24 |
8027611856 ps |
| T730 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2705085159 |
|
|
Jul 27 07:53:27 PM PDT 24 |
Jul 27 07:55:48 PM PDT 24 |
2786866140 ps |
| T375 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3544532835 |
|
|
Jul 27 07:54:57 PM PDT 24 |
Jul 27 08:07:27 PM PDT 24 |
5536223696 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1708449454 |
|
|
Jul 27 08:05:19 PM PDT 24 |
Jul 27 08:12:57 PM PDT 24 |
5213421240 ps |
| T861 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4071020253 |
|
|
Jul 27 08:27:13 PM PDT 24 |
Jul 27 08:33:06 PM PDT 24 |
4557983782 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1254716221 |
|
|
Jul 27 08:10:04 PM PDT 24 |
Jul 27 08:20:15 PM PDT 24 |
3690922733 ps |
| T1179 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.984572115 |
|
|
Jul 27 07:56:05 PM PDT 24 |
Jul 27 08:19:10 PM PDT 24 |
9252248920 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3652123399 |
|
|
Jul 27 08:03:32 PM PDT 24 |
Jul 27 08:07:57 PM PDT 24 |
2564884024 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.570845559 |
|
|
Jul 27 07:57:09 PM PDT 24 |
Jul 27 08:03:15 PM PDT 24 |
2930897360 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.477129815 |
|
|
Jul 27 07:55:16 PM PDT 24 |
Jul 27 07:58:49 PM PDT 24 |
2356061573 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1299769286 |
|
|
Jul 27 07:57:48 PM PDT 24 |
Jul 27 08:10:02 PM PDT 24 |
4638617659 ps |
| T820 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2307080457 |
|
|
Jul 27 08:24:53 PM PDT 24 |
Jul 27 08:31:24 PM PDT 24 |
3952475512 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2703836877 |
|
|
Jul 27 07:57:19 PM PDT 24 |
Jul 27 09:09:16 PM PDT 24 |
25502117430 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2457053981 |
|
|
Jul 27 07:57:10 PM PDT 24 |
Jul 27 08:02:39 PM PDT 24 |
2596295248 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1350581171 |
|
|
Jul 27 08:09:51 PM PDT 24 |
Jul 27 08:24:04 PM PDT 24 |
3923068928 ps |
| T1187 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.593494773 |
|
|
Jul 27 08:19:10 PM PDT 24 |
Jul 27 08:28:50 PM PDT 24 |
3645362220 ps |
| T365 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1354837466 |
|
|
Jul 27 08:06:35 PM PDT 24 |
Jul 27 08:20:10 PM PDT 24 |
5267541615 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.720971132 |
|
|
Jul 27 07:58:29 PM PDT 24 |
Jul 27 08:16:29 PM PDT 24 |
6787573439 ps |
| T1189 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2223712574 |
|
|
Jul 27 07:58:10 PM PDT 24 |
Jul 27 08:50:28 PM PDT 24 |
11883393544 ps |
| T52 |
/workspace/coverage/default/2.chip_jtag_csr_rw.3166783971 |
|
|
Jul 27 08:07:03 PM PDT 24 |
Jul 27 08:30:42 PM PDT 24 |
13357646504 ps |
| T66 |
/workspace/coverage/default/0.chip_sw_alert_test.1827115508 |
|
|
Jul 27 07:54:33 PM PDT 24 |
Jul 27 07:58:54 PM PDT 24 |
3005233496 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2476984153 |
|
|
Jul 27 08:13:36 PM PDT 24 |
Jul 27 08:33:28 PM PDT 24 |
7561810978 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2343637770 |
|
|
Jul 27 08:08:08 PM PDT 24 |
Jul 27 08:28:16 PM PDT 24 |
7069233662 ps |
| T1192 |
/workspace/coverage/default/1.chip_sival_flash_info_access.1158310453 |
|
|
Jul 27 07:55:29 PM PDT 24 |
Jul 27 08:00:15 PM PDT 24 |
3285791492 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.655834529 |
|
|
Jul 27 07:55:47 PM PDT 24 |
Jul 27 08:00:10 PM PDT 24 |
3491835500 ps |
| T835 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3302831828 |
|
|
Jul 27 08:23:30 PM PDT 24 |
Jul 27 08:29:25 PM PDT 24 |
3435788180 ps |
| T1194 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.936280369 |
|
|
Jul 27 08:02:57 PM PDT 24 |
Jul 27 08:16:26 PM PDT 24 |
5983055056 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1108193580 |
|
|
Jul 27 07:56:39 PM PDT 24 |
Jul 27 07:59:56 PM PDT 24 |
2914727600 ps |