| T1196 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1201617608 |
|
|
Jul 27 07:57:51 PM PDT 24 |
Jul 27 08:19:57 PM PDT 24 |
11808662892 ps |
| T1197 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3672710819 |
|
|
Jul 27 08:10:33 PM PDT 24 |
Jul 27 08:34:36 PM PDT 24 |
5972897450 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1886090547 |
|
|
Jul 27 08:16:25 PM PDT 24 |
Jul 27 08:20:57 PM PDT 24 |
3245812108 ps |
| T1199 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2106282705 |
|
|
Jul 27 08:19:46 PM PDT 24 |
Jul 27 09:21:32 PM PDT 24 |
14513023592 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2218215894 |
|
|
Jul 27 08:08:49 PM PDT 24 |
Jul 27 08:15:44 PM PDT 24 |
3172794824 ps |
| T812 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1527653964 |
|
|
Jul 27 07:54:21 PM PDT 24 |
Jul 27 08:05:04 PM PDT 24 |
6279519600 ps |
| T1201 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3546701670 |
|
|
Jul 27 08:10:33 PM PDT 24 |
Jul 27 10:13:54 PM PDT 24 |
23803301160 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2261265879 |
|
|
Jul 27 08:07:04 PM PDT 24 |
Jul 27 08:11:37 PM PDT 24 |
2276919544 ps |
| T157 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2554591243 |
|
|
Jul 27 08:11:58 PM PDT 24 |
Jul 27 08:17:25 PM PDT 24 |
3501697462 ps |
| T420 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2655504082 |
|
|
Jul 27 07:55:54 PM PDT 24 |
Jul 27 08:01:02 PM PDT 24 |
2831888118 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3482728528 |
|
|
Jul 27 08:10:30 PM PDT 24 |
Jul 27 08:14:28 PM PDT 24 |
3058631764 ps |
| T58 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3571784179 |
|
|
Jul 27 07:55:05 PM PDT 24 |
Jul 27 07:59:28 PM PDT 24 |
3593440080 ps |
| T278 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.451283128 |
|
|
Jul 27 08:23:59 PM PDT 24 |
Jul 27 08:34:50 PM PDT 24 |
5055727336 ps |
| T422 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.963745712 |
|
|
Jul 27 08:21:13 PM PDT 24 |
Jul 27 08:30:29 PM PDT 24 |
4659491924 ps |
| T423 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3641177728 |
|
|
Jul 27 08:26:24 PM PDT 24 |
Jul 27 08:36:49 PM PDT 24 |
6688886660 ps |
| T424 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2603910382 |
|
|
Jul 27 08:19:25 PM PDT 24 |
Jul 27 08:30:09 PM PDT 24 |
4064956812 ps |
| T30 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3311784976 |
|
|
Jul 27 07:54:41 PM PDT 24 |
Jul 27 07:59:01 PM PDT 24 |
3228817036 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1155933004 |
|
|
Jul 27 07:54:01 PM PDT 24 |
Jul 27 07:58:48 PM PDT 24 |
2985764048 ps |
| T1203 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2381671532 |
|
|
Jul 27 07:59:13 PM PDT 24 |
Jul 27 09:07:40 PM PDT 24 |
14979346760 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3835496036 |
|
|
Jul 27 08:03:37 PM PDT 24 |
Jul 27 08:31:03 PM PDT 24 |
8079928039 ps |
| T279 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2510184058 |
|
|
Jul 27 08:18:28 PM PDT 24 |
Jul 27 08:32:51 PM PDT 24 |
6260280400 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1820208363 |
|
|
Jul 27 07:53:46 PM PDT 24 |
Jul 27 09:01:25 PM PDT 24 |
18645836887 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2712180742 |
|
|
Jul 27 07:52:49 PM PDT 24 |
Jul 27 07:58:57 PM PDT 24 |
3398376798 ps |
| T376 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3932664197 |
|
|
Jul 27 07:54:18 PM PDT 24 |
Jul 27 07:59:28 PM PDT 24 |
3477559080 ps |
| T1206 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.856409221 |
|
|
Jul 27 08:19:13 PM PDT 24 |
Jul 27 09:53:12 PM PDT 24 |
20383867680 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1602203728 |
|
|
Jul 27 08:14:31 PM PDT 24 |
Jul 27 08:23:12 PM PDT 24 |
4010099880 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4273166003 |
|
|
Jul 27 08:11:59 PM PDT 24 |
Jul 27 08:15:55 PM PDT 24 |
2863734492 ps |
| T841 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1681310333 |
|
|
Jul 27 08:24:18 PM PDT 24 |
Jul 27 08:33:47 PM PDT 24 |
5416023420 ps |
| T1208 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.530718154 |
|
|
Jul 27 07:57:07 PM PDT 24 |
Jul 27 09:00:45 PM PDT 24 |
28754957580 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.3179075461 |
|
|
Jul 27 07:54:47 PM PDT 24 |
Jul 27 07:59:57 PM PDT 24 |
2414364700 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2451877158 |
|
|
Jul 27 08:09:57 PM PDT 24 |
Jul 27 08:15:28 PM PDT 24 |
3168300040 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1287084221 |
|
|
Jul 27 07:56:42 PM PDT 24 |
Jul 27 08:01:18 PM PDT 24 |
3935730551 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2259224566 |
|
|
Jul 27 08:02:47 PM PDT 24 |
Jul 27 08:07:52 PM PDT 24 |
3121939110 ps |
| T1212 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3903791807 |
|
|
Jul 27 07:52:55 PM PDT 24 |
Jul 27 07:57:28 PM PDT 24 |
3122344860 ps |
| T59 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2319119214 |
|
|
Jul 27 08:10:02 PM PDT 24 |
Jul 27 08:15:09 PM PDT 24 |
3341542300 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4203846224 |
|
|
Jul 27 07:54:44 PM PDT 24 |
Jul 27 08:02:21 PM PDT 24 |
3989561910 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2869562016 |
|
|
Jul 27 07:58:31 PM PDT 24 |
Jul 27 08:05:08 PM PDT 24 |
3526840152 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3052815909 |
|
|
Jul 27 07:58:55 PM PDT 24 |
Jul 27 08:03:55 PM PDT 24 |
3367392230 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1433157194 |
|
|
Jul 27 07:54:42 PM PDT 24 |
Jul 27 07:56:23 PM PDT 24 |
2319296045 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3324700847 |
|
|
Jul 27 08:08:46 PM PDT 24 |
Jul 27 08:15:27 PM PDT 24 |
4775243000 ps |
| T1218 |
/workspace/coverage/default/2.chip_sw_example_flash.2155470792 |
|
|
Jul 27 08:10:37 PM PDT 24 |
Jul 27 08:14:50 PM PDT 24 |
2571972450 ps |
| T1219 |
/workspace/coverage/default/4.chip_tap_straps_prod.2186375656 |
|
|
Jul 27 08:19:59 PM PDT 24 |
Jul 27 08:46:59 PM PDT 24 |
12932429907 ps |
| T1220 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.1058665859 |
|
|
Jul 27 08:22:15 PM PDT 24 |
Jul 27 08:33:53 PM PDT 24 |
4884175412 ps |
| T33 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3251387489 |
|
|
Jul 27 07:52:26 PM PDT 24 |
Jul 27 07:59:03 PM PDT 24 |
4941874896 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.117694284 |
|
|
Jul 27 07:54:03 PM PDT 24 |
Jul 27 08:03:30 PM PDT 24 |
6207363994 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.854032067 |
|
|
Jul 27 07:53:22 PM PDT 24 |
Jul 27 08:01:48 PM PDT 24 |
4782181748 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3713251319 |
|
|
Jul 27 08:11:48 PM PDT 24 |
Jul 27 08:16:25 PM PDT 24 |
3105419952 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.433805820 |
|
|
Jul 27 07:52:44 PM PDT 24 |
Jul 27 08:22:55 PM PDT 24 |
7888291878 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2800501273 |
|
|
Jul 27 07:58:35 PM PDT 24 |
Jul 27 08:05:02 PM PDT 24 |
3527549224 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2058364108 |
|
|
Jul 27 07:55:57 PM PDT 24 |
Jul 27 08:01:25 PM PDT 24 |
2895725045 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2995212094 |
|
|
Jul 27 08:07:40 PM PDT 24 |
Jul 27 08:12:29 PM PDT 24 |
3490121510 ps |
| T57 |
/workspace/coverage/default/1.chip_jtag_csr_rw.845033165 |
|
|
Jul 27 07:59:02 PM PDT 24 |
Jul 27 08:43:35 PM PDT 24 |
19849011920 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.189183549 |
|
|
Jul 27 07:52:13 PM PDT 24 |
Jul 28 12:17:07 AM PDT 24 |
78362166754 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.699639205 |
|
|
Jul 27 08:14:43 PM PDT 24 |
Jul 27 08:29:29 PM PDT 24 |
4334789034 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.4278713723 |
|
|
Jul 27 08:13:05 PM PDT 24 |
Jul 27 08:17:55 PM PDT 24 |
3328445190 ps |
| T1229 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2466707255 |
|
|
Jul 27 08:17:10 PM PDT 24 |
Jul 27 09:25:18 PM PDT 24 |
14278240500 ps |
| T1230 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.101266911 |
|
|
Jul 27 08:00:18 PM PDT 24 |
Jul 27 08:28:57 PM PDT 24 |
7638374528 ps |
| T709 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.575587968 |
|
|
Jul 27 08:11:58 PM PDT 24 |
Jul 27 08:20:57 PM PDT 24 |
3019674150 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.206078387 |
|
|
Jul 27 07:57:31 PM PDT 24 |
Jul 27 08:07:41 PM PDT 24 |
5318325583 ps |
| T794 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.954200568 |
|
|
Jul 27 08:19:48 PM PDT 24 |
Jul 27 08:31:09 PM PDT 24 |
4509140440 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1602384289 |
|
|
Jul 27 08:05:16 PM PDT 24 |
Jul 27 08:31:49 PM PDT 24 |
6783240840 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2958547333 |
|
|
Jul 27 08:09:49 PM PDT 24 |
Jul 27 08:23:00 PM PDT 24 |
9119038232 ps |
| T1234 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4081068291 |
|
|
Jul 27 07:56:38 PM PDT 24 |
Jul 27 08:05:10 PM PDT 24 |
5282344716 ps |
| T154 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.774414137 |
|
|
Jul 27 08:04:40 PM PDT 24 |
Jul 27 08:15:06 PM PDT 24 |
4212801352 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.995507379 |
|
|
Jul 27 08:15:56 PM PDT 24 |
Jul 27 08:57:21 PM PDT 24 |
22203351353 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.758970247 |
|
|
Jul 27 08:09:05 PM PDT 24 |
Jul 27 08:15:27 PM PDT 24 |
6300524922 ps |
| T806 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161447240 |
|
|
Jul 27 08:23:23 PM PDT 24 |
Jul 27 08:31:27 PM PDT 24 |
4167677072 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2857728173 |
|
|
Jul 27 07:53:14 PM PDT 24 |
Jul 27 07:58:11 PM PDT 24 |
3205754502 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3501781345 |
|
|
Jul 27 07:52:18 PM PDT 24 |
Jul 27 08:00:33 PM PDT 24 |
6336507323 ps |
| T1238 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3589505530 |
|
|
Jul 27 07:59:02 PM PDT 24 |
Jul 27 09:09:55 PM PDT 24 |
14745271512 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2834441203 |
|
|
Jul 27 07:56:01 PM PDT 24 |
Jul 27 08:01:32 PM PDT 24 |
3243642430 ps |
| T1240 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1395473097 |
|
|
Jul 27 08:19:07 PM PDT 24 |
Jul 27 08:25:20 PM PDT 24 |
6053677816 ps |
| T1241 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2826085410 |
|
|
Jul 27 08:21:28 PM PDT 24 |
Jul 27 08:32:37 PM PDT 24 |
7543716884 ps |
| T98 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2699091671 |
|
|
Jul 27 08:26:49 PM PDT 24 |
Jul 27 08:32:49 PM PDT 24 |
4203399864 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.478292661 |
|
|
Jul 27 08:10:49 PM PDT 24 |
Jul 27 10:00:21 PM PDT 24 |
46750242883 ps |
| T1243 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1267073379 |
|
|
Jul 27 08:23:22 PM PDT 24 |
Jul 27 08:38:39 PM PDT 24 |
6298430904 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3879637693 |
|
|
Jul 27 08:02:21 PM PDT 24 |
Jul 27 08:07:01 PM PDT 24 |
2716487001 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.1585796551 |
|
|
Jul 27 08:14:09 PM PDT 24 |
Jul 27 08:22:29 PM PDT 24 |
4625627948 ps |
| T765 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.959535263 |
|
|
Jul 27 08:26:56 PM PDT 24 |
Jul 27 08:37:53 PM PDT 24 |
5870178528 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3715630856 |
|
|
Jul 27 07:56:36 PM PDT 24 |
Jul 27 08:18:10 PM PDT 24 |
15199880826 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1380636478 |
|
|
Jul 27 07:52:01 PM PDT 24 |
Jul 27 08:01:34 PM PDT 24 |
4197855872 ps |
| T1248 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1715523344 |
|
|
Jul 27 08:11:34 PM PDT 24 |
Jul 27 08:23:34 PM PDT 24 |
7986482850 ps |
| T817 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3675058023 |
|
|
Jul 27 08:25:39 PM PDT 24 |
Jul 27 08:38:24 PM PDT 24 |
6309577580 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1342045258 |
|
|
Jul 27 08:10:51 PM PDT 24 |
Jul 27 08:15:34 PM PDT 24 |
3203717990 ps |
| T751 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.457507324 |
|
|
Jul 27 08:02:05 PM PDT 24 |
Jul 27 08:06:45 PM PDT 24 |
2861354252 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1352589458 |
|
|
Jul 27 07:58:33 PM PDT 24 |
Jul 27 08:05:03 PM PDT 24 |
4032932372 ps |
| T807 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.830194478 |
|
|
Jul 27 08:22:57 PM PDT 24 |
Jul 27 08:36:14 PM PDT 24 |
6145862614 ps |
| T1250 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.802659576 |
|
|
Jul 27 08:13:01 PM PDT 24 |
Jul 27 08:32:33 PM PDT 24 |
6098482320 ps |
| T1251 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3710530337 |
|
|
Jul 27 08:22:51 PM PDT 24 |
Jul 27 09:05:29 PM PDT 24 |
12785098680 ps |
| T1252 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2605645190 |
|
|
Jul 27 08:17:07 PM PDT 24 |
Jul 27 08:23:09 PM PDT 24 |
3526863350 ps |
| T1253 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2771682784 |
|
|
Jul 27 08:21:30 PM PDT 24 |
Jul 27 09:22:28 PM PDT 24 |
16491214354 ps |
| T305 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2159070282 |
|
|
Jul 27 08:16:10 PM PDT 24 |
Jul 27 08:20:59 PM PDT 24 |
2909988977 ps |
| T724 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2637534977 |
|
|
Jul 27 08:06:34 PM PDT 24 |
Jul 27 08:15:51 PM PDT 24 |
5514041786 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1008166593 |
|
|
Jul 27 07:56:22 PM PDT 24 |
Jul 27 08:03:03 PM PDT 24 |
3703295294 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1993127843 |
|
|
Jul 27 07:59:45 PM PDT 24 |
Jul 27 08:29:56 PM PDT 24 |
23896588680 ps |
| T830 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021701512 |
|
|
Jul 27 08:29:31 PM PDT 24 |
Jul 27 08:36:23 PM PDT 24 |
4217496040 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.328532274 |
|
|
Jul 27 08:06:24 PM PDT 24 |
Jul 27 08:39:54 PM PDT 24 |
20634416660 ps |
| T1256 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.4271595634 |
|
|
Jul 27 08:20:24 PM PDT 24 |
Jul 27 09:20:23 PM PDT 24 |
15742955929 ps |
| T759 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.523388489 |
|
|
Jul 27 07:56:12 PM PDT 24 |
Jul 27 08:08:39 PM PDT 24 |
4542504616 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2950249126 |
|
|
Jul 27 08:07:51 PM PDT 24 |
Jul 27 09:04:20 PM PDT 24 |
14075042152 ps |
| T1257 |
/workspace/coverage/default/1.chip_tap_straps_prod.985314956 |
|
|
Jul 27 08:06:15 PM PDT 24 |
Jul 27 08:09:06 PM PDT 24 |
2911958623 ps |
| T839 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3640357779 |
|
|
Jul 27 08:26:08 PM PDT 24 |
Jul 27 08:37:13 PM PDT 24 |
5646923024 ps |
| T1258 |
/workspace/coverage/default/0.rom_e2e_static_critical.3106130774 |
|
|
Jul 27 08:01:07 PM PDT 24 |
Jul 27 09:19:51 PM PDT 24 |
17131938796 ps |
| T73 |
/workspace/coverage/default/4.chip_tap_straps_rma.1441576750 |
|
|
Jul 27 08:19:48 PM PDT 24 |
Jul 27 08:31:15 PM PDT 24 |
6932480693 ps |
| T1259 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2851879661 |
|
|
Jul 27 08:12:31 PM PDT 24 |
Jul 27 08:51:02 PM PDT 24 |
11374817504 ps |
| T1260 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1793731954 |
|
|
Jul 27 08:21:39 PM PDT 24 |
Jul 27 08:33:41 PM PDT 24 |
4807133728 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1875583829 |
|
|
Jul 27 07:55:24 PM PDT 24 |
Jul 27 08:25:55 PM PDT 24 |
11741442423 ps |
| T74 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3724430956 |
|
|
Jul 27 08:18:59 PM PDT 24 |
Jul 27 08:24:24 PM PDT 24 |
4681717279 ps |
| T1262 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2387972811 |
|
|
Jul 27 08:23:33 PM PDT 24 |
Jul 27 09:08:44 PM PDT 24 |
13546387432 ps |
| T1263 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3266733076 |
|
|
Jul 27 07:59:54 PM PDT 24 |
Jul 27 08:09:59 PM PDT 24 |
5799226584 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3031175844 |
|
|
Jul 27 08:06:53 PM PDT 24 |
Jul 27 08:36:11 PM PDT 24 |
21646932335 ps |
| T837 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3931538308 |
|
|
Jul 27 08:26:20 PM PDT 24 |
Jul 27 08:33:57 PM PDT 24 |
4395558160 ps |
| T859 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.805911875 |
|
|
Jul 27 08:28:56 PM PDT 24 |
Jul 27 08:39:53 PM PDT 24 |
5686948312 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_example_concurrency.3180288662 |
|
|
Jul 27 08:00:14 PM PDT 24 |
Jul 27 08:04:20 PM PDT 24 |
2509171528 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3280387330 |
|
|
Jul 27 08:08:23 PM PDT 24 |
Jul 27 08:21:47 PM PDT 24 |
4620072152 ps |
| T1267 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.961823160 |
|
|
Jul 27 08:20:41 PM PDT 24 |
Jul 27 08:39:51 PM PDT 24 |
10456890728 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1697843367 |
|
|
Jul 27 07:54:30 PM PDT 24 |
Jul 27 07:59:02 PM PDT 24 |
2806983018 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2418531358 |
|
|
Jul 27 08:14:04 PM PDT 24 |
Jul 27 08:25:20 PM PDT 24 |
7000223808 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1685454827 |
|
|
Jul 27 07:53:11 PM PDT 24 |
Jul 27 07:58:34 PM PDT 24 |
3056142468 ps |
| T1270 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.844805545 |
|
|
Jul 27 08:20:42 PM PDT 24 |
Jul 27 08:29:31 PM PDT 24 |
4773209192 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_flash_init.888059290 |
|
|
Jul 27 07:57:16 PM PDT 24 |
Jul 27 08:35:02 PM PDT 24 |
19493801996 ps |
| T54 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3433407908 |
|
|
Jul 27 07:51:59 PM PDT 24 |
Jul 27 07:58:09 PM PDT 24 |
3530438461 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1290839978 |
|
|
Jul 27 08:06:48 PM PDT 24 |
Jul 27 08:15:03 PM PDT 24 |
5154860676 ps |
| T1273 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4128180344 |
|
|
Jul 27 08:11:16 PM PDT 24 |
Jul 27 08:17:53 PM PDT 24 |
3888167976 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.178925703 |
|
|
Jul 27 07:59:18 PM PDT 24 |
Jul 27 08:05:49 PM PDT 24 |
3335109810 ps |
| T1275 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.412886485 |
|
|
Jul 27 07:58:48 PM PDT 24 |
Jul 27 09:07:59 PM PDT 24 |
14961980712 ps |
| T195 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2917033210 |
|
|
Jul 27 07:55:23 PM PDT 24 |
Jul 27 08:04:49 PM PDT 24 |
3932448400 ps |
| T1276 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3571275148 |
|
|
Jul 27 08:28:22 PM PDT 24 |
Jul 27 08:39:04 PM PDT 24 |
5362431168 ps |
| T1277 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1029421730 |
|
|
Jul 27 08:14:53 PM PDT 24 |
Jul 27 08:22:56 PM PDT 24 |
4395269436 ps |
| T770 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.4235354687 |
|
|
Jul 27 08:21:14 PM PDT 24 |
Jul 27 08:29:11 PM PDT 24 |
4730468848 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1681128236 |
|
|
Jul 27 07:53:23 PM PDT 24 |
Jul 27 10:12:36 PM PDT 24 |
34314496152 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1063447882 |
|
|
Jul 27 07:53:09 PM PDT 24 |
Jul 27 07:58:56 PM PDT 24 |
3693487038 ps |
| T799 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3219118666 |
|
|
Jul 27 08:23:08 PM PDT 24 |
Jul 27 08:29:34 PM PDT 24 |
3520557930 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.600680239 |
|
|
Jul 27 08:00:17 PM PDT 24 |
Jul 27 08:19:40 PM PDT 24 |
5257599306 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2780277443 |
|
|
Jul 27 07:54:55 PM PDT 24 |
Jul 27 07:59:03 PM PDT 24 |
2847868765 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_coremark.699564374 |
|
|
Jul 27 07:54:43 PM PDT 24 |
Jul 28 12:22:09 AM PDT 24 |
72258487070 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.799635102 |
|
|
Jul 27 08:13:49 PM PDT 24 |
Jul 27 08:17:39 PM PDT 24 |
2501635256 ps |
| T1283 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2135647994 |
|
|
Jul 27 08:09:29 PM PDT 24 |
Jul 27 08:11:04 PM PDT 24 |
2453202442 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.835525146 |
|
|
Jul 27 08:15:30 PM PDT 24 |
Jul 27 08:36:59 PM PDT 24 |
8068026294 ps |
| T64 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1896710936 |
|
|
Jul 27 07:53:08 PM PDT 24 |
Jul 27 07:56:38 PM PDT 24 |
3663633180 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3070897858 |
|
|
Jul 27 07:55:27 PM PDT 24 |
Jul 27 08:15:53 PM PDT 24 |
6014659706 ps |
| T1286 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.428917212 |
|
|
Jul 27 08:23:10 PM PDT 24 |
Jul 27 08:29:38 PM PDT 24 |
4008685342 ps |
| T1287 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1621108084 |
|
|
Jul 27 08:10:49 PM PDT 24 |
Jul 27 08:15:49 PM PDT 24 |
2400949192 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1929003140 |
|
|
Jul 27 07:52:18 PM PDT 24 |
Jul 27 08:57:41 PM PDT 24 |
20932982877 ps |
| T818 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1047052795 |
|
|
Jul 27 08:22:44 PM PDT 24 |
Jul 27 08:29:38 PM PDT 24 |
4140596760 ps |
| T808 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775209875 |
|
|
Jul 27 08:28:56 PM PDT 24 |
Jul 27 08:37:33 PM PDT 24 |
3633337832 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2141096141 |
|
|
Jul 27 07:54:31 PM PDT 24 |
Jul 27 08:12:01 PM PDT 24 |
6437876144 ps |
| T1290 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3947345056 |
|
|
Jul 27 08:25:48 PM PDT 24 |
Jul 27 08:38:07 PM PDT 24 |
11235544423 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3508359345 |
|
|
Jul 27 08:02:43 PM PDT 24 |
Jul 27 08:55:13 PM PDT 24 |
33915361296 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.887284226 |
|
|
Jul 27 08:10:26 PM PDT 24 |
Jul 27 11:16:23 PM PDT 24 |
65464782621 ps |
| T838 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.4067623288 |
|
|
Jul 27 08:29:05 PM PDT 24 |
Jul 27 08:40:42 PM PDT 24 |
4296838896 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2142938336 |
|
|
Jul 27 08:08:00 PM PDT 24 |
Jul 27 08:11:32 PM PDT 24 |
3161200838 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1627335529 |
|
|
Jul 27 08:10:36 PM PDT 24 |
Jul 27 08:15:29 PM PDT 24 |
3423947587 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.1659507556 |
|
|
Jul 27 08:10:52 PM PDT 24 |
Jul 27 08:15:03 PM PDT 24 |
3140446750 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1768739110 |
|
|
Jul 27 07:54:34 PM PDT 24 |
Jul 27 09:11:25 PM PDT 24 |
21059942652 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.375335248 |
|
|
Jul 27 07:56:13 PM PDT 24 |
Jul 27 08:07:58 PM PDT 24 |
19661360000 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1589908929 |
|
|
Jul 27 08:05:47 PM PDT 24 |
Jul 27 08:16:00 PM PDT 24 |
4700640080 ps |
| T1298 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3924848000 |
|
|
Jul 27 07:58:54 PM PDT 24 |
Jul 27 08:59:47 PM PDT 24 |
11488784917 ps |
| T31 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1343390961 |
|
|
Jul 27 08:10:05 PM PDT 24 |
Jul 27 08:14:57 PM PDT 24 |
2611970930 ps |
| T1299 |
/workspace/coverage/default/1.rom_e2e_self_hash.1692851132 |
|
|
Jul 27 08:12:25 PM PDT 24 |
Jul 27 10:06:42 PM PDT 24 |
26270071940 ps |
| T858 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2046625241 |
|
|
Jul 27 08:23:31 PM PDT 24 |
Jul 27 08:35:10 PM PDT 24 |
5848995792 ps |
| T1300 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2179439759 |
|
|
Jul 27 08:10:48 PM PDT 24 |
Jul 27 08:22:17 PM PDT 24 |
4152031340 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3661964191 |
|
|
Jul 27 08:10:20 PM PDT 24 |
Jul 27 08:36:20 PM PDT 24 |
11945934340 ps |
| T850 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.757720944 |
|
|
Jul 27 08:26:42 PM PDT 24 |
Jul 27 08:39:13 PM PDT 24 |
6594803140 ps |
| T1302 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1173108087 |
|
|
Jul 27 08:09:52 PM PDT 24 |
Jul 27 09:27:16 PM PDT 24 |
15014974325 ps |
| T1303 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.4131520835 |
|
|
Jul 27 08:18:10 PM PDT 24 |
Jul 27 08:20:02 PM PDT 24 |
3159857791 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3576881728 |
|
|
Jul 27 08:15:29 PM PDT 24 |
Jul 27 08:19:19 PM PDT 24 |
3026209666 ps |
| T1305 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1806756025 |
|
|
Jul 27 08:24:20 PM PDT 24 |
Jul 27 08:33:58 PM PDT 24 |
3695242638 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.998713874 |
|
|
Jul 27 08:03:07 PM PDT 24 |
Jul 27 08:19:31 PM PDT 24 |
6260672233 ps |
| T1307 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1548517873 |
|
|
Jul 27 08:15:36 PM PDT 24 |
Jul 27 08:25:32 PM PDT 24 |
4845418890 ps |
| T67 |
/workspace/coverage/default/2.chip_sw_alert_test.1468860903 |
|
|
Jul 27 08:12:25 PM PDT 24 |
Jul 27 08:17:48 PM PDT 24 |
3104297324 ps |
| T1308 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2639644240 |
|
|
Jul 27 08:00:02 PM PDT 24 |
Jul 27 09:43:40 PM PDT 24 |
23842899080 ps |
| T1309 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797677478 |
|
|
Jul 27 08:28:01 PM PDT 24 |
Jul 27 08:34:58 PM PDT 24 |
4072920222 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3004626324 |
|
|
Jul 27 07:58:10 PM PDT 24 |
Jul 27 08:12:07 PM PDT 24 |
4736046156 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.684232308 |
|
|
Jul 27 08:11:12 PM PDT 24 |
Jul 27 08:19:38 PM PDT 24 |
4052774858 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.947234342 |
|
|
Jul 27 07:52:58 PM PDT 24 |
Jul 27 08:16:23 PM PDT 24 |
8913537380 ps |
| T1313 |
/workspace/coverage/default/1.chip_sw_example_rom.3713678269 |
|
|
Jul 27 07:52:40 PM PDT 24 |
Jul 27 07:54:55 PM PDT 24 |
2347516200 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2688980223 |
|
|
Jul 27 07:54:11 PM PDT 24 |
Jul 27 07:58:53 PM PDT 24 |
3341418719 ps |
| T263 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3286950857 |
|
|
Jul 27 08:22:09 PM PDT 24 |
Jul 27 08:32:52 PM PDT 24 |
5642133640 ps |
| T1315 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.862873531 |
|
|
Jul 27 08:08:48 PM PDT 24 |
Jul 27 08:12:21 PM PDT 24 |
3172403336 ps |
| T1316 |
/workspace/coverage/default/2.chip_sival_flash_info_access.3103042943 |
|
|
Jul 27 08:14:04 PM PDT 24 |
Jul 27 08:19:39 PM PDT 24 |
2991653856 ps |
| T1317 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.374294981 |
|
|
Jul 27 07:53:58 PM PDT 24 |
Jul 27 08:34:35 PM PDT 24 |
11268245016 ps |
| T1318 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3714241868 |
|
|
Jul 27 08:10:42 PM PDT 24 |
Jul 27 08:32:43 PM PDT 24 |
8803369792 ps |
| T840 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2474414871 |
|
|
Jul 27 08:28:41 PM PDT 24 |
Jul 27 08:41:54 PM PDT 24 |
5194920250 ps |
| T306 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1172747413 |
|
|
Jul 27 08:15:31 PM PDT 24 |
Jul 27 08:23:28 PM PDT 24 |
3124608724 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1011322182 |
|
|
Jul 27 08:02:11 PM PDT 24 |
Jul 27 08:05:48 PM PDT 24 |
2973448290 ps |
| T1320 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3374311236 |
|
|
Jul 27 08:20:20 PM PDT 24 |
Jul 27 09:23:56 PM PDT 24 |
15278343610 ps |
| T1321 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.110816217 |
|
|
Jul 27 08:07:30 PM PDT 24 |
Jul 27 08:12:37 PM PDT 24 |
3646058262 ps |
| T1322 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2251604710 |
|
|
Jul 27 08:15:31 PM PDT 24 |
Jul 27 08:27:08 PM PDT 24 |
4973075130 ps |
| T1323 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2234230168 |
|
|
Jul 27 08:14:20 PM PDT 24 |
Jul 27 08:25:24 PM PDT 24 |
4687151642 ps |
| T364 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.680732073 |
|
|
Jul 27 08:06:19 PM PDT 24 |
Jul 27 08:13:05 PM PDT 24 |
3644293214 ps |
| T264 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1452204781 |
|
|
Jul 27 08:33:41 PM PDT 24 |
Jul 27 08:45:50 PM PDT 24 |
6216367640 ps |
| T739 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1412271797 |
|
|
Jul 27 08:14:35 PM PDT 24 |
Jul 27 08:18:30 PM PDT 24 |
2498389520 ps |
| T166 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3692977778 |
|
|
Jul 27 08:14:19 PM PDT 24 |
Jul 27 08:21:32 PM PDT 24 |
4011233184 ps |
| T1324 |
/workspace/coverage/default/2.chip_sw_flash_init.4050712338 |
|
|
Jul 27 08:10:18 PM PDT 24 |
Jul 27 08:43:15 PM PDT 24 |
19548425623 ps |
| T1325 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1241940205 |
|
|
Jul 27 07:55:54 PM PDT 24 |
Jul 27 08:12:58 PM PDT 24 |
5628334700 ps |
| T767 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025652284 |
|
|
Jul 27 08:26:50 PM PDT 24 |
Jul 27 08:33:26 PM PDT 24 |
3355625090 ps |
| T1326 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1482845999 |
|
|
Jul 27 07:54:04 PM PDT 24 |
Jul 27 07:57:09 PM PDT 24 |
2431764008 ps |
| T1327 |
/workspace/coverage/default/1.chip_sw_aes_enc.3790614894 |
|
|
Jul 27 07:59:30 PM PDT 24 |
Jul 27 08:03:23 PM PDT 24 |
2753917674 ps |
| T1328 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.258227265 |
|
|
Jul 27 08:02:46 PM PDT 24 |
Jul 27 08:38:30 PM PDT 24 |
20920033704 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1154999554 |
|
|
Jul 27 08:08:44 PM PDT 24 |
Jul 27 08:26:25 PM PDT 24 |
8607831400 ps |
| T196 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3808922766 |
|
|
Jul 27 07:53:37 PM PDT 24 |
Jul 27 08:05:41 PM PDT 24 |
7375989250 ps |
| T1330 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1818474448 |
|
|
Jul 27 08:02:10 PM PDT 24 |
Jul 27 08:28:10 PM PDT 24 |
12442648680 ps |
| T1331 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2148171381 |
|
|
Jul 27 08:19:36 PM PDT 24 |
Jul 27 08:26:06 PM PDT 24 |
4086143306 ps |
| T1332 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3715886023 |
|
|
Jul 27 08:20:16 PM PDT 24 |
Jul 27 08:34:42 PM PDT 24 |
4032822740 ps |
| T1333 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.309028502 |
|
|
Jul 27 08:27:07 PM PDT 24 |
Jul 27 08:40:43 PM PDT 24 |
5835484716 ps |
| T1334 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4022439959 |
|
|
Jul 27 08:26:48 PM PDT 24 |
Jul 27 08:32:59 PM PDT 24 |
4111981880 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3305702841 |
|
|
Jul 27 08:00:27 PM PDT 24 |
Jul 27 08:10:42 PM PDT 24 |
6375876932 ps |
| T155 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3701901698 |
|
|
Jul 27 07:55:28 PM PDT 24 |
Jul 27 08:06:06 PM PDT 24 |
4207841190 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2096205042 |
|
|
Jul 27 08:08:57 PM PDT 24 |
Jul 27 08:26:00 PM PDT 24 |
5560543914 ps |
| T1335 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.3582931731 |
|
|
Jul 27 08:03:24 PM PDT 24 |
Jul 27 08:27:11 PM PDT 24 |
7286187924 ps |
| T843 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2497318799 |
|
|
Jul 27 08:29:29 PM PDT 24 |
Jul 27 08:39:40 PM PDT 24 |
3494358472 ps |
| T1336 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.247518862 |
|
|
Jul 27 07:57:55 PM PDT 24 |
Jul 27 08:24:27 PM PDT 24 |
9752763800 ps |
| T1337 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.246141721 |
|
|
Jul 27 07:53:04 PM PDT 24 |
Jul 27 07:56:07 PM PDT 24 |
2172720360 ps |
| T1338 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.3316368639 |
|
|
Jul 27 07:54:14 PM PDT 24 |
Jul 27 08:29:27 PM PDT 24 |
7893543996 ps |
| T768 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1793758669 |
|
|
Jul 27 08:26:17 PM PDT 24 |
Jul 27 08:37:05 PM PDT 24 |
4595172454 ps |
| T823 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1373221744 |
|
|
Jul 27 08:28:14 PM PDT 24 |
Jul 27 08:37:31 PM PDT 24 |
5792971112 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_power_virus.712731608 |
|
|
Jul 27 08:19:12 PM PDT 24 |
Jul 27 08:42:29 PM PDT 24 |
5670015910 ps |
| T1339 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2699276198 |
|
|
Jul 27 07:55:29 PM PDT 24 |
Jul 27 08:05:04 PM PDT 24 |
3885728404 ps |
| T1340 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1701357970 |
|
|
Jul 27 07:56:31 PM PDT 24 |
Jul 27 08:06:12 PM PDT 24 |
10010235136 ps |
| T1341 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1375905272 |
|
|
Jul 27 07:56:36 PM PDT 24 |
Jul 27 08:00:38 PM PDT 24 |
3554213128 ps |
| T1342 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.561928123 |
|
|
Jul 27 08:22:15 PM PDT 24 |
Jul 27 08:28:05 PM PDT 24 |
3366925240 ps |
| T1343 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4089467844 |
|
|
Jul 27 07:56:15 PM PDT 24 |
Jul 27 08:19:59 PM PDT 24 |
7013015536 ps |
| T1344 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3273258010 |
|
|
Jul 27 08:15:51 PM PDT 24 |
Jul 27 08:19:28 PM PDT 24 |
2968240918 ps |
| T1345 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2663385648 |
|
|
Jul 27 07:57:06 PM PDT 24 |
Jul 27 08:02:09 PM PDT 24 |
2600511600 ps |
| T99 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1052935063 |
|
|
Jul 27 08:23:57 PM PDT 24 |
Jul 27 08:32:30 PM PDT 24 |
3323379000 ps |
| T198 |
/workspace/coverage/default/1.chip_jtag_mem_access.1383497337 |
|
|
Jul 27 07:59:07 PM PDT 24 |
Jul 27 08:25:50 PM PDT 24 |
13327747720 ps |
| T1346 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2353860358 |
|
|
Jul 27 07:58:33 PM PDT 24 |
Jul 27 09:09:40 PM PDT 24 |
14679544562 ps |
| T1347 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.273271840 |
|
|
Jul 27 08:25:27 PM PDT 24 |
Jul 27 08:38:29 PM PDT 24 |
4787927992 ps |
| T801 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2161577863 |
|
|
Jul 27 08:33:20 PM PDT 24 |
Jul 27 08:45:19 PM PDT 24 |
5099533530 ps |
| T1348 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3598757848 |
|
|
Jul 27 08:24:22 PM PDT 24 |
Jul 27 08:35:04 PM PDT 24 |
5829143380 ps |
| T788 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.4118091446 |
|
|
Jul 27 08:23:05 PM PDT 24 |
Jul 27 08:33:57 PM PDT 24 |
5622409926 ps |
| T1349 |
/workspace/coverage/default/0.chip_sw_power_idle_load.3933161933 |
|
|
Jul 27 07:55:26 PM PDT 24 |
Jul 27 08:08:09 PM PDT 24 |
4597586786 ps |
| T1350 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1306102548 |
|
|
Jul 27 07:58:35 PM PDT 24 |
Jul 27 09:01:57 PM PDT 24 |
15170186850 ps |
| T1351 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.3120484269 |
|
|
Jul 27 07:53:33 PM PDT 24 |
Jul 27 07:55:04 PM PDT 24 |
2245170201 ps |
| T1352 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.14909745 |
|
|
Jul 27 07:57:11 PM PDT 24 |
Jul 27 08:03:55 PM PDT 24 |
4178617780 ps |
| T1353 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.502195060 |
|
|
Jul 27 08:09:28 PM PDT 24 |
Jul 27 08:27:32 PM PDT 24 |
8704422156 ps |
| T1354 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2574225040 |
|
|
Jul 27 08:27:34 PM PDT 24 |
Jul 27 08:39:18 PM PDT 24 |
6200192292 ps |
| T1355 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3459453649 |
|
|
Jul 27 07:55:52 PM PDT 24 |
Jul 27 07:59:01 PM PDT 24 |
3102816404 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_gpio.1331827505 |
|
|
Jul 27 07:57:34 PM PDT 24 |
Jul 27 08:05:42 PM PDT 24 |
4530448448 ps |
| T1356 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.619790382 |
|
|
Jul 27 08:18:26 PM PDT 24 |
Jul 27 08:29:07 PM PDT 24 |
4917325576 ps |
| T1357 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2255545241 |
|
|
Jul 27 07:58:47 PM PDT 24 |
Jul 27 08:06:33 PM PDT 24 |
5145868852 ps |
| T1358 |
/workspace/coverage/default/0.chip_sw_hmac_enc.717263594 |
|
|
Jul 27 07:56:26 PM PDT 24 |
Jul 27 08:00:22 PM PDT 24 |
2920599420 ps |
| T1359 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2361710524 |
|
|
Jul 27 08:09:23 PM PDT 24 |
Jul 27 08:33:49 PM PDT 24 |
8713127416 ps |
| T1360 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1249580668 |
|
|
Jul 27 08:15:01 PM PDT 24 |
Jul 27 08:20:40 PM PDT 24 |
3436889854 ps |
| T1361 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1260137999 |
|
|
Jul 27 07:54:09 PM PDT 24 |
Jul 27 07:58:59 PM PDT 24 |
2929610911 ps |
| T1362 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2806855721 |
|
|
Jul 27 08:10:51 PM PDT 24 |
Jul 27 08:16:52 PM PDT 24 |
6887356952 ps |
| T307 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1474004958 |
|
|
Jul 27 07:52:41 PM PDT 24 |
Jul 27 07:56:23 PM PDT 24 |
3328730770 ps |
| T1363 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1962938528 |
|
|
Jul 27 07:53:00 PM PDT 24 |
Jul 27 08:04:18 PM PDT 24 |
5009794560 ps |
| T1364 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.587879165 |
|
|
Jul 27 07:57:54 PM PDT 24 |
Jul 27 08:11:16 PM PDT 24 |
4626778154 ps |