| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.37 | 95.57 | 94.64 | 95.35 | 95.55 | 97.53 | 99.59 |
| T2764 | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2561595761 | Jul 27 08:43:10 PM PDT 24 | Jul 27 08:43:17 PM PDT 24 | 41090292 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/72.xbar_stress_all.1741038804 | Jul 27 08:44:52 PM PDT 24 | Jul 27 08:50:42 PM PDT 24 | 10148679048 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1435626529 | Jul 27 08:42:17 PM PDT 24 | Jul 27 08:43:18 PM PDT 24 | 5809093872 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3930173672 | Jul 27 08:32:57 PM PDT 24 | Jul 27 09:04:17 PM PDT 24 | 108034136549 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2119408409 | Jul 27 08:47:55 PM PDT 24 | Jul 27 08:52:03 PM PDT 24 | 2801714031 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/9.chip_tl_errors.1057552843 | Jul 27 08:30:48 PM PDT 24 | Jul 27 08:36:34 PM PDT 24 | 4456134700 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.592552683 | Jul 27 08:44:42 PM PDT 24 | Jul 27 08:52:40 PM PDT 24 | 13513183828 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1957370249 | Jul 27 08:45:47 PM PDT 24 | Jul 27 08:47:10 PM PDT 24 | 2019609579 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.673945011 | Jul 27 08:47:21 PM PDT 24 | Jul 27 08:51:15 PM PDT 24 | 636821370 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2798420731 | Jul 27 08:45:00 PM PDT 24 | Jul 27 08:45:17 PM PDT 24 | 153891992 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/28.xbar_random.929483851 | Jul 27 08:36:59 PM PDT 24 | Jul 27 08:37:17 PM PDT 24 | 380793929 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/55.xbar_same_source.3090062543 | Jul 27 08:41:52 PM PDT 24 | Jul 27 08:42:19 PM PDT 24 | 372316706 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1965791703 | Jul 27 08:36:32 PM PDT 24 | Jul 27 08:47:58 PM PDT 24 | 18337943110 ps | ||
| T735 | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2565854004 | Jul 27 08:40:53 PM PDT 24 | Jul 27 08:48:00 PM PDT 24 | 4594482723 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1737226346 | Jul 27 08:38:41 PM PDT 24 | Jul 27 08:39:01 PM PDT 24 | 163724298 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3649559500 | Jul 27 08:33:04 PM PDT 24 | Jul 27 08:34:43 PM PDT 24 | 9229246091 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.4256745426 | Jul 27 08:47:22 PM PDT 24 | Jul 27 09:17:18 PM PDT 24 | 106281326445 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.482463540 | Jul 27 08:37:05 PM PDT 24 | Jul 27 08:42:46 PM PDT 24 | 5954604460 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/53.xbar_error_random.1614250553 | Jul 27 08:41:28 PM PDT 24 | Jul 27 08:42:12 PM PDT 24 | 1094858704 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.571623927 | Jul 27 08:35:53 PM PDT 24 | Jul 27 08:36:03 PM PDT 24 | 92754554 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1386494398 | Jul 27 08:40:47 PM PDT 24 | Jul 27 08:42:28 PM PDT 24 | 5673311282 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/69.xbar_stress_all.4069283559 | Jul 27 08:44:28 PM PDT 24 | Jul 27 08:49:19 PM PDT 24 | 7378095959 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2027802616 | Jul 27 08:44:02 PM PDT 24 | Jul 27 08:44:09 PM PDT 24 | 57143591 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2060567075 | Jul 27 08:33:31 PM PDT 24 | Jul 27 08:39:16 PM PDT 24 | 4232540228 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3710307126 | Jul 27 08:48:12 PM PDT 24 | Jul 27 08:55:50 PM PDT 24 | 12672410598 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.135466496 | Jul 27 08:41:49 PM PDT 24 | Jul 27 08:42:40 PM PDT 24 | 506918544 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.207017444 | Jul 27 08:49:45 PM PDT 24 | Jul 27 08:51:25 PM PDT 24 | 5392321419 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.749230963 | Jul 27 08:41:22 PM PDT 24 | Jul 27 09:10:50 PM PDT 24 | 95934959936 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1067749584 | Jul 27 08:33:51 PM PDT 24 | Jul 27 08:35:29 PM PDT 24 | 1828894160 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/89.xbar_smoke.3646129400 | Jul 27 08:48:00 PM PDT 24 | Jul 27 08:48:06 PM PDT 24 | 33467506 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/60.xbar_smoke.1908682320 | Jul 27 08:42:33 PM PDT 24 | Jul 27 08:42:40 PM PDT 24 | 53341829 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3248325654 | Jul 27 08:48:20 PM PDT 24 | Jul 27 08:55:11 PM PDT 24 | 23415840138 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.800062710 | Jul 27 08:25:07 PM PDT 24 | Jul 27 08:28:50 PM PDT 24 | 5033367370 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2611542090 | Jul 27 08:45:17 PM PDT 24 | Jul 27 08:49:04 PM PDT 24 | 21886049037 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/23.xbar_smoke.2741788609 | Jul 27 08:35:48 PM PDT 24 | Jul 27 08:35:59 PM PDT 24 | 208201357 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/96.xbar_error_random.1705763837 | Jul 27 08:49:24 PM PDT 24 | Jul 27 08:50:34 PM PDT 24 | 2103942133 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/34.xbar_error_random.3291502874 | Jul 27 08:37:58 PM PDT 24 | Jul 27 08:38:05 PM PDT 24 | 34863701 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/40.xbar_smoke.2473849279 | Jul 27 08:39:08 PM PDT 24 | Jul 27 08:39:18 PM PDT 24 | 240426719 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3242928511 | Jul 27 08:44:01 PM PDT 24 | Jul 27 08:45:03 PM PDT 24 | 1348942273 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1967822588 | Jul 27 08:30:44 PM PDT 24 | Jul 27 08:47:25 PM PDT 24 | 11520734710 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1709725286 | Jul 27 08:25:58 PM PDT 24 | Jul 27 08:31:01 PM PDT 24 | 8013332975 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1900462815 | Jul 27 08:47:51 PM PDT 24 | Jul 27 08:48:56 PM PDT 24 | 722058812 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2311709016 | Jul 27 08:37:15 PM PDT 24 | Jul 27 09:25:38 PM PDT 24 | 174101292362 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2616716416 | Jul 27 08:47:05 PM PDT 24 | Jul 27 08:48:33 PM PDT 24 | 4924026865 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3454254098 | Jul 27 08:31:41 PM PDT 24 | Jul 27 08:34:21 PM PDT 24 | 1783202044 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/28.xbar_smoke.1574166765 | Jul 27 08:36:57 PM PDT 24 | Jul 27 08:37:06 PM PDT 24 | 157363807 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.926736772 | Jul 27 08:45:51 PM PDT 24 | Jul 27 08:46:59 PM PDT 24 | 1766138415 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2296849044 | Jul 27 08:41:01 PM PDT 24 | Jul 27 08:43:25 PM PDT 24 | 3117370779 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1410946140 | Jul 27 08:40:52 PM PDT 24 | Jul 27 08:57:34 PM PDT 24 | 56771382575 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/90.xbar_error_random.1384359022 | Jul 27 08:48:11 PM PDT 24 | Jul 27 08:48:57 PM PDT 24 | 581523094 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3011321364 | Jul 27 08:44:11 PM PDT 24 | Jul 27 08:48:13 PM PDT 24 | 3111406081 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1151086556 | Jul 27 08:28:39 PM PDT 24 | Jul 27 08:29:05 PM PDT 24 | 596047577 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3596673976 | Jul 27 08:46:22 PM PDT 24 | Jul 27 08:46:49 PM PDT 24 | 216876957 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.4202781664 | Jul 27 08:48:47 PM PDT 24 | Jul 27 08:51:55 PM PDT 24 | 17324216433 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2926475664 | Jul 27 08:42:40 PM PDT 24 | Jul 27 08:43:50 PM PDT 24 | 1522470111 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2961557696 | Jul 27 08:49:41 PM PDT 24 | Jul 27 08:49:48 PM PDT 24 | 49798641 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2039249829 | Jul 27 08:42:15 PM PDT 24 | Jul 27 08:56:44 PM PDT 24 | 82535361351 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.4032504651 | Jul 27 08:38:28 PM PDT 24 | Jul 27 08:38:55 PM PDT 24 | 538758001 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2141402049 | Jul 27 08:33:21 PM PDT 24 | Jul 27 08:40:30 PM PDT 24 | 1175860020 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1401598748 | Jul 27 08:45:57 PM PDT 24 | Jul 27 08:46:51 PM PDT 24 | 5043750086 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/61.xbar_error_random.2490085884 | Jul 27 08:42:53 PM PDT 24 | Jul 27 08:43:07 PM PDT 24 | 272830241 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.488808418 | Jul 27 08:47:52 PM PDT 24 | Jul 27 08:51:46 PM PDT 24 | 2749999932 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3673664242 | Jul 27 08:44:12 PM PDT 24 | Jul 27 09:23:24 PM PDT 24 | 136819825544 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3277128712 | Jul 27 08:47:35 PM PDT 24 | Jul 27 08:48:58 PM PDT 24 | 7457341404 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3848137865 | Jul 27 08:43:14 PM PDT 24 | Jul 27 08:55:07 PM PDT 24 | 6444510539 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1109241437 | Jul 27 08:33:50 PM PDT 24 | Jul 27 08:39:01 PM PDT 24 | 1197030880 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2616427843 | Jul 27 08:26:45 PM PDT 24 | Jul 27 08:30:13 PM PDT 24 | 5405084504 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.1651771235 | Jul 27 08:38:15 PM PDT 24 | Jul 27 08:43:10 PM PDT 24 | 29028102972 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1320046963 | Jul 27 08:39:48 PM PDT 24 | Jul 27 08:40:21 PM PDT 24 | 264439898 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2457564210 | Jul 27 08:44:53 PM PDT 24 | Jul 27 08:45:11 PM PDT 24 | 369892748 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/98.xbar_error_random.2295416995 | Jul 27 08:49:44 PM PDT 24 | Jul 27 08:49:57 PM PDT 24 | 100890284 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.4156125823 | Jul 27 08:40:55 PM PDT 24 | Jul 27 08:41:38 PM PDT 24 | 1017164939 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/36.xbar_random.3392978067 | Jul 27 08:38:25 PM PDT 24 | Jul 27 08:39:00 PM PDT 24 | 367157232 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1936967837 | Jul 27 08:48:34 PM PDT 24 | Jul 27 08:50:09 PM PDT 24 | 5760231730 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3442047393 | Jul 27 08:37:33 PM PDT 24 | Jul 27 08:38:00 PM PDT 24 | 208659952 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/46.xbar_same_source.213711224 | Jul 27 08:40:16 PM PDT 24 | Jul 27 08:40:30 PM PDT 24 | 154927324 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/43.xbar_smoke.3621518933 | Jul 27 08:39:44 PM PDT 24 | Jul 27 08:39:53 PM PDT 24 | 177270411 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3295629368 | Jul 27 08:44:45 PM PDT 24 | Jul 27 08:45:23 PM PDT 24 | 447583898 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.102506897 | Jul 27 08:49:31 PM PDT 24 | Jul 27 08:50:39 PM PDT 24 | 3869328501 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3611447729 | Jul 27 08:45:32 PM PDT 24 | Jul 27 08:48:37 PM PDT 24 | 3750005620 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3307220099 | Jul 27 08:39:25 PM PDT 24 | Jul 27 08:47:42 PM PDT 24 | 9343079654 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/42.xbar_random.3751054619 | Jul 27 08:39:32 PM PDT 24 | Jul 27 08:39:38 PM PDT 24 | 30626619 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/62.xbar_stress_all.1549561011 | Jul 27 08:43:07 PM PDT 24 | Jul 27 08:48:40 PM PDT 24 | 8008247487 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/95.xbar_same_source.3885962671 | Jul 27 08:49:05 PM PDT 24 | Jul 27 08:49:42 PM PDT 24 | 457384693 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/41.xbar_smoke.2369863315 | Jul 27 08:39:25 PM PDT 24 | Jul 27 08:39:35 PM PDT 24 | 224649207 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1990309119 | Jul 27 08:39:51 PM PDT 24 | Jul 27 08:46:57 PM PDT 24 | 10310210226 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/33.xbar_smoke.2701733553 | Jul 27 08:37:42 PM PDT 24 | Jul 27 08:37:49 PM PDT 24 | 45508462 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/52.xbar_same_source.2419341393 | Jul 27 08:41:20 PM PDT 24 | Jul 27 08:42:00 PM PDT 24 | 509592492 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1331042198 | Jul 27 08:48:12 PM PDT 24 | Jul 27 08:50:29 PM PDT 24 | 546083682 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.699827427 | Jul 27 08:41:56 PM PDT 24 | Jul 27 08:43:27 PM PDT 24 | 436681744 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.4031309434 | Jul 27 08:49:45 PM PDT 24 | Jul 27 08:50:27 PM PDT 24 | 914839670 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3106282507 | Jul 27 08:32:13 PM PDT 24 | Jul 27 08:33:07 PM PDT 24 | 1283460044 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1324679227 | Jul 27 08:48:07 PM PDT 24 | Jul 27 08:54:06 PM PDT 24 | 3374434585 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1305865494 | Jul 27 08:35:57 PM PDT 24 | Jul 27 08:37:24 PM PDT 24 | 4919637738 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.883169956 | Jul 27 08:25:47 PM PDT 24 | Jul 27 08:26:31 PM PDT 24 | 318146245 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.766951407 | Jul 27 08:48:32 PM PDT 24 | Jul 27 08:49:27 PM PDT 24 | 5305148587 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3894874181 | Jul 27 08:39:42 PM PDT 24 | Jul 27 08:46:05 PM PDT 24 | 2840317686 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1678944301 | Jul 27 08:35:09 PM PDT 24 | Jul 27 08:44:54 PM PDT 24 | 5652074690 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4192940036 | Jul 27 08:29:55 PM PDT 24 | Jul 27 08:31:16 PM PDT 24 | 4502419336 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1455105535 | Jul 27 08:35:42 PM PDT 24 | Jul 27 08:36:05 PM PDT 24 | 27793112 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/38.xbar_random.2656956923 | Jul 27 08:38:48 PM PDT 24 | Jul 27 08:40:02 PM PDT 24 | 1894185340 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1710340114 | Jul 27 08:36:40 PM PDT 24 | Jul 27 08:37:27 PM PDT 24 | 519629735 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.54014778 | Jul 27 08:31:14 PM PDT 24 | Jul 27 08:33:13 PM PDT 24 | 6566915515 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.4228229926 | Jul 27 08:38:31 PM PDT 24 | Jul 27 08:44:43 PM PDT 24 | 20583238274 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1003175485 | Jul 27 08:32:13 PM PDT 24 | Jul 27 08:49:50 PM PDT 24 | 8393612944 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1233967421 | Jul 27 08:34:55 PM PDT 24 | Jul 27 08:35:04 PM PDT 24 | 44905713 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1247151241 | Jul 27 08:33:51 PM PDT 24 | Jul 27 08:50:27 PM PDT 24 | 12020025489 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3744778924 | Jul 27 08:37:49 PM PDT 24 | Jul 27 08:48:47 PM PDT 24 | 4658479231 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3071090006 | Jul 27 08:46:21 PM PDT 24 | Jul 27 08:52:39 PM PDT 24 | 4567063415 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.4202010277 | Jul 27 08:42:41 PM PDT 24 | Jul 27 08:45:50 PM PDT 24 | 10720785576 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2507371032 | Jul 27 08:30:49 PM PDT 24 | Jul 27 08:31:12 PM PDT 24 | 210314161 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.885183093 | Jul 27 08:29:00 PM PDT 24 | Jul 27 08:37:06 PM PDT 24 | 6090813075 ps | ||
| T772 | /workspace/coverage/cover_reg_top/5.chip_tl_errors.3963793169 | Jul 27 08:28:20 PM PDT 24 | Jul 27 08:33:19 PM PDT 24 | 4938730175 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/20.xbar_error_random.4205037848 | Jul 27 08:35:18 PM PDT 24 | Jul 27 08:36:50 PM PDT 24 | 2107549712 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1234992980 | Jul 27 08:48:38 PM PDT 24 | Jul 27 08:48:45 PM PDT 24 | 15773058 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1373981711 | Jul 27 08:41:25 PM PDT 24 | Jul 27 08:53:28 PM PDT 24 | 42985343295 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/76.xbar_random.2213527097 | Jul 27 08:45:23 PM PDT 24 | Jul 27 08:45:43 PM PDT 24 | 230776120 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.669883142 | Jul 27 08:33:12 PM PDT 24 | Jul 27 08:34:15 PM PDT 24 | 5652929145 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/45.xbar_same_source.3924938924 | Jul 27 08:39:57 PM PDT 24 | Jul 27 08:40:30 PM PDT 24 | 420664491 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3666201307 | Jul 27 08:26:05 PM PDT 24 | Jul 27 08:37:44 PM PDT 24 | 5939922324 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1213770197 | Jul 27 08:42:08 PM PDT 24 | Jul 27 08:48:47 PM PDT 24 | 38778735374 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/72.xbar_same_source.197966990 | Jul 27 08:44:54 PM PDT 24 | Jul 27 08:45:33 PM PDT 24 | 517659868 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.234714933 | Jul 27 08:39:51 PM PDT 24 | Jul 27 08:58:07 PM PDT 24 | 103408329808 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/23.xbar_random.2849592210 | Jul 27 08:35:49 PM PDT 24 | Jul 27 08:36:04 PM PDT 24 | 120983712 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1401981149 | Jul 27 08:32:52 PM PDT 24 | Jul 27 08:34:04 PM PDT 24 | 4971068174 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3478140994 | Jul 27 08:48:29 PM PDT 24 | Jul 27 08:49:53 PM PDT 24 | 8283952980 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.340739181 | Jul 27 08:42:21 PM PDT 24 | Jul 27 08:42:35 PM PDT 24 | 102331460 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2947334105 | Jul 27 08:43:11 PM PDT 24 | Jul 27 08:50:13 PM PDT 24 | 6798557648 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2385263187 | Jul 27 08:47:34 PM PDT 24 | Jul 27 08:49:19 PM PDT 24 | 185302242 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1797241282 | Jul 27 08:40:56 PM PDT 24 | Jul 27 08:54:29 PM PDT 24 | 79593568221 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/21.xbar_error_random.2385942 | Jul 27 08:35:28 PM PDT 24 | Jul 27 08:35:34 PM PDT 24 | 32486459 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.4200799660 | Jul 27 08:48:11 PM PDT 24 | Jul 27 08:48:29 PM PDT 24 | 394697057 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.915177845 | Jul 27 08:47:35 PM PDT 24 | Jul 27 08:55:49 PM PDT 24 | 29142609998 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.695059488 | Jul 27 08:49:31 PM PDT 24 | Jul 27 08:50:05 PM PDT 24 | 380809586 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3469838315 | Jul 27 08:37:26 PM PDT 24 | Jul 27 08:40:29 PM PDT 24 | 17785502642 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.4089840223 | Jul 27 08:34:15 PM PDT 24 | Jul 27 08:34:27 PM PDT 24 | 215902721 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2945186425 | Jul 27 08:42:46 PM PDT 24 | Jul 27 08:43:10 PM PDT 24 | 249167079 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/49.xbar_random.2319438343 | Jul 27 08:40:52 PM PDT 24 | Jul 27 08:41:51 PM PDT 24 | 1542381044 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.164633670 | Jul 27 08:46:25 PM PDT 24 | Jul 27 08:46:31 PM PDT 24 | 53698377 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/3.xbar_smoke.922057890 | Jul 27 08:26:28 PM PDT 24 | Jul 27 08:26:38 PM PDT 24 | 214042904 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3661614212 | Jul 27 08:28:46 PM PDT 24 | Jul 27 08:37:22 PM PDT 24 | 6956797785 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1170624754 | Jul 27 08:43:00 PM PDT 24 | Jul 27 08:43:43 PM PDT 24 | 924329013 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3718977807 | Jul 27 08:46:29 PM PDT 24 | Jul 27 08:47:26 PM PDT 24 | 639923901 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3392727330 | Jul 27 08:42:39 PM PDT 24 | Jul 27 08:42:45 PM PDT 24 | 40343240 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2140531899 | Jul 27 08:45:00 PM PDT 24 | Jul 27 08:46:31 PM PDT 24 | 4993804823 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2096946745 | Jul 27 08:27:47 PM PDT 24 | Jul 27 08:32:09 PM PDT 24 | 4237004907 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2251873102 | Jul 27 08:45:18 PM PDT 24 | Jul 27 08:47:28 PM PDT 24 | 7554422670 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.625352983 | Jul 27 08:40:47 PM PDT 24 | Jul 27 08:50:10 PM PDT 24 | 4554224768 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.4039124602 | Jul 27 08:49:43 PM PDT 24 | Jul 27 09:31:17 PM PDT 24 | 141419922674 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/39.xbar_random.1313053351 | Jul 27 08:39:00 PM PDT 24 | Jul 27 08:39:13 PM PDT 24 | 124676107 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/19.xbar_smoke.1483612724 | Jul 27 08:34:48 PM PDT 24 | Jul 27 08:34:57 PM PDT 24 | 195886234 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3395684224 | Jul 27 08:45:03 PM PDT 24 | Jul 27 08:48:38 PM PDT 24 | 2603508091 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3410656997 | Jul 27 08:43:32 PM PDT 24 | Jul 27 08:44:15 PM PDT 24 | 1092361049 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2343783646 | Jul 27 08:32:45 PM PDT 24 | Jul 27 08:36:03 PM PDT 24 | 10302944037 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/35.xbar_error_random.2043090394 | Jul 27 08:38:13 PM PDT 24 | Jul 27 08:38:30 PM PDT 24 | 362673391 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4232815347 | Jul 27 08:38:31 PM PDT 24 | Jul 27 08:41:55 PM PDT 24 | 1969330028 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2957831640 | Jul 27 08:49:07 PM PDT 24 | Jul 27 08:49:37 PM PDT 24 | 358528941 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/18.xbar_same_source.276999542 | Jul 27 08:34:41 PM PDT 24 | Jul 27 08:35:13 PM PDT 24 | 903356738 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.2641155829 | Jul 27 08:47:48 PM PDT 24 | Jul 27 08:49:08 PM PDT 24 | 4806839971 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/64.xbar_error_random.1990499566 | Jul 27 08:43:22 PM PDT 24 | Jul 27 08:43:59 PM PDT 24 | 1047368477 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3507805178 | Jul 27 08:41:40 PM PDT 24 | Jul 27 08:41:44 PM PDT 24 | 6152228 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1095090953 | Jul 27 08:49:02 PM PDT 24 | Jul 27 08:51:30 PM PDT 24 | 300168224 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.306357933 | Jul 27 08:46:11 PM PDT 24 | Jul 27 08:47:34 PM PDT 24 | 4616598389 ps | ||
| T669 | /workspace/coverage/cover_reg_top/13.xbar_error_random.3769128459 | Jul 27 08:32:58 PM PDT 24 | Jul 27 08:33:36 PM PDT 24 | 387468708 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1535074035 | Jul 27 08:37:48 PM PDT 24 | Jul 27 09:09:18 PM PDT 24 | 103659725772 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/48.xbar_error_random.1502378542 | Jul 27 08:40:39 PM PDT 24 | Jul 27 08:42:05 PM PDT 24 | 2398759015 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3938565047 | Jul 27 08:43:49 PM PDT 24 | Jul 27 08:51:36 PM PDT 24 | 8813437251 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3096621765 | Jul 27 08:40:01 PM PDT 24 | Jul 27 08:41:21 PM PDT 24 | 4695146367 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1510226176 | Jul 27 08:41:13 PM PDT 24 | Jul 27 08:43:39 PM PDT 24 | 376506822 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3945222014 | Jul 27 08:26:46 PM PDT 24 | Jul 27 08:28:25 PM PDT 24 | 378349768 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.615131731 | Jul 27 08:31:56 PM PDT 24 | Jul 27 08:32:54 PM PDT 24 | 1125749734 ps | ||
| T25 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3733926912 | Jul 27 08:49:54 PM PDT 24 | Jul 27 08:54:47 PM PDT 24 | 5225109666 ps | ||
| T26 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4058339183 | Jul 27 08:49:55 PM PDT 24 | Jul 27 08:53:52 PM PDT 24 | 4923207026 ps | ||
| T27 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3440488605 | Jul 27 08:49:53 PM PDT 24 | Jul 27 08:53:34 PM PDT 24 | 4765976642 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.774603622 | Jul 27 08:50:08 PM PDT 24 | Jul 27 08:54:07 PM PDT 24 | 4846273952 ps | ||
| T185 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.21651967 | Jul 27 08:49:52 PM PDT 24 | Jul 27 08:53:32 PM PDT 24 | 4717382352 ps | ||
| T186 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.233123665 | Jul 27 08:50:05 PM PDT 24 | Jul 27 08:54:05 PM PDT 24 | 5577159480 ps | ||
| T192 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.241269224 | Jul 27 08:49:52 PM PDT 24 | Jul 27 08:53:47 PM PDT 24 | 4890119832 ps | ||
| T187 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3381088067 | Jul 27 08:50:08 PM PDT 24 | Jul 27 08:53:37 PM PDT 24 | 4721231164 ps | ||
| T188 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2523071507 | Jul 27 08:50:05 PM PDT 24 | Jul 27 08:54:23 PM PDT 24 | 5447298528 ps | ||
| T189 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.417587248 | Jul 27 08:49:56 PM PDT 24 | Jul 27 08:55:59 PM PDT 24 | 4705176724 ps |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.1306625303 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4899289400 ps |
| CPU time | 440.86 seconds |
| Started | Jul 27 08:27:09 PM PDT 24 |
| Finished | Jul 27 08:34:30 PM PDT 24 |
| Peak memory | 650620 kb |
| Host | smart-5500bdb1-c410-4076-854f-381c247b11ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1306625303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1306625303 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.4261827518 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 10115067442 ps |
| CPU time | 1061.15 seconds |
| Started | Jul 27 08:26:19 PM PDT 24 |
| Finished | Jul 27 08:44:00 PM PDT 24 |
| Peak memory | 652420 kb |
| Host | smart-b11c7eca-d6d0-4903-994e-d2bdff1a1cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261827518 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.4261827518 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.186055431 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5889597741 ps |
| CPU time | 572.48 seconds |
| Started | Jul 27 08:40:39 PM PDT 24 |
| Finished | Jul 27 08:50:12 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-8391efd3-bf85-458b-b12a-1c4f3e9b8761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186055431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.186055431 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1229286000 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4216481930 ps |
| CPU time | 583.88 seconds |
| Started | Jul 27 08:13:52 PM PDT 24 |
| Finished | Jul 27 08:23:36 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-4c7b191b-10a1-4fdb-bdb5-5fcd875e3733 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229286000 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1229286000 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1200241610 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 134218070144 ps |
| CPU time | 2347.3 seconds |
| Started | Jul 27 08:43:18 PM PDT 24 |
| Finished | Jul 27 09:22:25 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-90da5d35-2979-4b5a-897e-b79305c268fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200241610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1200241610 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3733926912 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5225109666 ps |
| CPU time | 293.53 seconds |
| Started | Jul 27 08:49:54 PM PDT 24 |
| Finished | Jul 27 08:54:47 PM PDT 24 |
| Peak memory | 657852 kb |
| Host | smart-8163b946-9262-425f-a106-e825c81461f4 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733926912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.3733926912 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2368928937 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 154832431571 ps |
| CPU time | 2575.78 seconds |
| Started | Jul 27 08:40:26 PM PDT 24 |
| Finished | Jul 27 09:23:22 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-2b9bbddc-b9bb-44f8-9951-82a05281d505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368928937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2368928937 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3317646799 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 12058388240 ps |
| CPU time | 2384.63 seconds |
| Started | Jul 27 08:14:00 PM PDT 24 |
| Finished | Jul 27 08:53:45 PM PDT 24 |
| Peak memory | 618768 kb |
| Host | smart-7133e206-b9d7-41ab-a955-ceecd83e51df |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3317646799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3317646799 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3709392808 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 110636278373 ps |
| CPU time | 1972.42 seconds |
| Started | Jul 27 08:48:53 PM PDT 24 |
| Finished | Jul 27 09:21:46 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-e25f153e-8280-4072-8623-ea21fd9e19c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709392808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3709392808 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.369586908 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11736632141 ps |
| CPU time | 2913.15 seconds |
| Started | Jul 27 08:13:47 PM PDT 24 |
| Finished | Jul 27 09:02:21 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-3fe71b11-7553-4c72-8104-45f2b3654b4a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369586908 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.rom_e2e_asm_init_test_unlocked0.369586908 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.1849884320 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 12634227480 ps |
| CPU time | 1238.2 seconds |
| Started | Jul 27 07:44:38 PM PDT 24 |
| Finished | Jul 27 08:05:17 PM PDT 24 |
| Peak memory | 604268 kb |
| Host | smart-2737a9dd-2eae-4dbf-883a-090007319128 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849884320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1849884320 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.288230208 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5671483336 ps |
| CPU time | 1379.68 seconds |
| Started | Jul 27 08:06:10 PM PDT 24 |
| Finished | Jul 27 08:29:10 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-f3c1ce14-3fb6-43ea-bc69-672cad08c9bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288230208 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.288230208 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2356719230 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 30315222440 ps |
| CPU time | 2613.83 seconds |
| Started | Jul 27 07:56:50 PM PDT 24 |
| Finished | Jul 27 08:40:24 PM PDT 24 |
| Peak memory | 620976 kb |
| Host | smart-0cd13bf1-4c67-4736-ad7d-8b2a4de43146 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2356719230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.2356719230 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.472287850 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 112657312110 ps |
| CPU time | 2122.19 seconds |
| Started | Jul 27 08:37:28 PM PDT 24 |
| Finished | Jul 27 09:12:51 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-b710ecba-f76b-42c6-a710-0fa40240d925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472287850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.472287850 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.3121878940 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5883926472 ps |
| CPU time | 1720.58 seconds |
| Started | Jul 27 08:12:12 PM PDT 24 |
| Finished | Jul 27 08:40:52 PM PDT 24 |
| Peak memory | 625428 kb |
| Host | smart-6eb3d981-555b-4acd-bf97-a2810e1cc1f4 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3121878940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.3121878940 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.841152808 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2813676880 ps |
| CPU time | 281.32 seconds |
| Started | Jul 27 07:59:53 PM PDT 24 |
| Finished | Jul 27 08:04:35 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-b348e092-e222-40ea-b0e3-74883e1f033d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841152808 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.841152808 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2800501273 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3527549224 ps |
| CPU time | 386.5 seconds |
| Started | Jul 27 07:58:35 PM PDT 24 |
| Finished | Jul 27 08:05:02 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-9a7d474a-9b4b-471f-a18b-e3de22239586 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2800501273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2800501273 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.826970398 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 86979879099 ps |
| CPU time | 1526.43 seconds |
| Started | Jul 27 08:43:25 PM PDT 24 |
| Finished | Jul 27 09:08:51 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-30cbc084-b232-42a5-b673-04461c9a98f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826970398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.826970398 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.754233730 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3594229088 ps |
| CPU time | 367.09 seconds |
| Started | Jul 27 08:09:03 PM PDT 24 |
| Finished | Jul 27 08:15:11 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-da2ca1e8-4765-4389-a677-fb191c10a552 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7542 33730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.754233730 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.1854109000 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 5251034792 ps |
| CPU time | 920.46 seconds |
| Started | Jul 27 08:05:20 PM PDT 24 |
| Finished | Jul 27 08:20:41 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-0d66ee54-cea2-4189-b7ba-6cccce01fa3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854109000 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.1854109000 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1953609812 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7290274760 ps |
| CPU time | 403.27 seconds |
| Started | Jul 27 08:14:58 PM PDT 24 |
| Finished | Jul 27 08:21:41 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-6907330d-3252-4e3a-bd02-065714383022 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953609812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1953609812 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2987732390 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 9251696336 ps |
| CPU time | 1523.9 seconds |
| Started | Jul 27 08:15:54 PM PDT 24 |
| Finished | Jul 27 08:41:18 PM PDT 24 |
| Peak memory | 611724 kb |
| Host | smart-925abd36-1c8e-4ecb-b70e-95730fd3c1cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298773 2390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2987732390 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2333595227 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 77769986388 ps |
| CPU time | 14945.3 seconds |
| Started | Jul 27 07:54:49 PM PDT 24 |
| Finished | Jul 28 12:03:56 AM PDT 24 |
| Peak memory | 635624 kb |
| Host | smart-e4d2b362-35b8-42ff-8392-a30703786330 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2333595227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2333595227 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.3173607169 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4626967412 ps |
| CPU time | 517.5 seconds |
| Started | Jul 27 08:09:17 PM PDT 24 |
| Finished | Jul 27 08:17:55 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-7780f657-9458-492d-9088-5dcd3755d09c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173607169 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3173607169 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3777557129 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 67549350043 ps |
| CPU time | 1211.35 seconds |
| Started | Jul 27 08:47:36 PM PDT 24 |
| Finished | Jul 27 09:07:47 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5ffea11a-0725-4fa7-93bc-44ed47ea95a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777557129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.3777557129 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2197921964 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 14472349729 ps |
| CPU time | 584.19 seconds |
| Started | Jul 27 08:44:26 PM PDT 24 |
| Finished | Jul 27 08:54:10 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-269097f7-dc86-482a-b476-0580b05ec37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197921964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.2197921964 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4233885428 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5890178184 ps |
| CPU time | 1181.94 seconds |
| Started | Jul 27 07:56:18 PM PDT 24 |
| Finished | Jul 27 08:16:01 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-767573f2-9c83-414f-881a-fa147818423b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4233885428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.4233885428 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.1343607656 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3686261836 ps |
| CPU time | 340.91 seconds |
| Started | Jul 27 08:35:58 PM PDT 24 |
| Finished | Jul 27 08:41:39 PM PDT 24 |
| Peak memory | 603452 kb |
| Host | smart-d962485e-04ca-40a5-a508-d8b59f8ebbf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343607656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1343607656 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2722711749 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 47809993550 ps |
| CPU time | 6239.1 seconds |
| Started | Jul 27 07:53:46 PM PDT 24 |
| Finished | Jul 27 09:37:46 PM PDT 24 |
| Peak memory | 621040 kb |
| Host | smart-0c963227-a7c3-4b88-bef1-16af28d9d879 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722711749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2722711749 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2528721445 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 30115741606 ps |
| CPU time | 3349.17 seconds |
| Started | Jul 27 08:34:07 PM PDT 24 |
| Finished | Jul 27 09:29:56 PM PDT 24 |
| Peak memory | 593456 kb |
| Host | smart-b8161e3a-1757-4ba0-911a-e28ecb98851f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528721445 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2528721445 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1676208984 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13928841694 ps |
| CPU time | 4165.55 seconds |
| Started | Jul 27 08:09:48 PM PDT 24 |
| Finished | Jul 27 09:19:15 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-62566019-ac05-4f16-a58a-3e0d55126753 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676208984 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1676208984 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1663618328 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5053886120 ps |
| CPU time | 543.35 seconds |
| Started | Jul 27 07:53:43 PM PDT 24 |
| Finished | Jul 27 08:02:46 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-b4149982-f0fd-482b-b1cb-56cb61358711 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636183 28 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1663618328 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904612141 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3715017324 ps |
| CPU time | 344.17 seconds |
| Started | Jul 27 08:29:52 PM PDT 24 |
| Finished | Jul 27 08:35:36 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-e55c6e91-d0ea-40e1-9821-41953d5a81dd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904612141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1904612141 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.845033165 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 19849011920 ps |
| CPU time | 2672.6 seconds |
| Started | Jul 27 07:59:02 PM PDT 24 |
| Finished | Jul 27 08:43:35 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-70c91b72-74af-41c3-8fec-91ae5bc34c06 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845033165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.845033165 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.4226987870 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 5040403429 ps |
| CPU time | 494.75 seconds |
| Started | Jul 27 08:49:19 PM PDT 24 |
| Finished | Jul 27 08:57:34 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-25d6de96-232d-4829-b4a9-89ee4c6eee58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226987870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.4226987870 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2461112712 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 85049771280 ps |
| CPU time | 852.87 seconds |
| Started | Jul 27 08:47:36 PM PDT 24 |
| Finished | Jul 27 09:01:49 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f270fda8-636c-4e7f-b5f6-04f1114c1cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461112712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2461112712 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.1874650946 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4460930304 ps |
| CPU time | 388.05 seconds |
| Started | Jul 27 08:27:12 PM PDT 24 |
| Finished | Jul 27 08:33:40 PM PDT 24 |
| Peak memory | 603400 kb |
| Host | smart-48a49dda-782d-4809-842b-a21c8fd12dd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874650946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.1874650946 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3607446661 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 13181425856 ps |
| CPU time | 1616.86 seconds |
| Started | Jul 27 08:12:40 PM PDT 24 |
| Finished | Jul 27 08:39:37 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-92415f05-d1d6-4a88-aa62-d5e9a5a55767 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607446661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3607446661 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3440488605 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4765976642 ps |
| CPU time | 221.41 seconds |
| Started | Jul 27 08:49:53 PM PDT 24 |
| Finished | Jul 27 08:53:34 PM PDT 24 |
| Peak memory | 641432 kb |
| Host | smart-16c60649-bbc6-40ee-be9a-f0f9952bc3eb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440488605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.3440488605 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1697843367 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2806983018 ps |
| CPU time | 272.11 seconds |
| Started | Jul 27 07:54:30 PM PDT 24 |
| Finished | Jul 27 07:59:02 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-bd7f7f95-d732-41fe-955d-d623b20c2f75 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697 843367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.1697843367 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.263899210 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 13846915600 ps |
| CPU time | 1691.87 seconds |
| Started | Jul 27 07:44:30 PM PDT 24 |
| Finished | Jul 27 08:12:42 PM PDT 24 |
| Peak memory | 608336 kb |
| Host | smart-8510a318-52cb-42bd-abc6-52a4377b6c5e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263899210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.263899210 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1145087368 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 5298060996 ps |
| CPU time | 801.19 seconds |
| Started | Jul 27 07:51:47 PM PDT 24 |
| Finished | Jul 27 08:05:09 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-93bb6c05-72c3-48a3-b42f-a1c63c52613e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1145087368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1145087368 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.30311029 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 22835964986 ps |
| CPU time | 2031.98 seconds |
| Started | Jul 27 07:54:41 PM PDT 24 |
| Finished | Jul 27 08:28:34 PM PDT 24 |
| Peak memory | 615500 kb |
| Host | smart-79502b63-f6f4-4d51-a911-d3062e33b0e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.30311029 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3166783971 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 13357646504 ps |
| CPU time | 1418.46 seconds |
| Started | Jul 27 08:07:03 PM PDT 24 |
| Finished | Jul 27 08:30:42 PM PDT 24 |
| Peak memory | 603248 kb |
| Host | smart-b24bebba-3567-498e-8fdf-d52073de12c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166783971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3166783971 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3579044649 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 12355483666 ps |
| CPU time | 685.78 seconds |
| Started | Jul 27 08:49:30 PM PDT 24 |
| Finished | Jul 27 09:00:56 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-b248ba47-5b78-471e-9eb0-7766364a2c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579044649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3579044649 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3236029912 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6714793640 ps |
| CPU time | 837.65 seconds |
| Started | Jul 27 08:12:17 PM PDT 24 |
| Finished | Jul 27 08:26:15 PM PDT 24 |
| Peak memory | 611540 kb |
| Host | smart-16f1bab1-5127-4c98-9add-b25b54f635e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236029912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3236029912 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3425693506 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4946839400 ps |
| CPU time | 553.29 seconds |
| Started | Jul 27 07:55:02 PM PDT 24 |
| Finished | Jul 27 08:04:15 PM PDT 24 |
| Peak memory | 611852 kb |
| Host | smart-cc8e9059-fc74-4b19-b790-4c6f31d516e1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3425693506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3425693506 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.148173828 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 10010263072 ps |
| CPU time | 419.45 seconds |
| Started | Jul 27 08:32:23 PM PDT 24 |
| Finished | Jul 27 08:39:23 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-e6b1d6d5-8d7a-4748-8602-d6f88567dc4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148173828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.148173828 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1063447882 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3693487038 ps |
| CPU time | 347.03 seconds |
| Started | Jul 27 07:53:09 PM PDT 24 |
| Finished | Jul 27 07:58:56 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-19dde0cc-fd13-48b3-a878-66bbc205b7ea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063 447882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1063447882 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.146106767 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 4268053179 ps |
| CPU time | 317.46 seconds |
| Started | Jul 27 08:25:17 PM PDT 24 |
| Finished | Jul 27 08:30:34 PM PDT 24 |
| Peak memory | 603316 kb |
| Host | smart-cbd5a516-05ae-4823-b64d-9a7ce6c1f682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146106767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.146106767 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2025298083 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5386439487 ps |
| CPU time | 480.51 seconds |
| Started | Jul 27 07:54:31 PM PDT 24 |
| Finished | Jul 27 08:02:32 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-62842a08-da1d-4651-8b3c-aecae1bb7d83 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 25298083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2025298083 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4047609159 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 12466777712 ps |
| CPU time | 1772.5 seconds |
| Started | Jul 27 08:10:32 PM PDT 24 |
| Finished | Jul 27 08:40:05 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-4e9a6b8a-1592-4878-8632-62dcdb7471b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=4047609159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.4047609159 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2609469950 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 43315658937 ps |
| CPU time | 5459.44 seconds |
| Started | Jul 27 08:09:46 PM PDT 24 |
| Finished | Jul 27 09:40:47 PM PDT 24 |
| Peak memory | 622532 kb |
| Host | smart-385facde-b008-4919-8009-0b6ae6bf52f5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2609469950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2609469950 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.1650997135 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4534211614 ps |
| CPU time | 665.02 seconds |
| Started | Jul 27 08:24:48 PM PDT 24 |
| Finished | Jul 27 08:35:54 PM PDT 24 |
| Peak memory | 650544 kb |
| Host | smart-d9769478-38f6-4a67-ad83-24eddeb95765 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1650997135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1650997135 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.632756921 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 9608065150 ps |
| CPU time | 683.03 seconds |
| Started | Jul 27 08:37:16 PM PDT 24 |
| Finished | Jul 27 08:48:40 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-fae7ffa3-5e9b-4dff-9ea0-7e69b863a101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632756921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_ with_rand_reset.632756921 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3485708318 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4045842400 ps |
| CPU time | 431.71 seconds |
| Started | Jul 27 08:29:07 PM PDT 24 |
| Finished | Jul 27 08:36:19 PM PDT 24 |
| Peak memory | 649420 kb |
| Host | smart-085e8323-9467-4cbc-ac2e-14819c8cf429 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485708318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3485708318 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1627335529 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3423947587 ps |
| CPU time | 292.99 seconds |
| Started | Jul 27 08:10:36 PM PDT 24 |
| Finished | Jul 27 08:15:29 PM PDT 24 |
| Peak memory | 618436 kb |
| Host | smart-b2dea892-4fe9-4169-8955-754d53d260b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627335529 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.1627335529 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.501754251 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5730592868 ps |
| CPU time | 758.67 seconds |
| Started | Jul 27 08:23:55 PM PDT 24 |
| Finished | Jul 27 08:36:34 PM PDT 24 |
| Peak memory | 650736 kb |
| Host | smart-d5f643e4-d279-4f45-b10b-30e432ca7b3c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 501754251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.501754251 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.224785518 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5636352908 ps |
| CPU time | 690.39 seconds |
| Started | Jul 27 08:26:11 PM PDT 24 |
| Finished | Jul 27 08:37:42 PM PDT 24 |
| Peak memory | 650488 kb |
| Host | smart-ea61afc7-ab70-46b4-8c3a-cfb70b344bf9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 224785518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.224785518 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1052935063 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3323379000 ps |
| CPU time | 512.06 seconds |
| Started | Jul 27 08:23:57 PM PDT 24 |
| Finished | Jul 27 08:32:30 PM PDT 24 |
| Peak memory | 649912 kb |
| Host | smart-38bcc9d7-6714-4df7-8452-3f054c7501db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052935063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1052935063 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1175970340 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 8024543659 ps |
| CPU time | 441.97 seconds |
| Started | Jul 27 08:26:11 PM PDT 24 |
| Finished | Jul 27 08:33:33 PM PDT 24 |
| Peak memory | 662764 kb |
| Host | smart-f204f968-7785-4c79-8fed-7a123e343de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175970340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1175970340 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4089177382 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 4847043594 ps |
| CPU time | 745.97 seconds |
| Started | Jul 27 07:55:37 PM PDT 24 |
| Finished | Jul 27 08:08:03 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-20e405a9-44b4-4f87-b1d2-7791612742c1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4089177382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.4089177382 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1506769989 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 6273126806 ps |
| CPU time | 1260.74 seconds |
| Started | Jul 27 08:14:39 PM PDT 24 |
| Finished | Jul 27 08:35:41 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-36d41519-2080-4872-b802-537f9130e509 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506769989 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1506769989 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2590188383 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4934545800 ps |
| CPU time | 681.45 seconds |
| Started | Jul 27 08:29:11 PM PDT 24 |
| Finished | Jul 27 08:40:32 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-bd81380d-d574-4284-8cb7-b3ed8557cf73 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2590188383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2590188383 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1025277811 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 7243043418 ps |
| CPU time | 544.53 seconds |
| Started | Jul 27 08:05:36 PM PDT 24 |
| Finished | Jul 27 08:14:41 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-de368261-2379-47a0-8b69-00d1b944e6bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10252778 11 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1025277811 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.535049802 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 6527411851 ps |
| CPU time | 845.16 seconds |
| Started | Jul 27 08:36:01 PM PDT 24 |
| Finished | Jul 27 08:50:07 PM PDT 24 |
| Peak memory | 576852 kb |
| Host | smart-5d74386a-bc51-48a4-8a44-8ed72fe364f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535049802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.535049802 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3333442603 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 9048120960 ps |
| CPU time | 1985.46 seconds |
| Started | Jul 27 08:21:09 PM PDT 24 |
| Finished | Jul 27 08:54:15 PM PDT 24 |
| Peak memory | 622968 kb |
| Host | smart-79d5d3e5-bbb0-413e-a17f-1109ecbf1797 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3333442603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3333442603 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2863950941 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 31737616566 ps |
| CPU time | 7485.86 seconds |
| Started | Jul 27 07:52:53 PM PDT 24 |
| Finished | Jul 27 09:57:41 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-e9b6995e-d078-496c-b9b0-5228e5ae0311 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2863950941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2863950941 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4289141452 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3117451942 ps |
| CPU time | 323.68 seconds |
| Started | Jul 27 07:53:02 PM PDT 24 |
| Finished | Jul 27 07:58:26 PM PDT 24 |
| Peak memory | 622272 kb |
| Host | smart-afa89474-1352-4ff1-a290-e04066cad605 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42891414 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.4289141452 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3571784179 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3593440080 ps |
| CPU time | 262.57 seconds |
| Started | Jul 27 07:55:05 PM PDT 24 |
| Finished | Jul 27 07:59:28 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-0bb0dcf3-2f5b-4d7b-ac51-d48c18a18817 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571784179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3571784179 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1441576750 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6932480693 ps |
| CPU time | 686.6 seconds |
| Started | Jul 27 08:19:48 PM PDT 24 |
| Finished | Jul 27 08:31:15 PM PDT 24 |
| Peak memory | 631320 kb |
| Host | smart-4bebc4da-93b3-4ac6-b79e-c5541ca201d6 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441576750 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1441576750 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2976898825 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4599476495 ps |
| CPU time | 644.47 seconds |
| Started | Jul 27 08:34:55 PM PDT 24 |
| Finished | Jul 27 08:45:40 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-9e35d1b2-55b9-47e2-aeff-b47b6d778b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976898825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2976898825 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.399462595 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 44436118920 ps |
| CPU time | 5915.97 seconds |
| Started | Jul 27 07:54:52 PM PDT 24 |
| Finished | Jul 27 09:33:30 PM PDT 24 |
| Peak memory | 622528 kb |
| Host | smart-b0c438ea-8f41-44bb-be46-873c948d59f9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=399462595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.399462595 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1712448850 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 4893409566 ps |
| CPU time | 392.2 seconds |
| Started | Jul 27 08:29:08 PM PDT 24 |
| Finished | Jul 27 08:35:40 PM PDT 24 |
| Peak memory | 598232 kb |
| Host | smart-2ca7298e-b815-4112-a351-c4471d1c9f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712448850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1712448850 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2795144638 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 20236964978 ps |
| CPU time | 3083.64 seconds |
| Started | Jul 27 07:58:53 PM PDT 24 |
| Finished | Jul 27 08:50:17 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-c55daf07-8be2-4ee8-837f-4064c13eb25b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795144638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2795144638 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3513102455 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 29131300102 ps |
| CPU time | 3293.69 seconds |
| Started | Jul 27 08:31:39 PM PDT 24 |
| Finished | Jul 27 09:26:33 PM PDT 24 |
| Peak memory | 593076 kb |
| Host | smart-3443c3ad-9f66-460b-971e-42591123c41e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513102455 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3513102455 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.110331953 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 6497807760 ps |
| CPU time | 1449.08 seconds |
| Started | Jul 27 07:57:30 PM PDT 24 |
| Finished | Jul 27 08:21:40 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-22b2eb28-11bd-4e87-b5f6-51b9c05384e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110331953 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.110331953 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1149565425 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 8049156451 ps |
| CPU time | 1549.79 seconds |
| Started | Jul 27 08:18:53 PM PDT 24 |
| Finished | Jul 27 08:44:43 PM PDT 24 |
| Peak memory | 625304 kb |
| Host | smart-d8020b6b-cf40-4714-9f54-ebc547d920c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149565425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1149565425 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.3734805263 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4595970372 ps |
| CPU time | 739.51 seconds |
| Started | Jul 27 07:53:00 PM PDT 24 |
| Finished | Jul 27 08:05:20 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-1f5bff7d-4159-4d62-ab4c-3d13205f8a59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734805263 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.3734805263 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.48166992 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2349989297 ps |
| CPU time | 376.13 seconds |
| Started | Jul 27 08:29:36 PM PDT 24 |
| Finished | Jul 27 08:35:52 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-2001fa4d-c156-4116-9f0f-37d3bca6ba1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48166992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_wi th_rand_reset.48166992 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1485555549 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4173848616 ps |
| CPU time | 324.02 seconds |
| Started | Jul 27 07:52:19 PM PDT 24 |
| Finished | Jul 27 07:57:43 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-e2b070e7-2c75-40d0-87f4-4257bdfe64e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485555549 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1485555549 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2319119214 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3341542300 ps |
| CPU time | 305.7 seconds |
| Started | Jul 27 08:10:02 PM PDT 24 |
| Finished | Jul 27 08:15:09 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-863146b6-67fb-4158-95c6-a61b9935e2c2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319119214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2319119214 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3176811824 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8632144240 ps |
| CPU time | 633.23 seconds |
| Started | Jul 27 08:05:14 PM PDT 24 |
| Finished | Jul 27 08:15:48 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-b8f66abb-494a-455d-909f-b74fef46297a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176811824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.3176811824 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.2187533597 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3954151203 ps |
| CPU time | 302.69 seconds |
| Started | Jul 27 08:35:17 PM PDT 24 |
| Finished | Jul 27 08:40:20 PM PDT 24 |
| Peak memory | 598372 kb |
| Host | smart-8e79e689-fd35-4d95-9f9f-d5101809a328 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187533597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.2187533597 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.863631748 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 16197127707 ps |
| CPU time | 718.08 seconds |
| Started | Jul 27 08:42:17 PM PDT 24 |
| Finished | Jul 27 08:54:15 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-0eb32b8f-cbef-4f7e-82cb-891b915ed9e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863631748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_reset_error.863631748 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4252932154 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 6864534560 ps |
| CPU time | 822.96 seconds |
| Started | Jul 27 07:58:39 PM PDT 24 |
| Finished | Jul 27 08:12:22 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-bf68cb06-a082-4c43-84de-4223db4cb804 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42529321 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.4252932154 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3234057114 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6583597832 ps |
| CPU time | 530.15 seconds |
| Started | Jul 27 08:16:35 PM PDT 24 |
| Finished | Jul 27 08:25:26 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-e938aaf0-3aa5-4307-95d1-2de73f5d3df5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32340571 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3234057114 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1941824516 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 743942395 ps |
| CPU time | 164.59 seconds |
| Started | Jul 27 08:35:20 PM PDT 24 |
| Finished | Jul 27 08:38:05 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-039599b5-6949-4592-9eff-70387ea55ce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941824516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.1941824516 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.561727190 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 14942107060 ps |
| CPU time | 637.16 seconds |
| Started | Jul 27 08:44:09 PM PDT 24 |
| Finished | Jul 27 08:54:46 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-be20ce4b-5656-4575-9de4-c77585442db9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561727190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.561727190 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3701901698 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4207841190 ps |
| CPU time | 637.48 seconds |
| Started | Jul 27 07:55:28 PM PDT 24 |
| Finished | Jul 27 08:06:06 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-ace2699b-bd4d-4b2a-8264-c7b4c1deb128 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701901698 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3701901698 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3793052398 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2902748249 ps |
| CPU time | 220.75 seconds |
| Started | Jul 27 08:01:16 PM PDT 24 |
| Finished | Jul 27 08:04:58 PM PDT 24 |
| Peak memory | 623436 kb |
| Host | smart-05baba48-ef7d-4610-91c0-621982fff40b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793052398 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3793052398 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.2636130449 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 5045413288 ps |
| CPU time | 821.04 seconds |
| Started | Jul 27 08:13:46 PM PDT 24 |
| Finished | Jul 27 08:27:27 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-76166e8b-1e19-4981-b277-5d504f32ccd6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636130449 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2636130449 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.847085343 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 45210379364 ps |
| CPU time | 5078.81 seconds |
| Started | Jul 27 07:56:10 PM PDT 24 |
| Finished | Jul 27 09:20:50 PM PDT 24 |
| Peak memory | 621560 kb |
| Host | smart-007f50bf-2576-41bf-860c-5ad7c97332e8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=847085343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.847085343 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.611816596 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4326136329 ps |
| CPU time | 308.02 seconds |
| Started | Jul 27 08:14:41 PM PDT 24 |
| Finished | Jul 27 08:19:50 PM PDT 24 |
| Peak memory | 622792 kb |
| Host | smart-1d13cc2e-e78e-42a1-a7bc-ec068bc1d686 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=611816596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.611816596 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.159123687 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 157106643658 ps |
| CPU time | 22554.9 seconds |
| Started | Jul 27 08:17:18 PM PDT 24 |
| Finished | Jul 28 02:33:15 AM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-56b37671-fd88-4ba2-9166-4592d5631748 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=159123687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.159123687 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1811898132 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 4327678798 ps |
| CPU time | 311.43 seconds |
| Started | Jul 27 08:36:16 PM PDT 24 |
| Finished | Jul 27 08:41:28 PM PDT 24 |
| Peak memory | 598360 kb |
| Host | smart-fbe2001e-3049-4ef2-a314-cc8b7e9c2888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811898132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1811898132 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.61470266 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 4226099310 ps |
| CPU time | 612.31 seconds |
| Started | Jul 27 07:52:35 PM PDT 24 |
| Finished | Jul 27 08:02:47 PM PDT 24 |
| Peak memory | 625352 kb |
| Host | smart-90153e65-f6a0-4f4e-bbde-d8ce3c002232 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61470266 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.61470266 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.468472943 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4218029244 ps |
| CPU time | 661.18 seconds |
| Started | Jul 27 07:51:07 PM PDT 24 |
| Finished | Jul 27 08:02:08 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-943ab43b-0c6c-401c-bde9-413371be7d0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468472943 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.468472943 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.774414137 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4212801352 ps |
| CPU time | 625.91 seconds |
| Started | Jul 27 08:04:40 PM PDT 24 |
| Finished | Jul 27 08:15:06 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-4f6cc9c3-1b55-478c-ba47-6b6a8d806269 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774414137 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.774414137 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2980310174 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3559837020 ps |
| CPU time | 617.39 seconds |
| Started | Jul 27 07:55:50 PM PDT 24 |
| Finished | Jul 27 08:06:08 PM PDT 24 |
| Peak memory | 613612 kb |
| Host | smart-7c89c453-2d2d-4fbb-8c0f-a4ea29e038ea |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980310174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2980310174 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.3160380803 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4826796100 ps |
| CPU time | 572.76 seconds |
| Started | Jul 27 08:23:22 PM PDT 24 |
| Finished | Jul 27 08:32:55 PM PDT 24 |
| Peak memory | 650872 kb |
| Host | smart-c23f2e7d-1df4-4115-a2b3-cd2093904274 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3160380803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3160380803 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1637978484 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 9609087413 ps |
| CPU time | 395.48 seconds |
| Started | Jul 27 08:32:57 PM PDT 24 |
| Finished | Jul 27 08:39:33 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-ecfae3f5-a795-41d3-a569-b9f4accbacde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637978484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1637978484 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1368834475 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 9013198603 ps |
| CPU time | 396.54 seconds |
| Started | Jul 27 08:33:24 PM PDT 24 |
| Finished | Jul 27 08:40:00 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-1e6ce2d8-a583-456c-a8bf-ad2624b98afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368834475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.1368834475 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3197533733 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3457690936 ps |
| CPU time | 461.62 seconds |
| Started | Jul 27 07:53:07 PM PDT 24 |
| Finished | Jul 27 08:00:49 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-08731688-2bce-43bf-a2de-cfa9753fa24f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319753 3733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3197533733 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2732466538 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2706895133 ps |
| CPU time | 285.66 seconds |
| Started | Jul 27 08:36:00 PM PDT 24 |
| Finished | Jul 27 08:40:45 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-45c7a58a-e0f3-45d2-9513-4d66ebbafa2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732466538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2732466538 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3023593464 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 48853653590 ps |
| CPU time | 6050.93 seconds |
| Started | Jul 27 08:11:05 PM PDT 24 |
| Finished | Jul 27 09:51:57 PM PDT 24 |
| Peak memory | 623268 kb |
| Host | smart-2f6e584c-8ad0-4356-8e40-a85d7e403717 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023593464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.3023593464 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.4030775644 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 545667983 ps |
| CPU time | 138.25 seconds |
| Started | Jul 27 08:24:49 PM PDT 24 |
| Finished | Jul 27 08:27:07 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-59f04350-5b35-4119-a5a8-dd051b6f5696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030775644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.4030775644 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.2946900180 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5250144795 ps |
| CPU time | 535.51 seconds |
| Started | Jul 27 08:29:36 PM PDT 24 |
| Finished | Jul 27 08:38:32 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-a4d8be31-4612-4323-9512-3d58108eeb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946900180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2946900180 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1877249204 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 7500156912 ps |
| CPU time | 504.09 seconds |
| Started | Jul 27 08:46:09 PM PDT 24 |
| Finished | Jul 27 08:54:33 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-659bd2d8-2345-4b96-9b16-d5f5ab983c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877249204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1877249204 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.238795854 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3692404020 ps |
| CPU time | 458.18 seconds |
| Started | Jul 27 07:59:02 PM PDT 24 |
| Finished | Jul 27 08:06:41 PM PDT 24 |
| Peak memory | 621716 kb |
| Host | smart-a5567148-ecfb-49f2-a290-8c675e280455 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238795 854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.238795854 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.681167518 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 51090269762 ps |
| CPU time | 5078.57 seconds |
| Started | Jul 27 07:55:20 PM PDT 24 |
| Finished | Jul 27 09:19:59 PM PDT 24 |
| Peak memory | 622000 kb |
| Host | smart-6e96e16d-ab53-448e-85ab-9066d43a8bab |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681167518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.681167518 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4221800302 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3724092910 ps |
| CPU time | 414.4 seconds |
| Started | Jul 27 07:53:16 PM PDT 24 |
| Finished | Jul 27 08:00:10 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-f6c593b0-dd30-4287-8f2d-28a763c6e365 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221800302 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.4221800302 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.889164347 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5664446086 ps |
| CPU time | 672.08 seconds |
| Started | Jul 27 08:27:18 PM PDT 24 |
| Finished | Jul 27 08:38:31 PM PDT 24 |
| Peak memory | 650568 kb |
| Host | smart-0973a926-4eb5-47da-87af-b0aed00a590c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 889164347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.889164347 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2838247095 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2955947880 ps |
| CPU time | 290.12 seconds |
| Started | Jul 27 07:53:12 PM PDT 24 |
| Finished | Jul 27 07:58:03 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-90369ef5-875e-4828-9f5b-b4c6c4e39afb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838247095 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2838247095 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.349462388 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3520880760 ps |
| CPU time | 277.51 seconds |
| Started | Jul 27 07:53:45 PM PDT 24 |
| Finished | Jul 27 07:58:23 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-393e07a9-bda6-4ba7-bc84-b8df48cd8531 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349462388 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.349462388 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1178272756 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10304592126 ps |
| CPU time | 998 seconds |
| Started | Jul 27 08:38:06 PM PDT 24 |
| Finished | Jul 27 08:54:44 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-7393cb57-f2fb-4d72-a49b-f3c00ab28bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178272756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.1178272756 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1405753334 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 9250863996 ps |
| CPU time | 825.63 seconds |
| Started | Jul 27 08:49:48 PM PDT 24 |
| Finished | Jul 27 09:03:34 PM PDT 24 |
| Peak memory | 582756 kb |
| Host | smart-27e3b7dd-4624-4c74-a527-120d61037a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405753334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1405753334 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.1407585142 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 4904005160 ps |
| CPU time | 898.97 seconds |
| Started | Jul 27 08:27:45 PM PDT 24 |
| Finished | Jul 27 08:42:45 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-ade13747-b81e-4c81-bb14-3c413a174b2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1407585142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1407585142 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3262870534 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 7515784212 ps |
| CPU time | 977.07 seconds |
| Started | Jul 27 07:55:00 PM PDT 24 |
| Finished | Jul 27 08:11:17 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-fcd4d6ef-ecbd-4f25-87c8-b043924ad19b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262870534 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3262870534 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749822168 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3476358924 ps |
| CPU time | 501.36 seconds |
| Started | Jul 27 07:55:19 PM PDT 24 |
| Finished | Jul 27 08:03:41 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-b459113b-367c-43a5-a07d-5dfadf5ff367 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749822168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.3749822168 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3716246262 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5552080240 ps |
| CPU time | 531.05 seconds |
| Started | Jul 27 07:52:18 PM PDT 24 |
| Finished | Jul 27 08:01:10 PM PDT 24 |
| Peak memory | 650768 kb |
| Host | smart-0ca05c05-4b63-4406-8d04-b6d84701c11f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3716246262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3716246262 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1336279941 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3616803016 ps |
| CPU time | 386.98 seconds |
| Started | Jul 27 08:00:47 PM PDT 24 |
| Finished | Jul 27 08:07:14 PM PDT 24 |
| Peak memory | 649376 kb |
| Host | smart-afbaabe9-5cd8-4050-b342-caf916fb379c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336279941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1336279941 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1527653964 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6279519600 ps |
| CPU time | 642.59 seconds |
| Started | Jul 27 07:54:21 PM PDT 24 |
| Finished | Jul 27 08:05:04 PM PDT 24 |
| Peak memory | 650272 kb |
| Host | smart-f47567a6-abdd-4865-b8e6-2f4ff24cc0f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1527653964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1527653964 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1047052795 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4140596760 ps |
| CPU time | 413.11 seconds |
| Started | Jul 27 08:22:44 PM PDT 24 |
| Finished | Jul 27 08:29:38 PM PDT 24 |
| Peak memory | 649432 kb |
| Host | smart-55be8861-5a47-403d-b5b1-1619d49af557 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047052795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1047052795 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.4235354687 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4730468848 ps |
| CPU time | 477.58 seconds |
| Started | Jul 27 08:21:14 PM PDT 24 |
| Finished | Jul 27 08:29:11 PM PDT 24 |
| Peak memory | 650504 kb |
| Host | smart-30f935c9-7b2b-4ee3-affb-f8a7dc6b7001 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4235354687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.4235354687 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2592265249 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3160274206 ps |
| CPU time | 364.92 seconds |
| Started | Jul 27 08:28:55 PM PDT 24 |
| Finished | Jul 27 08:35:00 PM PDT 24 |
| Peak memory | 649700 kb |
| Host | smart-f9cbb4d4-02f8-40ac-83d6-208246c5cab1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592265249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2592265249 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187663959 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4148899658 ps |
| CPU time | 412.37 seconds |
| Started | Jul 27 08:21:42 PM PDT 24 |
| Finished | Jul 27 08:28:34 PM PDT 24 |
| Peak memory | 649284 kb |
| Host | smart-6f1a9843-9bad-41ef-97e4-ebbc2383e565 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187663959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4187663959 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.2765841014 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5217909260 ps |
| CPU time | 613.48 seconds |
| Started | Jul 27 08:29:12 PM PDT 24 |
| Finished | Jul 27 08:39:26 PM PDT 24 |
| Peak memory | 650300 kb |
| Host | smart-b50d7c09-92cc-4341-a077-a8a47ff0cc1e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2765841014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.2765841014 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2922460113 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3711990680 ps |
| CPU time | 466.53 seconds |
| Started | Jul 27 08:22:28 PM PDT 24 |
| Finished | Jul 27 08:30:15 PM PDT 24 |
| Peak memory | 649428 kb |
| Host | smart-680088ec-6cc1-4c27-8cc0-de88bf55f13c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922460113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2922460113 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.335774523 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5569165500 ps |
| CPU time | 744.67 seconds |
| Started | Jul 27 08:23:28 PM PDT 24 |
| Finished | Jul 27 08:35:53 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-a33795b4-b866-457b-89b6-5859d4fa609b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 335774523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.335774523 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.2734905771 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5245975552 ps |
| CPU time | 652.51 seconds |
| Started | Jul 27 08:23:19 PM PDT 24 |
| Finished | Jul 27 08:34:12 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-cba155c1-3ad9-4b1e-ba70-8cbfa5426a25 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2734905771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.2734905771 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1960836844 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 3601605558 ps |
| CPU time | 422.33 seconds |
| Started | Jul 27 08:24:48 PM PDT 24 |
| Finished | Jul 27 08:31:51 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-11b0eab5-151b-470f-8fc4-224f2d195015 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960836844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1960836844 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.684232308 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 4052774858 ps |
| CPU time | 505.91 seconds |
| Started | Jul 27 08:11:12 PM PDT 24 |
| Finished | Jul 27 08:19:38 PM PDT 24 |
| Peak memory | 649540 kb |
| Host | smart-5fcd22ab-9dea-4332-a370-848903cb1b73 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684232308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.684232308 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.84578467 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 5929780078 ps |
| CPU time | 626.35 seconds |
| Started | Jul 27 08:14:11 PM PDT 24 |
| Finished | Jul 27 08:24:37 PM PDT 24 |
| Peak memory | 650532 kb |
| Host | smart-c050fbee-8249-429a-a186-31999b4f5cbb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 84578467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.84578467 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1807440344 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3188395264 ps |
| CPU time | 421.84 seconds |
| Started | Jul 27 08:26:26 PM PDT 24 |
| Finished | Jul 27 08:33:28 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-628acdf6-f5b3-47d3-bfdd-87896d6fd2b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807440344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1807440344 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.3567098224 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 6136432648 ps |
| CPU time | 631.97 seconds |
| Started | Jul 27 08:26:17 PM PDT 24 |
| Finished | Jul 27 08:36:49 PM PDT 24 |
| Peak memory | 650512 kb |
| Host | smart-11fc87b2-97a0-4f5d-a4b1-05344ceaecff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3567098224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3567098224 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161447240 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4167677072 ps |
| CPU time | 483.09 seconds |
| Started | Jul 27 08:23:23 PM PDT 24 |
| Finished | Jul 27 08:31:27 PM PDT 24 |
| Peak memory | 649508 kb |
| Host | smart-c61b2c79-d10d-4adc-896c-2ab1b8fa2c6f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161447240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3161447240 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.2046625241 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 5848995792 ps |
| CPU time | 698.69 seconds |
| Started | Jul 27 08:23:31 PM PDT 24 |
| Finished | Jul 27 08:35:10 PM PDT 24 |
| Peak memory | 650480 kb |
| Host | smart-5cf62f87-8591-44c9-9a1c-004710bd55ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2046625241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2046625241 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2991056519 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 4146055672 ps |
| CPU time | 455.33 seconds |
| Started | Jul 27 08:24:05 PM PDT 24 |
| Finished | Jul 27 08:31:41 PM PDT 24 |
| Peak memory | 649540 kb |
| Host | smart-2a2dc98e-3976-45d3-aaa6-27a6ddc78c9b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991056519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2991056519 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890938157 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3500824134 ps |
| CPU time | 473.22 seconds |
| Started | Jul 27 08:24:19 PM PDT 24 |
| Finished | Jul 27 08:32:12 PM PDT 24 |
| Peak memory | 649028 kb |
| Host | smart-375dab4b-5265-4c92-a40f-272fbaa017f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890938157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2890938157 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3302831828 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3435788180 ps |
| CPU time | 353.94 seconds |
| Started | Jul 27 08:23:30 PM PDT 24 |
| Finished | Jul 27 08:29:25 PM PDT 24 |
| Peak memory | 649676 kb |
| Host | smart-88b2e630-204c-404e-901a-1a177e2d4d3a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302831828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3302831828 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.1850560184 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6609866566 ps |
| CPU time | 795.79 seconds |
| Started | Jul 27 08:24:55 PM PDT 24 |
| Finished | Jul 27 08:38:11 PM PDT 24 |
| Peak memory | 650792 kb |
| Host | smart-337965e5-adcb-4238-823f-4f695d6908fd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1850560184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.1850560184 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599925417 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3722653920 ps |
| CPU time | 357.15 seconds |
| Started | Jul 27 08:23:11 PM PDT 24 |
| Finished | Jul 27 08:29:08 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-943704b4-c9ef-46fb-88af-2b8626fe4436 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599925417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1599925417 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.770187161 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5200962236 ps |
| CPU time | 762.35 seconds |
| Started | Jul 27 08:24:23 PM PDT 24 |
| Finished | Jul 27 08:37:06 PM PDT 24 |
| Peak memory | 650604 kb |
| Host | smart-d8bc927f-485a-4936-926e-ec72cfbfe7d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 770187161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.770187161 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.525101389 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3377332840 ps |
| CPU time | 496.87 seconds |
| Started | Jul 27 08:24:48 PM PDT 24 |
| Finished | Jul 27 08:33:05 PM PDT 24 |
| Peak memory | 649356 kb |
| Host | smart-418b3053-616f-4faf-87bd-d6fc6d5e224a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525101389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.525101389 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3431680873 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5885729736 ps |
| CPU time | 594.43 seconds |
| Started | Jul 27 08:23:19 PM PDT 24 |
| Finished | Jul 27 08:33:14 PM PDT 24 |
| Peak memory | 650600 kb |
| Host | smart-e70b2ade-02c8-4a05-b925-df94112f0017 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3431680873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3431680873 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3139493282 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5320790680 ps |
| CPU time | 580.69 seconds |
| Started | Jul 27 08:18:53 PM PDT 24 |
| Finished | Jul 27 08:28:34 PM PDT 24 |
| Peak memory | 650196 kb |
| Host | smart-5f57efdf-8120-4969-bb8f-41a876e2c0b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3139493282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3139493282 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2464770891 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3103708468 ps |
| CPU time | 412.11 seconds |
| Started | Jul 27 08:23:24 PM PDT 24 |
| Finished | Jul 27 08:30:17 PM PDT 24 |
| Peak memory | 649464 kb |
| Host | smart-31f203c7-8474-453c-88fe-56c7a04cbcab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464770891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2464770891 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.2574225040 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 6200192292 ps |
| CPU time | 703.95 seconds |
| Started | Jul 27 08:27:34 PM PDT 24 |
| Finished | Jul 27 08:39:18 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-ae4ea1a3-1f06-4f31-8a74-3d954ca57723 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2574225040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2574225040 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.146029385 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3898023660 ps |
| CPU time | 471.19 seconds |
| Started | Jul 27 08:27:42 PM PDT 24 |
| Finished | Jul 27 08:35:33 PM PDT 24 |
| Peak memory | 649068 kb |
| Host | smart-15b34a4e-0932-4ab6-b34c-78f5aea2323f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146029385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.146029385 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489578711 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3425641530 ps |
| CPU time | 340.17 seconds |
| Started | Jul 27 08:25:24 PM PDT 24 |
| Finished | Jul 27 08:31:05 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-208e7f5d-0abf-4fb9-bf1d-b53a9fcf5ed7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489578711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3489578711 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176399169 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3556824540 ps |
| CPU time | 395.73 seconds |
| Started | Jul 27 08:26:23 PM PDT 24 |
| Finished | Jul 27 08:32:59 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-1cf789f3-fef0-4cbb-b91e-31387065a2c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176399169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3176399169 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.1681310333 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5416023420 ps |
| CPU time | 569.56 seconds |
| Started | Jul 27 08:24:18 PM PDT 24 |
| Finished | Jul 27 08:33:47 PM PDT 24 |
| Peak memory | 650604 kb |
| Host | smart-039702bc-f90e-4e70-833a-eddade7144bd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1681310333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.1681310333 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3208341464 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3922134836 ps |
| CPU time | 502.38 seconds |
| Started | Jul 27 08:24:32 PM PDT 24 |
| Finished | Jul 27 08:32:55 PM PDT 24 |
| Peak memory | 649452 kb |
| Host | smart-0f70fe3c-13c9-4270-9441-7cd390c41733 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208341464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3208341464 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3752614319 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 5499029400 ps |
| CPU time | 808.59 seconds |
| Started | Jul 27 08:25:44 PM PDT 24 |
| Finished | Jul 27 08:39:13 PM PDT 24 |
| Peak memory | 650496 kb |
| Host | smart-eaeca592-1731-4e43-a18d-98d85ccf191e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3752614319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3752614319 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531055575 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 3666466736 ps |
| CPU time | 414.93 seconds |
| Started | Jul 27 08:25:57 PM PDT 24 |
| Finished | Jul 27 08:32:52 PM PDT 24 |
| Peak memory | 649548 kb |
| Host | smart-4361cc4b-dd4b-469e-89b7-ea18721af751 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531055575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1531055575 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1164924023 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3560235760 ps |
| CPU time | 467.14 seconds |
| Started | Jul 27 08:27:41 PM PDT 24 |
| Finished | Jul 27 08:35:29 PM PDT 24 |
| Peak memory | 649108 kb |
| Host | smart-7cc066d4-66bb-4a2a-a1d6-b4d0e9054659 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164924023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1164924023 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3931538308 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4395558160 ps |
| CPU time | 457.13 seconds |
| Started | Jul 27 08:26:20 PM PDT 24 |
| Finished | Jul 27 08:33:57 PM PDT 24 |
| Peak memory | 649688 kb |
| Host | smart-ab96d75a-20d2-435c-a9d0-c028fc6a09c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931538308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3931538308 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340541021 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3785593880 ps |
| CPU time | 400.72 seconds |
| Started | Jul 27 08:25:29 PM PDT 24 |
| Finished | Jul 27 08:32:10 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-171bb8af-64d5-4ae9-8799-068666f6456f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340541021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1340541021 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.3641177728 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 6688886660 ps |
| CPU time | 624.81 seconds |
| Started | Jul 27 08:26:24 PM PDT 24 |
| Finished | Jul 27 08:36:49 PM PDT 24 |
| Peak memory | 650592 kb |
| Host | smart-70ba0801-2759-497e-9ea6-329ee820d7f4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3641177728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3641177728 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1658058801 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 6207706282 ps |
| CPU time | 540.12 seconds |
| Started | Jul 27 08:25:45 PM PDT 24 |
| Finished | Jul 27 08:34:45 PM PDT 24 |
| Peak memory | 650920 kb |
| Host | smart-8a5bd6eb-37d4-40a8-b87f-054e65442a3f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1658058801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1658058801 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2496887032 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3785372880 ps |
| CPU time | 292.75 seconds |
| Started | Jul 27 08:25:56 PM PDT 24 |
| Finished | Jul 27 08:30:49 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-b4865c0c-839d-40f4-8a5f-1c5522f8742a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496887032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2496887032 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.220289893 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4365444656 ps |
| CPU time | 705.07 seconds |
| Started | Jul 27 08:26:37 PM PDT 24 |
| Finished | Jul 27 08:38:22 PM PDT 24 |
| Peak memory | 650600 kb |
| Host | smart-fe9740ac-a677-4d74-bf1a-9372d66e93d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 220289893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.220289893 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025652284 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3355625090 ps |
| CPU time | 395.89 seconds |
| Started | Jul 27 08:26:50 PM PDT 24 |
| Finished | Jul 27 08:33:26 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-9cffceca-7fbd-40a7-b54c-92d47d4dc25d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025652284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3025652284 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.800712355 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3251036088 ps |
| CPU time | 371.31 seconds |
| Started | Jul 27 08:26:39 PM PDT 24 |
| Finished | Jul 27 08:32:51 PM PDT 24 |
| Peak memory | 649720 kb |
| Host | smart-59f2a6d1-62bc-4c4e-b753-1c507375d0f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800712355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s w_alert_handler_lpg_sleep_mode_alerts.800712355 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.1400045856 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5159990000 ps |
| CPU time | 597.78 seconds |
| Started | Jul 27 08:25:50 PM PDT 24 |
| Finished | Jul 27 08:35:48 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-c7a05ff7-06da-4a64-9e01-03837859d72c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1400045856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.1400045856 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1793758669 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4595172454 ps |
| CPU time | 647.72 seconds |
| Started | Jul 27 08:26:17 PM PDT 24 |
| Finished | Jul 27 08:37:05 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-21d209cd-b40a-4829-a587-d76816cad461 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1793758669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1793758669 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3165147473 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3749927952 ps |
| CPU time | 423.78 seconds |
| Started | Jul 27 08:27:12 PM PDT 24 |
| Finished | Jul 27 08:34:16 PM PDT 24 |
| Peak memory | 649180 kb |
| Host | smart-4e3c4408-038e-4949-b22a-bc7f33923153 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165147473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3165147473 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.959535263 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5870178528 ps |
| CPU time | 656.51 seconds |
| Started | Jul 27 08:26:56 PM PDT 24 |
| Finished | Jul 27 08:37:53 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-64790fdd-5775-4920-9cf1-d52d019645a2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 959535263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.959535263 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.928722166 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3933673252 ps |
| CPU time | 398.28 seconds |
| Started | Jul 27 08:27:17 PM PDT 24 |
| Finished | Jul 27 08:33:56 PM PDT 24 |
| Peak memory | 649428 kb |
| Host | smart-a81f67fa-0afd-4454-a77c-a748420fcece |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928722166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_s w_alert_handler_lpg_sleep_mode_alerts.928722166 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.838064290 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5047523488 ps |
| CPU time | 511.87 seconds |
| Started | Jul 27 08:26:54 PM PDT 24 |
| Finished | Jul 27 08:35:26 PM PDT 24 |
| Peak memory | 650540 kb |
| Host | smart-738f4e0b-876b-4141-86b3-a48a1111b759 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 838064290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.838064290 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1467980798 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4939184560 ps |
| CPU time | 768.38 seconds |
| Started | Jul 27 08:27:19 PM PDT 24 |
| Finished | Jul 27 08:40:08 PM PDT 24 |
| Peak memory | 650544 kb |
| Host | smart-c99132d1-b1f5-4ce3-8608-8d5a87afe53c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1467980798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1467980798 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848684805 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3310691110 ps |
| CPU time | 360.05 seconds |
| Started | Jul 27 08:28:25 PM PDT 24 |
| Finished | Jul 27 08:34:26 PM PDT 24 |
| Peak memory | 649792 kb |
| Host | smart-96da8f71-302b-4da8-96c9-187ff77f5f94 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848684805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2848684805 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.1774329001 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5817163552 ps |
| CPU time | 689.98 seconds |
| Started | Jul 27 08:28:16 PM PDT 24 |
| Finished | Jul 27 08:39:47 PM PDT 24 |
| Peak memory | 650276 kb |
| Host | smart-e2b6a4f5-ec2d-4409-ba8e-64eaaf5c12e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1774329001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1774329001 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533723864 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4221928806 ps |
| CPU time | 360.72 seconds |
| Started | Jul 27 08:28:19 PM PDT 24 |
| Finished | Jul 27 08:34:20 PM PDT 24 |
| Peak memory | 649688 kb |
| Host | smart-b38c63c2-0405-4334-9f42-e621a303807e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533723864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2533723864 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2497318799 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3494358472 ps |
| CPU time | 610.81 seconds |
| Started | Jul 27 08:29:29 PM PDT 24 |
| Finished | Jul 27 08:39:40 PM PDT 24 |
| Peak memory | 649364 kb |
| Host | smart-e540b6ba-3311-4900-9377-4a7548e68cb3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497318799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2497318799 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021701512 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4217496040 ps |
| CPU time | 411.5 seconds |
| Started | Jul 27 08:29:31 PM PDT 24 |
| Finished | Jul 27 08:36:23 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-3d09e2fa-4543-40d8-90c4-e158764cab86 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021701512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3021701512 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.1373221744 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 5792971112 ps |
| CPU time | 556.36 seconds |
| Started | Jul 27 08:28:14 PM PDT 24 |
| Finished | Jul 27 08:37:31 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-f09ec298-7f15-44ee-bbcd-0c1ba4627478 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1373221744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.1373221744 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1155495763 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 6585228360 ps |
| CPU time | 768.82 seconds |
| Started | Jul 27 08:29:14 PM PDT 24 |
| Finished | Jul 27 08:42:04 PM PDT 24 |
| Peak memory | 650880 kb |
| Host | smart-833a4329-e3c7-401c-8a1e-5a06cd0a50c2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1155495763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1155495763 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233857879 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3083125272 ps |
| CPU time | 423.03 seconds |
| Started | Jul 27 08:30:43 PM PDT 24 |
| Finished | Jul 27 08:37:46 PM PDT 24 |
| Peak memory | 649440 kb |
| Host | smart-69775625-796f-4570-ac1e-9169202c42b5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233857879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3233857879 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1132880303 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3466967750 ps |
| CPU time | 348.81 seconds |
| Started | Jul 27 08:29:34 PM PDT 24 |
| Finished | Jul 27 08:35:22 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-536bbcf5-752e-4d60-9b59-2fffb6ea0d6e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132880303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1132880303 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.3207531644 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4917131688 ps |
| CPU time | 635.66 seconds |
| Started | Jul 27 08:30:16 PM PDT 24 |
| Finished | Jul 27 08:40:52 PM PDT 24 |
| Peak memory | 650740 kb |
| Host | smart-9db0b5bb-c280-452a-bc80-a9b9d874f7bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3207531644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3207531644 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.545140900 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4598141692 ps |
| CPU time | 255.42 seconds |
| Started | Jul 27 08:26:55 PM PDT 24 |
| Finished | Jul 27 08:31:10 PM PDT 24 |
| Peak memory | 659296 kb |
| Host | smart-2e9539a3-8842-4bc3-81d1-3dd7b3480fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545140900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_re set.545140900 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1622886385 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2618022868 ps |
| CPU time | 201.11 seconds |
| Started | Jul 27 07:54:19 PM PDT 24 |
| Finished | Jul 27 07:57:41 PM PDT 24 |
| Peak memory | 623464 kb |
| Host | smart-005f6eeb-5c86-428e-8f10-236b06e296bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622886385 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1622886385 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3408855072 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 16238598795 ps |
| CPU time | 2137.71 seconds |
| Started | Jul 27 08:23:00 PM PDT 24 |
| Finished | Jul 27 08:58:38 PM PDT 24 |
| Peak memory | 592528 kb |
| Host | smart-0ad99107-32d1-42a6-9fa8-0c98dae5878f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408855072 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3408855072 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2373443430 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2862629610 ps |
| CPU time | 210.26 seconds |
| Started | Jul 27 08:22:58 PM PDT 24 |
| Finished | Jul 27 08:26:29 PM PDT 24 |
| Peak memory | 603496 kb |
| Host | smart-bd019b83-a346-423a-8093-a1350be926c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373443430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2373443430 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.4032714851 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 5602105551 ps |
| CPU time | 656.65 seconds |
| Started | Jul 27 08:38:32 PM PDT 24 |
| Finished | Jul 27 08:49:29 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-4b120806-35d9-476d-8cb8-82fd79cc849f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032714851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.4032714851 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3722358711 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3909699016 ps |
| CPU time | 394.02 seconds |
| Started | Jul 27 07:53:17 PM PDT 24 |
| Finished | Jul 27 07:59:52 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-9e19f5fb-0248-4f4b-a35e-eff16c806033 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722358711 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3722358711 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4117572777 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5202400104 ps |
| CPU time | 361.49 seconds |
| Started | Jul 27 07:53:24 PM PDT 24 |
| Finished | Jul 27 07:59:25 PM PDT 24 |
| Peak memory | 611596 kb |
| Host | smart-589e65ed-cc82-4a13-978f-047153abc36b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4117572777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.4117572777 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1354837466 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5267541615 ps |
| CPU time | 815.14 seconds |
| Started | Jul 27 08:06:35 PM PDT 24 |
| Finished | Jul 27 08:20:10 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-e75291f3-22c6-4c14-9597-3790d1ba8a69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1354837466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1354837466 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.309028502 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 5835484716 ps |
| CPU time | 815.9 seconds |
| Started | Jul 27 08:27:07 PM PDT 24 |
| Finished | Jul 27 08:40:43 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-8a027135-b082-41d9-b626-5d137531d49e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 309028502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.309028502 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.123925515 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6600291805 ps |
| CPU time | 415.93 seconds |
| Started | Jul 27 07:52:42 PM PDT 24 |
| Finished | Jul 27 07:59:38 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-d52730d7-3909-4ca7-8137-358f92ead94b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123925515 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.123925515 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3808121460 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2966386620 ps |
| CPU time | 266.29 seconds |
| Started | Jul 27 08:08:19 PM PDT 24 |
| Finished | Jul 27 08:12:45 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-3f1c5104-fa5f-44dd-ae4a-11eb504a7c8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808121460 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3808121460 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4046663402 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 4432385142 ps |
| CPU time | 600.34 seconds |
| Started | Jul 27 07:52:32 PM PDT 24 |
| Finished | Jul 27 08:02:33 PM PDT 24 |
| Peak memory | 624916 kb |
| Host | smart-e22e3fa5-2a43-4f0c-8778-2cbba8d8ebb2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046663402 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.4046663402 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.1489792075 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13820417966 ps |
| CPU time | 1506.51 seconds |
| Started | Jul 27 08:06:35 PM PDT 24 |
| Finished | Jul 27 08:31:41 PM PDT 24 |
| Peak memory | 621776 kb |
| Host | smart-ac9fbb16-505b-41f2-a59a-9132651178b7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1489792075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1489792075 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1952257588 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 9800967121 ps |
| CPU time | 102.43 seconds |
| Started | Jul 27 08:31:06 PM PDT 24 |
| Finished | Jul 27 08:32:48 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-b819e1aa-7374-4ed5-b3e1-b7b52ce5a6a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952257588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1952257588 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.378199413 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4917306695 ps |
| CPU time | 519.09 seconds |
| Started | Jul 27 08:33:49 PM PDT 24 |
| Finished | Jul 27 08:42:28 PM PDT 24 |
| Peak memory | 597376 kb |
| Host | smart-c2f6ba6c-5325-4f8e-9ae1-a6076e4bdaee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378199413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.378199413 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3888908721 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4604109070 ps |
| CPU time | 408.11 seconds |
| Started | Jul 27 08:37:09 PM PDT 24 |
| Finished | Jul 27 08:43:57 PM PDT 24 |
| Peak memory | 603408 kb |
| Host | smart-6b338d28-c0cf-446b-b1d0-821f762b2a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888908721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3888908721 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1553146941 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 10370150198 ps |
| CPU time | 551.19 seconds |
| Started | Jul 27 08:27:45 PM PDT 24 |
| Finished | Jul 27 08:36:56 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-945c4c27-0cd4-4ac8-a307-f31037a5ea31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553146941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1553146941 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.3944047226 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3424046000 ps |
| CPU time | 315.63 seconds |
| Started | Jul 27 08:10:01 PM PDT 24 |
| Finished | Jul 27 08:15:18 PM PDT 24 |
| Peak memory | 612024 kb |
| Host | smart-2c5e5636-3e77-42b9-bcef-d326f824dba7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944047226 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3944047226 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.375335248 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 19661360000 ps |
| CPU time | 704.01 seconds |
| Started | Jul 27 07:56:13 PM PDT 24 |
| Finished | Jul 27 08:07:58 PM PDT 24 |
| Peak memory | 620300 kb |
| Host | smart-432ea4ac-86fd-4656-a619-7b7158fc5567 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=375335248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.375335248 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3441506865 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 22878758600 ps |
| CPU time | 6182.69 seconds |
| Started | Jul 27 07:55:50 PM PDT 24 |
| Finished | Jul 27 09:38:54 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-0bff6b6b-9135-44db-9db4-55437c9a61ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3441506865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3441506865 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2619274441 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2741266719 ps |
| CPU time | 254.31 seconds |
| Started | Jul 27 07:53:18 PM PDT 24 |
| Finished | Jul 27 07:57:33 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-71799496-4b21-47d4-9d03-d0d7d9737d44 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619274441 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.2619274441 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.406792522 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 5600517050 ps |
| CPU time | 495.49 seconds |
| Started | Jul 27 07:55:47 PM PDT 24 |
| Finished | Jul 27 08:04:03 PM PDT 24 |
| Peak memory | 611220 kb |
| Host | smart-0ce64ebc-8ee7-4b7d-bd83-4fc86948341f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=406792522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.406792522 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2421057514 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 6748218336 ps |
| CPU time | 419.81 seconds |
| Started | Jul 27 07:55:04 PM PDT 24 |
| Finished | Jul 27 08:02:05 PM PDT 24 |
| Peak memory | 617828 kb |
| Host | smart-7ddedf95-3ca5-457b-9b2f-b21d4fb2465a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2421057514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2421057514 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1342045258 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3203717990 ps |
| CPU time | 282.71 seconds |
| Started | Jul 27 08:10:51 PM PDT 24 |
| Finished | Jul 27 08:15:34 PM PDT 24 |
| Peak memory | 623452 kb |
| Host | smart-89197160-f07e-4b98-b717-f225a5652c34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342045258 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1342045258 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.3769128459 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 387468708 ps |
| CPU time | 37.41 seconds |
| Started | Jul 27 08:32:58 PM PDT 24 |
| Finished | Jul 27 08:33:36 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-b78d9d54-f694-46cc-9df2-ac783bdfe011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769128459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3769128459 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2329453091 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 20506259743 ps |
| CPU time | 760.17 seconds |
| Started | Jul 27 08:37:06 PM PDT 24 |
| Finished | Jul 27 08:49:46 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-4568f204-7802-4263-9458-8a74b2081f23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329453091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2329453091 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.921109749 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1850718098 ps |
| CPU time | 179.71 seconds |
| Started | Jul 27 08:38:22 PM PDT 24 |
| Finished | Jul 27 08:41:22 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-bd547f5d-8c9f-4988-ba83-963ea5b25859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921109749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_reset_error.921109749 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2565854004 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4594482723 ps |
| CPU time | 427.36 seconds |
| Started | Jul 27 08:40:53 PM PDT 24 |
| Finished | Jul 27 08:48:00 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-b6c6fadc-cc14-49e3-ac91-76541e71ea65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565854004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2565854004 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.70199619 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 4855769764 ps |
| CPU time | 531.94 seconds |
| Started | Jul 27 08:45:08 PM PDT 24 |
| Finished | Jul 27 08:54:00 PM PDT 24 |
| Peak memory | 576796 kb |
| Host | smart-793e3bcd-fd99-4b59-8249-971717b7e25e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70199619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_reset_error.70199619 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.672013594 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 15648628873 ps |
| CPU time | 505.15 seconds |
| Started | Jul 27 08:45:24 PM PDT 24 |
| Finished | Jul 27 08:53:49 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-16493a8c-1990-48b7-9ec3-da1befc4ea01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672013594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.672013594 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1312145060 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5900194360 ps |
| CPU time | 786.8 seconds |
| Started | Jul 27 07:53:54 PM PDT 24 |
| Finished | Jul 27 08:07:01 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-5e77e7d5-aef8-4374-a1dd-ce75b3ed92ef |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312145060 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.1312145060 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.898461559 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5702777032 ps |
| CPU time | 918.37 seconds |
| Started | Jul 27 07:56:44 PM PDT 24 |
| Finished | Jul 27 08:12:04 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-d802fc83-898e-406e-8be8-2b11f0d28e1f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898461559 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.898461559 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.523388489 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4542504616 ps |
| CPU time | 747.59 seconds |
| Started | Jul 27 07:56:12 PM PDT 24 |
| Finished | Jul 27 08:08:39 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-1973a146-6ac8-49ae-ab12-0c4c461f9aec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52338 8489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.523388489 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.680732073 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3644293214 ps |
| CPU time | 406.05 seconds |
| Started | Jul 27 08:06:19 PM PDT 24 |
| Finished | Jul 27 08:13:05 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-abea31c8-c0f3-4ff0-8c4b-2900eeef02d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680732073 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.680732073 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1404994457 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 5604014074 ps |
| CPU time | 504.88 seconds |
| Started | Jul 27 08:05:34 PM PDT 24 |
| Finished | Jul 27 08:13:59 PM PDT 24 |
| Peak memory | 631280 kb |
| Host | smart-727c7580-9da9-436a-93e0-413723bbfac2 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404994457 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1404994457 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3906968217 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 8281385912 ps |
| CPU time | 1343.58 seconds |
| Started | Jul 27 07:52:43 PM PDT 24 |
| Finished | Jul 27 08:15:07 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-f0026d9c-3e16-403c-a19c-08dd751f95d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3906968217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3906968217 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2635858874 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3149968584 ps |
| CPU time | 545.42 seconds |
| Started | Jul 27 07:54:18 PM PDT 24 |
| Finished | Jul 27 08:03:24 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-62103c1a-f102-4040-81aa-d8aa13bd5ea0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635858874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.2635858874 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1683785726 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 15453075436 ps |
| CPU time | 4790.6 seconds |
| Started | Jul 27 07:56:41 PM PDT 24 |
| Finished | Jul 27 09:16:32 PM PDT 24 |
| Peak memory | 611416 kb |
| Host | smart-cd2a5e07-9a88-4147-8c4b-cf96a3aff633 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837 85726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.1683785726 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1277006676 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 16761922540 ps |
| CPU time | 3885.97 seconds |
| Started | Jul 27 07:57:01 PM PDT 24 |
| Finished | Jul 27 09:01:48 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-af8bc8ff-9a44-418d-9865-529237f0afb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1277006676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1277006676 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.89508103 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 73331466316 ps |
| CPU time | 10397 seconds |
| Started | Jul 27 08:23:05 PM PDT 24 |
| Finished | Jul 27 11:16:24 PM PDT 24 |
| Peak memory | 638348 kb |
| Host | smart-34ab7acc-f4ec-4f0c-b6df-dbdab68af7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89508103 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.chip_csr_aliasing.89508103 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1700278541 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 11823541098 ps |
| CPU time | 1394.88 seconds |
| Started | Jul 27 08:22:45 PM PDT 24 |
| Finished | Jul 27 08:46:01 PM PDT 24 |
| Peak memory | 592372 kb |
| Host | smart-24632eb4-7710-4eee-8e41-0dae64a70810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700278541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.1700278541 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2828546982 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5690653856 ps |
| CPU time | 295.29 seconds |
| Started | Jul 27 08:24:20 PM PDT 24 |
| Finished | Jul 27 08:29:16 PM PDT 24 |
| Peak memory | 657800 kb |
| Host | smart-132f4f21-5f57-43b6-9ac7-d5f78fca5f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828546982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.2828546982 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3060227849 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 12709591536 ps |
| CPU time | 1158.86 seconds |
| Started | Jul 27 08:24:12 PM PDT 24 |
| Finished | Jul 27 08:43:31 PM PDT 24 |
| Peak memory | 650612 kb |
| Host | smart-e2e680df-cd95-4339-b610-ee614d9f1fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060227849 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.3060227849 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.2720359068 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 6737850225 ps |
| CPU time | 855.69 seconds |
| Started | Jul 27 08:24:13 PM PDT 24 |
| Finished | Jul 27 08:38:28 PM PDT 24 |
| Peak memory | 598428 kb |
| Host | smart-969360c4-c303-4016-be38-d6a7f796bf74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720359068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2720359068 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.686999632 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 6425202724 ps |
| CPU time | 257.04 seconds |
| Started | Jul 27 08:23:07 PM PDT 24 |
| Finished | Jul 27 08:27:24 PM PDT 24 |
| Peak memory | 589396 kb |
| Host | smart-58aa624e-cd79-44c2-b30f-d980556555a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686999632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .chip_prim_tl_access.686999632 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4136044272 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 11718033970 ps |
| CPU time | 321.48 seconds |
| Started | Jul 27 08:22:59 PM PDT 24 |
| Finished | Jul 27 08:28:21 PM PDT 24 |
| Peak memory | 589976 kb |
| Host | smart-ee22d309-0833-424a-960f-af86588045d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136044272 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.4136044272 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.1754475825 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 1971592429 ps |
| CPU time | 83.89 seconds |
| Started | Jul 27 08:23:29 PM PDT 24 |
| Finished | Jul 27 08:24:53 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-a103ba62-ee8e-470f-88a4-e658de53ab8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754475825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 1754475825 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.880790102 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 26079650589 ps |
| CPU time | 457.02 seconds |
| Started | Jul 27 08:23:36 PM PDT 24 |
| Finished | Jul 27 08:31:13 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e833dd65-8b8a-4e67-a8b8-d1d53b7c1b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880790102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de vice_slow_rsp.880790102 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2167510355 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1589703941 ps |
| CPU time | 64.39 seconds |
| Started | Jul 27 08:23:57 PM PDT 24 |
| Finished | Jul 27 08:25:01 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-cf75a654-1494-4515-ac7f-f7dc35393806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167510355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2167510355 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.198315643 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 558172013 ps |
| CPU time | 59.58 seconds |
| Started | Jul 27 08:23:41 PM PDT 24 |
| Finished | Jul 27 08:24:41 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-75a8d0ea-e06a-4872-8041-3168803efd87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198315643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.198315643 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2141394078 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 580310735 ps |
| CPU time | 58.39 seconds |
| Started | Jul 27 08:23:24 PM PDT 24 |
| Finished | Jul 27 08:24:23 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-a67c58a1-4f45-4d9a-ab20-24b2079a9a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141394078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2141394078 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2705263158 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 57665046981 ps |
| CPU time | 610.06 seconds |
| Started | Jul 27 08:23:28 PM PDT 24 |
| Finished | Jul 27 08:33:39 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-451c88be-080c-445e-881c-5093349875fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705263158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2705263158 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.164432871 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 60718080997 ps |
| CPU time | 1024.85 seconds |
| Started | Jul 27 08:23:27 PM PDT 24 |
| Finished | Jul 27 08:40:32 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-c7fd0c13-794b-4240-b2a0-91262f683236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164432871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.164432871 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2353113320 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 340618820 ps |
| CPU time | 34.72 seconds |
| Started | Jul 27 08:23:29 PM PDT 24 |
| Finished | Jul 27 08:24:04 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-421d740e-6907-47c3-aa5a-65d4d4b4848d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353113320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2353113320 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1810183849 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 430632355 ps |
| CPU time | 40.62 seconds |
| Started | Jul 27 08:23:58 PM PDT 24 |
| Finished | Jul 27 08:24:40 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-1643336a-5aa4-4ed2-a5df-9e4df259dbbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810183849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1810183849 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.3372866300 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 40243046 ps |
| CPU time | 5.98 seconds |
| Started | Jul 27 08:23:03 PM PDT 24 |
| Finished | Jul 27 08:23:09 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-6980329b-debc-45e5-bc7b-2b90b954d472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372866300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3372866300 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3622692052 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 7040853694 ps |
| CPU time | 73.19 seconds |
| Started | Jul 27 08:23:15 PM PDT 24 |
| Finished | Jul 27 08:24:28 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-a9d74e82-9238-4e6e-af74-8f7438bdf42b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622692052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3622692052 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1787400854 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 4093920394 ps |
| CPU time | 71.9 seconds |
| Started | Jul 27 08:23:35 PM PDT 24 |
| Finished | Jul 27 08:24:48 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-53d6e3a8-ecee-4783-853e-d36dcb70fc94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787400854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1787400854 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2525636126 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 46561066 ps |
| CPU time | 6.64 seconds |
| Started | Jul 27 08:23:03 PM PDT 24 |
| Finished | Jul 27 08:23:10 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-9cca2c4d-8f8e-4684-9934-fea3d8ba1747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525636126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .2525636126 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.734860837 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 12551363683 ps |
| CPU time | 517.01 seconds |
| Started | Jul 27 08:24:02 PM PDT 24 |
| Finished | Jul 27 08:32:39 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-9a6be46a-484b-47d2-81c9-867f2c5ef175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734860837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.734860837 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1723474611 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 878530938 ps |
| CPU time | 63.25 seconds |
| Started | Jul 27 08:24:18 PM PDT 24 |
| Finished | Jul 27 08:25:21 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-22600b28-315f-4b64-9474-307edde78b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723474611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1723474611 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.247034982 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 411176691 ps |
| CPU time | 215.45 seconds |
| Started | Jul 27 08:24:12 PM PDT 24 |
| Finished | Jul 27 08:27:48 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-c58ae7ff-d94c-4078-b88a-817c36e127e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247034982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.247034982 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2191038096 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 4795564390 ps |
| CPU time | 531.94 seconds |
| Started | Jul 27 08:24:25 PM PDT 24 |
| Finished | Jul 27 08:33:17 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-abeb49eb-7fad-43bc-a6db-b4e2d7aa7bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191038096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2191038096 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3481860736 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 213027504 ps |
| CPU time | 11.37 seconds |
| Started | Jul 27 08:23:38 PM PDT 24 |
| Finished | Jul 27 08:23:50 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-a7ea99a4-5c8e-4c9e-900d-ec2d9abc88db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481860736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3481860736 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3258631736 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 39080725155 ps |
| CPU time | 6017.68 seconds |
| Started | Jul 27 08:24:21 PM PDT 24 |
| Finished | Jul 27 10:04:39 PM PDT 24 |
| Peak memory | 594760 kb |
| Host | smart-5fbc45bf-3847-4fb9-99a2-568f7e907c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258631736 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3258631736 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1123290490 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 6051595601 ps |
| CPU time | 737.07 seconds |
| Started | Jul 27 08:24:25 PM PDT 24 |
| Finished | Jul 27 08:36:42 PM PDT 24 |
| Peak memory | 590208 kb |
| Host | smart-0723fed4-f509-4035-937b-5476f828bb08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123290490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1123290490 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.769322537 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5426430700 ps |
| CPU time | 269.65 seconds |
| Started | Jul 27 08:24:59 PM PDT 24 |
| Finished | Jul 27 08:29:28 PM PDT 24 |
| Peak memory | 659196 kb |
| Host | smart-ae3fe78a-c39f-4dc1-b271-a4ebf06f9897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769322537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.769322537 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1140104443 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 6754764864 ps |
| CPU time | 416.23 seconds |
| Started | Jul 27 08:25:05 PM PDT 24 |
| Finished | Jul 27 08:32:01 PM PDT 24 |
| Peak memory | 642236 kb |
| Host | smart-059a8fb7-4eb8-44fc-a18d-647536d2b197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140104443 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.1140104443 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1413072931 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 5393216660 ps |
| CPU time | 580.5 seconds |
| Started | Jul 27 08:24:57 PM PDT 24 |
| Finished | Jul 27 08:34:38 PM PDT 24 |
| Peak memory | 598676 kb |
| Host | smart-a89e8a05-b117-4e58-bf78-9308aa9f1266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413072931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1413072931 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1450387766 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 16228759180 ps |
| CPU time | 737.03 seconds |
| Started | Jul 27 08:24:34 PM PDT 24 |
| Finished | Jul 27 08:36:51 PM PDT 24 |
| Peak memory | 591112 kb |
| Host | smart-2203d263-d7f8-4194-b44a-a43ddd300ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450387766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.1450387766 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3365448029 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 18698779592 ps |
| CPU time | 747.06 seconds |
| Started | Jul 27 08:24:24 PM PDT 24 |
| Finished | Jul 27 08:36:51 PM PDT 24 |
| Peak memory | 590968 kb |
| Host | smart-2297e79e-b734-419a-9d28-5bb8716ff17b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365448029 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.3365448029 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4120795648 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 31817565413 ps |
| CPU time | 3055.35 seconds |
| Started | Jul 27 08:24:24 PM PDT 24 |
| Finished | Jul 27 09:15:20 PM PDT 24 |
| Peak memory | 593272 kb |
| Host | smart-a02f2663-fd88-48e2-93c4-7607d2977543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120795648 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.4120795648 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.834246526 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4253828800 ps |
| CPU time | 288.32 seconds |
| Started | Jul 27 08:24:30 PM PDT 24 |
| Finished | Jul 27 08:29:18 PM PDT 24 |
| Peak memory | 603472 kb |
| Host | smart-eb8938b3-4490-4e06-8f20-50374785013c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834246526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.834246526 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.992939052 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 404458977 ps |
| CPU time | 25.61 seconds |
| Started | Jul 27 08:24:46 PM PDT 24 |
| Finished | Jul 27 08:25:12 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-56925c8a-b362-4781-b16f-3564f80558f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992939052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.992939052 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2203635848 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 23644927772 ps |
| CPU time | 421.45 seconds |
| Started | Jul 27 08:24:43 PM PDT 24 |
| Finished | Jul 27 08:31:44 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-d7319ec8-8bb8-41ee-a214-d7bc21b188ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203635848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2203635848 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2551966027 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 227529642 ps |
| CPU time | 29.12 seconds |
| Started | Jul 27 08:24:47 PM PDT 24 |
| Finished | Jul 27 08:25:17 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-82f1d8fe-2c91-4b06-b864-882c3614c7d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551966027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .2551966027 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.980641693 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 496793608 ps |
| CPU time | 43.58 seconds |
| Started | Jul 27 08:24:50 PM PDT 24 |
| Finished | Jul 27 08:25:34 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-4eb3ec60-42f8-49b0-9e6d-405f6bed954b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980641693 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.980641693 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3152532992 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 1107191899 ps |
| CPU time | 47.9 seconds |
| Started | Jul 27 08:24:43 PM PDT 24 |
| Finished | Jul 27 08:25:32 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-87385a79-6213-4acb-ad45-756a5671a72e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152532992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3152532992 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.371446763 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 53205423033 ps |
| CPU time | 562.96 seconds |
| Started | Jul 27 08:24:40 PM PDT 24 |
| Finished | Jul 27 08:34:03 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9c517308-df55-4787-b0e7-d640b54ef1bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371446763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.371446763 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3237560776 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 29449057554 ps |
| CPU time | 533.45 seconds |
| Started | Jul 27 08:24:46 PM PDT 24 |
| Finished | Jul 27 08:33:39 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-3202d072-2bf2-4fac-8de1-4237b391b63f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237560776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3237560776 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3908331344 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 263506188 ps |
| CPU time | 27.54 seconds |
| Started | Jul 27 08:24:43 PM PDT 24 |
| Finished | Jul 27 08:25:11 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-6faadcb9-c158-4868-a140-a3b10b57be23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908331344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3908331344 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.1679277725 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 1073399148 ps |
| CPU time | 31.5 seconds |
| Started | Jul 27 08:24:49 PM PDT 24 |
| Finished | Jul 27 08:25:21 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-21332857-6f13-4de4-a922-3cb941d47f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679277725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1679277725 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.3082698713 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 246367108 ps |
| CPU time | 10.46 seconds |
| Started | Jul 27 08:24:21 PM PDT 24 |
| Finished | Jul 27 08:24:31 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-74ad7df3-a98d-4429-b058-d9556977374e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082698713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3082698713 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1067006294 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 7900630248 ps |
| CPU time | 86.82 seconds |
| Started | Jul 27 08:24:44 PM PDT 24 |
| Finished | Jul 27 08:26:11 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-70eccd71-faca-4915-89b9-6680fe363fc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067006294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1067006294 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.450722102 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 5112801066 ps |
| CPU time | 92.18 seconds |
| Started | Jul 27 08:25:14 PM PDT 24 |
| Finished | Jul 27 08:26:47 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-07797f16-4dca-478f-9d58-832ae29ebc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450722102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.450722102 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2189938033 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 49792323 ps |
| CPU time | 6.64 seconds |
| Started | Jul 27 08:24:36 PM PDT 24 |
| Finished | Jul 27 08:24:42 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-2ca2da06-4782-474f-9a40-f4690d48967a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189938033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .2189938033 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.806548810 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 9605247934 ps |
| CPU time | 449.23 seconds |
| Started | Jul 27 08:24:51 PM PDT 24 |
| Finished | Jul 27 08:32:21 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-371013f0-e5cc-41da-bd27-4f8b375a9f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806548810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.806548810 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.800062710 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 5033367370 ps |
| CPU time | 222.56 seconds |
| Started | Jul 27 08:25:07 PM PDT 24 |
| Finished | Jul 27 08:28:50 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-6fe4105e-e486-4898-a5db-34a8113dec4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800062710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.800062710 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.760071220 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 9860792191 ps |
| CPU time | 445.08 seconds |
| Started | Jul 27 08:24:59 PM PDT 24 |
| Finished | Jul 27 08:32:24 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-5be58cb0-9600-4237-bb47-e8b57a59c260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760071220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.760071220 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.896866367 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 330085638 ps |
| CPU time | 44.22 seconds |
| Started | Jul 27 08:25:14 PM PDT 24 |
| Finished | Jul 27 08:25:59 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-1f1347d4-fe02-4c33-b947-15cdcc9cc69a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896866367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.896866367 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1708084079 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 11627626822 ps |
| CPU time | 1007.39 seconds |
| Started | Jul 27 08:31:43 PM PDT 24 |
| Finished | Jul 27 08:48:31 PM PDT 24 |
| Peak memory | 640396 kb |
| Host | smart-6d8dc5cf-7e45-4f15-b21f-7fd8d3eb2878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708084079 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.1708084079 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2169554969 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 3991515163 ps |
| CPU time | 429.65 seconds |
| Started | Jul 27 08:31:43 PM PDT 24 |
| Finished | Jul 27 08:38:53 PM PDT 24 |
| Peak memory | 596660 kb |
| Host | smart-12c420a3-bd5a-4035-94ec-60164067f9f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169554969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2169554969 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3163623427 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 15688905978 ps |
| CPU time | 1967.39 seconds |
| Started | Jul 27 08:30:59 PM PDT 24 |
| Finished | Jul 27 09:03:46 PM PDT 24 |
| Peak memory | 592980 kb |
| Host | smart-4f94bab4-867b-41eb-918a-097a1a098ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163623427 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3163623427 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.1803736213 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3365206568 ps |
| CPU time | 184.7 seconds |
| Started | Jul 27 08:31:08 PM PDT 24 |
| Finished | Jul 27 08:34:12 PM PDT 24 |
| Peak memory | 603492 kb |
| Host | smart-e878af06-e15b-4e9c-8ebc-cbd2dc45b73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803736213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.1803736213 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3410983833 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 2142426111 ps |
| CPU time | 97.7 seconds |
| Started | Jul 27 08:31:24 PM PDT 24 |
| Finished | Jul 27 08:33:02 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-7235f7b5-2fdb-4218-9478-5ed022c028bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410983833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3410983833 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3091920418 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 55628538231 ps |
| CPU time | 1034.42 seconds |
| Started | Jul 27 08:31:24 PM PDT 24 |
| Finished | Jul 27 08:48:39 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-f5be7e10-2623-4d88-8c30-1fe4199e749c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091920418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.3091920418 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.998904759 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 851407266 ps |
| CPU time | 40.2 seconds |
| Started | Jul 27 08:31:32 PM PDT 24 |
| Finished | Jul 27 08:32:13 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-193ae876-a1a8-4cd4-8e4d-39ec7aa5efe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998904759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .998904759 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.1836862378 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 257738568 ps |
| CPU time | 13.17 seconds |
| Started | Jul 27 08:31:33 PM PDT 24 |
| Finished | Jul 27 08:31:46 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-097fa280-b1fc-4764-a1e0-5cd5469ab237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836862378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1836862378 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1663516334 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 566348323 ps |
| CPU time | 52.44 seconds |
| Started | Jul 27 08:31:13 PM PDT 24 |
| Finished | Jul 27 08:32:06 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-7202cbca-49e8-4f18-8301-75761aedfce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663516334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1663516334 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.4163987494 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 86488488572 ps |
| CPU time | 904.17 seconds |
| Started | Jul 27 08:31:17 PM PDT 24 |
| Finished | Jul 27 08:46:21 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-d4924703-e6d5-476b-9416-df6af287a4b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163987494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.4163987494 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.833557262 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 30204018942 ps |
| CPU time | 512.73 seconds |
| Started | Jul 27 08:31:15 PM PDT 24 |
| Finished | Jul 27 08:39:48 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-3defe861-8025-4cef-9308-35633179a5fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833557262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.833557262 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.680121807 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 227487798 ps |
| CPU time | 21.45 seconds |
| Started | Jul 27 08:31:13 PM PDT 24 |
| Finished | Jul 27 08:31:34 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-157c2cc2-a761-4f61-84f8-a34fd5a87bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680121807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.680121807 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2119418985 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 371627671 ps |
| CPU time | 15.83 seconds |
| Started | Jul 27 08:31:24 PM PDT 24 |
| Finished | Jul 27 08:31:40 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-af767c5f-d1d3-41b8-a2d2-dba98f7340df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119418985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2119418985 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2073292105 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 44024689 ps |
| CPU time | 6.58 seconds |
| Started | Jul 27 08:31:08 PM PDT 24 |
| Finished | Jul 27 08:31:14 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-6b0e2bf1-2625-4eee-a841-9dd7ab742cca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073292105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2073292105 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.54014778 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 6566915515 ps |
| CPU time | 118.91 seconds |
| Started | Jul 27 08:31:14 PM PDT 24 |
| Finished | Jul 27 08:33:13 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-6b4ae1f0-b7ef-487a-80e1-fbf2594fe20e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54014778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.54014778 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2078403915 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 56306924 ps |
| CPU time | 7.77 seconds |
| Started | Jul 27 08:31:06 PM PDT 24 |
| Finished | Jul 27 08:31:14 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-3fdb3fad-b1b4-48d3-89a1-514b0bda6002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078403915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.2078403915 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.3490737216 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 10020438337 ps |
| CPU time | 435.86 seconds |
| Started | Jul 27 08:31:34 PM PDT 24 |
| Finished | Jul 27 08:38:50 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-35623abe-9cb9-49b7-b92d-cdb5399b0ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490737216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3490737216 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2690418188 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 6362126778 ps |
| CPU time | 256.25 seconds |
| Started | Jul 27 08:31:44 PM PDT 24 |
| Finished | Jul 27 08:36:00 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-242cbc6d-c205-480d-977a-671d19d8cd44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690418188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2690418188 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3060268812 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 2216390220 ps |
| CPU time | 452.73 seconds |
| Started | Jul 27 08:31:32 PM PDT 24 |
| Finished | Jul 27 08:39:05 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-2f1ca718-5daa-40d6-a4c8-e68cc6b23029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060268812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.3060268812 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3454254098 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 1783202044 ps |
| CPU time | 160.14 seconds |
| Started | Jul 27 08:31:41 PM PDT 24 |
| Finished | Jul 27 08:34:21 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-55401a27-3de3-4570-8b4f-10c19710c870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454254098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.3454254098 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3406144252 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 431786962 ps |
| CPU time | 22.05 seconds |
| Started | Jul 27 08:31:31 PM PDT 24 |
| Finished | Jul 27 08:31:53 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-40643616-af57-4bd0-8204-de9445f3a412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406144252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3406144252 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1003175485 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 8393612944 ps |
| CPU time | 1056.31 seconds |
| Started | Jul 27 08:32:13 PM PDT 24 |
| Finished | Jul 27 08:49:50 PM PDT 24 |
| Peak memory | 652652 kb |
| Host | smart-3cf3b421-dfb4-46c4-aa15-8e8562fee6a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003175485 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.1003175485 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3612673998 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 5880381312 ps |
| CPU time | 619.33 seconds |
| Started | Jul 27 08:32:11 PM PDT 24 |
| Finished | Jul 27 08:42:31 PM PDT 24 |
| Peak memory | 598548 kb |
| Host | smart-f77d4e9a-dc3c-4b06-b931-c6124e277c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612673998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3612673998 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.3792214153 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3769058125 ps |
| CPU time | 318.79 seconds |
| Started | Jul 27 08:31:40 PM PDT 24 |
| Finished | Jul 27 08:36:59 PM PDT 24 |
| Peak memory | 598356 kb |
| Host | smart-0de9159a-a8fd-439f-8e59-4512dc176858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792214153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.3792214153 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.615131731 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 1125749734 ps |
| CPU time | 57.52 seconds |
| Started | Jul 27 08:31:56 PM PDT 24 |
| Finished | Jul 27 08:32:54 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-6db55c4b-b686-4ee2-8690-82be237c6a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615131731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 615131731 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1539258714 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 87660565614 ps |
| CPU time | 1584.29 seconds |
| Started | Jul 27 08:31:55 PM PDT 24 |
| Finished | Jul 27 08:58:19 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-5c7921b9-1d64-48fa-b3d1-464fc817e1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539258714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1539258714 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3012752270 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 134286454 ps |
| CPU time | 17.3 seconds |
| Started | Jul 27 08:32:12 PM PDT 24 |
| Finished | Jul 27 08:32:30 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-83e7a99b-9e94-41ed-ab8b-b63dedc99c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012752270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3012752270 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.689571969 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 222570847 ps |
| CPU time | 20.01 seconds |
| Started | Jul 27 08:32:01 PM PDT 24 |
| Finished | Jul 27 08:32:21 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-f0db92eb-d7fd-45b9-8386-23a2ad1b338d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689571969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.689571969 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.3079051234 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 2069774010 ps |
| CPU time | 83.21 seconds |
| Started | Jul 27 08:31:48 PM PDT 24 |
| Finished | Jul 27 08:33:11 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-f7383464-8174-4359-a46d-70cb9b133c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079051234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3079051234 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.58220631 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 61839486145 ps |
| CPU time | 630.95 seconds |
| Started | Jul 27 08:31:56 PM PDT 24 |
| Finished | Jul 27 08:42:28 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f0de93f2-0891-4704-a2bb-4139497588e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58220631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.58220631 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3761922160 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 43824511910 ps |
| CPU time | 784.39 seconds |
| Started | Jul 27 08:31:55 PM PDT 24 |
| Finished | Jul 27 08:45:00 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-acf78eee-c768-43a0-86a8-4bb683b5ac2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761922160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3761922160 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2373949237 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 423433769 ps |
| CPU time | 46.32 seconds |
| Started | Jul 27 08:31:55 PM PDT 24 |
| Finished | Jul 27 08:32:41 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-fa988f7e-e536-4042-97de-0de44b286636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373949237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2373949237 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.2560611123 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 788723789 ps |
| CPU time | 26.71 seconds |
| Started | Jul 27 08:32:03 PM PDT 24 |
| Finished | Jul 27 08:32:30 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-8fbbf357-f5ae-4fba-ab4e-55792f141851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560611123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2560611123 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.2108692801 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 39663682 ps |
| CPU time | 6.91 seconds |
| Started | Jul 27 08:31:44 PM PDT 24 |
| Finished | Jul 27 08:31:51 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-b2e13d05-7bed-4fc2-aa1b-ea77015d4faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108692801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2108692801 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.586337537 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 8232553588 ps |
| CPU time | 84.55 seconds |
| Started | Jul 27 08:31:49 PM PDT 24 |
| Finished | Jul 27 08:33:14 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-bd346aed-a51d-41d6-970f-66d6f5bd1cbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586337537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.586337537 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.805660668 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 5891189602 ps |
| CPU time | 101.37 seconds |
| Started | Jul 27 08:31:47 PM PDT 24 |
| Finished | Jul 27 08:33:29 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4e047bbc-ce56-49ca-9b37-1f7701b3e764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805660668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.805660668 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.705429184 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 49576735 ps |
| CPU time | 7.25 seconds |
| Started | Jul 27 08:31:48 PM PDT 24 |
| Finished | Jul 27 08:31:55 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-74dc88e6-d394-4e97-b614-cd2f4ce27f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705429184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays .705429184 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.2843434336 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 186240641 ps |
| CPU time | 22.2 seconds |
| Started | Jul 27 08:32:11 PM PDT 24 |
| Finished | Jul 27 08:32:33 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-46a5af46-7a57-4327-bb29-1e0a2fa5f525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843434336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2843434336 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1213823843 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 1085657976 ps |
| CPU time | 45.83 seconds |
| Started | Jul 27 08:32:15 PM PDT 24 |
| Finished | Jul 27 08:33:01 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-db77db31-155b-4ec4-82d9-2172602f9432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213823843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1213823843 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3675074165 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 583406521 ps |
| CPU time | 285.74 seconds |
| Started | Jul 27 08:32:12 PM PDT 24 |
| Finished | Jul 27 08:36:58 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-566c7e54-9251-4f7b-a4a1-91bb36f729b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675074165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3675074165 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2330560381 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 651575469 ps |
| CPU time | 197.12 seconds |
| Started | Jul 27 08:32:12 PM PDT 24 |
| Finished | Jul 27 08:35:29 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-744216e4-a763-4fa5-8cd9-3fd49d05324f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330560381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2330560381 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3106282507 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 1283460044 ps |
| CPU time | 53.61 seconds |
| Started | Jul 27 08:32:13 PM PDT 24 |
| Finished | Jul 27 08:33:07 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-09972f6c-025c-4a1d-8052-32da215bee1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106282507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3106282507 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3001720655 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 7018397340 ps |
| CPU time | 531.37 seconds |
| Started | Jul 27 08:32:36 PM PDT 24 |
| Finished | Jul 27 08:41:27 PM PDT 24 |
| Peak memory | 639260 kb |
| Host | smart-7aa91506-8772-48cc-b403-88a425270d1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001720655 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3001720655 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1267533248 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 6069579312 ps |
| CPU time | 654.97 seconds |
| Started | Jul 27 08:32:31 PM PDT 24 |
| Finished | Jul 27 08:43:26 PM PDT 24 |
| Peak memory | 598616 kb |
| Host | smart-664ec372-869e-4a90-8306-e90083833697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267533248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1267533248 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3687966696 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 30360615878 ps |
| CPU time | 3039.18 seconds |
| Started | Jul 27 08:32:13 PM PDT 24 |
| Finished | Jul 27 09:22:52 PM PDT 24 |
| Peak memory | 593352 kb |
| Host | smart-9fc69b9d-d7bb-4abd-98d2-788e02ee4d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687966696 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3687966696 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.568488444 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 3198097848 ps |
| CPU time | 200.65 seconds |
| Started | Jul 27 08:32:12 PM PDT 24 |
| Finished | Jul 27 08:35:33 PM PDT 24 |
| Peak memory | 603456 kb |
| Host | smart-f8ff2e9a-4dd8-42bf-a97c-92612ebcc1be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568488444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.568488444 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.1211832563 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 358107157 ps |
| CPU time | 30.98 seconds |
| Started | Jul 27 08:32:24 PM PDT 24 |
| Finished | Jul 27 08:32:55 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-9c21d1d8-9eab-4e81-a753-4e00daf01ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211832563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .1211832563 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.495330630 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 35884497377 ps |
| CPU time | 608.38 seconds |
| Started | Jul 27 08:32:19 PM PDT 24 |
| Finished | Jul 27 08:42:27 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-b5257d4e-74e9-4e4a-b315-bbc706beb72d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495330630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_d evice_slow_rsp.495330630 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2858018505 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 368302239 ps |
| CPU time | 17.43 seconds |
| Started | Jul 27 08:32:24 PM PDT 24 |
| Finished | Jul 27 08:32:42 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-ea58ad5c-0250-42a2-b728-486054d8590d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858018505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2858018505 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.2503527575 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 210393940 ps |
| CPU time | 10.94 seconds |
| Started | Jul 27 08:32:22 PM PDT 24 |
| Finished | Jul 27 08:32:33 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-e91a74a0-84e0-4693-b4a8-fb4bac2660cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503527575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2503527575 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1452192085 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 401491275 ps |
| CPU time | 34 seconds |
| Started | Jul 27 08:32:11 PM PDT 24 |
| Finished | Jul 27 08:32:45 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-01a7ca4b-f29c-4353-88b4-5bb288e34e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452192085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1452192085 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4069447555 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 28781434043 ps |
| CPU time | 312.05 seconds |
| Started | Jul 27 08:32:20 PM PDT 24 |
| Finished | Jul 27 08:37:32 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-45c9f9f7-4cac-4bd7-b759-1f99e24f87ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069447555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.4069447555 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1362150545 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 22809999041 ps |
| CPU time | 392.09 seconds |
| Started | Jul 27 08:32:21 PM PDT 24 |
| Finished | Jul 27 08:38:53 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-7cf99642-efdd-407b-9ec3-b623cd0671fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362150545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1362150545 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1399619862 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 416662819 ps |
| CPU time | 50.67 seconds |
| Started | Jul 27 08:32:13 PM PDT 24 |
| Finished | Jul 27 08:33:04 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-dad17e3d-72d4-4b1e-a06f-efcf80f363c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399619862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.1399619862 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.503267286 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 305366680 ps |
| CPU time | 23.12 seconds |
| Started | Jul 27 08:32:20 PM PDT 24 |
| Finished | Jul 27 08:32:43 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-8ecec3d1-aa6b-496c-8390-fcd4c9844462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503267286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.503267286 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.2259055917 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 224826782 ps |
| CPU time | 10.71 seconds |
| Started | Jul 27 08:32:13 PM PDT 24 |
| Finished | Jul 27 08:32:24 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-a3eade56-308a-4d8e-95c0-1ce194a27d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259055917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2259055917 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3087301739 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 9065058921 ps |
| CPU time | 102.7 seconds |
| Started | Jul 27 08:32:14 PM PDT 24 |
| Finished | Jul 27 08:33:57 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-7af9bbf7-af03-47dd-882f-750a2cab117c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087301739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3087301739 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1276875475 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 4832767610 ps |
| CPU time | 84.73 seconds |
| Started | Jul 27 08:32:15 PM PDT 24 |
| Finished | Jul 27 08:33:40 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d45d0c1d-bb17-402f-867c-c0b743b8d382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276875475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1276875475 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2735023577 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 43909500 ps |
| CPU time | 6.74 seconds |
| Started | Jul 27 08:32:13 PM PDT 24 |
| Finished | Jul 27 08:32:20 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-0068921e-2ed7-4b6e-88f9-1d87491f78bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735023577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.2735023577 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3721324921 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 6871037441 ps |
| CPU time | 259.01 seconds |
| Started | Jul 27 08:32:31 PM PDT 24 |
| Finished | Jul 27 08:36:50 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-80bc45e7-18fc-42d6-bd64-da34941c174d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721324921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.3721324921 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.752551528 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 479664263 ps |
| CPU time | 223.7 seconds |
| Started | Jul 27 08:32:29 PM PDT 24 |
| Finished | Jul 27 08:36:13 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-7266aac6-0a9e-4b4b-9aa2-06063ee2d1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752551528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_ with_rand_reset.752551528 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1616178958 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 488196148 ps |
| CPU time | 140.78 seconds |
| Started | Jul 27 08:32:28 PM PDT 24 |
| Finished | Jul 27 08:34:49 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-ba1cb71e-87b0-44e8-abd2-ae0dde998eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616178958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1616178958 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1078916231 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 212979871 ps |
| CPU time | 29.33 seconds |
| Started | Jul 27 08:32:24 PM PDT 24 |
| Finished | Jul 27 08:32:54 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-c87d523c-7e74-4a1c-8410-1f6a844803d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078916231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1078916231 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3899955654 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 9411052196 ps |
| CPU time | 1142.33 seconds |
| Started | Jul 27 08:33:07 PM PDT 24 |
| Finished | Jul 27 08:52:09 PM PDT 24 |
| Peak memory | 645924 kb |
| Host | smart-79352435-c4a1-40be-8104-8a764676e661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899955654 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.3899955654 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.1494160989 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 5530817580 ps |
| CPU time | 571.09 seconds |
| Started | Jul 27 08:33:06 PM PDT 24 |
| Finished | Jul 27 08:42:37 PM PDT 24 |
| Peak memory | 598080 kb |
| Host | smart-7d1ac9da-3e0c-49c4-9bbe-30ed78dd33a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494160989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.1494160989 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.686549321 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 17340343394 ps |
| CPU time | 2221.64 seconds |
| Started | Jul 27 08:32:36 PM PDT 24 |
| Finished | Jul 27 09:09:38 PM PDT 24 |
| Peak memory | 593060 kb |
| Host | smart-20c7c71f-2eab-4fb7-9c42-b1f04c4422aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686549321 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.686549321 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.560649469 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 3337595784 ps |
| CPU time | 202.77 seconds |
| Started | Jul 27 08:32:38 PM PDT 24 |
| Finished | Jul 27 08:36:01 PM PDT 24 |
| Peak memory | 598356 kb |
| Host | smart-e0f92c95-54cd-4951-890e-843a0ec1942a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560649469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.560649469 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.951978604 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 191531004 ps |
| CPU time | 14.25 seconds |
| Started | Jul 27 08:32:52 PM PDT 24 |
| Finished | Jul 27 08:33:06 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-76187af6-2ab4-4a14-b541-bb8c484d5c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951978604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device. 951978604 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3930173672 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 108034136549 ps |
| CPU time | 1879.36 seconds |
| Started | Jul 27 08:32:57 PM PDT 24 |
| Finished | Jul 27 09:04:17 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e130109e-0a85-49b1-8064-7e710a9dc970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930173672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.3930173672 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.813571464 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 285036764 ps |
| CPU time | 33.58 seconds |
| Started | Jul 27 08:32:57 PM PDT 24 |
| Finished | Jul 27 08:33:31 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-f7d7e708-7e9a-4ced-9131-589eb19b9861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813571464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr .813571464 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.443089015 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 264553355 ps |
| CPU time | 28.21 seconds |
| Started | Jul 27 08:32:45 PM PDT 24 |
| Finished | Jul 27 08:33:13 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-654356f9-c9a1-41ae-b076-0cad8e7f60db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443089015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.443089015 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.420510713 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 66128041331 ps |
| CPU time | 707.16 seconds |
| Started | Jul 27 08:32:46 PM PDT 24 |
| Finished | Jul 27 08:44:33 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-7685bcbd-a7a5-4d7c-add9-192364bf2348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420510713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.420510713 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2343783646 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 10302944037 ps |
| CPU time | 198.04 seconds |
| Started | Jul 27 08:32:45 PM PDT 24 |
| Finished | Jul 27 08:36:03 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-2eedc121-f009-45e9-af05-7053566ba327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343783646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2343783646 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1891776749 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 293756422 ps |
| CPU time | 23.86 seconds |
| Started | Jul 27 08:32:52 PM PDT 24 |
| Finished | Jul 27 08:33:16 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b094b22f-e79a-45bd-9720-489abde600fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891776749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.1891776749 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2306905642 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 84359916 ps |
| CPU time | 10.43 seconds |
| Started | Jul 27 08:32:57 PM PDT 24 |
| Finished | Jul 27 08:33:08 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-f35a9f3c-c05d-4d05-bcd7-799df6ff4b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306905642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2306905642 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.1087049488 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 53952179 ps |
| CPU time | 7.15 seconds |
| Started | Jul 27 08:32:37 PM PDT 24 |
| Finished | Jul 27 08:32:44 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-dc5785d7-0200-4dfb-86c2-7c1ea84fab8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087049488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1087049488 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2205101510 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 7872990872 ps |
| CPU time | 88.31 seconds |
| Started | Jul 27 08:32:37 PM PDT 24 |
| Finished | Jul 27 08:34:06 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-f6b2b3af-5c42-43c3-bf6e-0477372c8f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205101510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2205101510 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1401981149 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 4971068174 ps |
| CPU time | 72.21 seconds |
| Started | Jul 27 08:32:52 PM PDT 24 |
| Finished | Jul 27 08:34:04 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-97688781-1b99-4a3f-b6de-055fb23daf66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401981149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1401981149 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1287710588 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 47902616 ps |
| CPU time | 6.72 seconds |
| Started | Jul 27 08:32:36 PM PDT 24 |
| Finished | Jul 27 08:32:43 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-d81bb140-760d-48aa-9a86-46bc08e094e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287710588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.1287710588 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2845512361 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 1026169340 ps |
| CPU time | 83.62 seconds |
| Started | Jul 27 08:33:01 PM PDT 24 |
| Finished | Jul 27 08:34:24 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-2bfacdd9-90a8-456c-972b-07dbc1c2d21a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845512361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2845512361 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2046892361 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 362112426 ps |
| CPU time | 125.15 seconds |
| Started | Jul 27 08:32:56 PM PDT 24 |
| Finished | Jul 27 08:35:02 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-c4ec0b52-6b25-406d-be39-6ab302520cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046892361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.2046892361 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1476911437 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 3778742025 ps |
| CPU time | 582.03 seconds |
| Started | Jul 27 08:33:06 PM PDT 24 |
| Finished | Jul 27 08:42:48 PM PDT 24 |
| Peak memory | 577348 kb |
| Host | smart-639fa292-a41f-4be4-8c26-7be2e5901e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476911437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1476911437 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1480110214 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 483984919 ps |
| CPU time | 22.65 seconds |
| Started | Jul 27 08:32:57 PM PDT 24 |
| Finished | Jul 27 08:33:20 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-b4e5bad8-fb76-482c-8d7d-a4d09efce596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480110214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1480110214 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.4242290275 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 5680725788 ps |
| CPU time | 559.1 seconds |
| Started | Jul 27 08:33:31 PM PDT 24 |
| Finished | Jul 27 08:42:50 PM PDT 24 |
| Peak memory | 639248 kb |
| Host | smart-fe9e60f1-fbb2-4994-9753-c514b274aa23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242290275 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.4242290275 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.1803736297 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 5857880920 ps |
| CPU time | 613.14 seconds |
| Started | Jul 27 08:33:37 PM PDT 24 |
| Finished | Jul 27 08:43:51 PM PDT 24 |
| Peak memory | 598712 kb |
| Host | smart-e9dd2a96-3f69-40a7-816c-3195e106b44d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803736297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1803736297 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.581984120 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 28542411785 ps |
| CPU time | 3482.28 seconds |
| Started | Jul 27 08:33:07 PM PDT 24 |
| Finished | Jul 27 09:31:10 PM PDT 24 |
| Peak memory | 592956 kb |
| Host | smart-6155f2dc-4d9b-4db7-8de0-3070818f7cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581984120 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.581984120 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.3676803927 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4268309984 ps |
| CPU time | 336.74 seconds |
| Started | Jul 27 08:33:07 PM PDT 24 |
| Finished | Jul 27 08:38:44 PM PDT 24 |
| Peak memory | 603468 kb |
| Host | smart-35b34c2d-4a95-4b8d-bb43-4067f24489ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676803927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3676803927 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2973952105 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 73868944 ps |
| CPU time | 8.84 seconds |
| Started | Jul 27 08:33:15 PM PDT 24 |
| Finished | Jul 27 08:33:24 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-b6356682-f8e7-47e1-9e3d-c5a6fe7604e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973952105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2973952105 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3717158212 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 2763675176 ps |
| CPU time | 49.29 seconds |
| Started | Jul 27 08:33:13 PM PDT 24 |
| Finished | Jul 27 08:34:03 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-e6e10675-5d18-41ef-b6ea-b19a8d3992d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717158212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3717158212 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3482993147 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 1364150534 ps |
| CPU time | 56.88 seconds |
| Started | Jul 27 08:33:22 PM PDT 24 |
| Finished | Jul 27 08:34:19 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-1a9e1855-1ce8-4749-adfd-43ec6452faa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482993147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3482993147 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3405208485 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 34041551 ps |
| CPU time | 6.66 seconds |
| Started | Jul 27 08:33:24 PM PDT 24 |
| Finished | Jul 27 08:33:31 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-f11a64f1-33cd-48e5-9f99-a150459c2084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405208485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3405208485 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2066978813 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 90739168 ps |
| CPU time | 12.13 seconds |
| Started | Jul 27 08:33:10 PM PDT 24 |
| Finished | Jul 27 08:33:22 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-c96f8248-9c15-49a7-9f44-18209d5c3a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066978813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2066978813 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.669883142 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 5652929145 ps |
| CPU time | 62.15 seconds |
| Started | Jul 27 08:33:12 PM PDT 24 |
| Finished | Jul 27 08:34:15 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-42ced697-d35d-493a-86e1-05687772bf70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669883142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.669883142 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2059663523 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 33345872407 ps |
| CPU time | 576.36 seconds |
| Started | Jul 27 08:33:15 PM PDT 24 |
| Finished | Jul 27 08:42:51 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4e14111e-0b4f-418a-b96a-3bd2d7aba189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059663523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2059663523 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3377354913 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 267676369 ps |
| CPU time | 23.72 seconds |
| Started | Jul 27 08:33:13 PM PDT 24 |
| Finished | Jul 27 08:33:37 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-e6df4b14-1452-4ca4-921e-798b8b8c5bd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377354913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.3377354913 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.1023626387 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 144967055 ps |
| CPU time | 15.58 seconds |
| Started | Jul 27 08:33:12 PM PDT 24 |
| Finished | Jul 27 08:33:28 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-89d222b5-23d6-45d9-b445-cbad192d45d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023626387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1023626387 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.934218708 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 209768283 ps |
| CPU time | 9.38 seconds |
| Started | Jul 27 08:33:08 PM PDT 24 |
| Finished | Jul 27 08:33:17 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-a60cf454-c421-41a3-bac6-8f3948736154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934218708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.934218708 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3649559500 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 9229246091 ps |
| CPU time | 98.8 seconds |
| Started | Jul 27 08:33:04 PM PDT 24 |
| Finished | Jul 27 08:34:43 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-688e938e-28f0-4b54-a7b2-d6a58c1cbbd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649559500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3649559500 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.192731138 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 3520103402 ps |
| CPU time | 65.42 seconds |
| Started | Jul 27 08:33:09 PM PDT 24 |
| Finished | Jul 27 08:34:15 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-7c2e008e-b7e4-40df-8c4a-bc0cc73dff90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192731138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.192731138 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2724024167 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 39646354 ps |
| CPU time | 6.29 seconds |
| Started | Jul 27 08:33:07 PM PDT 24 |
| Finished | Jul 27 08:33:13 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-44cf3824-c791-4558-8aa3-c6ca3bff14ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724024167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2724024167 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.3513170234 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 13852158892 ps |
| CPU time | 568.02 seconds |
| Started | Jul 27 08:33:24 PM PDT 24 |
| Finished | Jul 27 08:42:52 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-3d1014eb-ce78-49d4-aa91-fa5ff9e3517c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513170234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3513170234 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1385999536 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 7640823868 ps |
| CPU time | 318.32 seconds |
| Started | Jul 27 08:33:23 PM PDT 24 |
| Finished | Jul 27 08:38:41 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-557d1655-7f7d-4a68-abb1-369f3c4855b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385999536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1385999536 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2141402049 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 1175860020 ps |
| CPU time | 428.74 seconds |
| Started | Jul 27 08:33:21 PM PDT 24 |
| Finished | Jul 27 08:40:30 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7b41b630-a9fd-4ffe-92a8-5062034847cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141402049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2141402049 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3492337578 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 568837187 ps |
| CPU time | 30 seconds |
| Started | Jul 27 08:33:22 PM PDT 24 |
| Finished | Jul 27 08:33:52 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-e7ed157c-2660-4799-875c-cd4f665ea9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492337578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3492337578 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1247151241 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 12020025489 ps |
| CPU time | 995.05 seconds |
| Started | Jul 27 08:33:51 PM PDT 24 |
| Finished | Jul 27 08:50:27 PM PDT 24 |
| Peak memory | 652648 kb |
| Host | smart-01638edb-0130-4d20-91f6-83b032b88d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247151241 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.1247151241 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3229628963 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 15158177145 ps |
| CPU time | 1470.45 seconds |
| Started | Jul 27 08:33:32 PM PDT 24 |
| Finished | Jul 27 08:58:03 PM PDT 24 |
| Peak memory | 593024 kb |
| Host | smart-1ea969dd-f807-4598-9c28-ac9f648c27e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229628963 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3229628963 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.2060567075 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 4232540228 ps |
| CPU time | 345.07 seconds |
| Started | Jul 27 08:33:31 PM PDT 24 |
| Finished | Jul 27 08:39:16 PM PDT 24 |
| Peak memory | 603360 kb |
| Host | smart-72de1d1a-ffdb-44c3-acaf-f8f888bcb0a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060567075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2060567075 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.2227017226 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 2096936393 ps |
| CPU time | 107.98 seconds |
| Started | Jul 27 08:33:42 PM PDT 24 |
| Finished | Jul 27 08:35:30 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-52d96c83-add8-4871-bf8d-dc49b8125e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227017226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .2227017226 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.556360517 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 44045046963 ps |
| CPU time | 703.08 seconds |
| Started | Jul 27 08:33:41 PM PDT 24 |
| Finished | Jul 27 08:45:24 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-5fd5cb4b-2348-42be-9550-a423c84789b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556360517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_d evice_slow_rsp.556360517 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4071101193 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 426566163 ps |
| CPU time | 18.67 seconds |
| Started | Jul 27 08:33:56 PM PDT 24 |
| Finished | Jul 27 08:34:15 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-2dfc775d-1b85-4d68-9ead-7b49cef0c041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071101193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.4071101193 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.1117750967 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 211049217 ps |
| CPU time | 22.44 seconds |
| Started | Jul 27 08:33:38 PM PDT 24 |
| Finished | Jul 27 08:34:01 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-f645aabd-5e91-4348-9c6e-a0502f8b845b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117750967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1117750967 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.2129936483 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 247351190 ps |
| CPU time | 27.96 seconds |
| Started | Jul 27 08:33:37 PM PDT 24 |
| Finished | Jul 27 08:34:05 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-d8daf922-e1cc-45ba-8b11-39ae6a81e718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129936483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.2129936483 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3502236791 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 98751089705 ps |
| CPU time | 1069.28 seconds |
| Started | Jul 27 08:33:39 PM PDT 24 |
| Finished | Jul 27 08:51:28 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-30ae6eba-ca56-4465-a0d4-3239bc4e1913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502236791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3502236791 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2026350036 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 20036318270 ps |
| CPU time | 361.59 seconds |
| Started | Jul 27 08:33:40 PM PDT 24 |
| Finished | Jul 27 08:39:42 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-7034dcfa-7468-411f-8200-59a740e0c65b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026350036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2026350036 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.661473909 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 279882974 ps |
| CPU time | 26.82 seconds |
| Started | Jul 27 08:33:38 PM PDT 24 |
| Finished | Jul 27 08:34:04 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-0bce4b7b-3637-4ebf-b910-32c11e585f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661473909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela ys.661473909 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1994792724 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 2131261035 ps |
| CPU time | 65.64 seconds |
| Started | Jul 27 08:33:39 PM PDT 24 |
| Finished | Jul 27 08:34:45 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-fc4b3015-78ed-4ec5-878f-8f9768d18848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994792724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1994792724 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.1870196204 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 246026376 ps |
| CPU time | 11.24 seconds |
| Started | Jul 27 08:33:32 PM PDT 24 |
| Finished | Jul 27 08:33:43 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-a9667163-d35c-42ed-8099-1f1775d44992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870196204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1870196204 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1008685424 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 9252393649 ps |
| CPU time | 100.85 seconds |
| Started | Jul 27 08:33:31 PM PDT 24 |
| Finished | Jul 27 08:35:12 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8a2ca208-7fa3-4032-8643-92234b17d3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008685424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1008685424 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2825085489 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 4892769709 ps |
| CPU time | 78.5 seconds |
| Started | Jul 27 08:33:31 PM PDT 24 |
| Finished | Jul 27 08:34:50 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-d1ebda1f-d1cc-4d6f-92d5-0e951bccbf00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825085489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2825085489 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2799378178 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 41025492 ps |
| CPU time | 6.15 seconds |
| Started | Jul 27 08:33:31 PM PDT 24 |
| Finished | Jul 27 08:33:38 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-c90aebd7-bb80-469e-956f-53b814b78a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799378178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2799378178 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1067749584 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 1828894160 ps |
| CPU time | 98.16 seconds |
| Started | Jul 27 08:33:51 PM PDT 24 |
| Finished | Jul 27 08:35:29 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-88f5329d-b0e4-4628-92b1-300da754933e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067749584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1067749584 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3643942803 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 2530396126 ps |
| CPU time | 207.44 seconds |
| Started | Jul 27 08:33:51 PM PDT 24 |
| Finished | Jul 27 08:37:19 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-4257037b-a1aa-447f-b463-20df7f7f0a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643942803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3643942803 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2812704346 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 16572786 ps |
| CPU time | 18.92 seconds |
| Started | Jul 27 08:33:53 PM PDT 24 |
| Finished | Jul 27 08:34:12 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-06f91786-ff9c-40ff-8750-6a968bfea71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812704346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2812704346 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1109241437 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 1197030880 ps |
| CPU time | 311.38 seconds |
| Started | Jul 27 08:33:50 PM PDT 24 |
| Finished | Jul 27 08:39:01 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-c6568f79-7af0-4139-a327-f66e3c4dfb39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109241437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.1109241437 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.380401515 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 1404775996 ps |
| CPU time | 59.44 seconds |
| Started | Jul 27 08:33:53 PM PDT 24 |
| Finished | Jul 27 08:34:52 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-49990303-dd6a-41f2-8ff5-fd160c169b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380401515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.380401515 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3801334173 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 10453425445 ps |
| CPU time | 950.56 seconds |
| Started | Jul 27 08:34:06 PM PDT 24 |
| Finished | Jul 27 08:49:57 PM PDT 24 |
| Peak memory | 652548 kb |
| Host | smart-1ad81526-a7fa-4501-9321-634f5bd91e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801334173 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.3801334173 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.157251100 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 5254158460 ps |
| CPU time | 644.27 seconds |
| Started | Jul 27 08:34:06 PM PDT 24 |
| Finished | Jul 27 08:44:50 PM PDT 24 |
| Peak memory | 599072 kb |
| Host | smart-22b25796-6508-42b1-84b4-f423d172ffb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157251100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.157251100 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3664268930 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 31717610726 ps |
| CPU time | 3703.32 seconds |
| Started | Jul 27 08:33:49 PM PDT 24 |
| Finished | Jul 27 09:35:33 PM PDT 24 |
| Peak memory | 593080 kb |
| Host | smart-39557248-6b57-4db2-97b3-82d6e6a93a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664268930 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.3664268930 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.1865951247 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3286068200 ps |
| CPU time | 213.32 seconds |
| Started | Jul 27 08:33:50 PM PDT 24 |
| Finished | Jul 27 08:37:24 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-35c5c7e1-aea6-41a8-8d39-354e39c861c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865951247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1865951247 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.461340267 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 12766917 ps |
| CPU time | 5.53 seconds |
| Started | Jul 27 08:34:00 PM PDT 24 |
| Finished | Jul 27 08:34:06 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-ac6e7a2b-6f71-4d63-bbbc-8e0b4a58dde2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461340267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device. 461340267 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3300973766 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 35139045917 ps |
| CPU time | 574.05 seconds |
| Started | Jul 27 08:33:58 PM PDT 24 |
| Finished | Jul 27 08:43:32 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-7ea436b9-4dff-4109-ab19-e07ea69d526f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300973766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3300973766 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1579182103 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 87628791 ps |
| CPU time | 12.78 seconds |
| Started | Jul 27 08:34:05 PM PDT 24 |
| Finished | Jul 27 08:34:18 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-0b4c1ee0-b85b-4ec0-aded-1491d07e1d06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579182103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1579182103 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.853942356 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 2056682254 ps |
| CPU time | 79.34 seconds |
| Started | Jul 27 08:33:57 PM PDT 24 |
| Finished | Jul 27 08:35:16 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-686c2e1a-1bfc-4bb7-b0c3-b5b90cdf4322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853942356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.853942356 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.4056163318 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 1235949986 ps |
| CPU time | 42.24 seconds |
| Started | Jul 27 08:33:56 PM PDT 24 |
| Finished | Jul 27 08:34:38 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5f16e28f-863b-4544-a8f3-9810d56fd85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056163318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.4056163318 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.51596199 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 23188790253 ps |
| CPU time | 244.65 seconds |
| Started | Jul 27 08:33:56 PM PDT 24 |
| Finished | Jul 27 08:38:01 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-006ba32b-16a3-45f3-880b-076704a9f35f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51596199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.51596199 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.730870943 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 9791695842 ps |
| CPU time | 163.06 seconds |
| Started | Jul 27 08:33:58 PM PDT 24 |
| Finished | Jul 27 08:36:41 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-f96d73f3-2533-45ef-aef9-be08ab6ee3f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730870943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.730870943 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1061626811 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 269973932 ps |
| CPU time | 28.59 seconds |
| Started | Jul 27 08:33:58 PM PDT 24 |
| Finished | Jul 27 08:34:27 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-ece34a4e-5a9f-4796-a738-84e8289d021b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061626811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1061626811 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.1899451560 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 104960691 ps |
| CPU time | 11.27 seconds |
| Started | Jul 27 08:33:56 PM PDT 24 |
| Finished | Jul 27 08:34:07 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-00e3a0f0-cdf7-4827-acb9-086ee89a93a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899451560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1899451560 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3003070404 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 54916441 ps |
| CPU time | 6.94 seconds |
| Started | Jul 27 08:34:05 PM PDT 24 |
| Finished | Jul 27 08:34:12 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-bcedd177-409e-479a-a744-5026489e6679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003070404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3003070404 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2673418589 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 9988380319 ps |
| CPU time | 104.29 seconds |
| Started | Jul 27 08:34:05 PM PDT 24 |
| Finished | Jul 27 08:35:50 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-2c021f6c-c4c2-48b8-9984-22fec8a00734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673418589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2673418589 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1285199043 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 5462614067 ps |
| CPU time | 91.28 seconds |
| Started | Jul 27 08:33:59 PM PDT 24 |
| Finished | Jul 27 08:35:30 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-d15f27b4-396a-4b29-9376-652c81465f79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285199043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1285199043 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1410129420 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 54797361 ps |
| CPU time | 7.39 seconds |
| Started | Jul 27 08:33:56 PM PDT 24 |
| Finished | Jul 27 08:34:04 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-18d4e08a-e12a-4cff-aad3-7bcce4589451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410129420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.1410129420 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.1478948353 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 2021027545 ps |
| CPU time | 200.5 seconds |
| Started | Jul 27 08:34:07 PM PDT 24 |
| Finished | Jul 27 08:37:28 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-938808a3-92a1-4050-882a-f2d17c0de561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478948353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1478948353 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3061769223 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 2512881669 ps |
| CPU time | 88.66 seconds |
| Started | Jul 27 08:34:05 PM PDT 24 |
| Finished | Jul 27 08:35:34 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-8a4c8d99-535e-4c8d-b83a-b29878865771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061769223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3061769223 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3879302737 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 786515441 ps |
| CPU time | 357.47 seconds |
| Started | Jul 27 08:34:10 PM PDT 24 |
| Finished | Jul 27 08:40:08 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-1825169f-eb4f-4a5b-9909-9644728de549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879302737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.3879302737 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1577323556 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3952578830 ps |
| CPU time | 421.64 seconds |
| Started | Jul 27 08:34:05 PM PDT 24 |
| Finished | Jul 27 08:41:07 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-ab8bcafc-560c-4aa0-8ca8-90ef1f3f9da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577323556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1577323556 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1504975723 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 245394236 ps |
| CPU time | 12.62 seconds |
| Started | Jul 27 08:34:03 PM PDT 24 |
| Finished | Jul 27 08:34:15 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-1fffdf58-06dd-4bf1-9e0b-191ab7a30cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504975723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1504975723 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2155334196 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6099788564 ps |
| CPU time | 489.08 seconds |
| Started | Jul 27 08:34:25 PM PDT 24 |
| Finished | Jul 27 08:42:34 PM PDT 24 |
| Peak memory | 637292 kb |
| Host | smart-40f0a841-8768-4d25-860a-8e1c45b6e51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155334196 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.2155334196 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2704523793 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 4534825959 ps |
| CPU time | 474.02 seconds |
| Started | Jul 27 08:34:22 PM PDT 24 |
| Finished | Jul 27 08:42:16 PM PDT 24 |
| Peak memory | 596576 kb |
| Host | smart-cbad5056-5b30-449a-8122-ec95646cca9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704523793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2704523793 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1364807829 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4302092435 ps |
| CPU time | 267.65 seconds |
| Started | Jul 27 08:34:17 PM PDT 24 |
| Finished | Jul 27 08:38:44 PM PDT 24 |
| Peak memory | 603460 kb |
| Host | smart-bf759683-1596-4f41-96bb-c0ccc7c93650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364807829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1364807829 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.4089840223 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 215902721 ps |
| CPU time | 12.06 seconds |
| Started | Jul 27 08:34:15 PM PDT 24 |
| Finished | Jul 27 08:34:27 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-28235e42-ad9d-4f44-8e9f-756641d79d40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089840223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .4089840223 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.812348590 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 81827950791 ps |
| CPU time | 1501.48 seconds |
| Started | Jul 27 08:34:22 PM PDT 24 |
| Finished | Jul 27 08:59:24 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-6bab7ea1-d4ac-4258-b4d0-bc27b7ffd30f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812348590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_d evice_slow_rsp.812348590 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2074084624 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 139912717 ps |
| CPU time | 18.45 seconds |
| Started | Jul 27 08:34:24 PM PDT 24 |
| Finished | Jul 27 08:34:43 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-d1f293c3-dee5-4105-9f20-0989b35d3eea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074084624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.2074084624 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.2429128115 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 284801329 ps |
| CPU time | 28.36 seconds |
| Started | Jul 27 08:34:21 PM PDT 24 |
| Finished | Jul 27 08:34:50 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-9a044f37-f26f-400b-994b-825807be49ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429128115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2429128115 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.3500643937 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 708858132 ps |
| CPU time | 30.86 seconds |
| Started | Jul 27 08:34:14 PM PDT 24 |
| Finished | Jul 27 08:34:45 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-13431bc7-7f99-461d-bcd4-017114d61f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500643937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3500643937 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2318755593 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 31564578106 ps |
| CPU time | 336.55 seconds |
| Started | Jul 27 08:34:14 PM PDT 24 |
| Finished | Jul 27 08:39:51 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-191bc820-e528-40fb-b5cc-69dc9fb17ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318755593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2318755593 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2226577205 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 46675042446 ps |
| CPU time | 818.15 seconds |
| Started | Jul 27 08:34:18 PM PDT 24 |
| Finished | Jul 27 08:47:57 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-c88e4b44-70e2-4ea2-bbef-256650e8681e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226577205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2226577205 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.617110158 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 419362771 ps |
| CPU time | 41.05 seconds |
| Started | Jul 27 08:34:14 PM PDT 24 |
| Finished | Jul 27 08:34:55 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-b2ef03e5-e4db-45d0-b190-2464f2971208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617110158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.617110158 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.1400406454 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 2264322880 ps |
| CPU time | 67.65 seconds |
| Started | Jul 27 08:34:21 PM PDT 24 |
| Finished | Jul 27 08:35:29 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d8d1706d-7305-4e3a-936b-3ec77e4d53b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400406454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1400406454 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.3322948505 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 45278649 ps |
| CPU time | 6.94 seconds |
| Started | Jul 27 08:34:17 PM PDT 24 |
| Finished | Jul 27 08:34:24 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-06a7b2bc-463f-43c2-84e3-c66bb97e17e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322948505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3322948505 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2100663214 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 9771955723 ps |
| CPU time | 113.59 seconds |
| Started | Jul 27 08:34:17 PM PDT 24 |
| Finished | Jul 27 08:36:10 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-7856c40c-f962-43e6-859b-f0ffbffa5dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100663214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2100663214 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1943842270 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 5764586965 ps |
| CPU time | 102.21 seconds |
| Started | Jul 27 08:34:15 PM PDT 24 |
| Finished | Jul 27 08:35:57 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-b1a92bef-204d-4d1c-a624-0ccd4c3a2ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943842270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1943842270 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3499174628 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 48611173 ps |
| CPU time | 7.09 seconds |
| Started | Jul 27 08:34:18 PM PDT 24 |
| Finished | Jul 27 08:34:26 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-e9d35ac1-80cf-4792-b24e-b5ddeed6eee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499174628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3499174628 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.4195231858 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 11625923809 ps |
| CPU time | 523.34 seconds |
| Started | Jul 27 08:34:27 PM PDT 24 |
| Finished | Jul 27 08:43:10 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-dbe338c8-b547-4c24-9688-507e6ac89d1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195231858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4195231858 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.4187383216 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 21586066939 ps |
| CPU time | 822.68 seconds |
| Started | Jul 27 08:34:21 PM PDT 24 |
| Finished | Jul 27 08:48:04 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-a7468f28-dfdb-49a8-823a-0343daa64ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187383216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.4187383216 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.15633079 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 11706491531 ps |
| CPU time | 723.04 seconds |
| Started | Jul 27 08:34:21 PM PDT 24 |
| Finished | Jul 27 08:46:24 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-5b80394f-4a11-4b5c-821d-eb57feda6ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_w ith_rand_reset.15633079 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2497011663 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 11815482031 ps |
| CPU time | 616.78 seconds |
| Started | Jul 27 08:34:21 PM PDT 24 |
| Finished | Jul 27 08:44:38 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-05943fad-24d0-4977-bfa4-18f51b07011b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497011663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.2497011663 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.8153830 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 155633531 ps |
| CPU time | 20.31 seconds |
| Started | Jul 27 08:34:24 PM PDT 24 |
| Finished | Jul 27 08:34:45 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-c12fdcbc-6de5-44c0-891c-ee770919884f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8153830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.8153830 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.4004236889 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 7077225952 ps |
| CPU time | 511.14 seconds |
| Started | Jul 27 08:34:46 PM PDT 24 |
| Finished | Jul 27 08:43:17 PM PDT 24 |
| Peak memory | 638044 kb |
| Host | smart-75e3bde6-063f-4cbc-be07-0ab8bb122590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004236889 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.4004236889 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.2641140201 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 3938837875 ps |
| CPU time | 395.55 seconds |
| Started | Jul 27 08:34:47 PM PDT 24 |
| Finished | Jul 27 08:41:23 PM PDT 24 |
| Peak memory | 598896 kb |
| Host | smart-0c588c56-a16b-47db-aecd-1141d7047ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641140201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.2641140201 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3600427288 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 31999117246 ps |
| CPU time | 3565.47 seconds |
| Started | Jul 27 08:34:25 PM PDT 24 |
| Finished | Jul 27 09:33:51 PM PDT 24 |
| Peak memory | 593316 kb |
| Host | smart-145f1162-2c75-4fc5-b58e-3d49a1330c17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600427288 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3600427288 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.899319883 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2905891149 ps |
| CPU time | 202.3 seconds |
| Started | Jul 27 08:34:33 PM PDT 24 |
| Finished | Jul 27 08:37:55 PM PDT 24 |
| Peak memory | 603452 kb |
| Host | smart-783b176c-926f-43af-ba02-89dfc1a55a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899319883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.899319883 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.4113400638 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 414662543 ps |
| CPU time | 33.28 seconds |
| Started | Jul 27 08:34:42 PM PDT 24 |
| Finished | Jul 27 08:35:15 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-bce0ac8b-ede5-4fd1-be7f-ab3e3f9b6e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113400638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .4113400638 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3065196063 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 81276213340 ps |
| CPU time | 1462.02 seconds |
| Started | Jul 27 08:34:40 PM PDT 24 |
| Finished | Jul 27 08:59:02 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e197052c-dbcf-44ea-8ebb-b913de0fb2bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065196063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3065196063 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.214387609 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 60696095 ps |
| CPU time | 7.03 seconds |
| Started | Jul 27 08:34:40 PM PDT 24 |
| Finished | Jul 27 08:34:47 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-602a84a6-8bba-4f50-b9dd-8bf5797e3aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214387609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .214387609 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2556617005 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 79058212 ps |
| CPU time | 9.73 seconds |
| Started | Jul 27 08:34:39 PM PDT 24 |
| Finished | Jul 27 08:34:49 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-823ee507-8a58-4aa5-8e2f-7c9bf0c5b668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556617005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2556617005 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.3546829023 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 502192995 ps |
| CPU time | 45.73 seconds |
| Started | Jul 27 08:34:31 PM PDT 24 |
| Finished | Jul 27 08:35:17 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d23e2373-e912-47c8-b45f-07b59bbec33c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546829023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3546829023 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.78380191 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 71498947191 ps |
| CPU time | 725.65 seconds |
| Started | Jul 27 08:34:31 PM PDT 24 |
| Finished | Jul 27 08:46:37 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-def13d47-a8e4-4fa4-91e5-41963d9d4090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78380191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.78380191 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1336977672 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 48818833120 ps |
| CPU time | 876.07 seconds |
| Started | Jul 27 08:34:31 PM PDT 24 |
| Finished | Jul 27 08:49:07 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a570ae8a-8b9d-4cfe-a4f0-179c470aa6ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336977672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1336977672 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.257523574 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 95306977 ps |
| CPU time | 13.83 seconds |
| Started | Jul 27 08:34:34 PM PDT 24 |
| Finished | Jul 27 08:34:47 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-298f9f7a-c294-4a6d-9e6d-d6344537c817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257523574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_dela ys.257523574 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.276999542 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 903356738 ps |
| CPU time | 32.42 seconds |
| Started | Jul 27 08:34:41 PM PDT 24 |
| Finished | Jul 27 08:35:13 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-792a73a0-73a2-40ae-9aee-497991c73fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276999542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.276999542 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.145104747 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 51189535 ps |
| CPU time | 7 seconds |
| Started | Jul 27 08:34:32 PM PDT 24 |
| Finished | Jul 27 08:34:39 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-6c692697-5ed0-4b4e-a5b4-12a27f116912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145104747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.145104747 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1832525258 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 5049356399 ps |
| CPU time | 54.62 seconds |
| Started | Jul 27 08:34:29 PM PDT 24 |
| Finished | Jul 27 08:35:24 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-afead22f-f434-4fa7-9c05-0f21a9e3d93c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832525258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1832525258 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.657457609 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 4220535549 ps |
| CPU time | 77.96 seconds |
| Started | Jul 27 08:34:33 PM PDT 24 |
| Finished | Jul 27 08:35:51 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-17675ff3-efb1-4e15-82f4-bdc18132c8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657457609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.657457609 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1164154821 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 45953088 ps |
| CPU time | 6.85 seconds |
| Started | Jul 27 08:34:28 PM PDT 24 |
| Finished | Jul 27 08:34:35 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-e0ddbcfa-3241-4f6e-b9b8-e90429b99782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164154821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1164154821 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.3435042176 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 2615841456 ps |
| CPU time | 104.6 seconds |
| Started | Jul 27 08:34:41 PM PDT 24 |
| Finished | Jul 27 08:36:26 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-d94d36a0-46f5-4547-bbef-6ab55ab12f54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435042176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3435042176 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1680792700 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 1348259103 ps |
| CPU time | 106.17 seconds |
| Started | Jul 27 08:34:51 PM PDT 24 |
| Finished | Jul 27 08:36:38 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-8daf9a32-e900-443c-bbf0-578f8ae978f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680792700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1680792700 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2200687438 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 3023845693 ps |
| CPU time | 457.03 seconds |
| Started | Jul 27 08:34:42 PM PDT 24 |
| Finished | Jul 27 08:42:19 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-02c7dbbe-ac80-4aac-91ae-b12b0004a347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200687438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.2200687438 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.4006812621 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 1562977281 ps |
| CPU time | 190.41 seconds |
| Started | Jul 27 08:34:49 PM PDT 24 |
| Finished | Jul 27 08:38:00 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-9526ae7b-25bc-4b54-b838-c91a4fd2725a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006812621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.4006812621 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3860248988 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 613621242 ps |
| CPU time | 32.77 seconds |
| Started | Jul 27 08:34:41 PM PDT 24 |
| Finished | Jul 27 08:35:14 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-ad251cbf-2f17-4755-b695-0af5fc919a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860248988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3860248988 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2186440479 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 5017041090 ps |
| CPU time | 430.24 seconds |
| Started | Jul 27 08:35:08 PM PDT 24 |
| Finished | Jul 27 08:42:18 PM PDT 24 |
| Peak memory | 644176 kb |
| Host | smart-78393251-735c-4459-bbbe-1e69bd0f2e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186440479 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.2186440479 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1678944301 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 5652074690 ps |
| CPU time | 584.41 seconds |
| Started | Jul 27 08:35:09 PM PDT 24 |
| Finished | Jul 27 08:44:54 PM PDT 24 |
| Peak memory | 598636 kb |
| Host | smart-023d3c8a-b437-4024-8e0e-7a47d613b4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678944301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1678944301 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2912962391 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 29305218471 ps |
| CPU time | 3607.89 seconds |
| Started | Jul 27 08:34:53 PM PDT 24 |
| Finished | Jul 27 09:35:01 PM PDT 24 |
| Peak memory | 593028 kb |
| Host | smart-22c3b412-fa34-4143-93e3-d5d647171e6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912962391 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2912962391 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.2125382129 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4279164254 ps |
| CPU time | 415.59 seconds |
| Started | Jul 27 08:34:49 PM PDT 24 |
| Finished | Jul 27 08:41:44 PM PDT 24 |
| Peak memory | 598352 kb |
| Host | smart-3c0a5f5a-3273-4149-840c-d471cb991b5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125382129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2125382129 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.3622132499 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 550912270 ps |
| CPU time | 25.55 seconds |
| Started | Jul 27 08:34:53 PM PDT 24 |
| Finished | Jul 27 08:35:19 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-2523a9db-d9d3-4fdd-937f-86c0ccaa4128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622132499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .3622132499 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.953089275 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 118482089429 ps |
| CPU time | 2160.51 seconds |
| Started | Jul 27 08:35:04 PM PDT 24 |
| Finished | Jul 27 09:11:05 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-fdfac616-3ad4-4a76-bb5d-8ab5cc673591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953089275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.953089275 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.4140215409 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 855693616 ps |
| CPU time | 34.72 seconds |
| Started | Jul 27 08:35:00 PM PDT 24 |
| Finished | Jul 27 08:35:35 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-39a4b654-d001-4071-93e9-f20200000e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140215409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.4140215409 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.1667005796 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 403375978 ps |
| CPU time | 40.74 seconds |
| Started | Jul 27 08:34:57 PM PDT 24 |
| Finished | Jul 27 08:35:37 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-4861b816-4521-4f55-94b2-cc9d25ea6ad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667005796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1667005796 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.2458175268 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1096340126 ps |
| CPU time | 37.91 seconds |
| Started | Jul 27 08:34:49 PM PDT 24 |
| Finished | Jul 27 08:35:27 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ba4058b6-aed7-4ea2-b4ae-26eb7cafc5f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458175268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2458175268 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2557588642 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 58162294694 ps |
| CPU time | 656.4 seconds |
| Started | Jul 27 08:34:48 PM PDT 24 |
| Finished | Jul 27 08:45:44 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-92a349ed-531a-4363-91c9-ce05496073b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557588642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2557588642 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1706213224 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 18256333701 ps |
| CPU time | 327.33 seconds |
| Started | Jul 27 08:34:49 PM PDT 24 |
| Finished | Jul 27 08:40:16 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-98471d6b-c65a-4d37-89c9-d39a61388f30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706213224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1706213224 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2253776756 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 394296508 ps |
| CPU time | 42.15 seconds |
| Started | Jul 27 08:34:48 PM PDT 24 |
| Finished | Jul 27 08:35:30 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-a7b60491-24dc-4382-9539-d7f91ba87501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253776756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2253776756 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.2091414849 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 598295029 ps |
| CPU time | 44.4 seconds |
| Started | Jul 27 08:35:03 PM PDT 24 |
| Finished | Jul 27 08:35:48 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-0b0399ef-ce2f-4787-b292-ff9ab1a850b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091414849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2091414849 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.1483612724 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 195886234 ps |
| CPU time | 9.75 seconds |
| Started | Jul 27 08:34:48 PM PDT 24 |
| Finished | Jul 27 08:34:57 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-9d3732b8-9be4-489a-8e1a-cc5ae384a039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483612724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1483612724 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.360512933 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 9901618337 ps |
| CPU time | 105.09 seconds |
| Started | Jul 27 08:34:47 PM PDT 24 |
| Finished | Jul 27 08:36:32 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-ad7eec1e-04c7-4157-a33a-65f5136d6e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360512933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.360512933 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1918613404 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 5907441269 ps |
| CPU time | 96.95 seconds |
| Started | Jul 27 08:34:50 PM PDT 24 |
| Finished | Jul 27 08:36:27 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-cfc80474-4079-4099-b552-6edaaa273f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918613404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1918613404 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2554332918 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 49025025 ps |
| CPU time | 6.83 seconds |
| Started | Jul 27 08:34:48 PM PDT 24 |
| Finished | Jul 27 08:34:55 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-82d9c274-41c4-4f94-b171-41fff448fdb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554332918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.2554332918 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1141087650 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 5962406948 ps |
| CPU time | 266.68 seconds |
| Started | Jul 27 08:35:00 PM PDT 24 |
| Finished | Jul 27 08:39:27 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-588875f2-f956-45e3-af9b-0185abf16b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141087650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1141087650 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.819454799 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 2237983329 ps |
| CPU time | 216.64 seconds |
| Started | Jul 27 08:34:57 PM PDT 24 |
| Finished | Jul 27 08:38:34 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-48ae708b-4623-4716-84c5-91f72d00b9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819454799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.819454799 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3415691577 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 11425927346 ps |
| CPU time | 561.18 seconds |
| Started | Jul 27 08:35:04 PM PDT 24 |
| Finished | Jul 27 08:44:25 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-bc0931d9-e0ec-427d-9381-5ae7d7c4faec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415691577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3415691577 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1233967421 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 44905713 ps |
| CPU time | 8.28 seconds |
| Started | Jul 27 08:34:55 PM PDT 24 |
| Finished | Jul 27 08:35:04 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-9fd1b47a-9604-473f-9f37-9d4f32e9d413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233967421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1233967421 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.922858520 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 56129761950 ps |
| CPU time | 8810.8 seconds |
| Started | Jul 27 08:25:46 PM PDT 24 |
| Finished | Jul 27 10:52:38 PM PDT 24 |
| Peak memory | 642840 kb |
| Host | smart-bc46ce4d-f018-4ea4-8873-825eb0ba0d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922858520 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.922858520 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1008205952 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 15131800655 ps |
| CPU time | 1456.65 seconds |
| Started | Jul 27 08:25:43 PM PDT 24 |
| Finished | Jul 27 08:50:00 PM PDT 24 |
| Peak memory | 593080 kb |
| Host | smart-e9eab687-55ee-46c2-8bc8-5ccf9696557f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008205952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1008205952 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.3666201307 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 5939922324 ps |
| CPU time | 698.23 seconds |
| Started | Jul 27 08:26:05 PM PDT 24 |
| Finished | Jul 27 08:37:44 PM PDT 24 |
| Peak memory | 599060 kb |
| Host | smart-a363e344-6ea5-4411-9bfd-d8f4dbb1a41e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666201307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.3666201307 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.128991299 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 14254957211 ps |
| CPU time | 534.54 seconds |
| Started | Jul 27 08:25:18 PM PDT 24 |
| Finished | Jul 27 08:34:12 PM PDT 24 |
| Peak memory | 591120 kb |
| Host | smart-37d6123a-5d75-4a40-a14d-1cc676bd0fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128991299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .chip_prim_tl_access.128991299 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.168603649 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 13777076148 ps |
| CPU time | 477.88 seconds |
| Started | Jul 27 08:26:20 PM PDT 24 |
| Finished | Jul 27 08:34:18 PM PDT 24 |
| Peak memory | 598256 kb |
| Host | smart-d680308a-a7d3-4ad8-9200-e796206509a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168603649 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.chip_rv_dm_lc_disabled.168603649 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.839518462 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 16792887954 ps |
| CPU time | 1992.55 seconds |
| Started | Jul 27 08:25:46 PM PDT 24 |
| Finished | Jul 27 08:58:59 PM PDT 24 |
| Peak memory | 593084 kb |
| Host | smart-0a44617d-5dd3-4664-ad3a-1fd22f363940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839518462 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.839518462 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.137615289 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 178755259 ps |
| CPU time | 21.06 seconds |
| Started | Jul 27 08:25:39 PM PDT 24 |
| Finished | Jul 27 08:26:00 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-3b17a8c9-89fc-4ce9-acbd-1b46fb45363b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137615289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.137615289 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3603226587 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 16227986154 ps |
| CPU time | 281.2 seconds |
| Started | Jul 27 08:25:39 PM PDT 24 |
| Finished | Jul 27 08:30:20 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-a50e4c8d-9627-4bae-a164-5d2d02c9b7fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603226587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.3603226587 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.883169956 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 318146245 ps |
| CPU time | 43.91 seconds |
| Started | Jul 27 08:25:47 PM PDT 24 |
| Finished | Jul 27 08:26:31 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-112f0a53-6e78-4283-b23f-82b1576a56b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883169956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr. 883169956 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3732109123 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 868725825 ps |
| CPU time | 33.67 seconds |
| Started | Jul 27 08:25:47 PM PDT 24 |
| Finished | Jul 27 08:26:20 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-6e95719f-18de-4b92-8c63-b65ac22a447c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732109123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3732109123 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.3695114890 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 90311093 ps |
| CPU time | 13.68 seconds |
| Started | Jul 27 08:25:35 PM PDT 24 |
| Finished | Jul 27 08:25:49 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-154ffdb8-8a5d-4386-9999-d105200c236b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695114890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3695114890 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2566896429 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 91423456271 ps |
| CPU time | 950.23 seconds |
| Started | Jul 27 08:25:30 PM PDT 24 |
| Finished | Jul 27 08:41:20 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-cf247b4a-6805-45c2-904a-cf40b83d5df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566896429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2566896429 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2389828761 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 32675784348 ps |
| CPU time | 598.55 seconds |
| Started | Jul 27 08:25:36 PM PDT 24 |
| Finished | Jul 27 08:35:35 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-7d83d6e2-3fea-4e0f-9641-621e543b6359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389828761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2389828761 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2664655812 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 199846182 ps |
| CPU time | 23.1 seconds |
| Started | Jul 27 08:25:40 PM PDT 24 |
| Finished | Jul 27 08:26:04 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-68afa573-86f7-4b80-9fe8-bff61e70b144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664655812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.2664655812 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1628268092 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 505608027 ps |
| CPU time | 38.21 seconds |
| Started | Jul 27 08:25:38 PM PDT 24 |
| Finished | Jul 27 08:26:16 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-ec5b0c11-800c-42af-b339-77e6446a9e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628268092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1628268092 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.3640887319 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 220522020 ps |
| CPU time | 9.85 seconds |
| Started | Jul 27 08:25:23 PM PDT 24 |
| Finished | Jul 27 08:25:33 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f818da7c-61af-4481-9332-3fec53b33529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640887319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3640887319 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3917770817 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 4880165065 ps |
| CPU time | 56.78 seconds |
| Started | Jul 27 08:25:23 PM PDT 24 |
| Finished | Jul 27 08:26:20 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-3de468f4-0f2b-475d-bef3-8d4ff32a2524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917770817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3917770817 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.628385686 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 3847600516 ps |
| CPU time | 67.98 seconds |
| Started | Jul 27 08:25:41 PM PDT 24 |
| Finished | Jul 27 08:26:49 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-51b9eeaf-6b0c-4f0f-8cb2-b3def0072b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628385686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.628385686 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2107735661 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 35914869 ps |
| CPU time | 6.44 seconds |
| Started | Jul 27 08:25:22 PM PDT 24 |
| Finished | Jul 27 08:25:28 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-1fc7fbda-662a-4b5b-90c2-32aa24dd76d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107735661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .2107735661 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2911613422 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 15636028165 ps |
| CPU time | 706.7 seconds |
| Started | Jul 27 08:26:08 PM PDT 24 |
| Finished | Jul 27 08:37:55 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-478df3dc-42fd-43a4-9e67-965fa15a8cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911613422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2911613422 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1709725286 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 8013332975 ps |
| CPU time | 303.04 seconds |
| Started | Jul 27 08:25:58 PM PDT 24 |
| Finished | Jul 27 08:31:01 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-1afb61b2-42e8-4d8d-95c1-1a242ad27ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709725286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1709725286 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.890956645 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 468192621 ps |
| CPU time | 200.58 seconds |
| Started | Jul 27 08:26:05 PM PDT 24 |
| Finished | Jul 27 08:29:26 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-ee57d499-33d7-4d68-898f-04295a2ca467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890956645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.890956645 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2192401454 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 104641531 ps |
| CPU time | 13.66 seconds |
| Started | Jul 27 08:26:06 PM PDT 24 |
| Finished | Jul 27 08:26:20 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-d69a435d-7e91-4f3b-848a-29278bd58f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192401454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2192401454 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2807150905 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 587527147 ps |
| CPU time | 29.7 seconds |
| Started | Jul 27 08:25:49 PM PDT 24 |
| Finished | Jul 27 08:26:19 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-789e9a5b-abe8-436f-b6ed-33fcbf484a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807150905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2807150905 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.4119559601 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2791826388 ps |
| CPU time | 166.81 seconds |
| Started | Jul 27 08:35:06 PM PDT 24 |
| Finished | Jul 27 08:37:53 PM PDT 24 |
| Peak memory | 598340 kb |
| Host | smart-205c5a93-582b-4b48-ab31-c20ab310f119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119559601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.4119559601 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.1019289546 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 873387865 ps |
| CPU time | 37.39 seconds |
| Started | Jul 27 08:35:21 PM PDT 24 |
| Finished | Jul 27 08:35:58 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-f426f419-992a-4ca0-919e-1da6255bacc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019289546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .1019289546 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.153990600 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 157913797565 ps |
| CPU time | 2855.47 seconds |
| Started | Jul 27 08:35:19 PM PDT 24 |
| Finished | Jul 27 09:22:55 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-b6202fde-a4e8-46d0-b0ba-4423baf242dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153990600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d evice_slow_rsp.153990600 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3859738613 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 132674278 ps |
| CPU time | 16.64 seconds |
| Started | Jul 27 08:35:20 PM PDT 24 |
| Finished | Jul 27 08:35:37 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-51407fbe-1377-49cc-9509-d1bbe3e8972d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859738613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3859738613 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.4205037848 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 2107549712 ps |
| CPU time | 92.53 seconds |
| Started | Jul 27 08:35:18 PM PDT 24 |
| Finished | Jul 27 08:36:50 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-5251f6d8-10d0-4599-8f6e-19ee483610db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205037848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4205037848 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2684151586 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 119020239 ps |
| CPU time | 15.05 seconds |
| Started | Jul 27 08:35:15 PM PDT 24 |
| Finished | Jul 27 08:35:30 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-007e97d9-d62b-43ef-a075-b1744c506a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684151586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2684151586 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1129370047 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 82165654475 ps |
| CPU time | 857.42 seconds |
| Started | Jul 27 08:35:18 PM PDT 24 |
| Finished | Jul 27 08:49:35 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-105dbb91-3d5a-4edf-be10-0fbd0cc4ed16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129370047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1129370047 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3782745682 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 28735913416 ps |
| CPU time | 487.43 seconds |
| Started | Jul 27 08:35:15 PM PDT 24 |
| Finished | Jul 27 08:43:22 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-761d7c5e-a5b7-43dd-a5bf-7b0552857bcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782745682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3782745682 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3389515804 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 37116835 ps |
| CPU time | 6.29 seconds |
| Started | Jul 27 08:35:20 PM PDT 24 |
| Finished | Jul 27 08:35:26 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-cf3bcadc-7f24-42be-9716-72fc076f5621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389515804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.3389515804 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.359075713 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 397239669 ps |
| CPU time | 27.88 seconds |
| Started | Jul 27 08:35:18 PM PDT 24 |
| Finished | Jul 27 08:35:46 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-a2e2343a-5340-4942-bfd1-2993d98539a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359075713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.359075713 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.2091530628 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 218780848 ps |
| CPU time | 9.39 seconds |
| Started | Jul 27 08:35:08 PM PDT 24 |
| Finished | Jul 27 08:35:18 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-f2ac596f-a669-47fd-8b60-609007981f79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091530628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2091530628 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2029545175 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 7828735271 ps |
| CPU time | 82.86 seconds |
| Started | Jul 27 08:35:07 PM PDT 24 |
| Finished | Jul 27 08:36:30 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-274fec2b-abec-4d86-b809-8762d8fcca25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029545175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2029545175 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2381383960 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 5982572134 ps |
| CPU time | 101.33 seconds |
| Started | Jul 27 08:35:15 PM PDT 24 |
| Finished | Jul 27 08:36:57 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-e3c5fd71-a5eb-4092-8d5f-1ba564892498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381383960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2381383960 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2645384668 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 47895744 ps |
| CPU time | 6.8 seconds |
| Started | Jul 27 08:35:09 PM PDT 24 |
| Finished | Jul 27 08:35:16 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-1d45ccc1-7bec-4e28-a547-52341308276a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645384668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2645384668 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3292393115 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1291866121 ps |
| CPU time | 54.49 seconds |
| Started | Jul 27 08:35:17 PM PDT 24 |
| Finished | Jul 27 08:36:12 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-e6bf1883-c7af-4433-9685-e79d24588138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292393115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3292393115 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.875475048 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 898857143 ps |
| CPU time | 82.14 seconds |
| Started | Jul 27 08:35:17 PM PDT 24 |
| Finished | Jul 27 08:36:39 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-d2482cde-5f99-4972-9ec3-54fef0606283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875475048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.875475048 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.395903412 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 374973384 ps |
| CPU time | 109.65 seconds |
| Started | Jul 27 08:35:16 PM PDT 24 |
| Finished | Jul 27 08:37:06 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-fe83fcdc-2f9e-4b13-a7c3-37719bbf1080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395903412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.395903412 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.523034386 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 824367188 ps |
| CPU time | 33.94 seconds |
| Started | Jul 27 08:35:17 PM PDT 24 |
| Finished | Jul 27 08:35:51 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-df09db8e-6b43-4977-9ed1-6635ed356d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523034386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.523034386 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2227323029 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 574878551 ps |
| CPU time | 51.52 seconds |
| Started | Jul 27 08:35:31 PM PDT 24 |
| Finished | Jul 27 08:36:22 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f8f03a23-5cd8-43c2-be7d-9586e4d5d120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227323029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2227323029 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2132144916 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 84808484286 ps |
| CPU time | 1522.51 seconds |
| Started | Jul 27 08:35:25 PM PDT 24 |
| Finished | Jul 27 09:00:48 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-fe3b9c11-dc90-4c95-ae04-7bef4caa613c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132144916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.2132144916 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1321991519 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 147167378 ps |
| CPU time | 18.72 seconds |
| Started | Jul 27 08:35:30 PM PDT 24 |
| Finished | Jul 27 08:35:50 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-9a921d88-0ef1-4e6b-8b03-2a5a8f76fd07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321991519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1321991519 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2385942 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 32486459 ps |
| CPU time | 6.26 seconds |
| Started | Jul 27 08:35:28 PM PDT 24 |
| Finished | Jul 27 08:35:34 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-05a10974-1261-4d3b-8f27-f1a844cad8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2385942 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2818114919 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 1105750607 ps |
| CPU time | 38.5 seconds |
| Started | Jul 27 08:35:24 PM PDT 24 |
| Finished | Jul 27 08:36:03 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-55a6732c-079f-408b-af3d-3f59a9375ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818114919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2818114919 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.46980782 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 67591552198 ps |
| CPU time | 724.55 seconds |
| Started | Jul 27 08:35:26 PM PDT 24 |
| Finished | Jul 27 08:47:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ff33ce94-8516-43c6-89d5-fd7a77699e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46980782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.46980782 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1992152941 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 45987910016 ps |
| CPU time | 800.34 seconds |
| Started | Jul 27 08:35:26 PM PDT 24 |
| Finished | Jul 27 08:48:46 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-320f3425-095a-4a18-959e-b29cc11d6155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992152941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1992152941 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.866764975 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 517799406 ps |
| CPU time | 47.28 seconds |
| Started | Jul 27 08:35:27 PM PDT 24 |
| Finished | Jul 27 08:36:15 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-09dfa2ee-81fe-412b-8310-7b8377867e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866764975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_dela ys.866764975 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.2947836094 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 1696214869 ps |
| CPU time | 57.67 seconds |
| Started | Jul 27 08:35:24 PM PDT 24 |
| Finished | Jul 27 08:36:21 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-8d098aec-6f84-4197-ac60-85ec278ac3cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947836094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2947836094 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3364588533 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 225276441 ps |
| CPU time | 10.93 seconds |
| Started | Jul 27 08:35:18 PM PDT 24 |
| Finished | Jul 27 08:35:29 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0cdb5617-0c9a-4cb6-8036-bb1e8160897f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364588533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3364588533 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2003527911 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 8505208111 ps |
| CPU time | 90.5 seconds |
| Started | Jul 27 08:35:24 PM PDT 24 |
| Finished | Jul 27 08:36:55 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-f0a4ccf1-a554-4a93-9ba7-72bc62ef12b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003527911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2003527911 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3267823701 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 5912493425 ps |
| CPU time | 97.5 seconds |
| Started | Jul 27 08:35:23 PM PDT 24 |
| Finished | Jul 27 08:37:01 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-ef517f00-80a6-4c24-b22c-da9f8194e324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267823701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3267823701 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1467297609 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 51569451 ps |
| CPU time | 7.32 seconds |
| Started | Jul 27 08:35:20 PM PDT 24 |
| Finished | Jul 27 08:35:28 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-a47606b9-2d9e-44b7-bdea-98143292f1f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467297609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1467297609 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.393938137 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 14350358809 ps |
| CPU time | 593.28 seconds |
| Started | Jul 27 08:35:24 PM PDT 24 |
| Finished | Jul 27 08:45:18 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-01d3f0b7-ec4a-4cc8-81f7-9ed16501c9b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393938137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.393938137 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3459943012 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 8821334501 ps |
| CPU time | 332.86 seconds |
| Started | Jul 27 08:35:32 PM PDT 24 |
| Finished | Jul 27 08:41:05 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-6dd56cbb-0ca0-4113-8578-9555eceef8fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459943012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3459943012 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3727819661 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 301309680 ps |
| CPU time | 164.22 seconds |
| Started | Jul 27 08:35:33 PM PDT 24 |
| Finished | Jul 27 08:38:17 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-ae21c771-75cb-4406-9531-170230d1a936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727819661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.3727819661 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.3430411951 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 343123080 ps |
| CPU time | 92.87 seconds |
| Started | Jul 27 08:35:32 PM PDT 24 |
| Finished | Jul 27 08:37:05 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-ca00dbe9-f90c-4673-96d8-4ab4f8029a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430411951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.3430411951 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1250551561 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 202500836 ps |
| CPU time | 23.87 seconds |
| Started | Jul 27 08:35:25 PM PDT 24 |
| Finished | Jul 27 08:35:49 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-999c6a29-1446-4fe5-b0c4-d506f57c1522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250551561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1250551561 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.17192055 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2985828660 ps |
| CPU time | 187.1 seconds |
| Started | Jul 27 08:35:34 PM PDT 24 |
| Finished | Jul 27 08:38:41 PM PDT 24 |
| Peak memory | 598372 kb |
| Host | smart-e56a1ec1-6578-4166-bcec-0f3043ce3545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17192055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.17192055 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.471166602 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 348105911 ps |
| CPU time | 29.67 seconds |
| Started | Jul 27 08:35:45 PM PDT 24 |
| Finished | Jul 27 08:36:15 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-80271eeb-8a1c-4d47-b218-0fca6d6e3a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471166602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 471166602 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3309472973 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 152160330183 ps |
| CPU time | 2580.73 seconds |
| Started | Jul 27 08:35:43 PM PDT 24 |
| Finished | Jul 27 09:18:44 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-e228658e-6a4c-4593-af8c-51cd03e0c5e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309472973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.3309472973 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1724712980 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 303457010 ps |
| CPU time | 32.07 seconds |
| Started | Jul 27 08:35:45 PM PDT 24 |
| Finished | Jul 27 08:36:17 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-38d50a27-41ea-4ef0-b4b5-bb08d2f3ace2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724712980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1724712980 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.571573853 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 468962632 ps |
| CPU time | 38.03 seconds |
| Started | Jul 27 08:35:45 PM PDT 24 |
| Finished | Jul 27 08:36:23 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-ca4de292-b284-4ada-86e2-e5a628a86263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571573853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.571573853 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.979630910 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 204312745 ps |
| CPU time | 11.34 seconds |
| Started | Jul 27 08:35:33 PM PDT 24 |
| Finished | Jul 27 08:35:45 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-2130e649-1534-45d4-820a-d082bb1aa9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979630910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.979630910 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1961999850 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 87346112336 ps |
| CPU time | 907.15 seconds |
| Started | Jul 27 08:35:34 PM PDT 24 |
| Finished | Jul 27 08:50:42 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a137edbb-930a-49c5-9c91-8185b0b5cef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961999850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1961999850 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.855283343 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 59844321661 ps |
| CPU time | 1094.6 seconds |
| Started | Jul 27 08:35:41 PM PDT 24 |
| Finished | Jul 27 08:53:56 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-7ef63b4c-dd2f-400b-ae77-9bc80a444cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855283343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.855283343 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.4150469079 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 424910027 ps |
| CPU time | 39.11 seconds |
| Started | Jul 27 08:35:35 PM PDT 24 |
| Finished | Jul 27 08:36:14 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-ab038e70-74ea-40da-80d8-f2613731791b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150469079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.4150469079 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.818912403 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 260610566 ps |
| CPU time | 23.78 seconds |
| Started | Jul 27 08:35:45 PM PDT 24 |
| Finished | Jul 27 08:36:09 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-cc3dddb1-2915-4efd-bda9-9e51b818fa0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818912403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.818912403 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.994748755 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 254566033 ps |
| CPU time | 10.82 seconds |
| Started | Jul 27 08:35:32 PM PDT 24 |
| Finished | Jul 27 08:35:43 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-10aa04dc-5e9c-43db-82e3-cf07929ee488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994748755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.994748755 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1743779829 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 10506243872 ps |
| CPU time | 117.91 seconds |
| Started | Jul 27 08:35:34 PM PDT 24 |
| Finished | Jul 27 08:37:32 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-b2f9c215-fc85-4582-bc5c-fc79ac884645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743779829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1743779829 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.336844988 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 4685440490 ps |
| CPU time | 79.68 seconds |
| Started | Jul 27 08:35:34 PM PDT 24 |
| Finished | Jul 27 08:36:54 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-10fe6661-3ea9-4c08-9af1-9d27a07df5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336844988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.336844988 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4108388792 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 46863733 ps |
| CPU time | 6.45 seconds |
| Started | Jul 27 08:35:33 PM PDT 24 |
| Finished | Jul 27 08:35:40 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-93d26093-1577-44fd-ad70-02d29874a435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108388792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4108388792 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.1694328780 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1440929973 ps |
| CPU time | 137.45 seconds |
| Started | Jul 27 08:35:42 PM PDT 24 |
| Finished | Jul 27 08:38:00 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-c041de17-189d-482f-8197-cad3cbdcd086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694328780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1694328780 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.4273457662 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 6929152225 ps |
| CPU time | 280.6 seconds |
| Started | Jul 27 08:35:43 PM PDT 24 |
| Finished | Jul 27 08:40:23 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-4427d761-65ba-487c-84b9-1b55c650c2d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273457662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4273457662 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3066130732 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 375246779 ps |
| CPU time | 169.57 seconds |
| Started | Jul 27 08:35:41 PM PDT 24 |
| Finished | Jul 27 08:38:31 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-fd6a73fc-c825-41aa-ae67-fec857f4a8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066130732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.3066130732 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1455105535 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 27793112 ps |
| CPU time | 22.78 seconds |
| Started | Jul 27 08:35:42 PM PDT 24 |
| Finished | Jul 27 08:36:05 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-a16d9f29-9e21-453e-90d2-13443b0e6045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455105535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.1455105535 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2151575243 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 137598265 ps |
| CPU time | 20.15 seconds |
| Started | Jul 27 08:35:41 PM PDT 24 |
| Finished | Jul 27 08:36:02 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-bdf7b03b-be88-4345-8566-7d64db15b13f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151575243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2151575243 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1454037172 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3159305696 ps |
| CPU time | 178.39 seconds |
| Started | Jul 27 08:35:49 PM PDT 24 |
| Finished | Jul 27 08:38:48 PM PDT 24 |
| Peak memory | 603480 kb |
| Host | smart-47600441-21d4-4c15-9261-4e1d5dc8c46e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454037172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1454037172 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.571623927 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 92754554 ps |
| CPU time | 10.47 seconds |
| Started | Jul 27 08:35:53 PM PDT 24 |
| Finished | Jul 27 08:36:03 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-043785b2-86d8-487f-ae14-1868e3547e65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571623927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device. 571623927 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3719932277 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 53530316130 ps |
| CPU time | 938.42 seconds |
| Started | Jul 27 08:35:53 PM PDT 24 |
| Finished | Jul 27 08:51:31 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-0e830770-fc72-4708-8a0a-3142442fa4c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719932277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.3719932277 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.4202655218 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 794042155 ps |
| CPU time | 34.68 seconds |
| Started | Jul 27 08:36:02 PM PDT 24 |
| Finished | Jul 27 08:36:36 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-d9172d0e-d959-4b81-adc4-6db87fbaedde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202655218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.4202655218 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1170404087 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1561123009 ps |
| CPU time | 54.92 seconds |
| Started | Jul 27 08:35:59 PM PDT 24 |
| Finished | Jul 27 08:36:54 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-cb6a1999-7e9f-462a-abb0-ffbd532d3b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170404087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1170404087 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2849592210 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 120983712 ps |
| CPU time | 15.42 seconds |
| Started | Jul 27 08:35:49 PM PDT 24 |
| Finished | Jul 27 08:36:04 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-cb8c11af-1b12-4fa0-92a2-9738231dd373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849592210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2849592210 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.1016857331 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 96727091627 ps |
| CPU time | 1002.89 seconds |
| Started | Jul 27 08:35:50 PM PDT 24 |
| Finished | Jul 27 08:52:33 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-59c0f4b2-d459-4747-ba68-97dcfe381e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016857331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1016857331 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.2465903622 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 40302949635 ps |
| CPU time | 717.55 seconds |
| Started | Jul 27 08:35:50 PM PDT 24 |
| Finished | Jul 27 08:47:48 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-84681ffb-34bf-4ced-85d3-45e112d8d658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465903622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.2465903622 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1080463526 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 377443688 ps |
| CPU time | 32.92 seconds |
| Started | Jul 27 08:35:50 PM PDT 24 |
| Finished | Jul 27 08:36:23 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-742efc5e-fa8b-43ad-9701-dfeea5651cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080463526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1080463526 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3806973642 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 261951226 ps |
| CPU time | 22.08 seconds |
| Started | Jul 27 08:35:57 PM PDT 24 |
| Finished | Jul 27 08:36:20 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-13d35fcc-a5bf-4875-b34b-f1c19853fe82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806973642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3806973642 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.2741788609 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 208201357 ps |
| CPU time | 10.41 seconds |
| Started | Jul 27 08:35:48 PM PDT 24 |
| Finished | Jul 27 08:35:59 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-af28bf52-fbcf-4916-b246-e8786b138704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741788609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2741788609 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1883887101 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 7928472820 ps |
| CPU time | 87.68 seconds |
| Started | Jul 27 08:35:52 PM PDT 24 |
| Finished | Jul 27 08:37:19 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-2c029210-8c64-44e4-a093-7b66ed068792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883887101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1883887101 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.521604930 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 4944410110 ps |
| CPU time | 85.7 seconds |
| Started | Jul 27 08:35:52 PM PDT 24 |
| Finished | Jul 27 08:37:18 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-f5def12d-40f0-49b5-9ba1-d313ae11e29b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521604930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.521604930 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.802941253 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 43071924 ps |
| CPU time | 6.91 seconds |
| Started | Jul 27 08:35:54 PM PDT 24 |
| Finished | Jul 27 08:36:01 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-f20fefe9-9e02-4f6f-b100-bedd54ab01e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802941253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .802941253 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2132731952 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 2734169252 ps |
| CPU time | 218.18 seconds |
| Started | Jul 27 08:36:01 PM PDT 24 |
| Finished | Jul 27 08:39:39 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-91dd1245-534a-4bcb-a2fe-4bfa78b9d8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132731952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2132731952 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2244273846 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1946238339 ps |
| CPU time | 181.25 seconds |
| Started | Jul 27 08:36:00 PM PDT 24 |
| Finished | Jul 27 08:39:01 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-2812eecb-8010-4167-8ae7-f3b7b801958d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244273846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.2244273846 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.3494414068 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 564999795 ps |
| CPU time | 26.37 seconds |
| Started | Jul 27 08:35:59 PM PDT 24 |
| Finished | Jul 27 08:36:25 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-ac217b06-46db-45b1-967e-26ddfda503a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494414068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.3494414068 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.1243874686 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 381687301 ps |
| CPU time | 18.77 seconds |
| Started | Jul 27 08:36:08 PM PDT 24 |
| Finished | Jul 27 08:36:26 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-224c2720-ea29-4542-a1ae-c6e15fb4f69b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243874686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .1243874686 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.712647467 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 28577133975 ps |
| CPU time | 507.75 seconds |
| Started | Jul 27 08:36:06 PM PDT 24 |
| Finished | Jul 27 08:44:34 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-f660e35d-0f60-4320-8fce-1e14b7f8e818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712647467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_d evice_slow_rsp.712647467 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.399433636 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 126158641 ps |
| CPU time | 15.78 seconds |
| Started | Jul 27 08:36:13 PM PDT 24 |
| Finished | Jul 27 08:36:29 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-603908a1-246b-4232-b106-6b303b42888a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399433636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr .399433636 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.3136556841 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 1823866337 ps |
| CPU time | 66 seconds |
| Started | Jul 27 08:36:09 PM PDT 24 |
| Finished | Jul 27 08:37:15 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-03980a93-f8a1-4651-b7ce-54b37eb3e4bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136556841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3136556841 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.3408514558 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 932905912 ps |
| CPU time | 37.8 seconds |
| Started | Jul 27 08:35:59 PM PDT 24 |
| Finished | Jul 27 08:36:37 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-bcfc5cd3-0d5b-4b2c-b6aa-2991048d4f23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408514558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3408514558 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3430530914 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 38320066717 ps |
| CPU time | 390.41 seconds |
| Started | Jul 27 08:36:09 PM PDT 24 |
| Finished | Jul 27 08:42:40 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-88a192f1-89dd-4487-8cc3-941e2089b74d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430530914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3430530914 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.383810621 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 21837994478 ps |
| CPU time | 383.52 seconds |
| Started | Jul 27 08:36:07 PM PDT 24 |
| Finished | Jul 27 08:42:30 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-80e85b31-f40e-4f22-9a32-b44d63c158e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383810621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.383810621 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.1441905415 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 112434751 ps |
| CPU time | 12.73 seconds |
| Started | Jul 27 08:35:58 PM PDT 24 |
| Finished | Jul 27 08:36:11 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-16844d4a-eb2a-406a-8872-c83dce74e346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441905415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.1441905415 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.2894898854 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 2711391230 ps |
| CPU time | 82.93 seconds |
| Started | Jul 27 08:36:08 PM PDT 24 |
| Finished | Jul 27 08:37:31 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-d3131ee0-6f68-457c-8e53-7e24f2d845f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894898854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2894898854 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1760958947 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 228628832 ps |
| CPU time | 10.85 seconds |
| Started | Jul 27 08:36:01 PM PDT 24 |
| Finished | Jul 27 08:36:11 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-3227d67b-8a9d-4b87-b7c6-ae8c897ab019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760958947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1760958947 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3257677615 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 8610824139 ps |
| CPU time | 90.32 seconds |
| Started | Jul 27 08:36:00 PM PDT 24 |
| Finished | Jul 27 08:37:30 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-2608c5c7-830b-4030-93fc-088496359f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257677615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3257677615 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.1305865494 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 4919637738 ps |
| CPU time | 86.84 seconds |
| Started | Jul 27 08:35:57 PM PDT 24 |
| Finished | Jul 27 08:37:24 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-593e0cd0-18f9-4972-bbb3-78be80fcf7a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305865494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1305865494 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.565090810 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 52308796 ps |
| CPU time | 7.14 seconds |
| Started | Jul 27 08:35:58 PM PDT 24 |
| Finished | Jul 27 08:36:05 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-f78a223f-b4cd-45be-8ddd-c180eca70462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565090810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .565090810 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.4058119001 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4224726653 ps |
| CPU time | 166.56 seconds |
| Started | Jul 27 08:36:07 PM PDT 24 |
| Finished | Jul 27 08:38:53 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-e6bd0952-cd4b-441a-8125-6abcf7f3d169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058119001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4058119001 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3481881464 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 302767244 ps |
| CPU time | 22.72 seconds |
| Started | Jul 27 08:36:15 PM PDT 24 |
| Finished | Jul 27 08:36:38 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-9f16c696-7351-4cd0-bdda-e51096dd0d09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481881464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3481881464 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2586417635 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 366525635 ps |
| CPU time | 138.51 seconds |
| Started | Jul 27 08:36:16 PM PDT 24 |
| Finished | Jul 27 08:38:35 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-75772751-76a5-46fe-84f7-328f0d45a4c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586417635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2586417635 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1876140226 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 304364777 ps |
| CPU time | 70.34 seconds |
| Started | Jul 27 08:36:15 PM PDT 24 |
| Finished | Jul 27 08:37:25 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-fb1282d4-8cc5-4427-994b-d301cea87e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876140226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1876140226 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2144082350 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 268446686 ps |
| CPU time | 34.62 seconds |
| Started | Jul 27 08:36:06 PM PDT 24 |
| Finished | Jul 27 08:36:41 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-eebcb248-a614-43b9-8080-8a8e41d3a453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144082350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2144082350 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.174430008 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 891481457 ps |
| CPU time | 80.63 seconds |
| Started | Jul 27 08:36:26 PM PDT 24 |
| Finished | Jul 27 08:37:47 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-f5f9adc8-2b2c-490d-bef8-37f30e1f1f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174430008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 174430008 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.3513848541 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 54771524400 ps |
| CPU time | 916.47 seconds |
| Started | Jul 27 08:36:25 PM PDT 24 |
| Finished | Jul 27 08:51:42 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-56a42cc8-b831-4dc9-a0ef-fbbb5b54e809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513848541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.3513848541 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2369670567 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 140895539 ps |
| CPU time | 17.74 seconds |
| Started | Jul 27 08:36:31 PM PDT 24 |
| Finished | Jul 27 08:36:48 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-af1cd1f9-2066-411b-b8bd-c1e55224dcf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369670567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2369670567 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.3476639202 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 141210727 ps |
| CPU time | 15.18 seconds |
| Started | Jul 27 08:36:34 PM PDT 24 |
| Finished | Jul 27 08:36:49 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-bff59eda-aec5-4a76-adde-5691230c9a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476639202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3476639202 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.1144499029 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 594524049 ps |
| CPU time | 59.58 seconds |
| Started | Jul 27 08:36:25 PM PDT 24 |
| Finished | Jul 27 08:37:25 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-91d27bfe-9034-46bb-9570-242a26d36a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144499029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1144499029 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3917502574 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 38819934024 ps |
| CPU time | 405.06 seconds |
| Started | Jul 27 08:36:27 PM PDT 24 |
| Finished | Jul 27 08:43:12 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-50eb8d06-6796-4264-bbf8-723f5aac0e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917502574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3917502574 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.4035263924 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 4495510044 ps |
| CPU time | 73.15 seconds |
| Started | Jul 27 08:36:25 PM PDT 24 |
| Finished | Jul 27 08:37:38 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-92519ac0-75a0-41d3-8839-1e8035f85ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035263924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4035263924 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2030163760 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 458577062 ps |
| CPU time | 47.83 seconds |
| Started | Jul 27 08:36:27 PM PDT 24 |
| Finished | Jul 27 08:37:15 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-a66f75fe-c795-4831-9e3b-2c35ae9e1f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030163760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2030163760 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3320249364 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 265841729 ps |
| CPU time | 22.68 seconds |
| Started | Jul 27 08:36:25 PM PDT 24 |
| Finished | Jul 27 08:36:48 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8f73f0b0-ed94-470b-9837-86350d4ac1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320249364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3320249364 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.2466336656 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 50272248 ps |
| CPU time | 6.58 seconds |
| Started | Jul 27 08:36:15 PM PDT 24 |
| Finished | Jul 27 08:36:22 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-5a7cc1f2-3fcd-48f6-a3a7-4197f2041c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466336656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2466336656 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.922523809 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 7311799954 ps |
| CPU time | 77.94 seconds |
| Started | Jul 27 08:36:24 PM PDT 24 |
| Finished | Jul 27 08:37:42 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-ea53fadd-5eaf-418d-8c79-57f48246318f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922523809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.922523809 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1227738466 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 5283181151 ps |
| CPU time | 91.59 seconds |
| Started | Jul 27 08:36:24 PM PDT 24 |
| Finished | Jul 27 08:37:55 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-7bd830c5-a9c2-41ad-8eda-4bc8ffacc515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227738466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1227738466 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.4142163231 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 46049126 ps |
| CPU time | 6.9 seconds |
| Started | Jul 27 08:36:24 PM PDT 24 |
| Finished | Jul 27 08:36:31 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-6f9d2ab9-2706-4244-9eca-c7eb30934802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142163231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.4142163231 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1965791703 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 18337943110 ps |
| CPU time | 685.34 seconds |
| Started | Jul 27 08:36:32 PM PDT 24 |
| Finished | Jul 27 08:47:58 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-9958dad7-29fd-4c8c-89eb-a175036c09d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965791703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1965791703 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3507010616 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 14898828453 ps |
| CPU time | 594.84 seconds |
| Started | Jul 27 08:36:33 PM PDT 24 |
| Finished | Jul 27 08:46:28 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-845111ee-8fe2-418d-9600-d15f9e460f62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507010616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3507010616 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.4268537811 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 5921409852 ps |
| CPU time | 458.2 seconds |
| Started | Jul 27 08:36:33 PM PDT 24 |
| Finished | Jul 27 08:44:11 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-d1d1d10e-4606-4307-b7bf-0beb1ffbc4dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268537811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.4268537811 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2533232098 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 304892748 ps |
| CPU time | 135.92 seconds |
| Started | Jul 27 08:36:35 PM PDT 24 |
| Finished | Jul 27 08:38:51 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-6b142664-d420-485f-a236-d29eeb4038ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533232098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2533232098 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3719211293 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 212214262 ps |
| CPU time | 13.4 seconds |
| Started | Jul 27 08:36:34 PM PDT 24 |
| Finished | Jul 27 08:36:47 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e8f400af-6e8d-4a5e-94cb-b7ecdccac9a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719211293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3719211293 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.2154152845 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3157760480 ps |
| CPU time | 200.19 seconds |
| Started | Jul 27 08:36:32 PM PDT 24 |
| Finished | Jul 27 08:39:52 PM PDT 24 |
| Peak memory | 598260 kb |
| Host | smart-e8ff4236-afc9-4665-b965-1024174214e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154152845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2154152845 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.546516534 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1343885455 ps |
| CPU time | 56.49 seconds |
| Started | Jul 27 08:36:42 PM PDT 24 |
| Finished | Jul 27 08:37:39 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-0eb1f217-af19-4de4-9147-bf873e2d128a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546516534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device. 546516534 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1662265266 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 100510033329 ps |
| CPU time | 1713.32 seconds |
| Started | Jul 27 08:36:41 PM PDT 24 |
| Finished | Jul 27 09:05:15 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-722f17a2-b0d3-43f4-b129-d6186746727d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662265266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.1662265266 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3631445659 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 276113676 ps |
| CPU time | 30.16 seconds |
| Started | Jul 27 08:36:45 PM PDT 24 |
| Finished | Jul 27 08:37:16 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-28b2b7eb-f3e0-44c3-9eaf-aa8dbb2cccc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631445659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.3631445659 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.1791303484 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 476386549 ps |
| CPU time | 44.86 seconds |
| Started | Jul 27 08:36:43 PM PDT 24 |
| Finished | Jul 27 08:37:28 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-26009fd3-a759-4a06-841d-52c5f09f127b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791303484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1791303484 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1192272136 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 407806929 ps |
| CPU time | 18.34 seconds |
| Started | Jul 27 08:36:45 PM PDT 24 |
| Finished | Jul 27 08:37:04 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-58ff65dc-493a-4ebb-a7c3-7c85e5035796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192272136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1192272136 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4266345471 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 99806240339 ps |
| CPU time | 1081.11 seconds |
| Started | Jul 27 08:36:41 PM PDT 24 |
| Finished | Jul 27 08:54:42 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-d71b9384-b43d-48d6-bf6b-6339c51e78db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266345471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4266345471 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1847374003 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 5740595694 ps |
| CPU time | 99.21 seconds |
| Started | Jul 27 08:36:40 PM PDT 24 |
| Finished | Jul 27 08:38:19 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-65b5b64f-410a-4bd2-b7be-f7f93f89b83c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847374003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1847374003 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1710340114 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 519629735 ps |
| CPU time | 46.45 seconds |
| Started | Jul 27 08:36:40 PM PDT 24 |
| Finished | Jul 27 08:37:27 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f707c963-b327-440e-8dfa-9e2cf9a2b0c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710340114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.1710340114 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1143556361 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1936922574 ps |
| CPU time | 61.04 seconds |
| Started | Jul 27 08:36:40 PM PDT 24 |
| Finished | Jul 27 08:37:42 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-5e318231-40f3-4d16-9eb1-84e7da06e7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143556361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1143556361 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.2531762770 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 202598490 ps |
| CPU time | 9.61 seconds |
| Started | Jul 27 08:36:35 PM PDT 24 |
| Finished | Jul 27 08:36:45 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-923ac161-642b-4aa0-aa7c-cf6ba32c0513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531762770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.2531762770 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3945985077 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 9630040925 ps |
| CPU time | 114.65 seconds |
| Started | Jul 27 08:36:33 PM PDT 24 |
| Finished | Jul 27 08:38:28 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4433550f-66a9-417e-990a-6ba7513e4643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945985077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3945985077 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.2364781022 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 6381749842 ps |
| CPU time | 113.71 seconds |
| Started | Jul 27 08:36:46 PM PDT 24 |
| Finished | Jul 27 08:38:39 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b382981a-1ad6-482d-bdd9-1abad88f9bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364781022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2364781022 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1688688631 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 45873909 ps |
| CPU time | 6.41 seconds |
| Started | Jul 27 08:36:37 PM PDT 24 |
| Finished | Jul 27 08:36:43 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-85741e75-db41-47d2-b18a-07c0e5d29a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688688631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1688688631 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2923080724 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3031295119 ps |
| CPU time | 276.98 seconds |
| Started | Jul 27 08:36:40 PM PDT 24 |
| Finished | Jul 27 08:41:17 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-504fa77c-0e16-4c31-989b-5cb928094677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923080724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2923080724 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1351895185 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 4065982017 ps |
| CPU time | 348.75 seconds |
| Started | Jul 27 08:36:41 PM PDT 24 |
| Finished | Jul 27 08:42:30 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-bb14059c-7cb2-4234-8237-193679660440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351895185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1351895185 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.488742967 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 1841955745 ps |
| CPU time | 204.79 seconds |
| Started | Jul 27 08:36:41 PM PDT 24 |
| Finished | Jul 27 08:40:06 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-cd35e3db-894c-4bc7-82ed-932f1c86440b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488742967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_rand_reset.488742967 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.650176560 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 3678758198 ps |
| CPU time | 228.89 seconds |
| Started | Jul 27 08:36:39 PM PDT 24 |
| Finished | Jul 27 08:40:28 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-78bfdc42-6fd0-4b7b-98b3-533da749ec07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650176560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.650176560 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2163585192 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 1366343355 ps |
| CPU time | 67.69 seconds |
| Started | Jul 27 08:36:42 PM PDT 24 |
| Finished | Jul 27 08:37:50 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-390965f8-d1c5-4a12-ae0c-ebc20ea5bd12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163585192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2163585192 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.3031056203 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 2882926394 ps |
| CPU time | 101.59 seconds |
| Started | Jul 27 08:36:43 PM PDT 24 |
| Finished | Jul 27 08:38:25 PM PDT 24 |
| Peak memory | 598268 kb |
| Host | smart-7543ce38-554b-4331-a47f-833e5b5579f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031056203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3031056203 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.580987098 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 2306633220 ps |
| CPU time | 92.52 seconds |
| Started | Jul 27 08:36:48 PM PDT 24 |
| Finished | Jul 27 08:38:20 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-48100b1d-b5d1-41af-a670-99db3313e422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580987098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device. 580987098 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.178263352 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 77530607848 ps |
| CPU time | 1380.1 seconds |
| Started | Jul 27 08:36:51 PM PDT 24 |
| Finished | Jul 27 08:59:51 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-9af4eb90-efcf-467a-a6de-f34273d3e736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178263352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d evice_slow_rsp.178263352 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3848981707 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 1087854940 ps |
| CPU time | 45.33 seconds |
| Started | Jul 27 08:36:49 PM PDT 24 |
| Finished | Jul 27 08:37:35 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-953217cb-1414-4edf-9d0c-a6a3d8e92f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848981707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.3848981707 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.1863511050 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 268069615 ps |
| CPU time | 25.09 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:37:23 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-46bf8b8a-7b2a-4839-9076-9f25f0c6e7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863511050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1863511050 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3162430285 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 499657423 ps |
| CPU time | 47.18 seconds |
| Started | Jul 27 08:36:44 PM PDT 24 |
| Finished | Jul 27 08:37:31 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-bcb25acb-bd7b-4f83-9f30-8d5acf25682a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162430285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3162430285 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.1329432451 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 36880207580 ps |
| CPU time | 387.1 seconds |
| Started | Jul 27 08:36:56 PM PDT 24 |
| Finished | Jul 27 08:43:23 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-a32356c0-dee5-452f-8dde-0f16e532470b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329432451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1329432451 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.4205302095 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 45229208032 ps |
| CPU time | 816.9 seconds |
| Started | Jul 27 08:36:49 PM PDT 24 |
| Finished | Jul 27 08:50:26 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-4016ffd2-b576-4704-9a1a-ac932c4bc72b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205302095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4205302095 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2394305820 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 226614425 ps |
| CPU time | 21.31 seconds |
| Started | Jul 27 08:36:39 PM PDT 24 |
| Finished | Jul 27 08:37:00 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-d5d4a6db-ab29-4926-8edd-b5734fe029e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394305820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.2394305820 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1703205317 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 918256060 ps |
| CPU time | 33.38 seconds |
| Started | Jul 27 08:36:48 PM PDT 24 |
| Finished | Jul 27 08:37:22 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d94fbbb8-69dd-4861-b985-ade274b373fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703205317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1703205317 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.1888213311 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 173972798 ps |
| CPU time | 8.6 seconds |
| Started | Jul 27 08:36:44 PM PDT 24 |
| Finished | Jul 27 08:36:52 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-f4c315f8-dc11-4aa3-b401-a5e263d166df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888213311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1888213311 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.3177673880 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 9712117846 ps |
| CPU time | 102.44 seconds |
| Started | Jul 27 08:36:41 PM PDT 24 |
| Finished | Jul 27 08:38:23 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-5922bd3f-4117-49b1-a3b5-e8c2ea86c6fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177673880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.3177673880 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3692712993 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 6541604592 ps |
| CPU time | 119.13 seconds |
| Started | Jul 27 08:36:47 PM PDT 24 |
| Finished | Jul 27 08:38:47 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-6b47b914-63fe-455c-a2fd-616eb79debd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692712993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3692712993 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1361493650 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 47233069 ps |
| CPU time | 6.45 seconds |
| Started | Jul 27 08:36:40 PM PDT 24 |
| Finished | Jul 27 08:36:47 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-50166010-fb16-42fb-9ef2-cbfd242d13ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361493650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1361493650 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2116962150 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2916067180 ps |
| CPU time | 144.36 seconds |
| Started | Jul 27 08:36:56 PM PDT 24 |
| Finished | Jul 27 08:39:21 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-5cf168b6-8543-4949-be65-41fad740779a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116962150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2116962150 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2748805175 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 1485455016 ps |
| CPU time | 54.82 seconds |
| Started | Jul 27 08:36:58 PM PDT 24 |
| Finished | Jul 27 08:37:53 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-7ca4d57b-0922-4678-b195-91a421234410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748805175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2748805175 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.143665178 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 5230578125 ps |
| CPU time | 447.02 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:44:24 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-200fbcc0-e709-4cf6-a563-b6319c2a74b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143665178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.143665178 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4156182702 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 6790962587 ps |
| CPU time | 289.39 seconds |
| Started | Jul 27 08:36:59 PM PDT 24 |
| Finished | Jul 27 08:41:48 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-4bc5ac06-07ba-4fc7-9f92-8d36808c07a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156182702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.4156182702 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.95072281 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 915035978 ps |
| CPU time | 40.68 seconds |
| Started | Jul 27 08:36:49 PM PDT 24 |
| Finished | Jul 27 08:37:29 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-93c69f78-d9da-4e62-b085-7a14fe0eafc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95072281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.95072281 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.920210856 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4283027424 ps |
| CPU time | 433.1 seconds |
| Started | Jul 27 08:36:58 PM PDT 24 |
| Finished | Jul 27 08:44:11 PM PDT 24 |
| Peak memory | 603424 kb |
| Host | smart-5a6f89a9-c4e4-4181-b024-22bdec7c016c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920210856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.920210856 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.2464127806 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 2249682638 ps |
| CPU time | 99.23 seconds |
| Started | Jul 27 08:37:01 PM PDT 24 |
| Finished | Jul 27 08:38:40 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-822a4e4a-5d90-47c0-a8ee-3ac2a0f1c3b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464127806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .2464127806 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2182069195 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 86469585425 ps |
| CPU time | 1558.82 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 09:02:56 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-b6261270-e427-43da-af66-60eb4c7f761c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182069195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.2182069195 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.3603561273 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 1293744518 ps |
| CPU time | 63.36 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:38:00 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-858cd399-b4be-48c7-8022-befde2a8ffa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603561273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.3603561273 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.1280544370 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 105535308 ps |
| CPU time | 7.16 seconds |
| Started | Jul 27 08:36:59 PM PDT 24 |
| Finished | Jul 27 08:37:07 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-d79e4c2d-cc6f-4b4e-b7af-098bdc9ee200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280544370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1280544370 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.929483851 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 380793929 ps |
| CPU time | 17.49 seconds |
| Started | Jul 27 08:36:59 PM PDT 24 |
| Finished | Jul 27 08:37:17 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5062aef6-0a2c-433e-954d-c01efd337489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929483851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.929483851 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.69676849 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 38287275359 ps |
| CPU time | 404.4 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:43:42 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-d55cc17e-93d8-46ce-89ba-5db8f3b913c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69676849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.69676849 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3059002603 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 64904358801 ps |
| CPU time | 1121.9 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:55:40 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-95a9cfa7-5c3d-4b9d-87fd-25a0aed42133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059002603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3059002603 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.612286547 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 288771669 ps |
| CPU time | 29.12 seconds |
| Started | Jul 27 08:37:00 PM PDT 24 |
| Finished | Jul 27 08:37:29 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-fd3c43f7-7b63-48af-8e2a-d7cebef69906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612286547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_dela ys.612286547 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.2887467203 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 327421282 ps |
| CPU time | 28.1 seconds |
| Started | Jul 27 08:36:59 PM PDT 24 |
| Finished | Jul 27 08:37:27 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b456c71c-8237-41c7-80af-1594f6e5ebb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887467203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.2887467203 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.1574166765 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 157363807 ps |
| CPU time | 8.53 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:37:06 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-930815f9-25e5-401c-a88c-d422dea9230b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574166765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.1574166765 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2504593490 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 8268039775 ps |
| CPU time | 90.12 seconds |
| Started | Jul 27 08:36:59 PM PDT 24 |
| Finished | Jul 27 08:38:29 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-1c14a358-4cac-4b56-8299-2e274b6f1438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504593490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2504593490 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3460369789 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 4635569117 ps |
| CPU time | 81.47 seconds |
| Started | Jul 27 08:36:58 PM PDT 24 |
| Finished | Jul 27 08:38:20 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-1b8600de-428e-48d9-891d-9a45d7a2d9eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460369789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3460369789 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3073524371 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 48020320 ps |
| CPU time | 6.72 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:37:04 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-52969d2f-b67b-409a-82ba-6b60b5c40ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073524371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3073524371 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.112065152 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 12401740029 ps |
| CPU time | 483.85 seconds |
| Started | Jul 27 08:36:57 PM PDT 24 |
| Finished | Jul 27 08:45:01 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-d3c34317-6ac6-4e4d-82d6-6eb170f11294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112065152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.112065152 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2012518848 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 735811078 ps |
| CPU time | 251.9 seconds |
| Started | Jul 27 08:37:01 PM PDT 24 |
| Finished | Jul 27 08:41:13 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-65c74da2-a500-43b9-9f5f-f84fca629782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012518848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.2012518848 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.482463540 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 5954604460 ps |
| CPU time | 340.18 seconds |
| Started | Jul 27 08:37:05 PM PDT 24 |
| Finished | Jul 27 08:42:46 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-da24456c-ad27-426f-a437-22a30d856926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482463540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_reset_error.482463540 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.2885703384 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1244376503 ps |
| CPU time | 54.31 seconds |
| Started | Jul 27 08:36:56 PM PDT 24 |
| Finished | Jul 27 08:37:50 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-6a6bb504-d873-4559-9cc2-29d81d15b5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885703384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2885703384 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3951926133 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1090412395 ps |
| CPU time | 90.15 seconds |
| Started | Jul 27 08:37:06 PM PDT 24 |
| Finished | Jul 27 08:38:36 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-e83c2322-beb4-44fd-bb82-5407026dc936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951926133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3951926133 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2288289569 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 114699197370 ps |
| CPU time | 2057.66 seconds |
| Started | Jul 27 08:37:05 PM PDT 24 |
| Finished | Jul 27 09:11:23 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-d725823a-7c97-40d8-ba14-4222ec8a77c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288289569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.2288289569 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1958988198 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 1274260015 ps |
| CPU time | 54.72 seconds |
| Started | Jul 27 08:37:16 PM PDT 24 |
| Finished | Jul 27 08:38:11 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-77b506c2-fe2c-4987-9c0c-e733d675a9be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958988198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1958988198 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.1461331885 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 94341263 ps |
| CPU time | 11.54 seconds |
| Started | Jul 27 08:37:07 PM PDT 24 |
| Finished | Jul 27 08:37:19 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-81982d4b-0512-4f6f-b953-fc6b1729f223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461331885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.1461331885 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.986765464 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 545345080 ps |
| CPU time | 47.95 seconds |
| Started | Jul 27 08:37:07 PM PDT 24 |
| Finished | Jul 27 08:37:55 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-aa71abb1-2910-4117-828c-b617058a6aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986765464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.986765464 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2208256861 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 16633112296 ps |
| CPU time | 171.77 seconds |
| Started | Jul 27 08:37:05 PM PDT 24 |
| Finished | Jul 27 08:39:57 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-a54622d8-c428-4a73-8454-9ad4d2b7ae65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208256861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2208256861 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3403658787 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 34780039943 ps |
| CPU time | 589.11 seconds |
| Started | Jul 27 08:37:06 PM PDT 24 |
| Finished | Jul 27 08:46:55 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-bff6f51a-164c-41f7-a63b-f1a4e85cd12f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403658787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3403658787 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.285485290 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 246773954 ps |
| CPU time | 25.84 seconds |
| Started | Jul 27 08:37:07 PM PDT 24 |
| Finished | Jul 27 08:37:33 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-20f5dc3d-934b-4e19-9940-805abc18f3b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285485290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela ys.285485290 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.3642745935 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 196154277 ps |
| CPU time | 18.82 seconds |
| Started | Jul 27 08:37:05 PM PDT 24 |
| Finished | Jul 27 08:37:24 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ebcdc839-aa46-49f7-b334-e6ce6b4f744d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642745935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3642745935 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.3758210279 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 203231972 ps |
| CPU time | 8.79 seconds |
| Started | Jul 27 08:37:07 PM PDT 24 |
| Finished | Jul 27 08:37:15 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-412f5f65-b26c-44d0-bac0-6b88ada6e4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758210279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3758210279 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.2357410569 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 8173049377 ps |
| CPU time | 85.63 seconds |
| Started | Jul 27 08:37:07 PM PDT 24 |
| Finished | Jul 27 08:38:32 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-1b4ce24d-6b59-4045-915b-95d61a886ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357410569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.2357410569 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.274590539 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 5031366858 ps |
| CPU time | 84.42 seconds |
| Started | Jul 27 08:37:06 PM PDT 24 |
| Finished | Jul 27 08:38:31 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-6188ed3f-a58f-4004-90ae-9104671e1834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274590539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.274590539 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3814305983 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 41484860 ps |
| CPU time | 6.74 seconds |
| Started | Jul 27 08:37:05 PM PDT 24 |
| Finished | Jul 27 08:37:12 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-f7f46a6b-47cf-4009-a0d8-b9e3c2f13bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814305983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3814305983 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.4110338918 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 13329818132 ps |
| CPU time | 559.48 seconds |
| Started | Jul 27 08:37:21 PM PDT 24 |
| Finished | Jul 27 08:46:41 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-f4214c1e-33d6-4a3a-af31-744ff8e3403e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110338918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4110338918 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2842412569 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 2758510660 ps |
| CPU time | 233.56 seconds |
| Started | Jul 27 08:37:16 PM PDT 24 |
| Finished | Jul 27 08:41:10 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-e5fbce42-73e0-4d78-9023-2fe0a9f37a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842412569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2842412569 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.830578492 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3234044438 ps |
| CPU time | 399.51 seconds |
| Started | Jul 27 08:37:17 PM PDT 24 |
| Finished | Jul 27 08:43:57 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-33e82e0f-ff09-42aa-ba90-65370c5510fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830578492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_reset_error.830578492 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2835847845 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 151654113 ps |
| CPU time | 22.38 seconds |
| Started | Jul 27 08:37:15 PM PDT 24 |
| Finished | Jul 27 08:37:38 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-0c693032-7528-44c9-bde8-596f9c75f888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835847845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2835847845 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3549998679 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 25519296632 ps |
| CPU time | 4313.69 seconds |
| Started | Jul 27 08:26:22 PM PDT 24 |
| Finished | Jul 27 09:38:16 PM PDT 24 |
| Peak memory | 593528 kb |
| Host | smart-a61c258f-6f53-48d8-84a5-7058cc291ad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549998679 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3549998679 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.170482590 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 62436989207 ps |
| CPU time | 6537.71 seconds |
| Started | Jul 27 08:26:22 PM PDT 24 |
| Finished | Jul 27 10:15:20 PM PDT 24 |
| Peak memory | 592480 kb |
| Host | smart-5d399f12-27c8-4d81-919c-37c1ec2ff8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170482590 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.170482590 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1420960338 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 12220852200 ps |
| CPU time | 916.08 seconds |
| Started | Jul 27 08:27:04 PM PDT 24 |
| Finished | Jul 27 08:42:20 PM PDT 24 |
| Peak memory | 645064 kb |
| Host | smart-5be5c119-7147-41d1-9a7e-5aecb03af17e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420960338 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.1420960338 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1640530308 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 4281457170 ps |
| CPU time | 436.9 seconds |
| Started | Jul 27 08:26:53 PM PDT 24 |
| Finished | Jul 27 08:34:10 PM PDT 24 |
| Peak memory | 598416 kb |
| Host | smart-10a70051-d8f7-4dad-8e67-1c16bee751d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640530308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1640530308 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1352836207 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 29063629871 ps |
| CPU time | 3812.77 seconds |
| Started | Jul 27 08:26:21 PM PDT 24 |
| Finished | Jul 27 09:29:54 PM PDT 24 |
| Peak memory | 593052 kb |
| Host | smart-bb7882a8-5e65-4ff3-b5fe-e9b5f8838d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352836207 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1352836207 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.1017545832 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3391065765 ps |
| CPU time | 229.49 seconds |
| Started | Jul 27 08:26:19 PM PDT 24 |
| Finished | Jul 27 08:30:09 PM PDT 24 |
| Peak memory | 603480 kb |
| Host | smart-3e72de4b-b219-4408-93ad-7669a552205b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017545832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.1017545832 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3459721411 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 1138849701 ps |
| CPU time | 111.25 seconds |
| Started | Jul 27 08:26:39 PM PDT 24 |
| Finished | Jul 27 08:28:30 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-eeeee895-9c87-4829-b932-5e5a683e52f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459721411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3459721411 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3639767409 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 105880181758 ps |
| CPU time | 1955.99 seconds |
| Started | Jul 27 08:26:36 PM PDT 24 |
| Finished | Jul 27 08:59:12 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-829a30cf-88bf-4df2-809d-bdfd8e51f07c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639767409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3639767409 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.399420797 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 635382122 ps |
| CPU time | 31.39 seconds |
| Started | Jul 27 08:26:47 PM PDT 24 |
| Finished | Jul 27 08:27:19 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-c7378bc9-6638-4988-a4bc-be541738b5c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399420797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr. 399420797 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.1753825260 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 461701275 ps |
| CPU time | 23.22 seconds |
| Started | Jul 27 08:26:53 PM PDT 24 |
| Finished | Jul 27 08:27:17 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-df10ec35-3ce4-476e-b1ef-25330257f497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753825260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1753825260 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1579995804 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 388662344 ps |
| CPU time | 41.59 seconds |
| Started | Jul 27 08:26:29 PM PDT 24 |
| Finished | Jul 27 08:27:11 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-cd9644c3-bd98-4645-a8aa-c7d99efa3807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579995804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1579995804 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.4148424713 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 80701691192 ps |
| CPU time | 898.46 seconds |
| Started | Jul 27 08:26:38 PM PDT 24 |
| Finished | Jul 27 08:41:37 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-037b569d-920a-4bfa-9f2e-4a50be512863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148424713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.4148424713 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1130656779 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 44728697961 ps |
| CPU time | 780.78 seconds |
| Started | Jul 27 08:26:36 PM PDT 24 |
| Finished | Jul 27 08:39:37 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-8bf76fc0-d709-4483-b769-d95a926f601c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130656779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1130656779 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1381669789 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 457140413 ps |
| CPU time | 49.94 seconds |
| Started | Jul 27 08:26:28 PM PDT 24 |
| Finished | Jul 27 08:27:18 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-bd8f5202-07cb-4403-87f4-843b102877c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381669789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.1381669789 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.991072603 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 535927071 ps |
| CPU time | 39.83 seconds |
| Started | Jul 27 08:26:36 PM PDT 24 |
| Finished | Jul 27 08:27:16 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-4ba57178-e67a-428c-8815-9c9e40e05d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991072603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.991072603 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.922057890 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 214042904 ps |
| CPU time | 10.59 seconds |
| Started | Jul 27 08:26:28 PM PDT 24 |
| Finished | Jul 27 08:26:38 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f1c30980-62cb-45b4-af22-f37d18f2ef63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922057890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.922057890 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.488956289 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 6147481151 ps |
| CPU time | 62.91 seconds |
| Started | Jul 27 08:26:28 PM PDT 24 |
| Finished | Jul 27 08:27:31 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-7cdb7561-1b26-47f5-8e59-7597a87909ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488956289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.488956289 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.597697120 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 5921936377 ps |
| CPU time | 104.41 seconds |
| Started | Jul 27 08:26:29 PM PDT 24 |
| Finished | Jul 27 08:28:14 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-162cc82c-f30d-465e-952c-7a81b00a35d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597697120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.597697120 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3825120070 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 45351239 ps |
| CPU time | 6.92 seconds |
| Started | Jul 27 08:26:30 PM PDT 24 |
| Finished | Jul 27 08:26:37 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-6cb9ccba-7ba8-4509-b7d4-df50feceddcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825120070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .3825120070 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2849899540 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 8234930462 ps |
| CPU time | 317.41 seconds |
| Started | Jul 27 08:26:48 PM PDT 24 |
| Finished | Jul 27 08:32:06 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-64826ce5-7704-4e9c-a880-77fc1a80acda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849899540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2849899540 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2616427843 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 5405084504 ps |
| CPU time | 208.21 seconds |
| Started | Jul 27 08:26:45 PM PDT 24 |
| Finished | Jul 27 08:30:13 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-4731279f-458d-408c-9fa8-96dd43dba88d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616427843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2616427843 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3857944618 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1295555095 ps |
| CPU time | 285.88 seconds |
| Started | Jul 27 08:28:13 PM PDT 24 |
| Finished | Jul 27 08:33:01 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-e3b316e6-5f1c-450d-8bb5-8048b1771f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857944618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.3857944618 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3945222014 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 378349768 ps |
| CPU time | 98.67 seconds |
| Started | Jul 27 08:26:46 PM PDT 24 |
| Finished | Jul 27 08:28:25 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-c8606e7c-5411-409d-8d84-971e901043c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945222014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.3945222014 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.4123072547 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 83778016 ps |
| CPU time | 7.27 seconds |
| Started | Jul 27 08:26:39 PM PDT 24 |
| Finished | Jul 27 08:26:46 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-e52399be-0dd2-4fe7-9a87-09cd740fa178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123072547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.4123072547 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.112161466 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 600923693 ps |
| CPU time | 30.23 seconds |
| Started | Jul 27 08:37:18 PM PDT 24 |
| Finished | Jul 27 08:37:48 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-90955c7c-26e5-4434-9256-dd3414aa5229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112161466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device. 112161466 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2311709016 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 174101292362 ps |
| CPU time | 2902.31 seconds |
| Started | Jul 27 08:37:15 PM PDT 24 |
| Finished | Jul 27 09:25:38 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-22a103a4-9e42-4f1a-b176-4f1c1d265a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311709016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2311709016 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2331073893 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 597153232 ps |
| CPU time | 26.02 seconds |
| Started | Jul 27 08:37:27 PM PDT 24 |
| Finished | Jul 27 08:37:53 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-9a84e5c1-8ef7-43dd-822b-085fa27fac79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331073893 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2331073893 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.516221622 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 2241706246 ps |
| CPU time | 92.24 seconds |
| Started | Jul 27 08:37:24 PM PDT 24 |
| Finished | Jul 27 08:38:56 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-80b8584a-747d-43d3-883e-45dd58edf521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516221622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.516221622 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.939531030 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 245149245 ps |
| CPU time | 25.48 seconds |
| Started | Jul 27 08:37:16 PM PDT 24 |
| Finished | Jul 27 08:37:42 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-a03c4335-de04-412f-b834-409b5aa9357c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939531030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.939531030 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1907143639 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 81047159610 ps |
| CPU time | 824.81 seconds |
| Started | Jul 27 08:37:14 PM PDT 24 |
| Finished | Jul 27 08:50:59 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-fb33358f-ada0-462c-b90c-b89a38aa87fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907143639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1907143639 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1463526291 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 59513294370 ps |
| CPU time | 1058.87 seconds |
| Started | Jul 27 08:37:15 PM PDT 24 |
| Finished | Jul 27 08:54:54 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-a31c87b9-dfa3-4e2e-870e-c0fce7f43833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463526291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1463526291 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3923692712 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 521347707 ps |
| CPU time | 54.7 seconds |
| Started | Jul 27 08:37:16 PM PDT 24 |
| Finished | Jul 27 08:38:11 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-48cd4285-6d9b-41ef-8a0c-a85be111ea53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923692712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3923692712 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2267509363 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2144788145 ps |
| CPU time | 73.52 seconds |
| Started | Jul 27 08:37:25 PM PDT 24 |
| Finished | Jul 27 08:38:38 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-655a976c-2605-4dab-96c1-f3507df4406d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267509363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2267509363 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.2734694629 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 253816406 ps |
| CPU time | 10.89 seconds |
| Started | Jul 27 08:37:19 PM PDT 24 |
| Finished | Jul 27 08:37:30 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-f61eb4e2-cbca-4975-9898-69cb34c24128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734694629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.2734694629 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3825426836 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 10735760414 ps |
| CPU time | 115.55 seconds |
| Started | Jul 27 08:37:19 PM PDT 24 |
| Finished | Jul 27 08:39:14 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-f983bc29-f29a-4a87-a226-828415b7ee7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825426836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3825426836 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2530832729 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 4967896623 ps |
| CPU time | 85.7 seconds |
| Started | Jul 27 08:37:15 PM PDT 24 |
| Finished | Jul 27 08:38:40 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-d9fb1e73-8a05-4d64-ae04-508f7d85d8db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530832729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2530832729 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.3547187312 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 46485788 ps |
| CPU time | 6.43 seconds |
| Started | Jul 27 08:37:16 PM PDT 24 |
| Finished | Jul 27 08:37:23 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-996639a7-2fde-4e62-a05b-68da888ebd89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547187312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.3547187312 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.924422596 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 6701290615 ps |
| CPU time | 239.85 seconds |
| Started | Jul 27 08:37:25 PM PDT 24 |
| Finished | Jul 27 08:41:25 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-e3c71122-9465-46be-a585-b74ec9c30f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924422596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.924422596 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1751129646 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 9666805417 ps |
| CPU time | 314.5 seconds |
| Started | Jul 27 08:37:24 PM PDT 24 |
| Finished | Jul 27 08:42:39 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-00aea881-db60-421b-b10e-69d93c28f61d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751129646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1751129646 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3752103326 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 4138707004 ps |
| CPU time | 270.35 seconds |
| Started | Jul 27 08:37:26 PM PDT 24 |
| Finished | Jul 27 08:41:57 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-d776c42c-c170-486e-a235-673dad93728d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752103326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3752103326 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.278158390 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 353458684 ps |
| CPU time | 72.49 seconds |
| Started | Jul 27 08:37:26 PM PDT 24 |
| Finished | Jul 27 08:38:39 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-ad6a1ec7-722f-40b1-bba6-ad4e7b3b4418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278158390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_reset_error.278158390 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4157795325 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 1015346219 ps |
| CPU time | 47.79 seconds |
| Started | Jul 27 08:37:26 PM PDT 24 |
| Finished | Jul 27 08:38:13 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-df431629-9313-4de6-b64c-0cda6ed653ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157795325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4157795325 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.2576164013 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 2413268953 ps |
| CPU time | 104.51 seconds |
| Started | Jul 27 08:37:26 PM PDT 24 |
| Finished | Jul 27 08:39:10 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-d2257d63-c95f-477c-b0c8-d08efc55b6ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576164013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2576164013 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3442047393 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 208659952 ps |
| CPU time | 27.13 seconds |
| Started | Jul 27 08:37:33 PM PDT 24 |
| Finished | Jul 27 08:38:00 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-103cf563-873b-4570-87f1-ce67b1c11269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442047393 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3442047393 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.34424557 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 179873157 ps |
| CPU time | 19.08 seconds |
| Started | Jul 27 08:37:32 PM PDT 24 |
| Finished | Jul 27 08:37:51 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-decbe179-1614-4e92-9370-c770614f1851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.34424557 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.3739336864 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 1131781883 ps |
| CPU time | 47.23 seconds |
| Started | Jul 27 08:37:27 PM PDT 24 |
| Finished | Jul 27 08:38:14 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-5745b395-98af-483a-aa31-c1408505306d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739336864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.3739336864 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3469838315 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 17785502642 ps |
| CPU time | 183.44 seconds |
| Started | Jul 27 08:37:26 PM PDT 24 |
| Finished | Jul 27 08:40:29 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-059a2756-23fe-4194-a52a-32d97933f831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469838315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3469838315 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.602928282 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 37204368829 ps |
| CPU time | 675.08 seconds |
| Started | Jul 27 08:37:28 PM PDT 24 |
| Finished | Jul 27 08:48:43 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-c0e9bad9-2315-49a1-8810-cf1899f2e3a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602928282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.602928282 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1639356430 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 42864313 ps |
| CPU time | 6.58 seconds |
| Started | Jul 27 08:37:24 PM PDT 24 |
| Finished | Jul 27 08:37:31 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-33ec5077-775f-45e2-973b-9d32a6c0f20a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639356430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.1639356430 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.3701889864 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 2650214929 ps |
| CPU time | 88.78 seconds |
| Started | Jul 27 08:37:37 PM PDT 24 |
| Finished | Jul 27 08:39:06 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-055a9fc2-98b0-4403-bd03-d42e794238dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701889864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3701889864 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.37946712 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 168744256 ps |
| CPU time | 8.79 seconds |
| Started | Jul 27 08:37:25 PM PDT 24 |
| Finished | Jul 27 08:37:34 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-9aeceba0-d068-4be6-a880-fda2eae4a8d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37946712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.37946712 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3538173513 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 9254930286 ps |
| CPU time | 108.97 seconds |
| Started | Jul 27 08:37:28 PM PDT 24 |
| Finished | Jul 27 08:39:17 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-574b4616-4c70-4250-9f9c-45b7e14714d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538173513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3538173513 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.181709448 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 3448302355 ps |
| CPU time | 63.26 seconds |
| Started | Jul 27 08:37:29 PM PDT 24 |
| Finished | Jul 27 08:38:33 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-ac2d4021-de27-4c84-9c27-2efece3e28a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181709448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.181709448 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1713830819 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 43356264 ps |
| CPU time | 6.63 seconds |
| Started | Jul 27 08:37:24 PM PDT 24 |
| Finished | Jul 27 08:37:31 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-4ef4491c-1243-48ba-8092-75b86723ec15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713830819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.1713830819 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.2285058350 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 9124370295 ps |
| CPU time | 360.56 seconds |
| Started | Jul 27 08:37:32 PM PDT 24 |
| Finished | Jul 27 08:43:32 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-f573cb27-4b24-4aee-8023-1c39fce21be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285058350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2285058350 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1936700232 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 9757534277 ps |
| CPU time | 352.38 seconds |
| Started | Jul 27 08:37:33 PM PDT 24 |
| Finished | Jul 27 08:43:26 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-b1c753a3-d48b-4070-8c76-51016f6ee4da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936700232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1936700232 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.4119752732 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 8692605970 ps |
| CPU time | 659.22 seconds |
| Started | Jul 27 08:37:33 PM PDT 24 |
| Finished | Jul 27 08:48:32 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-9b854072-9492-4226-a406-4db078cedce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119752732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.4119752732 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2539382461 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 53275741 ps |
| CPU time | 7.62 seconds |
| Started | Jul 27 08:37:32 PM PDT 24 |
| Finished | Jul 27 08:37:40 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-beb51546-4f31-472b-9542-910f566993c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539382461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2539382461 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3122698915 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 139164349 ps |
| CPU time | 21.4 seconds |
| Started | Jul 27 08:37:35 PM PDT 24 |
| Finished | Jul 27 08:37:56 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4655928c-2c9e-439b-932f-8a4e67763ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122698915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3122698915 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2240309749 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 3040540868 ps |
| CPU time | 150.5 seconds |
| Started | Jul 27 08:37:43 PM PDT 24 |
| Finished | Jul 27 08:40:14 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-618de21d-b84d-4808-ad87-5f3b0ec614e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240309749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2240309749 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.59189349 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 121874597158 ps |
| CPU time | 2050.02 seconds |
| Started | Jul 27 08:37:50 PM PDT 24 |
| Finished | Jul 27 09:12:00 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-547851cf-e476-4e99-878e-d1fdac69b208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59189349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_de vice_slow_rsp.59189349 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1541769590 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 1186482948 ps |
| CPU time | 52.92 seconds |
| Started | Jul 27 08:37:42 PM PDT 24 |
| Finished | Jul 27 08:38:36 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-d6453e93-d6a2-4399-a8f6-3fd903856b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541769590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1541769590 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.1580632162 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 980547436 ps |
| CPU time | 37.76 seconds |
| Started | Jul 27 08:37:44 PM PDT 24 |
| Finished | Jul 27 08:38:21 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-e61ff9f3-d955-4c08-a05c-3ea5ef443e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580632162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1580632162 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3027600214 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 1318781158 ps |
| CPU time | 40.48 seconds |
| Started | Jul 27 08:37:33 PM PDT 24 |
| Finished | Jul 27 08:38:13 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-bd51b183-2580-47e4-8722-127c210c1861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027600214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3027600214 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2073949230 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 101685496358 ps |
| CPU time | 1045.5 seconds |
| Started | Jul 27 08:37:42 PM PDT 24 |
| Finished | Jul 27 08:55:08 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-113ebf8e-e6c1-435d-a7ee-5c0da4c968ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073949230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2073949230 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3370714238 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 10857942294 ps |
| CPU time | 181.33 seconds |
| Started | Jul 27 08:37:45 PM PDT 24 |
| Finished | Jul 27 08:40:46 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-ca961248-6a67-4bd0-a832-338785beb972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370714238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3370714238 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2776635145 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 192688843 ps |
| CPU time | 23.41 seconds |
| Started | Jul 27 08:37:32 PM PDT 24 |
| Finished | Jul 27 08:37:55 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-e005878f-3e7f-431a-bf36-88a93aced1ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776635145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2776635145 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.1416475524 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1113692689 ps |
| CPU time | 36.76 seconds |
| Started | Jul 27 08:37:43 PM PDT 24 |
| Finished | Jul 27 08:38:20 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-5740cfb8-a687-4b75-b73f-24d31f5b4dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416475524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1416475524 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.930958328 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 168381420 ps |
| CPU time | 9.15 seconds |
| Started | Jul 27 08:37:35 PM PDT 24 |
| Finished | Jul 27 08:37:44 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-31b8ace4-69cc-4c4d-ba35-9aaca2938f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930958328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.930958328 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.4147953672 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 6801641553 ps |
| CPU time | 72.92 seconds |
| Started | Jul 27 08:37:33 PM PDT 24 |
| Finished | Jul 27 08:38:46 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-5121de27-44cd-4a0f-901a-0d9a683293c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147953672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4147953672 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3603840814 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 5528431538 ps |
| CPU time | 96.88 seconds |
| Started | Jul 27 08:37:33 PM PDT 24 |
| Finished | Jul 27 08:39:10 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-0a1d5b1d-1798-4eaf-ab0e-15473517601a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603840814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3603840814 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.274223938 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 52799955 ps |
| CPU time | 6.9 seconds |
| Started | Jul 27 08:37:37 PM PDT 24 |
| Finished | Jul 27 08:37:44 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-959ee99b-8e1b-4818-9ad3-3df1d47db55f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274223938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays .274223938 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.11310797 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 3049314489 ps |
| CPU time | 105.95 seconds |
| Started | Jul 27 08:37:43 PM PDT 24 |
| Finished | Jul 27 08:39:29 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-9d76172e-e787-46cf-8054-a45759a7000f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11310797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.11310797 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3163921689 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 2965966069 ps |
| CPU time | 122.98 seconds |
| Started | Jul 27 08:37:43 PM PDT 24 |
| Finished | Jul 27 08:39:46 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-4bf5a982-8542-4215-a054-90478cc27197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163921689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3163921689 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3744778924 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 4658479231 ps |
| CPU time | 657.31 seconds |
| Started | Jul 27 08:37:49 PM PDT 24 |
| Finished | Jul 27 08:48:47 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-8c87beb6-16bf-4628-8a6e-a29dab011a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744778924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3744778924 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1520158709 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 14010752916 ps |
| CPU time | 703.19 seconds |
| Started | Jul 27 08:37:42 PM PDT 24 |
| Finished | Jul 27 08:49:26 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-08e590bd-6c6f-486c-b07d-45d92c4a849e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520158709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1520158709 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1606287308 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 1295324927 ps |
| CPU time | 54.03 seconds |
| Started | Jul 27 08:37:40 PM PDT 24 |
| Finished | Jul 27 08:38:34 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-1bc96ba2-fedc-48f4-b12d-13614a6dd320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606287308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1606287308 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1105791441 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 774173529 ps |
| CPU time | 72.75 seconds |
| Started | Jul 27 08:37:49 PM PDT 24 |
| Finished | Jul 27 08:39:02 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-18b543a1-4b38-43fa-8917-9ea26f4436ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105791441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1105791441 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1535074035 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 103659725772 ps |
| CPU time | 1890.01 seconds |
| Started | Jul 27 08:37:48 PM PDT 24 |
| Finished | Jul 27 09:09:18 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-e2cb6417-c27e-478f-9b9a-ab5ed6d7f351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535074035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1535074035 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1692809142 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 1459034206 ps |
| CPU time | 67.12 seconds |
| Started | Jul 27 08:37:51 PM PDT 24 |
| Finished | Jul 27 08:38:58 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-c214da88-516c-4a1d-a5d2-da78ab4d647a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692809142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1692809142 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1613677965 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 146521442 ps |
| CPU time | 8.15 seconds |
| Started | Jul 27 08:37:50 PM PDT 24 |
| Finished | Jul 27 08:37:58 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-85db3300-2dc5-41fc-bba6-c7a2e4b7217c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613677965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1613677965 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.4108527038 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 366937530 ps |
| CPU time | 17.44 seconds |
| Started | Jul 27 08:37:51 PM PDT 24 |
| Finished | Jul 27 08:38:08 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-836f9ffd-87a9-4622-86cb-744a6fe210db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108527038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.4108527038 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3287717080 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 5762167714 ps |
| CPU time | 61.53 seconds |
| Started | Jul 27 08:37:59 PM PDT 24 |
| Finished | Jul 27 08:39:00 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-001e8460-23c6-4b57-bc1f-70e7c27dc3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287717080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3287717080 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1731415490 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 15039384162 ps |
| CPU time | 257.08 seconds |
| Started | Jul 27 08:37:49 PM PDT 24 |
| Finished | Jul 27 08:42:06 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-df96dafa-5edd-4228-951e-6381da18201d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731415490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1731415490 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.1639030811 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 487707296 ps |
| CPU time | 44.29 seconds |
| Started | Jul 27 08:37:55 PM PDT 24 |
| Finished | Jul 27 08:38:40 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-8b023a8b-acc3-4fc9-a07a-5de778387e8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639030811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.1639030811 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.1356646433 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 302867497 ps |
| CPU time | 26.62 seconds |
| Started | Jul 27 08:37:50 PM PDT 24 |
| Finished | Jul 27 08:38:17 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-00f01363-e6aa-47f2-94db-af8286141c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356646433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1356646433 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2701733553 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 45508462 ps |
| CPU time | 6.08 seconds |
| Started | Jul 27 08:37:42 PM PDT 24 |
| Finished | Jul 27 08:37:49 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-bdc6efec-a505-4eb7-8791-e0929b12a777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701733553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2701733553 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2403151425 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 9386240430 ps |
| CPU time | 98.63 seconds |
| Started | Jul 27 08:37:50 PM PDT 24 |
| Finished | Jul 27 08:39:29 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-16ee1429-7e7f-4207-b502-533e7a9113d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403151425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2403151425 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2637049411 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 5329732992 ps |
| CPU time | 86.77 seconds |
| Started | Jul 27 08:37:48 PM PDT 24 |
| Finished | Jul 27 08:39:15 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-146fad0d-d615-4e83-95aa-a6d688688ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637049411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2637049411 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2320649823 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 51549518 ps |
| CPU time | 6.86 seconds |
| Started | Jul 27 08:37:51 PM PDT 24 |
| Finished | Jul 27 08:37:58 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-1b7edc45-e8af-4a35-9ffc-a37bef41ceb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320649823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2320649823 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.1609009245 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 14984059850 ps |
| CPU time | 666.2 seconds |
| Started | Jul 27 08:37:58 PM PDT 24 |
| Finished | Jul 27 08:49:04 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-bbefe06f-2654-4357-8889-657438a81e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609009245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1609009245 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.492849085 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 729200583 ps |
| CPU time | 58.96 seconds |
| Started | Jul 27 08:37:57 PM PDT 24 |
| Finished | Jul 27 08:38:56 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-6d7cd473-0d99-42f7-849e-feb47484345f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492849085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.492849085 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2963562392 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 2241695474 ps |
| CPU time | 412.2 seconds |
| Started | Jul 27 08:38:03 PM PDT 24 |
| Finished | Jul 27 08:44:55 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-cad01d05-2e4b-4c9b-965b-613b86e77b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963562392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2963562392 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.4151992654 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 12901714433 ps |
| CPU time | 668.56 seconds |
| Started | Jul 27 08:37:59 PM PDT 24 |
| Finished | Jul 27 08:49:08 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-dba692dd-c70f-4aff-9be0-1693ca7bcb30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151992654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.4151992654 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.3460918973 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 278361456 ps |
| CPU time | 36.12 seconds |
| Started | Jul 27 08:37:59 PM PDT 24 |
| Finished | Jul 27 08:38:35 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-e1647c17-26a3-41db-9d5e-e5c3977c6d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460918973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3460918973 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3039577892 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 591703928 ps |
| CPU time | 58.02 seconds |
| Started | Jul 27 08:37:58 PM PDT 24 |
| Finished | Jul 27 08:38:56 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-3c7c9c6a-a8ea-417d-9506-1f20333976a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039577892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .3039577892 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3517854856 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 121603172709 ps |
| CPU time | 2026.14 seconds |
| Started | Jul 27 08:38:03 PM PDT 24 |
| Finished | Jul 27 09:11:49 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-cc38cb9e-dfdb-44d3-8720-57f7a3fe9431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517854856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.3517854856 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2509006252 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 989432556 ps |
| CPU time | 40.72 seconds |
| Started | Jul 27 08:38:06 PM PDT 24 |
| Finished | Jul 27 08:38:47 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-30b5a6c5-73f1-4d11-bb8b-a9e022d14326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509006252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.2509006252 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3291502874 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 34863701 ps |
| CPU time | 6.38 seconds |
| Started | Jul 27 08:37:58 PM PDT 24 |
| Finished | Jul 27 08:38:05 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-5ab01b66-e508-4d26-93fb-6eefc7b4aba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291502874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3291502874 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.2686417860 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 1105364440 ps |
| CPU time | 37.82 seconds |
| Started | Jul 27 08:37:57 PM PDT 24 |
| Finished | Jul 27 08:38:35 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ce34b3b3-6868-4cc7-96ff-3f8a3cf4b93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686417860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2686417860 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2068085369 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 93545739681 ps |
| CPU time | 1015.42 seconds |
| Started | Jul 27 08:37:59 PM PDT 24 |
| Finished | Jul 27 08:54:54 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-7e874348-e060-41ac-a530-1c38eec11050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068085369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2068085369 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.71534986 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 36924797247 ps |
| CPU time | 657.93 seconds |
| Started | Jul 27 08:38:01 PM PDT 24 |
| Finished | Jul 27 08:48:59 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-0e85a9b9-567a-4997-9c1d-e312daf47224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71534986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.71534986 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.470231948 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 322592102 ps |
| CPU time | 31.11 seconds |
| Started | Jul 27 08:38:00 PM PDT 24 |
| Finished | Jul 27 08:38:32 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-e20fb6f3-4ca4-438d-8758-22a495794311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470231948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.470231948 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.2075094502 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 167388334 ps |
| CPU time | 15.96 seconds |
| Started | Jul 27 08:37:59 PM PDT 24 |
| Finished | Jul 27 08:38:15 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-52b30f03-76d4-4ddf-a864-04978c250937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075094502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2075094502 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.1524421699 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 239462228 ps |
| CPU time | 10.91 seconds |
| Started | Jul 27 08:38:03 PM PDT 24 |
| Finished | Jul 27 08:38:14 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-96801ea2-ea2a-4fc4-8c37-917826f7c516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524421699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1524421699 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2780544493 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 9467899067 ps |
| CPU time | 99.18 seconds |
| Started | Jul 27 08:38:03 PM PDT 24 |
| Finished | Jul 27 08:39:42 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-e7767e0f-b773-4899-9b4f-461d5c6ffed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780544493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2780544493 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1828422643 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 4383873851 ps |
| CPU time | 79.12 seconds |
| Started | Jul 27 08:38:02 PM PDT 24 |
| Finished | Jul 27 08:39:21 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-6220da91-9e7e-401e-964f-d91285734a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828422643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1828422643 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3481263133 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 49618023 ps |
| CPU time | 6.32 seconds |
| Started | Jul 27 08:38:01 PM PDT 24 |
| Finished | Jul 27 08:38:08 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-a1b7fd70-e12b-492a-9b2f-b0dd0349f5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481263133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3481263133 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.2278660233 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1566700840 ps |
| CPU time | 71.06 seconds |
| Started | Jul 27 08:38:06 PM PDT 24 |
| Finished | Jul 27 08:39:17 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-d2f03c84-79a5-460e-9125-cbdb2a1991db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278660233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.2278660233 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3229564673 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 7402526849 ps |
| CPU time | 270.21 seconds |
| Started | Jul 27 08:38:13 PM PDT 24 |
| Finished | Jul 27 08:42:44 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-26a24f68-b894-4ce7-93cd-66d7e2b05ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229564673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3229564673 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2973456205 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 221872402 ps |
| CPU time | 95.95 seconds |
| Started | Jul 27 08:38:09 PM PDT 24 |
| Finished | Jul 27 08:39:45 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-1803a1eb-cfb9-4b75-adb2-9aff68f3b61f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973456205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2973456205 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2995481207 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 1237025615 ps |
| CPU time | 49.33 seconds |
| Started | Jul 27 08:38:13 PM PDT 24 |
| Finished | Jul 27 08:39:03 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-f09b7109-de88-4528-aaf6-326153054891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995481207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2995481207 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3268925432 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 160877488 ps |
| CPU time | 12.76 seconds |
| Started | Jul 27 08:38:16 PM PDT 24 |
| Finished | Jul 27 08:38:29 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7fef2696-dcba-49ef-9fe9-f82e773a57b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268925432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3268925432 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.290687799 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 83015133325 ps |
| CPU time | 1422.97 seconds |
| Started | Jul 27 08:38:13 PM PDT 24 |
| Finished | Jul 27 09:01:56 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-08d43dcf-fe3b-416f-a03d-291bb4b40653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290687799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.290687799 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3668391365 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 20933273 ps |
| CPU time | 5.74 seconds |
| Started | Jul 27 08:38:16 PM PDT 24 |
| Finished | Jul 27 08:38:21 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-6ee534ef-3499-4b61-b281-85f603d66d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668391365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.3668391365 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2043090394 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 362673391 ps |
| CPU time | 16.71 seconds |
| Started | Jul 27 08:38:13 PM PDT 24 |
| Finished | Jul 27 08:38:30 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-a8e2c34d-2e4d-42d1-959a-31c48a0060a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043090394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2043090394 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.1402351646 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 777589955 ps |
| CPU time | 29.63 seconds |
| Started | Jul 27 08:38:13 PM PDT 24 |
| Finished | Jul 27 08:38:43 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-add0e28d-a748-49af-8818-f6193a483b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402351646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.1402351646 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.1651771235 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 29028102972 ps |
| CPU time | 295.17 seconds |
| Started | Jul 27 08:38:15 PM PDT 24 |
| Finished | Jul 27 08:43:10 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-0dbe029b-afb3-4ea8-95e7-19f27bc2661f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651771235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.1651771235 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.1522504804 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 29503223091 ps |
| CPU time | 523.75 seconds |
| Started | Jul 27 08:38:13 PM PDT 24 |
| Finished | Jul 27 08:46:57 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-bb80aad2-2395-470b-aa55-51f303e9c93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522504804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1522504804 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2191431400 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 248570736 ps |
| CPU time | 26.03 seconds |
| Started | Jul 27 08:38:16 PM PDT 24 |
| Finished | Jul 27 08:38:42 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-1e7fd949-dd42-4ef3-98f4-e55c23cbd765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191431400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2191431400 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.2384558274 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 783903172 ps |
| CPU time | 26.39 seconds |
| Started | Jul 27 08:38:17 PM PDT 24 |
| Finished | Jul 27 08:38:44 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-d6ef8399-294b-47e1-90d0-4b8a41bdf284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384558274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2384558274 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.304123771 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 36903372 ps |
| CPU time | 5.99 seconds |
| Started | Jul 27 08:38:05 PM PDT 24 |
| Finished | Jul 27 08:38:11 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-6ea42e75-6b42-4ab5-ad46-dac77714a9d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304123771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.304123771 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3282198262 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 7303082154 ps |
| CPU time | 75.98 seconds |
| Started | Jul 27 08:38:08 PM PDT 24 |
| Finished | Jul 27 08:39:24 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c45673e3-df95-4658-b439-0c851e3de7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282198262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3282198262 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3035325713 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 5125876507 ps |
| CPU time | 84.66 seconds |
| Started | Jul 27 08:38:08 PM PDT 24 |
| Finished | Jul 27 08:39:33 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-e461e277-13e5-4ba2-8029-5e6ba22bce35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035325713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3035325713 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3893987336 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 49404149 ps |
| CPU time | 6.72 seconds |
| Started | Jul 27 08:38:06 PM PDT 24 |
| Finished | Jul 27 08:38:12 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-d1965535-47b2-4aa7-8297-b1d60e8cc921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893987336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.3893987336 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2631668013 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 8965175199 ps |
| CPU time | 347.53 seconds |
| Started | Jul 27 08:38:16 PM PDT 24 |
| Finished | Jul 27 08:44:03 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-ddc6578e-393e-4db8-bf5a-56b756f424b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631668013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2631668013 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3627759073 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 2212758173 ps |
| CPU time | 187.86 seconds |
| Started | Jul 27 08:38:20 PM PDT 24 |
| Finished | Jul 27 08:41:28 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-8d46e8be-2a86-4dcd-b928-6e9a532e411b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627759073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3627759073 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1868460949 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 6045285739 ps |
| CPU time | 834.2 seconds |
| Started | Jul 27 08:38:16 PM PDT 24 |
| Finished | Jul 27 08:52:10 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-95fc2ac0-7f3f-4eee-be7c-50875afc8a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868460949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1868460949 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.951553049 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 469863225 ps |
| CPU time | 25.03 seconds |
| Started | Jul 27 08:38:17 PM PDT 24 |
| Finished | Jul 27 08:38:42 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-1aed41b2-c931-47ca-b621-fbdaf5096a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951553049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.951553049 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.2789739859 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 2279679755 ps |
| CPU time | 101.82 seconds |
| Started | Jul 27 08:38:32 PM PDT 24 |
| Finished | Jul 27 08:40:14 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-a0032258-7566-42a5-ad3b-1bb8ae8e5156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789739859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .2789739859 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.4228229926 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 20583238274 ps |
| CPU time | 371.89 seconds |
| Started | Jul 27 08:38:31 PM PDT 24 |
| Finished | Jul 27 08:44:43 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-43536d96-3eb4-45c5-84d0-c53a6fc2c229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228229926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.4228229926 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3330253548 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1450838506 ps |
| CPU time | 62.23 seconds |
| Started | Jul 27 08:38:34 PM PDT 24 |
| Finished | Jul 27 08:39:36 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-890df200-fa15-4abc-a7ca-946bf6eb3ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330253548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3330253548 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.561393139 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 2299426054 ps |
| CPU time | 81.85 seconds |
| Started | Jul 27 08:38:31 PM PDT 24 |
| Finished | Jul 27 08:39:53 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-39a7f2ed-ac25-4354-9c08-da2d3aad6f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561393139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.561393139 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.3392978067 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 367157232 ps |
| CPU time | 35.52 seconds |
| Started | Jul 27 08:38:25 PM PDT 24 |
| Finished | Jul 27 08:39:00 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ba261974-54f7-438e-b0cb-bce106927ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392978067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3392978067 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3432791042 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 12653060145 ps |
| CPU time | 132.15 seconds |
| Started | Jul 27 08:38:30 PM PDT 24 |
| Finished | Jul 27 08:40:42 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-7054eb6c-321b-4727-9733-a188823bd2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432791042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3432791042 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.1151891533 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 36982501237 ps |
| CPU time | 690.86 seconds |
| Started | Jul 27 08:38:31 PM PDT 24 |
| Finished | Jul 27 08:50:02 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-b5602445-ab03-4180-a743-cc517842927f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151891533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1151891533 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2023835780 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 349398544 ps |
| CPU time | 35.8 seconds |
| Started | Jul 27 08:38:20 PM PDT 24 |
| Finished | Jul 27 08:38:56 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-f674a8f2-97c3-4633-bfe2-173406abffd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023835780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2023835780 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.3600186840 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 158442484 ps |
| CPU time | 8.52 seconds |
| Started | Jul 27 08:38:30 PM PDT 24 |
| Finished | Jul 27 08:38:38 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-6df72d27-fc82-44c0-94fb-33604964778d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600186840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3600186840 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.2220992213 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 43474107 ps |
| CPU time | 6.95 seconds |
| Started | Jul 27 08:38:24 PM PDT 24 |
| Finished | Jul 27 08:38:31 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-df29d91f-68ba-40c4-9c25-20d16b848818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220992213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2220992213 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1643540384 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 7806401416 ps |
| CPU time | 82.23 seconds |
| Started | Jul 27 08:38:21 PM PDT 24 |
| Finished | Jul 27 08:39:43 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-ff8dc854-bff9-4709-a268-2ffe9d09caae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643540384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1643540384 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2015659605 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 5178394166 ps |
| CPU time | 89.96 seconds |
| Started | Jul 27 08:38:23 PM PDT 24 |
| Finished | Jul 27 08:39:53 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-64ff6cf9-98e1-4c9f-ad10-d92ab76461cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015659605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2015659605 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.2018471876 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 35289985 ps |
| CPU time | 6.5 seconds |
| Started | Jul 27 08:38:20 PM PDT 24 |
| Finished | Jul 27 08:38:27 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-d58adbee-d0eb-4bce-a953-b345ac6b5263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018471876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.2018471876 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1062399831 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 1714311735 ps |
| CPU time | 77.09 seconds |
| Started | Jul 27 08:38:33 PM PDT 24 |
| Finished | Jul 27 08:39:50 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-c2b422c4-b769-4c0f-9efc-c20579fccf2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062399831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1062399831 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.258047207 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 5945213 ps |
| CPU time | 3.96 seconds |
| Started | Jul 27 08:38:29 PM PDT 24 |
| Finished | Jul 27 08:38:33 PM PDT 24 |
| Peak memory | 565276 kb |
| Host | smart-94e348c7-45ce-4b54-ac86-3ba71923b66c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258047207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.258047207 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.4232815347 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 1969330028 ps |
| CPU time | 203.88 seconds |
| Started | Jul 27 08:38:31 PM PDT 24 |
| Finished | Jul 27 08:41:55 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-82edd913-dc1d-498e-afe7-d8d8044fb6e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232815347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.4232815347 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.4032504651 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 538758001 ps |
| CPU time | 27.26 seconds |
| Started | Jul 27 08:38:28 PM PDT 24 |
| Finished | Jul 27 08:38:55 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-8ab4bde0-031a-4f8f-9bdd-d032f0f31e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032504651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4032504651 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.1652540708 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 233270437 ps |
| CPU time | 17.78 seconds |
| Started | Jul 27 08:38:37 PM PDT 24 |
| Finished | Jul 27 08:38:55 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-73b30d9d-673a-4155-ab6c-46bf6b14c349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652540708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .1652540708 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.384249080 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 22251854206 ps |
| CPU time | 398.88 seconds |
| Started | Jul 27 08:38:42 PM PDT 24 |
| Finished | Jul 27 08:45:21 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-3f117123-8315-41bd-a581-dde71c24e07b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384249080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.384249080 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1737226346 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 163724298 ps |
| CPU time | 20.31 seconds |
| Started | Jul 27 08:38:41 PM PDT 24 |
| Finished | Jul 27 08:39:01 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-3f78b5e5-ac22-434b-8398-def722bc37b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737226346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1737226346 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2803496524 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 307096691 ps |
| CPU time | 30.53 seconds |
| Started | Jul 27 08:38:39 PM PDT 24 |
| Finished | Jul 27 08:39:09 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-45474e6e-950c-4947-bd5f-ece20c378e58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803496524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2803496524 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2301016141 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 88184666 ps |
| CPU time | 11.34 seconds |
| Started | Jul 27 08:38:38 PM PDT 24 |
| Finished | Jul 27 08:38:50 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-06a1b4d2-3eb9-4376-8c2b-20517f80e667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301016141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2301016141 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.140242334 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 60505140864 ps |
| CPU time | 627.83 seconds |
| Started | Jul 27 08:38:43 PM PDT 24 |
| Finished | Jul 27 08:49:11 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-434ca74f-f842-441f-8be7-cfc542e21e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140242334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.140242334 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3314928335 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 45210697656 ps |
| CPU time | 771.25 seconds |
| Started | Jul 27 08:38:40 PM PDT 24 |
| Finished | Jul 27 08:51:32 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-55efb014-f4fc-45f3-91e0-50706698ba56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314928335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3314928335 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1659017214 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 441179792 ps |
| CPU time | 43.64 seconds |
| Started | Jul 27 08:38:41 PM PDT 24 |
| Finished | Jul 27 08:39:25 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-3cca2de4-0fc9-4905-8af7-886fa7f91ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659017214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1659017214 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.507777227 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 1860247497 ps |
| CPU time | 57.97 seconds |
| Started | Jul 27 08:38:41 PM PDT 24 |
| Finished | Jul 27 08:39:39 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-221c0a9a-81e0-4267-87e0-45d10e5af4ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507777227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.507777227 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.1428910906 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 40384063 ps |
| CPU time | 6.11 seconds |
| Started | Jul 27 08:38:29 PM PDT 24 |
| Finished | Jul 27 08:38:35 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-f070b44d-1c6d-4b72-9352-91d63330f12c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428910906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1428910906 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.932770801 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 8084229991 ps |
| CPU time | 83.33 seconds |
| Started | Jul 27 08:38:41 PM PDT 24 |
| Finished | Jul 27 08:40:05 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-e3783c01-be72-4249-bada-62636d26e80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932770801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.932770801 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.257261089 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 5155572452 ps |
| CPU time | 94.24 seconds |
| Started | Jul 27 08:38:38 PM PDT 24 |
| Finished | Jul 27 08:40:13 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-785ae794-f118-43cf-985d-2c1a67c68e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257261089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.257261089 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3432017665 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 47381128 ps |
| CPU time | 7.08 seconds |
| Started | Jul 27 08:38:29 PM PDT 24 |
| Finished | Jul 27 08:38:36 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-a61cf8f2-bfa3-457d-90b9-638a41f8a803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432017665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.3432017665 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.553691568 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 9253214970 ps |
| CPU time | 382.08 seconds |
| Started | Jul 27 08:38:39 PM PDT 24 |
| Finished | Jul 27 08:45:01 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-3789d216-622b-496f-9225-b0e67b7ca7c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553691568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.553691568 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.337207990 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 5280090131 ps |
| CPU time | 192.16 seconds |
| Started | Jul 27 08:38:42 PM PDT 24 |
| Finished | Jul 27 08:41:54 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-180dc746-3a03-45d1-a910-36430847f04b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337207990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.337207990 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.4053700667 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 75221782 ps |
| CPU time | 24.94 seconds |
| Started | Jul 27 08:38:41 PM PDT 24 |
| Finished | Jul 27 08:39:06 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-e022f432-2716-402b-b4ee-5cebdb33d6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053700667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.4053700667 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2059916631 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 976432975 ps |
| CPU time | 93.14 seconds |
| Started | Jul 27 08:38:38 PM PDT 24 |
| Finished | Jul 27 08:40:11 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-9049187f-2473-4390-8381-fd03ef21fa75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059916631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2059916631 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.2081094537 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 303092086 ps |
| CPU time | 36.35 seconds |
| Started | Jul 27 08:38:42 PM PDT 24 |
| Finished | Jul 27 08:39:18 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-9566be88-1ecb-4ae5-9d38-0685bed0a261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081094537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2081094537 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1460976442 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 2335031880 ps |
| CPU time | 107.26 seconds |
| Started | Jul 27 08:38:47 PM PDT 24 |
| Finished | Jul 27 08:40:35 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-25dafa23-3357-4f0a-a7e6-b4f6a318d08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460976442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1460976442 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1786595989 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 61823690343 ps |
| CPU time | 1098.62 seconds |
| Started | Jul 27 08:38:47 PM PDT 24 |
| Finished | Jul 27 08:57:06 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-3940e15b-7dd8-42f2-9d4e-38a5f6263806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786595989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.1786595989 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1152218654 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 710467861 ps |
| CPU time | 31.2 seconds |
| Started | Jul 27 08:38:45 PM PDT 24 |
| Finished | Jul 27 08:39:17 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-e8de50d7-7424-45a5-8791-073335253f34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152218654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.1152218654 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.4226053211 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 1760544128 ps |
| CPU time | 63.46 seconds |
| Started | Jul 27 08:38:49 PM PDT 24 |
| Finished | Jul 27 08:39:52 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-5b59daff-2af2-4cc1-9390-7e7e2eb9c9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226053211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4226053211 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.2656956923 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 1894185340 ps |
| CPU time | 74.4 seconds |
| Started | Jul 27 08:38:48 PM PDT 24 |
| Finished | Jul 27 08:40:02 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-f17fafed-37fb-4708-ae50-31f5b627737f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656956923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2656956923 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1454119929 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 32406104391 ps |
| CPU time | 352.89 seconds |
| Started | Jul 27 08:38:49 PM PDT 24 |
| Finished | Jul 27 08:44:42 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-037c034a-c44f-4c5b-a2f4-982cc9469d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454119929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1454119929 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.4201141189 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 39300623901 ps |
| CPU time | 710.74 seconds |
| Started | Jul 27 08:38:49 PM PDT 24 |
| Finished | Jul 27 08:50:40 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ea921890-8abb-4f1b-aab0-c64987b37bca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201141189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.4201141189 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.79139562 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 245223267 ps |
| CPU time | 26.65 seconds |
| Started | Jul 27 08:38:47 PM PDT 24 |
| Finished | Jul 27 08:39:14 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-de983fa3-f947-4a50-aba3-ca15818387cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79139562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delay s.79139562 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1693524989 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 2355242289 ps |
| CPU time | 73.56 seconds |
| Started | Jul 27 08:38:49 PM PDT 24 |
| Finished | Jul 27 08:40:03 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-4afe2594-409f-40e2-ac12-9b382922742a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693524989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1693524989 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.3496273951 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 211830297 ps |
| CPU time | 10.08 seconds |
| Started | Jul 27 08:38:40 PM PDT 24 |
| Finished | Jul 27 08:38:50 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6562d79e-30c2-4b7b-9e28-08fc82504108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496273951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3496273951 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2562600360 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 9224263912 ps |
| CPU time | 102.03 seconds |
| Started | Jul 27 08:38:47 PM PDT 24 |
| Finished | Jul 27 08:40:30 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-af5b594e-49ab-4287-97c0-27e48fca75a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562600360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2562600360 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.986402534 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 3404873371 ps |
| CPU time | 58.63 seconds |
| Started | Jul 27 08:38:45 PM PDT 24 |
| Finished | Jul 27 08:39:44 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-645709f2-27aa-4d74-accf-7effff128e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986402534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.986402534 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1686795774 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 44607329 ps |
| CPU time | 6.78 seconds |
| Started | Jul 27 08:38:37 PM PDT 24 |
| Finished | Jul 27 08:38:44 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-70a21b2d-e861-4fcd-9bb5-7cbc07e0e919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686795774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1686795774 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.2585937225 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 571193486 ps |
| CPU time | 53.46 seconds |
| Started | Jul 27 08:38:54 PM PDT 24 |
| Finished | Jul 27 08:39:47 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-fa64ad94-48c9-400d-a815-b42c68b8acc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585937225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2585937225 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1396495290 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 404871593 ps |
| CPU time | 43.49 seconds |
| Started | Jul 27 08:38:59 PM PDT 24 |
| Finished | Jul 27 08:39:42 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-2314af5c-8870-408c-8b4a-81a9520f268c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396495290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1396495290 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1016097291 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 5521744437 ps |
| CPU time | 788.39 seconds |
| Started | Jul 27 08:38:56 PM PDT 24 |
| Finished | Jul 27 08:52:04 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-53d50b91-ccbd-4c0c-a11a-d0c2bd8a995d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016097291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1016097291 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.1585512178 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 3105238128 ps |
| CPU time | 413.89 seconds |
| Started | Jul 27 08:38:58 PM PDT 24 |
| Finished | Jul 27 08:45:52 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-f626519d-3d3b-4cc4-9caa-31659dd471d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585512178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.1585512178 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1100649798 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 134727370 ps |
| CPU time | 20.61 seconds |
| Started | Jul 27 08:38:45 PM PDT 24 |
| Finished | Jul 27 08:39:06 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-b57dd8a2-020b-451c-b3a3-93c839565f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100649798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1100649798 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.369200373 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 563241242 ps |
| CPU time | 40.9 seconds |
| Started | Jul 27 08:38:58 PM PDT 24 |
| Finished | Jul 27 08:39:39 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-4b2c8ff9-0932-4514-85fe-528537ba1665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369200373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 369200373 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2181544407 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 69492682921 ps |
| CPU time | 1283.1 seconds |
| Started | Jul 27 08:38:55 PM PDT 24 |
| Finished | Jul 27 09:00:18 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-d6eff231-e16c-486d-82a2-ae96cc69a4cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181544407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.2181544407 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1497001583 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 84478526 ps |
| CPU time | 12.47 seconds |
| Started | Jul 27 08:39:07 PM PDT 24 |
| Finished | Jul 27 08:39:19 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-353fb9ac-aedf-452e-a4b0-4437dba727ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497001583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1497001583 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.621662107 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 328041298 ps |
| CPU time | 30.66 seconds |
| Started | Jul 27 08:39:07 PM PDT 24 |
| Finished | Jul 27 08:39:37 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-a1086276-90bd-4e82-a37e-dc4dc5349d85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621662107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.621662107 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1313053351 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 124676107 ps |
| CPU time | 13.27 seconds |
| Started | Jul 27 08:39:00 PM PDT 24 |
| Finished | Jul 27 08:39:13 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0bd80f91-6614-4343-b0d2-ec787d5bfc57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313053351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1313053351 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1508296778 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 66422506019 ps |
| CPU time | 659.1 seconds |
| Started | Jul 27 08:38:54 PM PDT 24 |
| Finished | Jul 27 08:49:53 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-8f3e7047-7fe7-4ad4-a087-a75118a7f802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508296778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1508296778 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1645161533 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 57210014722 ps |
| CPU time | 1053.98 seconds |
| Started | Jul 27 08:38:56 PM PDT 24 |
| Finished | Jul 27 08:56:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1eefb0b8-3455-4a2c-a065-a8fb118e817e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645161533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1645161533 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.4290842883 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 429636778 ps |
| CPU time | 38.86 seconds |
| Started | Jul 27 08:38:59 PM PDT 24 |
| Finished | Jul 27 08:39:38 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-cc7ada16-193c-4cda-9295-290095a6f313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290842883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.4290842883 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.2143546346 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 258302035 ps |
| CPU time | 10.68 seconds |
| Started | Jul 27 08:39:06 PM PDT 24 |
| Finished | Jul 27 08:39:16 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-d9d3d235-f442-47ae-8095-b31ef37b3bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143546346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2143546346 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2383707449 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 43470443 ps |
| CPU time | 6.6 seconds |
| Started | Jul 27 08:38:59 PM PDT 24 |
| Finished | Jul 27 08:39:06 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-08c72e9c-89cc-43f7-b52a-957e610948f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383707449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2383707449 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2836775209 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 8279555442 ps |
| CPU time | 84.07 seconds |
| Started | Jul 27 08:38:54 PM PDT 24 |
| Finished | Jul 27 08:40:18 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-f75a706f-ec09-4115-9c34-436f13f309fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836775209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2836775209 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2052826042 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 3688489180 ps |
| CPU time | 63.38 seconds |
| Started | Jul 27 08:38:54 PM PDT 24 |
| Finished | Jul 27 08:39:58 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-e00dd929-880f-4583-a8e8-3656bcff8152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052826042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2052826042 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.3590749202 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 51754434 ps |
| CPU time | 7.35 seconds |
| Started | Jul 27 08:38:57 PM PDT 24 |
| Finished | Jul 27 08:39:04 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-76615c92-f710-4de0-a87f-07bfab812ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590749202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.3590749202 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.1587441651 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 1839777861 ps |
| CPU time | 164.23 seconds |
| Started | Jul 27 08:39:07 PM PDT 24 |
| Finished | Jul 27 08:41:51 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-8af453c0-8ef4-4dc2-8010-9e166796321e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587441651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1587441651 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3623000868 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 12250729574 ps |
| CPU time | 477.28 seconds |
| Started | Jul 27 08:39:04 PM PDT 24 |
| Finished | Jul 27 08:47:01 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-ca95d2fb-a12a-4423-b24d-ce09f9c44e36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623000868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3623000868 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.733813292 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 768389233 ps |
| CPU time | 216.07 seconds |
| Started | Jul 27 08:39:05 PM PDT 24 |
| Finished | Jul 27 08:42:41 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-fd00fd66-5fa6-46f1-9626-730598f2167d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733813292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_ with_rand_reset.733813292 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2774484141 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 10383355161 ps |
| CPU time | 519.27 seconds |
| Started | Jul 27 08:39:09 PM PDT 24 |
| Finished | Jul 27 08:47:48 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-36056ea7-f0fe-45f0-9fb9-89a2f0f7eba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774484141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.2774484141 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2832911852 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 765779140 ps |
| CPU time | 35.66 seconds |
| Started | Jul 27 08:39:03 PM PDT 24 |
| Finished | Jul 27 08:39:39 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-df2ad2d6-0756-4e8c-8558-7a67751ce0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832911852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2832911852 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3496571119 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 67954941784 ps |
| CPU time | 6282.09 seconds |
| Started | Jul 27 08:27:05 PM PDT 24 |
| Finished | Jul 27 10:11:48 PM PDT 24 |
| Peak memory | 591168 kb |
| Host | smart-09be8b7c-3d2e-4ecd-bd03-1ed9926f477e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496571119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3496571119 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1620777725 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5189343064 ps |
| CPU time | 268.11 seconds |
| Started | Jul 27 08:27:59 PM PDT 24 |
| Finished | Jul 27 08:32:27 PM PDT 24 |
| Peak memory | 664224 kb |
| Host | smart-0bf94cc2-c420-4701-96b5-0e1209041817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620777725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.1620777725 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.787200296 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 5558879920 ps |
| CPU time | 466.46 seconds |
| Started | Jul 27 08:27:53 PM PDT 24 |
| Finished | Jul 27 08:35:39 PM PDT 24 |
| Peak memory | 641452 kb |
| Host | smart-586f32d9-8f3a-4c76-b868-0a571865a85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787200296 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.787200296 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.2792083008 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4599712617 ps |
| CPU time | 392.7 seconds |
| Started | Jul 27 08:27:53 PM PDT 24 |
| Finished | Jul 27 08:34:25 PM PDT 24 |
| Peak memory | 597644 kb |
| Host | smart-6233706d-8741-4006-9363-a04bf99ef85e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792083008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2792083008 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1550171920 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 31653038904 ps |
| CPU time | 3461.96 seconds |
| Started | Jul 27 08:27:11 PM PDT 24 |
| Finished | Jul 27 09:24:54 PM PDT 24 |
| Peak memory | 593340 kb |
| Host | smart-30e7351c-f287-4745-a3fc-bbcad8f3d3fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550171920 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1550171920 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.2452009541 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 71045811 ps |
| CPU time | 11.9 seconds |
| Started | Jul 27 08:27:29 PM PDT 24 |
| Finished | Jul 27 08:27:41 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-2a075af0-96e2-40c0-8667-3035932ddf94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452009541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 2452009541 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1592993956 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 61827617690 ps |
| CPU time | 1082.42 seconds |
| Started | Jul 27 08:27:29 PM PDT 24 |
| Finished | Jul 27 08:45:31 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-754fab85-2737-4de1-921d-9fb768539c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592993956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1592993956 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1531457659 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 1354841988 ps |
| CPU time | 41.38 seconds |
| Started | Jul 27 08:27:38 PM PDT 24 |
| Finished | Jul 27 08:28:20 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e0e287e4-5862-4d58-95eb-4d79598e8a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531457659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1531457659 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.3797240559 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 862880418 ps |
| CPU time | 24.89 seconds |
| Started | Jul 27 08:27:38 PM PDT 24 |
| Finished | Jul 27 08:28:03 PM PDT 24 |
| Peak memory | 575080 kb |
| Host | smart-d5d7e6a9-697f-4fe3-975c-92089933bd69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797240559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3797240559 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2921907489 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 2324047455 ps |
| CPU time | 97.75 seconds |
| Started | Jul 27 08:27:22 PM PDT 24 |
| Finished | Jul 27 08:29:00 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-62d75603-8513-45a7-858f-a48593a0df99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921907489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2921907489 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1799649294 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 105513924704 ps |
| CPU time | 1057.42 seconds |
| Started | Jul 27 08:27:26 PM PDT 24 |
| Finished | Jul 27 08:45:04 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-4a802fe5-fc00-4fed-b45a-cfb138cb4baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799649294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1799649294 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.4020543523 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 23644449189 ps |
| CPU time | 439.05 seconds |
| Started | Jul 27 08:27:31 PM PDT 24 |
| Finished | Jul 27 08:34:50 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-304ccc48-6682-4771-986c-65ca8aebd024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020543523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.4020543523 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3477800044 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 276836604 ps |
| CPU time | 29.07 seconds |
| Started | Jul 27 08:27:28 PM PDT 24 |
| Finished | Jul 27 08:27:57 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ef29e511-606d-4e87-85e7-5a0156a58f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477800044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3477800044 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.2680863581 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 1890612320 ps |
| CPU time | 60.43 seconds |
| Started | Jul 27 08:27:31 PM PDT 24 |
| Finished | Jul 27 08:28:32 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d8fd659a-db87-4816-8039-28326a60f7c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680863581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2680863581 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.1491407900 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 144024339 ps |
| CPU time | 9.38 seconds |
| Started | Jul 27 08:27:25 PM PDT 24 |
| Finished | Jul 27 08:27:35 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-ff35e25d-5ac2-40bc-a296-3c21e8681a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491407900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1491407900 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.38018194 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 8564682972 ps |
| CPU time | 92.34 seconds |
| Started | Jul 27 08:27:12 PM PDT 24 |
| Finished | Jul 27 08:28:45 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-8133cb50-0f7c-46ad-8f93-2818f61ff7f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38018194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.38018194 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.122945410 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 5885269781 ps |
| CPU time | 110.2 seconds |
| Started | Jul 27 08:27:24 PM PDT 24 |
| Finished | Jul 27 08:29:15 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-71c91721-5b67-460f-982e-f225a6737479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122945410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.122945410 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2211182973 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 51057818 ps |
| CPU time | 7.2 seconds |
| Started | Jul 27 08:27:10 PM PDT 24 |
| Finished | Jul 27 08:27:17 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-46165878-6170-44fa-a6ef-cdab5a0c5a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211182973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2211182973 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.4170710840 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1100620808 ps |
| CPU time | 102.96 seconds |
| Started | Jul 27 08:27:45 PM PDT 24 |
| Finished | Jul 27 08:29:28 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-bc6735c9-f01f-4ab3-9582-d769033e31f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170710840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4170710840 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3839449112 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 15990873130 ps |
| CPU time | 676.06 seconds |
| Started | Jul 27 08:27:47 PM PDT 24 |
| Finished | Jul 27 08:39:03 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-e4b4c80c-d7c4-4a2a-a3fa-42a0a1c6967a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839449112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3839449112 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2096946745 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 4237004907 ps |
| CPU time | 261.14 seconds |
| Started | Jul 27 08:27:47 PM PDT 24 |
| Finished | Jul 27 08:32:09 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-350ffb63-fbdd-457f-9323-8c30b056ce7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096946745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2096946745 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3985599259 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 154165097 ps |
| CPU time | 20.15 seconds |
| Started | Jul 27 08:27:37 PM PDT 24 |
| Finished | Jul 27 08:27:57 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-0ebfb852-6a43-49c8-8e8d-a05b1b24ecaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985599259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3985599259 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.2129365704 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 1224671971 ps |
| CPU time | 86.89 seconds |
| Started | Jul 27 08:39:12 PM PDT 24 |
| Finished | Jul 27 08:40:39 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-c4b1edb9-ef20-447b-8e3c-1dddd105135e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129365704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .2129365704 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.828591932 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 14895836929 ps |
| CPU time | 279.99 seconds |
| Started | Jul 27 08:39:17 PM PDT 24 |
| Finished | Jul 27 08:43:57 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-ff329032-4982-4003-a818-d043e360a4b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828591932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.828591932 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.673312258 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 332696295 ps |
| CPU time | 43.77 seconds |
| Started | Jul 27 08:39:16 PM PDT 24 |
| Finished | Jul 27 08:40:00 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-ed349f1c-e580-41e0-85c2-770e899ab0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673312258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .673312258 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.725196130 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 1695884076 ps |
| CPU time | 60.36 seconds |
| Started | Jul 27 08:39:13 PM PDT 24 |
| Finished | Jul 27 08:40:14 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-9a536d99-68e6-4968-8a4d-c93ecfe7c1f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725196130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.725196130 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2186812830 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 1690064083 ps |
| CPU time | 67.56 seconds |
| Started | Jul 27 08:39:04 PM PDT 24 |
| Finished | Jul 27 08:40:12 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-5148a140-b7d7-4946-a6f2-695907bc0677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186812830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2186812830 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2195542136 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 10545601981 ps |
| CPU time | 117.68 seconds |
| Started | Jul 27 08:39:05 PM PDT 24 |
| Finished | Jul 27 08:41:03 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-215ee7b5-21b2-4204-ae6e-fcf33c3f4fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195542136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2195542136 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2412452056 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 4383335682 ps |
| CPU time | 78.29 seconds |
| Started | Jul 27 08:39:13 PM PDT 24 |
| Finished | Jul 27 08:40:31 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-3a293798-5e98-4a16-af7b-4bceb7401315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412452056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2412452056 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2470227660 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 224011799 ps |
| CPU time | 22.62 seconds |
| Started | Jul 27 08:39:07 PM PDT 24 |
| Finished | Jul 27 08:39:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-06e14a8e-4d14-45d6-94b9-7e5cbb6f9c53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470227660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2470227660 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3223660166 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 444086545 ps |
| CPU time | 36.14 seconds |
| Started | Jul 27 08:39:18 PM PDT 24 |
| Finished | Jul 27 08:39:54 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-8811cdbf-fc37-404f-a209-65b3fb20a21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223660166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3223660166 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.2473849279 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 240426719 ps |
| CPU time | 10.11 seconds |
| Started | Jul 27 08:39:08 PM PDT 24 |
| Finished | Jul 27 08:39:18 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-a4c778cf-74af-4749-b3f2-3b666ce9818a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473849279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2473849279 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2943954527 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 8507613698 ps |
| CPU time | 86.71 seconds |
| Started | Jul 27 08:39:07 PM PDT 24 |
| Finished | Jul 27 08:40:34 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-276ee6d4-d543-419d-b07b-1c7d90b14b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943954527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2943954527 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.539281599 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 4065842134 ps |
| CPU time | 70.01 seconds |
| Started | Jul 27 08:39:05 PM PDT 24 |
| Finished | Jul 27 08:40:16 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-99952098-f359-4c4f-9171-c8379739435f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539281599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.539281599 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2733754068 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 39986321 ps |
| CPU time | 6.68 seconds |
| Started | Jul 27 08:39:07 PM PDT 24 |
| Finished | Jul 27 08:39:14 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-606333d4-28f7-4614-90fb-f697d2a60de6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733754068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2733754068 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3411538487 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 4235967007 ps |
| CPU time | 180.43 seconds |
| Started | Jul 27 08:39:17 PM PDT 24 |
| Finished | Jul 27 08:42:17 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-c31c8236-ae7b-4a43-a7c8-3272e78bb61f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411538487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3411538487 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.143535611 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 11944591098 ps |
| CPU time | 451.76 seconds |
| Started | Jul 27 08:39:16 PM PDT 24 |
| Finished | Jul 27 08:46:48 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-21f7b16f-af16-48c1-9944-47d33a225734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143535611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.143535611 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1088681304 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 821100384 ps |
| CPU time | 216.89 seconds |
| Started | Jul 27 08:39:16 PM PDT 24 |
| Finished | Jul 27 08:42:53 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-06a2fec7-cdff-4e33-804b-6920cf3438f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088681304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.1088681304 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3307220099 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 9343079654 ps |
| CPU time | 496.82 seconds |
| Started | Jul 27 08:39:25 PM PDT 24 |
| Finished | Jul 27 08:47:42 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-38c6cd85-5e7d-4b26-9992-5d801a2a3721 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307220099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3307220099 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.887596459 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 974967497 ps |
| CPU time | 43.78 seconds |
| Started | Jul 27 08:39:16 PM PDT 24 |
| Finished | Jul 27 08:40:00 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-297f1ebf-7943-4e42-a39e-2d0d866b269f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887596459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.887596459 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.556627168 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 3117195461 ps |
| CPU time | 121.88 seconds |
| Started | Jul 27 08:39:20 PM PDT 24 |
| Finished | Jul 27 08:41:22 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-9458f1bd-8ed6-4d05-85a2-c4b93dbc7489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556627168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 556627168 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1697848565 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 52763575033 ps |
| CPU time | 896.74 seconds |
| Started | Jul 27 08:39:30 PM PDT 24 |
| Finished | Jul 27 08:54:27 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-4753e2e4-e54b-4b61-9aa3-c63235949d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697848565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1697848565 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3015529286 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1228198583 ps |
| CPU time | 47.58 seconds |
| Started | Jul 27 08:39:22 PM PDT 24 |
| Finished | Jul 27 08:40:09 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-e6be2e47-87d4-4e8f-bc7b-50fdcb889e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015529286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3015529286 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3954178932 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 530403530 ps |
| CPU time | 48.21 seconds |
| Started | Jul 27 08:39:22 PM PDT 24 |
| Finished | Jul 27 08:40:11 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-67b9a3c8-833b-4cf5-b0d3-659cf3cdbe6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954178932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3954178932 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.267917333 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 712731506 ps |
| CPU time | 27.01 seconds |
| Started | Jul 27 08:39:21 PM PDT 24 |
| Finished | Jul 27 08:39:48 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-64c5ab56-c7c7-4f9f-8c38-b6a5ca69a937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267917333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.267917333 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.3821580100 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 100464193346 ps |
| CPU time | 962.67 seconds |
| Started | Jul 27 08:39:30 PM PDT 24 |
| Finished | Jul 27 08:55:33 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e7433a37-e4d9-42b0-9616-bc2946f20ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821580100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.3821580100 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2899441389 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 11143989519 ps |
| CPU time | 205.7 seconds |
| Started | Jul 27 08:39:24 PM PDT 24 |
| Finished | Jul 27 08:42:49 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-944c8665-9215-4760-aeb9-126a2d8eb7fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899441389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2899441389 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.3282431184 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 591426518 ps |
| CPU time | 52.05 seconds |
| Started | Jul 27 08:39:23 PM PDT 24 |
| Finished | Jul 27 08:40:15 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-dae7e489-64b6-4ba9-b06b-219ea76d26ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282431184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.3282431184 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.2001816749 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 354568103 ps |
| CPU time | 26.75 seconds |
| Started | Jul 27 08:39:21 PM PDT 24 |
| Finished | Jul 27 08:39:48 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-edb3fa53-3b5b-4d6f-b397-1249dcbc4c1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001816749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2001816749 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.2369863315 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 224649207 ps |
| CPU time | 10.04 seconds |
| Started | Jul 27 08:39:25 PM PDT 24 |
| Finished | Jul 27 08:39:35 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-6b71d18b-e927-42c6-8263-728ce7fe6603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369863315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2369863315 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2821604156 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 7121250952 ps |
| CPU time | 80.59 seconds |
| Started | Jul 27 08:39:25 PM PDT 24 |
| Finished | Jul 27 08:40:46 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-0e3da644-1e79-493f-9fc6-5821b329acb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821604156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2821604156 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.4144564044 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 5006864510 ps |
| CPU time | 88.24 seconds |
| Started | Jul 27 08:39:20 PM PDT 24 |
| Finished | Jul 27 08:40:48 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-decdda87-0e28-4ddc-8509-90e8eed68769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144564044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.4144564044 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3922861835 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 51532489 ps |
| CPU time | 6.51 seconds |
| Started | Jul 27 08:39:29 PM PDT 24 |
| Finished | Jul 27 08:39:36 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-9d975046-093f-490a-b2ae-6f31ec7dcba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922861835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.3922861835 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.1217882635 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 702388070 ps |
| CPU time | 63.61 seconds |
| Started | Jul 27 08:39:32 PM PDT 24 |
| Finished | Jul 27 08:40:36 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-93df333e-574e-48d6-bc9e-e5acc463a85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217882635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1217882635 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2335013505 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 2773524618 ps |
| CPU time | 302.1 seconds |
| Started | Jul 27 08:39:35 PM PDT 24 |
| Finished | Jul 27 08:44:37 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-b798a48f-6934-4ffd-a841-42bbee04dcae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335013505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2335013505 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1608970603 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 8234281727 ps |
| CPU time | 575.49 seconds |
| Started | Jul 27 08:39:32 PM PDT 24 |
| Finished | Jul 27 08:49:08 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-253dbafb-6f93-44f3-8753-a6a4fa7849ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608970603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1608970603 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1024741911 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 1325466077 ps |
| CPU time | 243.82 seconds |
| Started | Jul 27 08:39:33 PM PDT 24 |
| Finished | Jul 27 08:43:37 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-bdc0ffef-b75b-40ae-82be-19d0b784d46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024741911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1024741911 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.980642813 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 202208273 ps |
| CPU time | 28.48 seconds |
| Started | Jul 27 08:39:19 PM PDT 24 |
| Finished | Jul 27 08:39:48 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-0a3fdfed-999a-42f4-a02b-a8a44b4125ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980642813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.980642813 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.1244063201 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 83482052 ps |
| CPU time | 8.85 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:39:49 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-f469e9d2-d700-4e02-bd38-d438c56d5227 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244063201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .1244063201 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1568191364 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 29311048360 ps |
| CPU time | 513.48 seconds |
| Started | Jul 27 08:39:39 PM PDT 24 |
| Finished | Jul 27 08:48:13 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-46383ebd-3e9a-49b3-bf86-cf6ff5a2a54e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568191364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.1568191364 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.451828952 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 544403482 ps |
| CPU time | 25.55 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:40:06 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-06cbeba1-bd1b-4a73-ab2b-21362cbee9c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451828952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr .451828952 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1976970054 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 389952530 ps |
| CPU time | 35.47 seconds |
| Started | Jul 27 08:39:44 PM PDT 24 |
| Finished | Jul 27 08:40:19 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-305f0de5-e214-4ea5-a8f7-caf217e172e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976970054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1976970054 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3751054619 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 30626619 ps |
| CPU time | 6.2 seconds |
| Started | Jul 27 08:39:32 PM PDT 24 |
| Finished | Jul 27 08:39:38 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-8da088da-d7ce-4f31-b2c8-9df36df08c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751054619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3751054619 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3601477130 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 15937938182 ps |
| CPU time | 165.76 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:42:26 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-c05a20a3-a6bf-4e64-b89a-eadf54585293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601477130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3601477130 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.3367321668 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 67971235467 ps |
| CPU time | 1127.5 seconds |
| Started | Jul 27 08:39:41 PM PDT 24 |
| Finished | Jul 27 08:58:29 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-978bf5f5-1a0a-4b12-8de2-e173d910be12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367321668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3367321668 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.634122312 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 486089571 ps |
| CPU time | 49.61 seconds |
| Started | Jul 27 08:39:33 PM PDT 24 |
| Finished | Jul 27 08:40:23 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-901e5d12-2fcb-4a89-b055-2d93e91f254d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634122312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.634122312 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2332475107 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 2517476682 ps |
| CPU time | 74.48 seconds |
| Started | Jul 27 08:39:42 PM PDT 24 |
| Finished | Jul 27 08:40:56 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-fe6daa60-f410-420d-87a7-14cebffa42f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332475107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2332475107 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2930256381 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 180805557 ps |
| CPU time | 9.12 seconds |
| Started | Jul 27 08:39:32 PM PDT 24 |
| Finished | Jul 27 08:39:41 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-14d94338-97e4-41ce-8694-3b22e85a512c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930256381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2930256381 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.2550070756 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 10028888848 ps |
| CPU time | 107.38 seconds |
| Started | Jul 27 08:39:31 PM PDT 24 |
| Finished | Jul 27 08:41:19 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-68a3df4e-5c0b-459a-b2a4-e58e270ef2fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550070756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2550070756 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2230357489 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 4976585430 ps |
| CPU time | 90.22 seconds |
| Started | Jul 27 08:39:32 PM PDT 24 |
| Finished | Jul 27 08:41:02 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-cfa00de8-842c-4e20-aeb9-8d319c39101f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230357489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2230357489 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.888444281 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 45057977 ps |
| CPU time | 6.61 seconds |
| Started | Jul 27 08:39:33 PM PDT 24 |
| Finished | Jul 27 08:39:40 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-7a60a1f0-2326-415f-a9f0-592f1bd0b9e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888444281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .888444281 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.2237860922 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 13913994773 ps |
| CPU time | 525.91 seconds |
| Started | Jul 27 08:39:41 PM PDT 24 |
| Finished | Jul 27 08:48:27 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-ca7622c6-7815-4c7d-a6bd-2ae5adbd1d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237860922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2237860922 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.484667006 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 7840377836 ps |
| CPU time | 322.74 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:45:03 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-0c0e51d2-b5c3-43da-8a44-b83dac135bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484667006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.484667006 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3031778848 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 454500463 ps |
| CPU time | 151.89 seconds |
| Started | Jul 27 08:39:47 PM PDT 24 |
| Finished | Jul 27 08:42:19 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-076a5ed2-c296-45a7-a000-d727f2e1d31d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031778848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.3031778848 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3894874181 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 2840317686 ps |
| CPU time | 382.61 seconds |
| Started | Jul 27 08:39:42 PM PDT 24 |
| Finished | Jul 27 08:46:05 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-3fd8eab5-b417-4445-9ee7-c1cc8471b68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894874181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.3894874181 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2776143411 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 49954911 ps |
| CPU time | 8.72 seconds |
| Started | Jul 27 08:39:44 PM PDT 24 |
| Finished | Jul 27 08:39:53 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-78bad21a-558e-41eb-b002-d114417bfe2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776143411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2776143411 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.450995493 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 1929226775 ps |
| CPU time | 76.24 seconds |
| Started | Jul 27 08:39:41 PM PDT 24 |
| Finished | Jul 27 08:40:57 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-1473eae6-e27f-42e1-acec-ebe706c16ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450995493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 450995493 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1222306504 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 49772166150 ps |
| CPU time | 830.41 seconds |
| Started | Jul 27 08:39:41 PM PDT 24 |
| Finished | Jul 27 08:53:32 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-20ef3c72-e263-495f-aff6-6609f4aeee7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222306504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1222306504 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3549765223 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 266301278 ps |
| CPU time | 31.28 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:40:11 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-58b0ec15-ff9f-4d1d-b5e5-d7868b8a2036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549765223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.3549765223 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.538043440 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 357516967 ps |
| CPU time | 29.39 seconds |
| Started | Jul 27 08:39:42 PM PDT 24 |
| Finished | Jul 27 08:40:11 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-4905b460-fafe-45f0-8d5a-e0c5683ae4f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538043440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.538043440 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.834102222 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 1754812257 ps |
| CPU time | 66 seconds |
| Started | Jul 27 08:39:42 PM PDT 24 |
| Finished | Jul 27 08:40:48 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ba79cd65-fc4d-4865-b949-11bcf7dffedd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834102222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.834102222 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2057003977 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 30992481823 ps |
| CPU time | 347.12 seconds |
| Started | Jul 27 08:39:41 PM PDT 24 |
| Finished | Jul 27 08:45:29 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-69176569-7e8a-4895-a3da-d77112e5db3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057003977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2057003977 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.79444691 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 23936992259 ps |
| CPU time | 445.5 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:47:06 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-f8937da3-86c2-4d6c-bae6-413a2d6d8c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79444691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.79444691 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3374003446 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 332529239 ps |
| CPU time | 34.48 seconds |
| Started | Jul 27 08:39:46 PM PDT 24 |
| Finished | Jul 27 08:40:21 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-d90ced23-2428-4745-8b04-d8dd2292bbf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374003446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3374003446 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.325558520 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 182116006 ps |
| CPU time | 8.02 seconds |
| Started | Jul 27 08:39:43 PM PDT 24 |
| Finished | Jul 27 08:39:52 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-6950d5bc-b28d-4056-a0c4-1cf45454d270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325558520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.325558520 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.3621518933 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 177270411 ps |
| CPU time | 8.3 seconds |
| Started | Jul 27 08:39:44 PM PDT 24 |
| Finished | Jul 27 08:39:53 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-0a109ead-aae6-491c-b1af-f9617c9a7a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621518933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3621518933 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2053892734 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 6768686111 ps |
| CPU time | 77.52 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:40:58 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-9cfc7157-9274-41b4-8fc9-fc79aad8322c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053892734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2053892734 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.532135937 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 5460201813 ps |
| CPU time | 90.73 seconds |
| Started | Jul 27 08:39:40 PM PDT 24 |
| Finished | Jul 27 08:41:11 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-2235080e-0564-4623-8d45-deb8d337e54a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532135937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.532135937 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3102903091 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 52006317 ps |
| CPU time | 6.78 seconds |
| Started | Jul 27 08:39:41 PM PDT 24 |
| Finished | Jul 27 08:39:48 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-ca74909a-fe0f-4129-a4ee-23bbce843ee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102903091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3102903091 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3512100083 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 6833686911 ps |
| CPU time | 273.04 seconds |
| Started | Jul 27 08:39:42 PM PDT 24 |
| Finished | Jul 27 08:44:16 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-40bb7b5b-0d8b-46c2-af58-27b11f6c353a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512100083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3512100083 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1782819892 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 722024304 ps |
| CPU time | 30.48 seconds |
| Started | Jul 27 08:39:50 PM PDT 24 |
| Finished | Jul 27 08:40:20 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e542ebe6-10db-47c5-af27-276ddcdbe1a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782819892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1782819892 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.4148231414 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 252903908 ps |
| CPU time | 74.74 seconds |
| Started | Jul 27 08:39:47 PM PDT 24 |
| Finished | Jul 27 08:41:02 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-2793ba90-0cba-4ed5-9cef-c0861e4fe499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148231414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.4148231414 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3388465715 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 532373079 ps |
| CPU time | 247.66 seconds |
| Started | Jul 27 08:39:48 PM PDT 24 |
| Finished | Jul 27 08:43:56 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-df846063-17ce-4c09-bc9a-a4bcd9e76c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388465715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.3388465715 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2977281755 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1042972230 ps |
| CPU time | 54.83 seconds |
| Started | Jul 27 08:39:45 PM PDT 24 |
| Finished | Jul 27 08:40:40 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-e04a5892-5d22-4ff7-97e2-1e7d57c28d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977281755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2977281755 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.4165072221 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 3569906838 ps |
| CPU time | 161.28 seconds |
| Started | Jul 27 08:39:52 PM PDT 24 |
| Finished | Jul 27 08:42:33 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-56e37f92-da09-49dd-b339-58e22de5b6cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165072221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .4165072221 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3193339763 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 97013982588 ps |
| CPU time | 1691.12 seconds |
| Started | Jul 27 08:39:50 PM PDT 24 |
| Finished | Jul 27 09:08:02 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-f2e2226c-f3d7-449a-be3e-72a9359bf2a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193339763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3193339763 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1320046963 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 264439898 ps |
| CPU time | 33.82 seconds |
| Started | Jul 27 08:39:48 PM PDT 24 |
| Finished | Jul 27 08:40:21 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-f0ab2fbd-4524-492f-803f-d2a34110a251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320046963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1320046963 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.678160357 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 853529205 ps |
| CPU time | 32.15 seconds |
| Started | Jul 27 08:39:49 PM PDT 24 |
| Finished | Jul 27 08:40:21 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-c60fae3a-3817-43ef-998f-a61b68d44a30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678160357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.678160357 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.3124931227 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 2188313375 ps |
| CPU time | 78.96 seconds |
| Started | Jul 27 08:39:48 PM PDT 24 |
| Finished | Jul 27 08:41:07 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-ba874ff9-2f05-418a-913a-bfc9ddbe589f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124931227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3124931227 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.234714933 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 103408329808 ps |
| CPU time | 1095.66 seconds |
| Started | Jul 27 08:39:51 PM PDT 24 |
| Finished | Jul 27 08:58:07 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-c7b3f777-a462-4bd7-8350-769594be6871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234714933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.234714933 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.29028455 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 24498072238 ps |
| CPU time | 430.76 seconds |
| Started | Jul 27 08:39:52 PM PDT 24 |
| Finished | Jul 27 08:47:02 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-4eb13b74-9429-40a7-9781-9b4b81b05cc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29028455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.29028455 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2591422833 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 95567022 ps |
| CPU time | 12.9 seconds |
| Started | Jul 27 08:39:50 PM PDT 24 |
| Finished | Jul 27 08:40:03 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-840ed516-76d2-4e6c-a6ec-0b22ef8894d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591422833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2591422833 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.2597660018 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 2115634939 ps |
| CPU time | 79.36 seconds |
| Started | Jul 27 08:39:52 PM PDT 24 |
| Finished | Jul 27 08:41:11 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-0e5b2e75-4799-4adb-9c1b-dee1dcfdfaf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597660018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2597660018 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3162533558 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 220100167 ps |
| CPU time | 10.34 seconds |
| Started | Jul 27 08:39:54 PM PDT 24 |
| Finished | Jul 27 08:40:04 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-ee5a6b3d-6e4d-4810-a7ee-920252343d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162533558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3162533558 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2807275758 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 9306229840 ps |
| CPU time | 98.84 seconds |
| Started | Jul 27 08:39:49 PM PDT 24 |
| Finished | Jul 27 08:41:28 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-6fce66e5-d3b6-4d49-8f0b-3b4a6e306c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807275758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2807275758 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.4222012055 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 4792669500 ps |
| CPU time | 82.93 seconds |
| Started | Jul 27 08:39:51 PM PDT 24 |
| Finished | Jul 27 08:41:14 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-bd3b343d-e822-4eac-931e-3f4dbfe76a7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222012055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4222012055 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2380034561 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 52267123 ps |
| CPU time | 7.31 seconds |
| Started | Jul 27 08:39:54 PM PDT 24 |
| Finished | Jul 27 08:40:01 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-9e949d3c-a4fe-4cca-abd0-730a91d8b71e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380034561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.2380034561 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2554026835 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 6790203458 ps |
| CPU time | 258.86 seconds |
| Started | Jul 27 08:39:49 PM PDT 24 |
| Finished | Jul 27 08:44:08 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-22d3e257-5225-49ab-85a8-d7eda48ddd73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554026835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2554026835 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1990309119 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 10310210226 ps |
| CPU time | 425.68 seconds |
| Started | Jul 27 08:39:51 PM PDT 24 |
| Finished | Jul 27 08:46:57 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-655c0958-95f4-4786-b783-2d5c412e01b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990309119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1990309119 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1676946935 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 530427165 ps |
| CPU time | 193.27 seconds |
| Started | Jul 27 08:39:50 PM PDT 24 |
| Finished | Jul 27 08:43:04 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-4abca381-bb94-4894-83ad-8c6c4ba5a3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676946935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1676946935 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2260590963 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 116463029 ps |
| CPU time | 45.73 seconds |
| Started | Jul 27 08:39:52 PM PDT 24 |
| Finished | Jul 27 08:40:38 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-0a4053a7-78c9-4f55-a462-b740e31b215b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260590963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2260590963 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2889959406 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 1031060868 ps |
| CPU time | 46.43 seconds |
| Started | Jul 27 08:39:49 PM PDT 24 |
| Finished | Jul 27 08:40:36 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-05490534-cf0e-48eb-810f-e77ced8f444e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889959406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2889959406 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.736089461 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 1533211981 ps |
| CPU time | 62.38 seconds |
| Started | Jul 27 08:39:57 PM PDT 24 |
| Finished | Jul 27 08:40:59 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-70ada550-5ff8-4829-b8bc-7ffc5c6e32c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736089461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device. 736089461 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1290483781 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 62438170741 ps |
| CPU time | 1110.69 seconds |
| Started | Jul 27 08:39:56 PM PDT 24 |
| Finished | Jul 27 08:58:27 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7e24f6dc-7458-4770-a751-51d400552b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290483781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1290483781 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2202801267 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 1052245423 ps |
| CPU time | 42.84 seconds |
| Started | Jul 27 08:40:05 PM PDT 24 |
| Finished | Jul 27 08:40:48 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-742459c8-6346-48df-a657-08d8d942bfb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202801267 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2202801267 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.4255776101 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 1418733791 ps |
| CPU time | 51.65 seconds |
| Started | Jul 27 08:39:57 PM PDT 24 |
| Finished | Jul 27 08:40:49 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-7e59142b-0a7d-463a-be37-6188758ac645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255776101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.4255776101 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.3979267544 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 113360782 ps |
| CPU time | 13.81 seconds |
| Started | Jul 27 08:39:59 PM PDT 24 |
| Finished | Jul 27 08:40:13 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-3561368f-3323-48ae-a7ca-4662e5b08063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979267544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.3979267544 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3987197460 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 18948829290 ps |
| CPU time | 177.51 seconds |
| Started | Jul 27 08:40:00 PM PDT 24 |
| Finished | Jul 27 08:42:57 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-4257462c-5ce6-4b55-a3f2-59aa0bc94f3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987197460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3987197460 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2816554003 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 15109233569 ps |
| CPU time | 258.02 seconds |
| Started | Jul 27 08:39:58 PM PDT 24 |
| Finished | Jul 27 08:44:16 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-de2ef3ad-89d1-44cb-87fc-16701ce9dad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816554003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2816554003 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2880258560 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 336361159 ps |
| CPU time | 25.79 seconds |
| Started | Jul 27 08:39:59 PM PDT 24 |
| Finished | Jul 27 08:40:25 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-37084bd7-ffca-44bd-be43-11f9d4282e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880258560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2880258560 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3924938924 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 420664491 ps |
| CPU time | 32.5 seconds |
| Started | Jul 27 08:39:57 PM PDT 24 |
| Finished | Jul 27 08:40:30 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-062c8600-539f-404e-8dd3-2c32d2819fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924938924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3924938924 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2548886810 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 180641044 ps |
| CPU time | 9.17 seconds |
| Started | Jul 27 08:39:57 PM PDT 24 |
| Finished | Jul 27 08:40:07 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-52fb6edc-7ed7-4378-a21f-b0abf8eca50c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548886810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2548886810 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1352154599 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 6796059203 ps |
| CPU time | 74.07 seconds |
| Started | Jul 27 08:40:00 PM PDT 24 |
| Finished | Jul 27 08:41:14 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-96cb2879-08c2-460a-a03a-0140d3adf406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352154599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1352154599 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3096621765 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 4695146367 ps |
| CPU time | 80.2 seconds |
| Started | Jul 27 08:40:01 PM PDT 24 |
| Finished | Jul 27 08:41:21 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-836577a0-f3bf-4a0f-bbfc-48bc2e074b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096621765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3096621765 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3613620233 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 46853595 ps |
| CPU time | 6.55 seconds |
| Started | Jul 27 08:40:00 PM PDT 24 |
| Finished | Jul 27 08:40:07 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a2d50452-0310-4de9-ab79-52e59be0fe8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613620233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.3613620233 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.1269188150 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 7985894423 ps |
| CPU time | 344.01 seconds |
| Started | Jul 27 08:40:05 PM PDT 24 |
| Finished | Jul 27 08:45:49 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-01dfb970-02b0-4127-aa72-2c9323dd30e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269188150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1269188150 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.705214632 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 18342926944 ps |
| CPU time | 612.73 seconds |
| Started | Jul 27 08:40:04 PM PDT 24 |
| Finished | Jul 27 08:50:17 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-53f42f1b-6b08-406e-8b13-5ab8a0e55c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705214632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.705214632 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.903069736 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 2564073079 ps |
| CPU time | 311.73 seconds |
| Started | Jul 27 08:40:08 PM PDT 24 |
| Finished | Jul 27 08:45:20 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-5adf76d7-0671-4a30-a532-913d242bdaae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903069736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_ with_rand_reset.903069736 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1310220304 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 2135545324 ps |
| CPU time | 268.67 seconds |
| Started | Jul 27 08:40:08 PM PDT 24 |
| Finished | Jul 27 08:44:37 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-0f8f63ab-dd84-496b-828c-45320bfb8e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310220304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.1310220304 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3687767318 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 643613515 ps |
| CPU time | 31.18 seconds |
| Started | Jul 27 08:40:04 PM PDT 24 |
| Finished | Jul 27 08:40:36 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-a086b728-2848-4df6-9827-1bd5f7de9a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687767318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3687767318 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.996149817 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 348358353 ps |
| CPU time | 36.59 seconds |
| Started | Jul 27 08:40:12 PM PDT 24 |
| Finished | Jul 27 08:40:49 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-b2c063cc-5564-4ece-9560-ecdf03f06544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996149817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device. 996149817 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.3165238842 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 41167275101 ps |
| CPU time | 744.01 seconds |
| Started | Jul 27 08:40:12 PM PDT 24 |
| Finished | Jul 27 08:52:36 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-1ad07cbf-2e74-47b7-ac6d-94d1935cfd53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165238842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.3165238842 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2241850234 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 149055125 ps |
| CPU time | 21.19 seconds |
| Started | Jul 27 08:40:13 PM PDT 24 |
| Finished | Jul 27 08:40:34 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-d2f055fc-a74b-4439-9b5f-2280babb5947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241850234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2241850234 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.3063499711 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 1898037805 ps |
| CPU time | 62.37 seconds |
| Started | Jul 27 08:40:17 PM PDT 24 |
| Finished | Jul 27 08:41:20 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-eec798dc-10b9-4bab-b0aa-203a22f89860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063499711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3063499711 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2349429236 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 513186707 ps |
| CPU time | 46.91 seconds |
| Started | Jul 27 08:40:08 PM PDT 24 |
| Finished | Jul 27 08:40:55 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-da739cbd-4582-44c1-8ec2-a1e53ccf7ac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349429236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2349429236 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2572689007 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 3217320591 ps |
| CPU time | 35.61 seconds |
| Started | Jul 27 08:40:17 PM PDT 24 |
| Finished | Jul 27 08:40:53 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-1c7fea96-c9a7-4169-a0bd-4cc946090eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572689007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2572689007 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2917346848 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 28331015698 ps |
| CPU time | 534.5 seconds |
| Started | Jul 27 08:40:12 PM PDT 24 |
| Finished | Jul 27 08:49:07 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-74318d0c-f149-440a-9aa2-e630e4873966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917346848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2917346848 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.4024256834 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 442505715 ps |
| CPU time | 38.04 seconds |
| Started | Jul 27 08:40:07 PM PDT 24 |
| Finished | Jul 27 08:40:45 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-a81faee5-1587-4538-b609-82afd808520b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024256834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.4024256834 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.213711224 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 154927324 ps |
| CPU time | 14.06 seconds |
| Started | Jul 27 08:40:16 PM PDT 24 |
| Finished | Jul 27 08:40:30 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-2790ea10-1da0-4496-a257-93fd2f8cd8d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213711224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.213711224 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.3406755877 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 225179260 ps |
| CPU time | 10.48 seconds |
| Started | Jul 27 08:40:12 PM PDT 24 |
| Finished | Jul 27 08:40:22 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-32f1bbb2-1e6a-437a-9b2d-a6d8e2718801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406755877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3406755877 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3235543745 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 8141605410 ps |
| CPU time | 94.8 seconds |
| Started | Jul 27 08:40:08 PM PDT 24 |
| Finished | Jul 27 08:41:43 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-f37e19f5-29c5-4332-a0c6-fe644e3c76db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235543745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3235543745 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3264733203 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 4380458646 ps |
| CPU time | 79.48 seconds |
| Started | Jul 27 08:40:12 PM PDT 24 |
| Finished | Jul 27 08:41:31 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-37e0e631-0b98-4e73-a909-3ee4956cc92b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264733203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3264733203 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2438615018 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 41890860 ps |
| CPU time | 5.85 seconds |
| Started | Jul 27 08:40:06 PM PDT 24 |
| Finished | Jul 27 08:40:12 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-7c8b7bff-5103-4a08-be98-7e9e12bcf343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438615018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.2438615018 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.4070123159 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 338175092 ps |
| CPU time | 30.4 seconds |
| Started | Jul 27 08:40:13 PM PDT 24 |
| Finished | Jul 27 08:40:43 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-8e776884-3f86-40ea-ae58-49ea2b0881c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070123159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.4070123159 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.3317841633 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 7848253343 ps |
| CPU time | 320.02 seconds |
| Started | Jul 27 08:40:15 PM PDT 24 |
| Finished | Jul 27 08:45:35 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-c11c291b-9512-43eb-8a3f-bf613aa51bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317841633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3317841633 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2730487028 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 136632144 ps |
| CPU time | 73.78 seconds |
| Started | Jul 27 08:40:13 PM PDT 24 |
| Finished | Jul 27 08:41:27 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-0b72aeaf-7eee-4d62-a0f6-d39d13898c90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730487028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.2730487028 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.860859937 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 218177687 ps |
| CPU time | 49.86 seconds |
| Started | Jul 27 08:40:13 PM PDT 24 |
| Finished | Jul 27 08:41:03 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-1831d6ae-92c7-43d5-a76b-f12f88d8d573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860859937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_reset_error.860859937 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3519697622 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 1359945377 ps |
| CPU time | 70.13 seconds |
| Started | Jul 27 08:40:14 PM PDT 24 |
| Finished | Jul 27 08:41:24 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-2920e677-98b1-4a32-9f8d-d75840bea85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519697622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3519697622 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2614120390 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 770305306 ps |
| CPU time | 62.58 seconds |
| Started | Jul 27 08:40:21 PM PDT 24 |
| Finished | Jul 27 08:41:24 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d0de24ba-2b6d-4aff-98a9-b5785491ddc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614120390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2614120390 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2245707506 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 109561855 ps |
| CPU time | 16.1 seconds |
| Started | Jul 27 08:40:22 PM PDT 24 |
| Finished | Jul 27 08:40:38 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-42dd9ea9-64e3-4713-9a29-682a9a50b678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245707506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2245707506 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.4194358106 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 579859914 ps |
| CPU time | 41.24 seconds |
| Started | Jul 27 08:40:20 PM PDT 24 |
| Finished | Jul 27 08:41:02 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-cdc7c5c4-c84e-41fd-9295-5d3c5a8c03a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194358106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.4194358106 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.1444205884 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 407047865 ps |
| CPU time | 16.2 seconds |
| Started | Jul 27 08:40:22 PM PDT 24 |
| Finished | Jul 27 08:40:38 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-9270f3e5-5a63-4494-8db4-fe265271bad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444205884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1444205884 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.631141657 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 22230012516 ps |
| CPU time | 253.12 seconds |
| Started | Jul 27 08:40:22 PM PDT 24 |
| Finished | Jul 27 08:44:36 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-6192ba7b-c785-427e-a721-69f59c45e33d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631141657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.631141657 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3301072938 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 48157121589 ps |
| CPU time | 831.41 seconds |
| Started | Jul 27 08:40:23 PM PDT 24 |
| Finished | Jul 27 08:54:14 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-f0cc1d1e-02bf-45a8-abd9-244a1f4c9df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301072938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3301072938 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.631269181 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 214051075 ps |
| CPU time | 24.72 seconds |
| Started | Jul 27 08:40:21 PM PDT 24 |
| Finished | Jul 27 08:40:46 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-32435ecb-a5d2-4f15-806d-9e665d53db5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631269181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.631269181 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.3084359032 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 1327029023 ps |
| CPU time | 41.19 seconds |
| Started | Jul 27 08:40:21 PM PDT 24 |
| Finished | Jul 27 08:41:02 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-dbdaec75-6011-4087-9e28-a10f3fdb7f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084359032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3084359032 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.3707638963 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 214348670 ps |
| CPU time | 10.33 seconds |
| Started | Jul 27 08:40:13 PM PDT 24 |
| Finished | Jul 27 08:40:23 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-fd575bd7-9a09-4d81-b5e1-6c56126baadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707638963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3707638963 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.912337933 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 7582928834 ps |
| CPU time | 79.71 seconds |
| Started | Jul 27 08:40:14 PM PDT 24 |
| Finished | Jul 27 08:41:34 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-d2e06eb9-8b37-425c-998b-0a601005cf1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912337933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.912337933 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1724102721 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 5794513165 ps |
| CPU time | 97.39 seconds |
| Started | Jul 27 08:40:22 PM PDT 24 |
| Finished | Jul 27 08:41:59 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-62205023-b791-4d44-9459-9eb7b0760763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724102721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1724102721 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3546830819 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 41528441 ps |
| CPU time | 6.38 seconds |
| Started | Jul 27 08:40:14 PM PDT 24 |
| Finished | Jul 27 08:40:21 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-1d20c376-adb7-405b-a68d-06a36c812bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546830819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.3546830819 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.4151169708 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 6223586217 ps |
| CPU time | 236.99 seconds |
| Started | Jul 27 08:40:21 PM PDT 24 |
| Finished | Jul 27 08:44:18 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-1a7fd055-9ee9-47d1-b925-62f28f992764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151169708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4151169708 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.561170320 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 4168536170 ps |
| CPU time | 363.93 seconds |
| Started | Jul 27 08:40:24 PM PDT 24 |
| Finished | Jul 27 08:46:28 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-c6c18e6b-47a5-48fd-8f75-2d411e331821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561170320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.561170320 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3052880686 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1361494620 ps |
| CPU time | 133.74 seconds |
| Started | Jul 27 08:40:24 PM PDT 24 |
| Finished | Jul 27 08:42:38 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-c04b0a61-4774-42a5-b9aa-bf6372e69139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052880686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3052880686 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3821934674 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 171453874 ps |
| CPU time | 45.76 seconds |
| Started | Jul 27 08:40:22 PM PDT 24 |
| Finished | Jul 27 08:41:08 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-1d7b4606-73e7-4369-988c-bc1bd8332ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821934674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3821934674 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3805534555 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 434857435 ps |
| CPU time | 18.86 seconds |
| Started | Jul 27 08:40:21 PM PDT 24 |
| Finished | Jul 27 08:40:40 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c23431b9-83cc-4631-bb34-fb1904f0a179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805534555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3805534555 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1661453509 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 576584048 ps |
| CPU time | 26.4 seconds |
| Started | Jul 27 08:40:30 PM PDT 24 |
| Finished | Jul 27 08:40:56 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-d78b6ba3-3022-4079-9ebb-2ef746ee1d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661453509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1661453509 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3612400946 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 56467292192 ps |
| CPU time | 926.47 seconds |
| Started | Jul 27 08:40:33 PM PDT 24 |
| Finished | Jul 27 08:55:59 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-ddaf8892-8705-40f3-a5f2-00c8f7aad1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612400946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3612400946 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1251721575 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 84559991 ps |
| CPU time | 12.94 seconds |
| Started | Jul 27 08:40:37 PM PDT 24 |
| Finished | Jul 27 08:40:50 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-34cfb710-0e9d-4807-97f6-c8a512c58db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251721575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1251721575 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.1502378542 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 2398759015 ps |
| CPU time | 86.28 seconds |
| Started | Jul 27 08:40:39 PM PDT 24 |
| Finished | Jul 27 08:42:05 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4a61fb04-8297-46b0-ac35-94f0ec695f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502378542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.1502378542 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.4006575866 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 320780469 ps |
| CPU time | 15.88 seconds |
| Started | Jul 27 08:40:32 PM PDT 24 |
| Finished | Jul 27 08:40:48 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-8f748142-ec65-46eb-9565-1607eba9b455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006575866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.4006575866 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3279117191 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 108283156314 ps |
| CPU time | 1144.41 seconds |
| Started | Jul 27 08:40:28 PM PDT 24 |
| Finished | Jul 27 08:59:33 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ca0da5dc-9182-4785-8c55-cde27f92bf4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279117191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3279117191 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.106967318 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 54256248471 ps |
| CPU time | 919.12 seconds |
| Started | Jul 27 08:40:34 PM PDT 24 |
| Finished | Jul 27 08:55:53 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-0e832db7-5656-4672-8ae0-d1178d94a7e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106967318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.106967318 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1186978555 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 591566325 ps |
| CPU time | 63.19 seconds |
| Started | Jul 27 08:40:29 PM PDT 24 |
| Finished | Jul 27 08:41:33 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-8a06a0bf-5ffe-457f-922c-843e693ee059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186978555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1186978555 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1530181336 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 243842622 ps |
| CPU time | 22.46 seconds |
| Started | Jul 27 08:40:38 PM PDT 24 |
| Finished | Jul 27 08:41:00 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-c68225bc-677d-4a7c-b05b-703ca1de31cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530181336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1530181336 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2748711803 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 232191418 ps |
| CPU time | 9.86 seconds |
| Started | Jul 27 08:40:21 PM PDT 24 |
| Finished | Jul 27 08:40:31 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-f171a9db-3624-47c3-9c04-b5f8ff23925f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748711803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2748711803 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2824522499 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 7828164006 ps |
| CPU time | 80.56 seconds |
| Started | Jul 27 08:40:34 PM PDT 24 |
| Finished | Jul 27 08:41:54 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-106db823-9084-4d67-b8a8-bbe73fb28d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824522499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2824522499 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3801825145 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 5002585680 ps |
| CPU time | 86.82 seconds |
| Started | Jul 27 08:40:34 PM PDT 24 |
| Finished | Jul 27 08:42:01 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-c530337a-8d95-4d92-b927-5310d8d84f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801825145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3801825145 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1984680576 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 54128970 ps |
| CPU time | 6.98 seconds |
| Started | Jul 27 08:40:30 PM PDT 24 |
| Finished | Jul 27 08:40:37 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-be3a25b1-643c-4222-b7e9-ae7c4dc472d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984680576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.1984680576 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3719556973 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 8423313094 ps |
| CPU time | 321.83 seconds |
| Started | Jul 27 08:40:39 PM PDT 24 |
| Finished | Jul 27 08:46:01 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-190597cc-cb31-493b-b1be-169e21f7bc77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719556973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3719556973 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2563962487 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 12992740755 ps |
| CPU time | 547.44 seconds |
| Started | Jul 27 08:40:41 PM PDT 24 |
| Finished | Jul 27 08:49:48 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-418761d8-41ae-473c-8ecb-66a3f0166ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563962487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2563962487 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4208410313 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 22495602 ps |
| CPU time | 12.5 seconds |
| Started | Jul 27 08:40:39 PM PDT 24 |
| Finished | Jul 27 08:40:51 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-44ba07a9-0736-4a2c-a148-d040b872da55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208410313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.4208410313 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.1004902275 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 288966534 ps |
| CPU time | 14.98 seconds |
| Started | Jul 27 08:40:43 PM PDT 24 |
| Finished | Jul 27 08:40:58 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-41773c22-bf09-4a77-b2b6-d943abddb250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004902275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1004902275 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.873249419 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 1090935264 ps |
| CPU time | 45.72 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:41:32 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-f3657e3c-0dab-4bc1-9a00-3ce58c73caae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873249419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device. 873249419 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1799164230 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 80859488310 ps |
| CPU time | 1499.68 seconds |
| Started | Jul 27 08:40:48 PM PDT 24 |
| Finished | Jul 27 09:05:48 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-f5e03c9c-e9fe-4c2f-83d8-61a3aa690e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799164230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1799164230 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1513251387 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 1412837198 ps |
| CPU time | 59.65 seconds |
| Started | Jul 27 08:40:51 PM PDT 24 |
| Finished | Jul 27 08:41:51 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a4478b6d-953d-4b75-83e2-1fa2ed97f19f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513251387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1513251387 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.1548332141 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 497157209 ps |
| CPU time | 47.94 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:41:35 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-0e481dde-6cc3-46b5-aa33-dfe4c3f056e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548332141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1548332141 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2319438343 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 1542381044 ps |
| CPU time | 59.4 seconds |
| Started | Jul 27 08:40:52 PM PDT 24 |
| Finished | Jul 27 08:41:51 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-d73d73ce-9b98-4c03-845c-e9c6ca19696b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319438343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2319438343 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3955375787 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 53081484220 ps |
| CPU time | 553.21 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:50:00 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-95c1ef24-7ff4-4771-be37-f70eb327b1e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955375787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3955375787 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1410946140 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 56771382575 ps |
| CPU time | 1001.34 seconds |
| Started | Jul 27 08:40:52 PM PDT 24 |
| Finished | Jul 27 08:57:34 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-489ddd14-7172-4fb1-8470-6a4edbe33a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410946140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1410946140 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.4176757489 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 68564264 ps |
| CPU time | 9.08 seconds |
| Started | Jul 27 08:40:52 PM PDT 24 |
| Finished | Jul 27 08:41:02 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-91f4fa26-dea0-45a2-ab88-4439e2da0eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176757489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.4176757489 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3326902953 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 515077737 ps |
| CPU time | 38.89 seconds |
| Started | Jul 27 08:40:52 PM PDT 24 |
| Finished | Jul 27 08:41:31 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-ac27d314-07a1-417a-af09-a0346f0a7887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326902953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3326902953 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1707460710 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 147098277 ps |
| CPU time | 7.87 seconds |
| Started | Jul 27 08:40:38 PM PDT 24 |
| Finished | Jul 27 08:40:46 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-2df5bc15-4ab0-4f35-b402-21c4540cef3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707460710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1707460710 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.819851713 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 9470354578 ps |
| CPU time | 94.94 seconds |
| Started | Jul 27 08:40:38 PM PDT 24 |
| Finished | Jul 27 08:42:13 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-23751e7a-2409-4ce0-ac6c-d1d648c27808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819851713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.819851713 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1386494398 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 5673311282 ps |
| CPU time | 101.07 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:42:28 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-34374aa0-21c4-4ef9-a7c6-d66ac545c14d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386494398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1386494398 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3849133402 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 45556857 ps |
| CPU time | 6.24 seconds |
| Started | Jul 27 08:40:37 PM PDT 24 |
| Finished | Jul 27 08:40:43 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-adcaad68-da9f-4cea-b239-5af9348326b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849133402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.3849133402 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.2898239701 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 4678247694 ps |
| CPU time | 369.91 seconds |
| Started | Jul 27 08:40:52 PM PDT 24 |
| Finished | Jul 27 08:47:02 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-4ca760a9-3974-4b01-8066-e7f6a88cb8eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898239701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2898239701 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.625352983 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 4554224768 ps |
| CPU time | 563.54 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:50:10 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-1a4e99ca-871e-4cf6-b794-45834ce9292a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625352983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_ with_rand_reset.625352983 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3687537452 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 207831188 ps |
| CPU time | 72.96 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:42:00 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-9e015558-c517-49fd-9f3e-0f6b386f6237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687537452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3687537452 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3251253855 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 563406252 ps |
| CPU time | 26.81 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:41:14 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-aa8e4059-e607-4a69-8cab-3a71e09a5fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251253855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3251253855 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.885183093 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 6090813075 ps |
| CPU time | 485.46 seconds |
| Started | Jul 27 08:29:00 PM PDT 24 |
| Finished | Jul 27 08:37:06 PM PDT 24 |
| Peak memory | 646248 kb |
| Host | smart-7b2dbcc2-8911-48f1-a4f4-fea00c073288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885183093 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.885183093 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.3081422578 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 3796448312 ps |
| CPU time | 313.69 seconds |
| Started | Jul 27 08:28:53 PM PDT 24 |
| Finished | Jul 27 08:34:07 PM PDT 24 |
| Peak memory | 598852 kb |
| Host | smart-8054fdfe-5729-4035-97b0-d3ba754b81bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081422578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3081422578 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.709224447 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 30244801092 ps |
| CPU time | 2727.02 seconds |
| Started | Jul 27 08:28:05 PM PDT 24 |
| Finished | Jul 27 09:13:32 PM PDT 24 |
| Peak memory | 592932 kb |
| Host | smart-87e1ed54-1d6b-46d2-bac1-0731a64fab80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709224447 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.709224447 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.3963793169 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4938730175 ps |
| CPU time | 299.44 seconds |
| Started | Jul 27 08:28:20 PM PDT 24 |
| Finished | Jul 27 08:33:19 PM PDT 24 |
| Peak memory | 603276 kb |
| Host | smart-9f135e7b-7043-4cc5-ad6f-9a33c1c9a467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963793169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3963793169 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1783097139 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 626712447 ps |
| CPU time | 46.31 seconds |
| Started | Jul 27 08:28:35 PM PDT 24 |
| Finished | Jul 27 08:29:22 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-774791d2-99ff-489a-8ec0-25aff0c5eb1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783097139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1783097139 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.98417280 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 68196325007 ps |
| CPU time | 1193.36 seconds |
| Started | Jul 27 08:28:37 PM PDT 24 |
| Finished | Jul 27 08:48:31 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-d73bcf69-5e01-4d4b-9688-cf87bb5a0ae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98417280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_dev ice_slow_rsp.98417280 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1151086556 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 596047577 ps |
| CPU time | 26.21 seconds |
| Started | Jul 27 08:28:39 PM PDT 24 |
| Finished | Jul 27 08:29:05 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-f028f116-00ff-43e7-8379-a6d42df43adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151086556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1151086556 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1036476183 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 415504353 ps |
| CPU time | 40.16 seconds |
| Started | Jul 27 08:28:38 PM PDT 24 |
| Finished | Jul 27 08:29:18 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-047d23e5-83ec-4eb9-bf83-76e1156c0aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036476183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1036476183 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1182163494 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 28799599 ps |
| CPU time | 6.05 seconds |
| Started | Jul 27 08:28:32 PM PDT 24 |
| Finished | Jul 27 08:28:38 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-d66f1a20-12bb-4bf1-804b-33fde3116b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182163494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1182163494 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2336518855 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 102733484000 ps |
| CPU time | 1099.31 seconds |
| Started | Jul 27 08:28:31 PM PDT 24 |
| Finished | Jul 27 08:46:51 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-6c09ab2a-0cec-41dc-9ea3-9d7db08ab318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336518855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2336518855 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.4283100288 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 51498888870 ps |
| CPU time | 911.85 seconds |
| Started | Jul 27 08:28:29 PM PDT 24 |
| Finished | Jul 27 08:43:41 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-8d9b0fad-e4b8-4116-a8cc-bda1e908840a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283100288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4283100288 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.4124823789 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 148820701 ps |
| CPU time | 19.57 seconds |
| Started | Jul 27 08:28:38 PM PDT 24 |
| Finished | Jul 27 08:28:58 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-003c99c6-f65f-4f3b-99f0-a292473132cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124823789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.4124823789 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.665807865 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1716968075 ps |
| CPU time | 52.58 seconds |
| Started | Jul 27 08:28:37 PM PDT 24 |
| Finished | Jul 27 08:29:30 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-f035f399-cfdc-493a-8d18-d63f5124dea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665807865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.665807865 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2502670006 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 223386445 ps |
| CPU time | 10.85 seconds |
| Started | Jul 27 08:28:22 PM PDT 24 |
| Finished | Jul 27 08:28:33 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-68dd3833-afae-4293-8b48-6f8d7f7723e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502670006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2502670006 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2106363561 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 5995900996 ps |
| CPU time | 60.17 seconds |
| Started | Jul 27 08:28:19 PM PDT 24 |
| Finished | Jul 27 08:29:19 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-d040edae-0c63-4659-b63f-cd31ef4029bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106363561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2106363561 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1980009105 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 5275019643 ps |
| CPU time | 92.41 seconds |
| Started | Jul 27 08:28:20 PM PDT 24 |
| Finished | Jul 27 08:29:52 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-3e6ad43c-0c93-472e-a2ed-481da810d4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980009105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1980009105 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.711766289 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 49345764 ps |
| CPU time | 7.21 seconds |
| Started | Jul 27 08:28:19 PM PDT 24 |
| Finished | Jul 27 08:28:26 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-1d1a8b0e-f41b-42a6-8aff-49f12895f06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711766289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays. 711766289 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.998508942 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 2624535744 ps |
| CPU time | 100.42 seconds |
| Started | Jul 27 08:28:53 PM PDT 24 |
| Finished | Jul 27 08:30:33 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-29c236c2-17cf-4a7f-8039-b9e52dd0202b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998508942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.998508942 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2163824442 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 5122526974 ps |
| CPU time | 189.41 seconds |
| Started | Jul 27 08:28:48 PM PDT 24 |
| Finished | Jul 27 08:31:57 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-36462760-453e-403c-a1b4-d34b9057523a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163824442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2163824442 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3661614212 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 6956797785 ps |
| CPU time | 515.1 seconds |
| Started | Jul 27 08:28:46 PM PDT 24 |
| Finished | Jul 27 08:37:22 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-bed49aaa-5588-4db7-9bfe-963f86fe699c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661614212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3661614212 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1800976184 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 105967426 ps |
| CPU time | 32.04 seconds |
| Started | Jul 27 08:28:56 PM PDT 24 |
| Finished | Jul 27 08:29:28 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-c322be2b-48f3-4282-afc3-a3378d9c1629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800976184 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1800976184 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2392441616 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 85061729 ps |
| CPU time | 6.32 seconds |
| Started | Jul 27 08:28:37 PM PDT 24 |
| Finished | Jul 27 08:28:44 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-d7e0fdbb-4ccc-4ec9-9e7d-8c6a3c8a89de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392441616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2392441616 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1493171191 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 552575550 ps |
| CPU time | 27.7 seconds |
| Started | Jul 27 08:41:01 PM PDT 24 |
| Finished | Jul 27 08:41:29 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-77ed35c7-f816-4729-8c70-ae6b433bbcad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493171191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1493171191 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1965439394 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 42554305515 ps |
| CPU time | 773.27 seconds |
| Started | Jul 27 08:40:55 PM PDT 24 |
| Finished | Jul 27 08:53:48 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-6863da1f-9336-48d3-a79f-932949c1db6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965439394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1965439394 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.4156125823 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 1017164939 ps |
| CPU time | 42.89 seconds |
| Started | Jul 27 08:40:55 PM PDT 24 |
| Finished | Jul 27 08:41:38 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ee753761-c7dc-46c8-a391-4945b0e02c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156125823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.4156125823 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.103714271 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 657466026 ps |
| CPU time | 24.69 seconds |
| Started | Jul 27 08:41:02 PM PDT 24 |
| Finished | Jul 27 08:41:27 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-318ac849-1b5d-4ff5-858d-734c33d743a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103714271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.103714271 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.479457608 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 116723789 ps |
| CPU time | 13.8 seconds |
| Started | Jul 27 08:41:01 PM PDT 24 |
| Finished | Jul 27 08:41:15 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-f315b6c6-4853-43d6-8d1c-1d00df377094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479457608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.479457608 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1797241282 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 79593568221 ps |
| CPU time | 812.32 seconds |
| Started | Jul 27 08:40:56 PM PDT 24 |
| Finished | Jul 27 08:54:29 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-de0a2cd3-e09a-49a7-9395-df0e45743382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797241282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1797241282 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1976005063 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 35389815488 ps |
| CPU time | 605.48 seconds |
| Started | Jul 27 08:40:57 PM PDT 24 |
| Finished | Jul 27 08:51:02 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-8f9f4287-9396-4575-93c4-d7aa3a34f4c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976005063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1976005063 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3224891522 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 253056072 ps |
| CPU time | 23.76 seconds |
| Started | Jul 27 08:40:54 PM PDT 24 |
| Finished | Jul 27 08:41:18 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-72618850-c1f4-42fd-9b85-4c0b0007dfb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224891522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3224891522 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.4166790313 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 330992681 ps |
| CPU time | 26.62 seconds |
| Started | Jul 27 08:41:01 PM PDT 24 |
| Finished | Jul 27 08:41:28 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-08e4ee79-37ba-446b-9891-96c71dc7ff9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166790313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.4166790313 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.1740785719 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 44438216 ps |
| CPU time | 6.77 seconds |
| Started | Jul 27 08:40:51 PM PDT 24 |
| Finished | Jul 27 08:40:58 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-fbf56a84-4ec9-4997-bbbf-b9764079e624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740785719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.1740785719 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2517348520 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 7370713924 ps |
| CPU time | 81.2 seconds |
| Started | Jul 27 08:40:47 PM PDT 24 |
| Finished | Jul 27 08:42:08 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-2d205a7f-35a8-4738-82d2-07aeef84fbcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517348520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2517348520 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2644666617 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 5354375548 ps |
| CPU time | 101.88 seconds |
| Started | Jul 27 08:40:55 PM PDT 24 |
| Finished | Jul 27 08:42:37 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-65f7f580-2115-4758-948c-400c37472537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644666617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2644666617 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2736320395 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 46070677 ps |
| CPU time | 6.72 seconds |
| Started | Jul 27 08:40:49 PM PDT 24 |
| Finished | Jul 27 08:40:56 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-cee5e34f-3150-4fd2-b342-bc5cfee55822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736320395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.2736320395 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3426488999 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3640012837 ps |
| CPU time | 163.15 seconds |
| Started | Jul 27 08:40:57 PM PDT 24 |
| Finished | Jul 27 08:43:41 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-f3fb3a6c-ca15-4805-8054-e585e5e78273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426488999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3426488999 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2296849044 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 3117370779 ps |
| CPU time | 143.86 seconds |
| Started | Jul 27 08:41:01 PM PDT 24 |
| Finished | Jul 27 08:43:25 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-a72dabad-01b4-4cc5-8d48-798df4d9d44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296849044 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2296849044 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1131127454 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 347064044 ps |
| CPU time | 255.3 seconds |
| Started | Jul 27 08:40:57 PM PDT 24 |
| Finished | Jul 27 08:45:13 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-9015d8f6-691a-4d28-9694-14b5e7d848f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131127454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1131127454 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.753679980 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 430349738 ps |
| CPU time | 199.48 seconds |
| Started | Jul 27 08:40:56 PM PDT 24 |
| Finished | Jul 27 08:44:16 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-312e34d9-b1cf-4869-899d-4a674143d838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753679980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.753679980 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2159338837 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 308418359 ps |
| CPU time | 17.69 seconds |
| Started | Jul 27 08:40:55 PM PDT 24 |
| Finished | Jul 27 08:41:13 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-507e9140-515b-4b89-8820-114032afe397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159338837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2159338837 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.4213052493 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 2764155645 ps |
| CPU time | 130.88 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 08:43:16 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-16ad1875-a0f0-47d5-a4a8-0997ca4049ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213052493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .4213052493 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2792504980 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 95388931006 ps |
| CPU time | 1632.15 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 09:08:17 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-7c79e2a5-d438-4434-ad55-dfd5346800db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792504980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.2792504980 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3183742614 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 81149784 ps |
| CPU time | 12.6 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 08:41:18 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-58902b2f-0e28-4af0-b990-2b3c149b1f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183742614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3183742614 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.3480306374 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 1561807771 ps |
| CPU time | 55.65 seconds |
| Started | Jul 27 08:41:04 PM PDT 24 |
| Finished | Jul 27 08:42:00 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-604359c1-ce55-4127-a137-d8c1bc997037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480306374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.3480306374 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3498702385 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 695694658 ps |
| CPU time | 27.36 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 08:41:33 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ed2eee22-692d-4014-892f-f5bbf8e928fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498702385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3498702385 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2268013828 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 21491903561 ps |
| CPU time | 221.36 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 08:44:47 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-af97caef-047c-4504-beee-0e112107a2bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268013828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2268013828 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2293073893 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 58496732201 ps |
| CPU time | 1029.86 seconds |
| Started | Jul 27 08:41:07 PM PDT 24 |
| Finished | Jul 27 08:58:17 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-ab643335-a73e-445e-99f1-0a2661229227 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293073893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2293073893 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1410938687 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 438794065 ps |
| CPU time | 42.41 seconds |
| Started | Jul 27 08:41:04 PM PDT 24 |
| Finished | Jul 27 08:41:47 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-209204d3-a04c-481c-9eb4-103cfda18739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410938687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1410938687 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.3370776335 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 2408394776 ps |
| CPU time | 80.24 seconds |
| Started | Jul 27 08:41:01 PM PDT 24 |
| Finished | Jul 27 08:42:22 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-c97a16cb-6a17-441a-83be-a408d80117f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370776335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3370776335 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.2790297301 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 226598613 ps |
| CPU time | 10.85 seconds |
| Started | Jul 27 08:40:54 PM PDT 24 |
| Finished | Jul 27 08:41:05 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-dfbf9504-6cc8-4f28-a60d-09bbf8c2c11e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790297301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2790297301 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1472945951 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 7262297046 ps |
| CPU time | 81.24 seconds |
| Started | Jul 27 08:41:03 PM PDT 24 |
| Finished | Jul 27 08:42:25 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-4fb9b931-72f8-4f32-963e-45b248c495fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472945951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1472945951 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.66579843 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 4307498688 ps |
| CPU time | 78.96 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 08:42:25 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-591273b1-f3be-4861-9ee6-6ca957683baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66579843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.66579843 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3642940581 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 58647760 ps |
| CPU time | 6.88 seconds |
| Started | Jul 27 08:41:01 PM PDT 24 |
| Finished | Jul 27 08:41:08 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-233df186-1cec-4af4-b8c6-8a99a04b65b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642940581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.3642940581 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.2113822449 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 7763636657 ps |
| CPU time | 276.54 seconds |
| Started | Jul 27 08:41:14 PM PDT 24 |
| Finished | Jul 27 08:45:50 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a4a2ccdd-dd75-4764-802a-39857c43459b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113822449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2113822449 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.242191088 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 8947046206 ps |
| CPU time | 327.28 seconds |
| Started | Jul 27 08:41:16 PM PDT 24 |
| Finished | Jul 27 08:46:44 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-4870027b-2318-40b6-bea7-858ca0425e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242191088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.242191088 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1510226176 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 376506822 ps |
| CPU time | 145.62 seconds |
| Started | Jul 27 08:41:13 PM PDT 24 |
| Finished | Jul 27 08:43:39 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-328782f1-b339-474f-91bb-1d1dc6b17124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510226176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1510226176 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2996976192 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 181636996 ps |
| CPU time | 27.09 seconds |
| Started | Jul 27 08:41:11 PM PDT 24 |
| Finished | Jul 27 08:41:38 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-502b28b0-d26e-494d-b0a9-de25338a9adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996976192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.2996976192 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.220145571 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 817847369 ps |
| CPU time | 39.79 seconds |
| Started | Jul 27 08:41:05 PM PDT 24 |
| Finished | Jul 27 08:41:45 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-86d87409-da0d-4463-9d23-0c4b0bcf16d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220145571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.220145571 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.210540474 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 112546281 ps |
| CPU time | 11.65 seconds |
| Started | Jul 27 08:41:15 PM PDT 24 |
| Finished | Jul 27 08:41:26 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-bffedb5d-4d14-4e14-a3a0-55afd5e61181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210540474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 210540474 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.749230963 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 95934959936 ps |
| CPU time | 1767.84 seconds |
| Started | Jul 27 08:41:22 PM PDT 24 |
| Finished | Jul 27 09:10:50 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-93fe75a2-5729-4b28-bb92-f3235f162f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749230963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d evice_slow_rsp.749230963 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.4058280276 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 1228731514 ps |
| CPU time | 47.24 seconds |
| Started | Jul 27 08:41:22 PM PDT 24 |
| Finished | Jul 27 08:42:09 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-fe0e589f-9c9c-4a7d-9891-3f64e09de2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058280276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.4058280276 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.161003821 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 2234397651 ps |
| CPU time | 76 seconds |
| Started | Jul 27 08:41:14 PM PDT 24 |
| Finished | Jul 27 08:42:31 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-935bcf7b-d38c-4ea6-8408-18184b5ee0dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161003821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.161003821 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1398176818 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 507350191 ps |
| CPU time | 54.47 seconds |
| Started | Jul 27 08:41:12 PM PDT 24 |
| Finished | Jul 27 08:42:07 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-ad1d2b4d-207c-410a-99d3-192ba00d5f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398176818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1398176818 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2937939173 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 99283728085 ps |
| CPU time | 1090.27 seconds |
| Started | Jul 27 08:41:10 PM PDT 24 |
| Finished | Jul 27 08:59:21 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-499b3364-ab59-4380-b9ab-12c3319452da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937939173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2937939173 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1689900963 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 63046929992 ps |
| CPU time | 1085.92 seconds |
| Started | Jul 27 08:41:14 PM PDT 24 |
| Finished | Jul 27 08:59:20 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-e6888255-c0f5-408f-bb70-924b7de03afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689900963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1689900963 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.78954676 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 38654563 ps |
| CPU time | 6.14 seconds |
| Started | Jul 27 08:41:13 PM PDT 24 |
| Finished | Jul 27 08:41:19 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-3b582416-6dd2-403d-90b3-a3eb0e5f9fe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78954676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delay s.78954676 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2419341393 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 509592492 ps |
| CPU time | 39.44 seconds |
| Started | Jul 27 08:41:20 PM PDT 24 |
| Finished | Jul 27 08:42:00 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-7841e3d3-6063-4557-8f21-a30bb3a52ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419341393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2419341393 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3480787934 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 226219105 ps |
| CPU time | 9.75 seconds |
| Started | Jul 27 08:41:22 PM PDT 24 |
| Finished | Jul 27 08:41:32 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-91b0554e-e80b-4918-bdcf-4f8c7d869fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480787934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3480787934 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1888286040 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 9719364072 ps |
| CPU time | 100.61 seconds |
| Started | Jul 27 08:41:15 PM PDT 24 |
| Finished | Jul 27 08:42:56 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-4a69b6b9-baf2-4ab4-ac9b-aa29d9707e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888286040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1888286040 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3768275510 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 5713891712 ps |
| CPU time | 97.3 seconds |
| Started | Jul 27 08:41:21 PM PDT 24 |
| Finished | Jul 27 08:42:59 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-b2c90874-5b86-45fe-bc35-f1c065586cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768275510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3768275510 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3576579345 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 44495561 ps |
| CPU time | 7 seconds |
| Started | Jul 27 08:41:10 PM PDT 24 |
| Finished | Jul 27 08:41:17 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-812ae2a6-2bcc-4023-9ea5-c787cb08cb9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576579345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3576579345 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2242426237 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 18077697462 ps |
| CPU time | 825.51 seconds |
| Started | Jul 27 08:41:23 PM PDT 24 |
| Finished | Jul 27 08:55:09 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-28f46bfb-1f90-431d-8b07-1b9d68bf9e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242426237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2242426237 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.237844605 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 685726728 ps |
| CPU time | 48.76 seconds |
| Started | Jul 27 08:41:19 PM PDT 24 |
| Finished | Jul 27 08:42:08 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-0e3ba997-1066-41fb-986e-9f247e05cb10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237844605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.237844605 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.210832521 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 6400725765 ps |
| CPU time | 467.39 seconds |
| Started | Jul 27 08:41:21 PM PDT 24 |
| Finished | Jul 27 08:49:09 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-41488a88-69ff-44cb-8f6a-8e435ae69815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210832521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.210832521 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1112699145 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 4161585348 ps |
| CPU time | 389.36 seconds |
| Started | Jul 27 08:41:19 PM PDT 24 |
| Finished | Jul 27 08:47:49 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-3b70965c-2d49-4748-8a52-678cb9527983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112699145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1112699145 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.3673206619 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 261128906 ps |
| CPU time | 14.92 seconds |
| Started | Jul 27 08:41:23 PM PDT 24 |
| Finished | Jul 27 08:41:38 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-2542ce5c-cca9-465f-a110-a8c778faed1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673206619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.3673206619 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1501844868 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 1264956148 ps |
| CPU time | 63.96 seconds |
| Started | Jul 27 08:41:20 PM PDT 24 |
| Finished | Jul 27 08:42:24 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-773b992d-a596-4996-b725-99411fd3bc68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501844868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .1501844868 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1820921556 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 21631125773 ps |
| CPU time | 378.62 seconds |
| Started | Jul 27 08:41:28 PM PDT 24 |
| Finished | Jul 27 08:47:46 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-bb710c45-4650-4f70-8bca-59726bab6342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820921556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1820921556 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3811620460 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 200341018 ps |
| CPU time | 26.16 seconds |
| Started | Jul 27 08:41:26 PM PDT 24 |
| Finished | Jul 27 08:41:52 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-038c8e7a-5911-4fe3-840a-439eb1570843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811620460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3811620460 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.1614250553 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 1094858704 ps |
| CPU time | 42.98 seconds |
| Started | Jul 27 08:41:28 PM PDT 24 |
| Finished | Jul 27 08:42:12 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-0531d089-1421-4b4c-9d7b-a1feb789dd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614250553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.1614250553 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.39362214 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 345445655 ps |
| CPU time | 14.54 seconds |
| Started | Jul 27 08:41:19 PM PDT 24 |
| Finished | Jul 27 08:41:34 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-56a22ea3-a7fd-41a8-ac74-2aa02226bced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39362214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.39362214 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.1268245822 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 58888489649 ps |
| CPU time | 623.59 seconds |
| Started | Jul 27 08:41:20 PM PDT 24 |
| Finished | Jul 27 08:51:44 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-7f3412c9-84ab-426d-b899-a97f57c3965d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268245822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1268245822 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1373981711 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 42985343295 ps |
| CPU time | 722.17 seconds |
| Started | Jul 27 08:41:25 PM PDT 24 |
| Finished | Jul 27 08:53:28 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-3e8914c7-f582-4694-967a-4844b05cdd5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373981711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1373981711 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.4201439704 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 382765903 ps |
| CPU time | 39.98 seconds |
| Started | Jul 27 08:41:21 PM PDT 24 |
| Finished | Jul 27 08:42:01 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-db45ccbc-617f-449b-a1b8-20a192ba1b9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201439704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.4201439704 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.386970797 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 92007260 ps |
| CPU time | 9.81 seconds |
| Started | Jul 27 08:41:27 PM PDT 24 |
| Finished | Jul 27 08:41:37 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-530008ee-246e-4761-a2b9-035134ea91ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386970797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.386970797 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.3942047255 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 164213803 ps |
| CPU time | 8.68 seconds |
| Started | Jul 27 08:41:25 PM PDT 24 |
| Finished | Jul 27 08:41:34 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-27beac49-e316-4242-9639-4f1c604ebeaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942047255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.3942047255 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3598675217 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 8670348708 ps |
| CPU time | 93.04 seconds |
| Started | Jul 27 08:41:22 PM PDT 24 |
| Finished | Jul 27 08:42:55 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-027f2a3d-6451-4061-a5ef-d3e234670bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598675217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3598675217 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.3025832308 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 5797521330 ps |
| CPU time | 101.72 seconds |
| Started | Jul 27 08:41:21 PM PDT 24 |
| Finished | Jul 27 08:43:03 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-7aa53ccf-f813-4b64-b196-26d90851fbef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025832308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.3025832308 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.801983843 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 43182215 ps |
| CPU time | 6.33 seconds |
| Started | Jul 27 08:41:21 PM PDT 24 |
| Finished | Jul 27 08:41:28 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-7a4fe6c1-f502-4589-904f-0329841cce00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801983843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .801983843 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2169621644 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 10295723969 ps |
| CPU time | 427.86 seconds |
| Started | Jul 27 08:41:26 PM PDT 24 |
| Finished | Jul 27 08:48:34 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-ebde6994-a8d4-44c1-8263-f86865fa0d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169621644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2169621644 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.4283032395 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 7732378419 ps |
| CPU time | 292.3 seconds |
| Started | Jul 27 08:41:29 PM PDT 24 |
| Finished | Jul 27 08:46:21 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-57d0fe0e-7870-48b7-9a88-84493abf8f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283032395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.4283032395 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2714598867 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 518600855 ps |
| CPU time | 166.41 seconds |
| Started | Jul 27 08:41:26 PM PDT 24 |
| Finished | Jul 27 08:44:13 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-e6bb5c7d-83c7-4600-9bf0-cad0f922fdc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714598867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.2714598867 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1600749509 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 8444528344 ps |
| CPU time | 523.73 seconds |
| Started | Jul 27 08:41:31 PM PDT 24 |
| Finished | Jul 27 08:50:14 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-8efb6e53-3f88-44ad-8968-49533e3ddf6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600749509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.1600749509 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2966945903 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 203167666 ps |
| CPU time | 23 seconds |
| Started | Jul 27 08:41:25 PM PDT 24 |
| Finished | Jul 27 08:41:49 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-548b29af-72bf-4669-965b-086489eadb52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966945903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2966945903 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1641626982 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 1167074644 ps |
| CPU time | 97.14 seconds |
| Started | Jul 27 08:41:39 PM PDT 24 |
| Finished | Jul 27 08:43:17 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-66d26a84-aa49-48b2-95b7-0900121b0efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641626982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .1641626982 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.946678306 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 68368278042 ps |
| CPU time | 1170.68 seconds |
| Started | Jul 27 08:41:38 PM PDT 24 |
| Finished | Jul 27 09:01:08 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-01d5dc6a-b653-40d3-9065-1c561c206b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946678306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_d evice_slow_rsp.946678306 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3713571999 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 289169471 ps |
| CPU time | 36.24 seconds |
| Started | Jul 27 08:41:35 PM PDT 24 |
| Finished | Jul 27 08:42:12 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-b34d8d2e-7251-4ca3-93ba-c0ec8ca34d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713571999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.3713571999 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.722435567 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 780359021 ps |
| CPU time | 29.68 seconds |
| Started | Jul 27 08:41:40 PM PDT 24 |
| Finished | Jul 27 08:42:09 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-a3e1c199-3897-4816-a65a-611a78fdabb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722435567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.722435567 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.2523569132 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 566611300 ps |
| CPU time | 23.42 seconds |
| Started | Jul 27 08:41:31 PM PDT 24 |
| Finished | Jul 27 08:41:54 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-b5ac985f-94c4-4bd7-ba3f-d1b3d3e6e14a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523569132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2523569132 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2398951301 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 100616973237 ps |
| CPU time | 1101.47 seconds |
| Started | Jul 27 08:41:40 PM PDT 24 |
| Finished | Jul 27 09:00:02 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-b133af0c-57b0-4fc2-abd0-2896aa1c4ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398951301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2398951301 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2848500722 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 32070696369 ps |
| CPU time | 583.29 seconds |
| Started | Jul 27 08:41:40 PM PDT 24 |
| Finished | Jul 27 08:51:24 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-c5868feb-0bb5-4c22-b7c4-b8f3e55ae9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848500722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2848500722 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.1260534151 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 608454076 ps |
| CPU time | 58.29 seconds |
| Started | Jul 27 08:41:28 PM PDT 24 |
| Finished | Jul 27 08:42:27 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-fe94d836-8931-440a-ae13-704ce50fa6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260534151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.1260534151 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.3301511048 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 1339138331 ps |
| CPU time | 44.16 seconds |
| Started | Jul 27 08:41:37 PM PDT 24 |
| Finished | Jul 27 08:42:21 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-e35fd666-c892-431c-be78-e733bf1b9197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301511048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3301511048 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.13693435 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 203253722 ps |
| CPU time | 8.54 seconds |
| Started | Jul 27 08:41:26 PM PDT 24 |
| Finished | Jul 27 08:41:35 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-af4069f4-c623-4860-9c05-4eb38d7fe478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13693435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.13693435 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.770154914 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 8112074299 ps |
| CPU time | 89.43 seconds |
| Started | Jul 27 08:41:26 PM PDT 24 |
| Finished | Jul 27 08:42:56 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-56574219-4f88-40a9-a2b0-020fed019c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770154914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.770154914 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3249960700 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 4997064677 ps |
| CPU time | 90.79 seconds |
| Started | Jul 27 08:41:28 PM PDT 24 |
| Finished | Jul 27 08:42:59 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-a5b6d848-3473-4b97-b00c-cf20b2eb8bdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249960700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.3249960700 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.562360121 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 34455340 ps |
| CPU time | 5.96 seconds |
| Started | Jul 27 08:41:29 PM PDT 24 |
| Finished | Jul 27 08:41:35 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-3341b156-0212-4e1f-9ada-4465d4ca2d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562360121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays .562360121 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3347714007 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 1610190636 ps |
| CPU time | 139.12 seconds |
| Started | Jul 27 08:41:35 PM PDT 24 |
| Finished | Jul 27 08:43:55 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-20c11f9b-8240-473e-b4ef-1cc941117bfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347714007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3347714007 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3507805178 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 6152228 ps |
| CPU time | 3.9 seconds |
| Started | Jul 27 08:41:40 PM PDT 24 |
| Finished | Jul 27 08:41:44 PM PDT 24 |
| Peak memory | 565412 kb |
| Host | smart-d274ed17-b19b-4081-ac03-920a397a13b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507805178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3507805178 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.122827886 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 490377656 ps |
| CPU time | 253.6 seconds |
| Started | Jul 27 08:41:40 PM PDT 24 |
| Finished | Jul 27 08:45:53 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-1a84d8b2-c586-4723-bfc4-c2657310a0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122827886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.122827886 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3361494031 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 6102563134 ps |
| CPU time | 404.33 seconds |
| Started | Jul 27 08:41:50 PM PDT 24 |
| Finished | Jul 27 08:48:34 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-38ebdaa4-cd01-4670-aac9-0bedf5af5ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361494031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3361494031 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.495137033 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 632169196 ps |
| CPU time | 30.45 seconds |
| Started | Jul 27 08:41:39 PM PDT 24 |
| Finished | Jul 27 08:42:10 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-6002ec27-5d7e-4600-8975-ecd7ea51e47e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495137033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.495137033 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.135466496 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 506918544 ps |
| CPU time | 50.9 seconds |
| Started | Jul 27 08:41:49 PM PDT 24 |
| Finished | Jul 27 08:42:40 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-823a2513-f4b9-4305-b3c8-918bfb0a9891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135466496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device. 135466496 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3915258049 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 49667562776 ps |
| CPU time | 880.82 seconds |
| Started | Jul 27 08:41:49 PM PDT 24 |
| Finished | Jul 27 08:56:30 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ea1e553a-d9bc-4442-b7fd-88345a9f9ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915258049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3915258049 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.638766280 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 35917128 ps |
| CPU time | 7.46 seconds |
| Started | Jul 27 08:42:01 PM PDT 24 |
| Finished | Jul 27 08:42:08 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-6c6997a6-9eba-4ab4-abad-1679f247883e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638766280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .638766280 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.357209415 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 518515438 ps |
| CPU time | 21.89 seconds |
| Started | Jul 27 08:41:47 PM PDT 24 |
| Finished | Jul 27 08:42:09 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-099635b4-e99f-480c-96ff-b5a42e1d89ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357209415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.357209415 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1782716486 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 247549758 ps |
| CPU time | 23 seconds |
| Started | Jul 27 08:41:48 PM PDT 24 |
| Finished | Jul 27 08:42:11 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-916c3014-4999-41f9-a4ec-732e1c962d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782716486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1782716486 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.1578283250 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 64132200416 ps |
| CPU time | 699.48 seconds |
| Started | Jul 27 08:41:50 PM PDT 24 |
| Finished | Jul 27 08:53:29 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-deeb63b0-fcd3-4d2d-af4e-183c227b06ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578283250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.1578283250 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.4102932266 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 24690981282 ps |
| CPU time | 404.58 seconds |
| Started | Jul 27 08:41:47 PM PDT 24 |
| Finished | Jul 27 08:48:32 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-d55cee94-879a-4719-a9d4-f069f0a7cf21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102932266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.4102932266 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1548379163 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 524677865 ps |
| CPU time | 40.02 seconds |
| Started | Jul 27 08:41:47 PM PDT 24 |
| Finished | Jul 27 08:42:28 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-fa585036-ecf9-4567-b097-48dcaaab3cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548379163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1548379163 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3090062543 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 372316706 ps |
| CPU time | 27.67 seconds |
| Started | Jul 27 08:41:52 PM PDT 24 |
| Finished | Jul 27 08:42:19 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-0ce7e648-aa40-40d4-953e-ca37de984627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090062543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3090062543 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1513852551 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 47867204 ps |
| CPU time | 6.79 seconds |
| Started | Jul 27 08:41:49 PM PDT 24 |
| Finished | Jul 27 08:41:55 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-5a5759af-06c3-4795-91c6-a55bf99d4bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513852551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1513852551 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3833187473 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 7178497385 ps |
| CPU time | 78.66 seconds |
| Started | Jul 27 08:41:49 PM PDT 24 |
| Finished | Jul 27 08:43:07 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-8b398749-2bab-424f-b5ac-c991f3c868ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833187473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3833187473 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3665161058 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 4331994481 ps |
| CPU time | 74.38 seconds |
| Started | Jul 27 08:41:48 PM PDT 24 |
| Finished | Jul 27 08:43:02 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-83585941-e84d-4b88-bcc9-4fe3873ab7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665161058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.3665161058 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1697714446 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 58893529 ps |
| CPU time | 7.36 seconds |
| Started | Jul 27 08:41:49 PM PDT 24 |
| Finished | Jul 27 08:41:56 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-547adcff-836e-4b64-b6a3-925f725b41b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697714446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.1697714446 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3940815004 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 2700563763 ps |
| CPU time | 244 seconds |
| Started | Jul 27 08:42:05 PM PDT 24 |
| Finished | Jul 27 08:46:09 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-92335dff-4c4e-4fd1-85b6-44236ddd1ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940815004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3940815004 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1268519383 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 2567172687 ps |
| CPU time | 89.12 seconds |
| Started | Jul 27 08:41:57 PM PDT 24 |
| Finished | Jul 27 08:43:26 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-4f36c53d-f8f5-4405-9cfb-cfef650d1ce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268519383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1268519383 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2428207076 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 3443557111 ps |
| CPU time | 339.73 seconds |
| Started | Jul 27 08:42:03 PM PDT 24 |
| Finished | Jul 27 08:47:43 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-4f3793b2-48d2-41ca-a199-c18d24a00e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428207076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2428207076 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2507260258 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 4818154852 ps |
| CPU time | 360.3 seconds |
| Started | Jul 27 08:41:59 PM PDT 24 |
| Finished | Jul 27 08:48:00 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-cfca6b4f-e689-4723-bf95-f062cfceae98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507260258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2507260258 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.853427346 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 523677783 ps |
| CPU time | 26.23 seconds |
| Started | Jul 27 08:41:49 PM PDT 24 |
| Finished | Jul 27 08:42:15 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-f0497ad4-9e1e-4b22-a55d-1b9f520e9b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853427346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.853427346 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2744223479 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 580679019 ps |
| CPU time | 52.4 seconds |
| Started | Jul 27 08:41:58 PM PDT 24 |
| Finished | Jul 27 08:42:50 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-7b2fc9bf-517e-458b-af02-5acc20559af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744223479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2744223479 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2888755854 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 69129817443 ps |
| CPU time | 1194.2 seconds |
| Started | Jul 27 08:42:02 PM PDT 24 |
| Finished | Jul 27 09:01:56 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-4b2a0565-1b01-418d-932a-389512c24b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888755854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2888755854 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2143759127 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 588307797 ps |
| CPU time | 24.44 seconds |
| Started | Jul 27 08:41:56 PM PDT 24 |
| Finished | Jul 27 08:42:21 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-16906a49-15a7-40bd-9dbb-7db81fc46762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143759127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.2143759127 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3947770406 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 283719542 ps |
| CPU time | 13.27 seconds |
| Started | Jul 27 08:42:01 PM PDT 24 |
| Finished | Jul 27 08:42:14 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-92489484-a9bd-43f7-b14f-a4295ddd294e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947770406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3947770406 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.56469626 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 231757394 ps |
| CPU time | 26.65 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 08:42:33 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-003b77ee-bba0-4397-98b2-2241097a3b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56469626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.56469626 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1122210824 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 85588776420 ps |
| CPU time | 931.7 seconds |
| Started | Jul 27 08:42:05 PM PDT 24 |
| Finished | Jul 27 08:57:37 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-e9cd427b-d269-453f-8223-f0876a255d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122210824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1122210824 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.3310198975 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 24020562279 ps |
| CPU time | 415.94 seconds |
| Started | Jul 27 08:42:00 PM PDT 24 |
| Finished | Jul 27 08:48:56 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-99cc52a3-2619-4ffe-9de4-62403b88c94a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310198975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.3310198975 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3241814348 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 638877825 ps |
| CPU time | 58.8 seconds |
| Started | Jul 27 08:41:59 PM PDT 24 |
| Finished | Jul 27 08:42:58 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-e7f7a90b-7e18-46b7-b563-83f19efe8774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241814348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3241814348 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.819647074 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 448840163 ps |
| CPU time | 34.5 seconds |
| Started | Jul 27 08:42:02 PM PDT 24 |
| Finished | Jul 27 08:42:36 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-8802b60e-de1d-46f4-99da-8b090a50f4d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819647074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.819647074 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.756459704 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 209137886 ps |
| CPU time | 10.47 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 08:42:17 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f04320e5-dd9c-491c-8049-7862231793fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756459704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.756459704 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2750971911 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 9117724413 ps |
| CPU time | 108.35 seconds |
| Started | Jul 27 08:41:57 PM PDT 24 |
| Finished | Jul 27 08:43:46 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-58f39b77-70a3-4d98-8fc8-0d5b1f1c4635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750971911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2750971911 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3975623631 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 6071458534 ps |
| CPU time | 106.65 seconds |
| Started | Jul 27 08:41:56 PM PDT 24 |
| Finished | Jul 27 08:43:43 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-bc0e6e95-94cb-4e1e-8bff-4194b89273e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975623631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.3975623631 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2153412913 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 41007220 ps |
| CPU time | 6.67 seconds |
| Started | Jul 27 08:42:00 PM PDT 24 |
| Finished | Jul 27 08:42:07 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-92e20019-9f51-451c-a22e-56cb19ec9583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153412913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.2153412913 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3191234280 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 3719573919 ps |
| CPU time | 156.62 seconds |
| Started | Jul 27 08:42:00 PM PDT 24 |
| Finished | Jul 27 08:44:37 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-a7d45154-95c6-4108-893c-8664ada5cd67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191234280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3191234280 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.894293243 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 5712966619 ps |
| CPU time | 225.99 seconds |
| Started | Jul 27 08:41:56 PM PDT 24 |
| Finished | Jul 27 08:45:42 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-d6826eef-754a-49da-8089-8318a6048907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894293243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.894293243 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.170009219 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 400691038 ps |
| CPU time | 115.17 seconds |
| Started | Jul 27 08:41:58 PM PDT 24 |
| Finished | Jul 27 08:43:54 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-4a5203db-0a4c-4091-86bb-19c481055809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170009219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_ with_rand_reset.170009219 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.699827427 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 436681744 ps |
| CPU time | 90.69 seconds |
| Started | Jul 27 08:41:56 PM PDT 24 |
| Finished | Jul 27 08:43:27 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-c54422fe-7d0f-4c68-941d-ce70df27a859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699827427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.699827427 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1863527181 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 305769203 ps |
| CPU time | 40.8 seconds |
| Started | Jul 27 08:42:02 PM PDT 24 |
| Finished | Jul 27 08:42:43 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-02cf3292-a916-4c8a-8a5a-db2cad936115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863527181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1863527181 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1156300392 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 918859465 ps |
| CPU time | 86.41 seconds |
| Started | Jul 27 08:42:05 PM PDT 24 |
| Finished | Jul 27 08:43:32 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-62fa7c7b-fb7b-419b-ae32-f957b6933272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156300392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .1156300392 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.3576901434 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 108723335469 ps |
| CPU time | 1809.4 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 09:12:16 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7bec6a47-372a-4ae3-862f-1eb5c938c037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576901434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.3576901434 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3211992026 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 21038326 ps |
| CPU time | 5.38 seconds |
| Started | Jul 27 08:42:07 PM PDT 24 |
| Finished | Jul 27 08:42:12 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-b99dda50-6cb3-4ffb-8519-d7770dd3d8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211992026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.3211992026 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.3433241164 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 1033136756 ps |
| CPU time | 34.82 seconds |
| Started | Jul 27 08:42:08 PM PDT 24 |
| Finished | Jul 27 08:42:42 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-0d64ab0b-6828-4b17-b18b-8f57b1b752f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433241164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.3433241164 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1705659870 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 114169104 ps |
| CPU time | 7.77 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 08:42:14 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-5239e348-535d-4cd2-9cf5-8295731debbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705659870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1705659870 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1213770197 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 38778735374 ps |
| CPU time | 399.13 seconds |
| Started | Jul 27 08:42:08 PM PDT 24 |
| Finished | Jul 27 08:48:47 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-e3d041ad-2f0e-463d-a1bd-c2beed014313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213770197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1213770197 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.346922592 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 29947903673 ps |
| CPU time | 555.26 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 08:51:22 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-faa8abab-8e0a-4b38-ae71-8ae377632fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346922592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.346922592 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3872118400 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 89652561 ps |
| CPU time | 11.52 seconds |
| Started | Jul 27 08:42:07 PM PDT 24 |
| Finished | Jul 27 08:42:19 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-d623b84f-a161-4f81-ad91-4e2ce7a6ce63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872118400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3872118400 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.3369773091 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 2567126750 ps |
| CPU time | 81.81 seconds |
| Started | Jul 27 08:42:11 PM PDT 24 |
| Finished | Jul 27 08:43:33 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-931305d6-8bed-4f5e-9883-2c5cff37a781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369773091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3369773091 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.4217930796 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 210833017 ps |
| CPU time | 8.95 seconds |
| Started | Jul 27 08:42:03 PM PDT 24 |
| Finished | Jul 27 08:42:12 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-b210bb1d-4ccb-4f71-92d1-c2581a610185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217930796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.4217930796 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.2812732226 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 8318717913 ps |
| CPU time | 88.75 seconds |
| Started | Jul 27 08:42:07 PM PDT 24 |
| Finished | Jul 27 08:43:36 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-ebd07bd0-a51f-42fc-9ebb-dc26f6ece5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812732226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.2812732226 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2021071440 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 6113615562 ps |
| CPU time | 103.79 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 08:43:49 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-90b1aab8-4273-4c9c-98ec-b0a82e31ae11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021071440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2021071440 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.4124742026 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 45596491 ps |
| CPU time | 6.35 seconds |
| Started | Jul 27 08:42:08 PM PDT 24 |
| Finished | Jul 27 08:42:15 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-0f443ff5-61ed-48d0-8b1a-9cdeb37910c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124742026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.4124742026 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.239003419 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 11253870064 ps |
| CPU time | 430.98 seconds |
| Started | Jul 27 08:42:06 PM PDT 24 |
| Finished | Jul 27 08:49:18 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-3f44feb7-8422-4608-8fc1-82c9de2eb6bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239003419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.239003419 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.3626004704 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 22131252453 ps |
| CPU time | 797.69 seconds |
| Started | Jul 27 08:42:17 PM PDT 24 |
| Finished | Jul 27 08:55:35 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-279c49d6-69e9-4abc-9a47-9eab4744ece3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626004704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.3626004704 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2763167802 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 9119339739 ps |
| CPU time | 553.69 seconds |
| Started | Jul 27 08:42:10 PM PDT 24 |
| Finished | Jul 27 08:51:24 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-92b0be9a-1973-4bce-a9d9-889c1fd4c67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763167802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.2763167802 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3084387574 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 200648891 ps |
| CPU time | 27.08 seconds |
| Started | Jul 27 08:42:10 PM PDT 24 |
| Finished | Jul 27 08:42:37 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f12a47ac-1056-4040-a75c-cce1fb53040a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084387574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3084387574 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3063900505 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 119425284 ps |
| CPU time | 10.62 seconds |
| Started | Jul 27 08:42:14 PM PDT 24 |
| Finished | Jul 27 08:42:25 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-0b069579-93ab-4cb6-ac2c-fbad6833595b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063900505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3063900505 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.4073222556 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 82744035624 ps |
| CPU time | 1438.84 seconds |
| Started | Jul 27 08:42:17 PM PDT 24 |
| Finished | Jul 27 09:06:16 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-da6062e8-9884-41a2-88ad-403556fd77d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073222556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.4073222556 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.340739181 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 102331460 ps |
| CPU time | 14.42 seconds |
| Started | Jul 27 08:42:21 PM PDT 24 |
| Finished | Jul 27 08:42:35 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-2256002a-d64e-4e22-bdb4-5da480a79f2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340739181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr .340739181 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.630768741 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 1783411462 ps |
| CPU time | 61.35 seconds |
| Started | Jul 27 08:42:26 PM PDT 24 |
| Finished | Jul 27 08:43:27 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-2003a6b6-182d-44d0-a546-836ced70af6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630768741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.630768741 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1173322438 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2026954025 ps |
| CPU time | 84.99 seconds |
| Started | Jul 27 08:42:14 PM PDT 24 |
| Finished | Jul 27 08:43:39 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-299e75ed-af9f-4ce9-bbfc-eb09f45c9e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173322438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1173322438 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2039249829 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 82535361351 ps |
| CPU time | 869.02 seconds |
| Started | Jul 27 08:42:15 PM PDT 24 |
| Finished | Jul 27 08:56:44 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-fc8e10b5-c30d-4a87-a0b7-4dd8c7d65e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039249829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2039249829 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1358890283 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 70644470056 ps |
| CPU time | 1211.99 seconds |
| Started | Jul 27 08:42:13 PM PDT 24 |
| Finished | Jul 27 09:02:25 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-45844f4b-f0b9-448f-8cda-443c3768b3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358890283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1358890283 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3437385722 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 526598344 ps |
| CPU time | 46.03 seconds |
| Started | Jul 27 08:42:15 PM PDT 24 |
| Finished | Jul 27 08:43:01 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-9cb3af19-cca3-417a-891c-69ee39e17e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437385722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3437385722 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.98461971 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 419580359 ps |
| CPU time | 30.49 seconds |
| Started | Jul 27 08:42:18 PM PDT 24 |
| Finished | Jul 27 08:42:48 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-1341c953-4e82-40a0-a4bc-34f4eaa477cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98461971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.98461971 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.4257313505 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 46331535 ps |
| CPU time | 6.83 seconds |
| Started | Jul 27 08:42:17 PM PDT 24 |
| Finished | Jul 27 08:42:24 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-02003f32-77d3-4d1a-8986-6f59ed69da18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257313505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.4257313505 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1435626529 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 5809093872 ps |
| CPU time | 60.69 seconds |
| Started | Jul 27 08:42:17 PM PDT 24 |
| Finished | Jul 27 08:43:18 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-7921bc35-ff0a-4da6-906c-93a377539ce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435626529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1435626529 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3158990442 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 3518696699 ps |
| CPU time | 59.29 seconds |
| Started | Jul 27 08:42:13 PM PDT 24 |
| Finished | Jul 27 08:43:12 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-68a1c453-9b1c-4e96-a034-079ba26c4433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158990442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3158990442 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1724849903 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 48522453 ps |
| CPU time | 6.47 seconds |
| Started | Jul 27 08:42:14 PM PDT 24 |
| Finished | Jul 27 08:42:20 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-dfec90f0-8171-46a3-99c1-c87b8d882d09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724849903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1724849903 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.1839116092 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 3585265918 ps |
| CPU time | 316.03 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:47:38 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-31b24941-5046-4611-a4c3-454509a7f36b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839116092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1839116092 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1390274628 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 4269197608 ps |
| CPU time | 432.22 seconds |
| Started | Jul 27 08:42:24 PM PDT 24 |
| Finished | Jul 27 08:49:37 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-53630da2-4965-499a-8c58-fe755e5739af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390274628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1390274628 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3898094317 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 175451099 ps |
| CPU time | 50.98 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:43:13 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-e2c29df5-3a3e-4f5a-9d29-424e62a239b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898094317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3898094317 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3160144215 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 105279321 ps |
| CPU time | 79.36 seconds |
| Started | Jul 27 08:42:26 PM PDT 24 |
| Finished | Jul 27 08:43:45 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-90cdaee8-4d58-4ae7-bebe-dd2488529f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160144215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3160144215 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2090303040 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 353759700 ps |
| CPU time | 18.79 seconds |
| Started | Jul 27 08:42:26 PM PDT 24 |
| Finished | Jul 27 08:42:45 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-602385ec-3a7f-4076-9ef5-04f6d69519af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090303040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2090303040 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.675019966 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 2990191087 ps |
| CPU time | 124.82 seconds |
| Started | Jul 27 08:42:29 PM PDT 24 |
| Finished | Jul 27 08:44:34 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-4417022c-13c9-45e7-a772-2ddb0a1ace80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675019966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device. 675019966 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.89240747 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 89109272358 ps |
| CPU time | 1583.04 seconds |
| Started | Jul 27 08:42:31 PM PDT 24 |
| Finished | Jul 27 09:08:55 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-1fd3b58c-1c4e-4140-9a16-a3fb86ea4022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89240747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_de vice_slow_rsp.89240747 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1968325088 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 325166961 ps |
| CPU time | 34.66 seconds |
| Started | Jul 27 08:42:34 PM PDT 24 |
| Finished | Jul 27 08:43:08 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-bb82f903-8f22-4a75-b788-b3a7d09a6ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968325088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1968325088 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2886163514 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 318397522 ps |
| CPU time | 31.18 seconds |
| Started | Jul 27 08:42:29 PM PDT 24 |
| Finished | Jul 27 08:43:00 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-deaab4a2-4d61-4904-bb7c-b3a9c26e816d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886163514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2886163514 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.1667458475 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 605456893 ps |
| CPU time | 55.1 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:43:17 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-ce5f4ac1-52bd-4348-b109-7ebc3b81fc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667458475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1667458475 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3664788662 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 12855368296 ps |
| CPU time | 140.93 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:44:43 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-714b7105-4265-4917-beaf-980df1f7d94b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664788662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3664788662 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1251677344 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 52382354523 ps |
| CPU time | 868.09 seconds |
| Started | Jul 27 08:42:35 PM PDT 24 |
| Finished | Jul 27 08:57:03 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-fb5823aa-230b-466d-8ad5-b0f0e973687b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251677344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1251677344 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1007821995 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 153285870 ps |
| CPU time | 16.59 seconds |
| Started | Jul 27 08:42:21 PM PDT 24 |
| Finished | Jul 27 08:42:37 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-bd69ccba-d746-4795-923e-89ed6e2fd529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007821995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.1007821995 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.186615846 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 1896005020 ps |
| CPU time | 56.72 seconds |
| Started | Jul 27 08:42:33 PM PDT 24 |
| Finished | Jul 27 08:43:30 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-bf232356-609e-49ef-823d-82fef73ccb4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186615846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.186615846 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.4194837870 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 33790947 ps |
| CPU time | 6 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:42:28 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-c56bdd80-6c26-4c5d-98a7-f0dc6b954d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194837870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.4194837870 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1099269687 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 6028275883 ps |
| CPU time | 67.44 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:43:29 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-8bb5613a-f381-407a-b943-c7d29d854e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099269687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1099269687 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2153401212 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 4263094978 ps |
| CPU time | 72.37 seconds |
| Started | Jul 27 08:42:22 PM PDT 24 |
| Finished | Jul 27 08:43:34 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-7acf812b-99be-4e3f-a1fc-9259efd46c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153401212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2153401212 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.294052570 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 34253584 ps |
| CPU time | 5.68 seconds |
| Started | Jul 27 08:42:21 PM PDT 24 |
| Finished | Jul 27 08:42:26 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-604e1779-de93-4fbb-ae0d-8d7f89332b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294052570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays .294052570 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.2732237895 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 1544610964 ps |
| CPU time | 118.49 seconds |
| Started | Jul 27 08:42:33 PM PDT 24 |
| Finished | Jul 27 08:44:31 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-53948a20-9d43-4afd-a888-9783729f4358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732237895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2732237895 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.2397024148 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 1702149159 ps |
| CPU time | 69.9 seconds |
| Started | Jul 27 08:42:29 PM PDT 24 |
| Finished | Jul 27 08:43:40 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-d2e20391-6b24-49af-835e-ef95756dcccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397024148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.2397024148 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.616696605 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 12953204676 ps |
| CPU time | 711.93 seconds |
| Started | Jul 27 08:42:30 PM PDT 24 |
| Finished | Jul 27 08:54:22 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-85f12838-7880-4fbb-ae61-d876c1b5248a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616696605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.616696605 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.421928487 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 6494792514 ps |
| CPU time | 329.23 seconds |
| Started | Jul 27 08:42:29 PM PDT 24 |
| Finished | Jul 27 08:47:59 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-c5e0d67a-91a4-43a8-863f-e5797b37596a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421928487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_reset_error.421928487 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3706390581 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 29152706 ps |
| CPU time | 6 seconds |
| Started | Jul 27 08:42:35 PM PDT 24 |
| Finished | Jul 27 08:42:41 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-914af142-4e0f-4b64-a2e0-01c05f9999d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706390581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3706390581 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2731875011 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 12965927336 ps |
| CPU time | 1113.23 seconds |
| Started | Jul 27 08:29:38 PM PDT 24 |
| Finished | Jul 27 08:48:11 PM PDT 24 |
| Peak memory | 652336 kb |
| Host | smart-c264f456-447f-457a-a7a6-2e0ee3b625de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731875011 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.2731875011 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.842624294 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3752861874 ps |
| CPU time | 350 seconds |
| Started | Jul 27 08:29:37 PM PDT 24 |
| Finished | Jul 27 08:35:27 PM PDT 24 |
| Peak memory | 598648 kb |
| Host | smart-a2d2a860-a6c7-4595-b514-b6d68cfdc980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842624294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.842624294 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.2999019856 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 15593572115 ps |
| CPU time | 2189.14 seconds |
| Started | Jul 27 08:28:55 PM PDT 24 |
| Finished | Jul 27 09:05:24 PM PDT 24 |
| Peak memory | 592880 kb |
| Host | smart-df4161de-c6a6-4d77-a525-61533f5e84dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999019856 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.2999019856 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3021811311 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 321971500 ps |
| CPU time | 18.52 seconds |
| Started | Jul 27 08:29:22 PM PDT 24 |
| Finished | Jul 27 08:29:40 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-f2baa831-3581-4029-ab61-731c621c6247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021811311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3021811311 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.930586563 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 73850325624 ps |
| CPU time | 1311.03 seconds |
| Started | Jul 27 08:29:24 PM PDT 24 |
| Finished | Jul 27 08:51:15 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-ed6c26e4-36aa-4a89-bbfe-832dc9955188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930586563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.930586563 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1627408764 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 35141602 ps |
| CPU time | 7.35 seconds |
| Started | Jul 27 08:29:31 PM PDT 24 |
| Finished | Jul 27 08:29:38 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-7ff7dc55-a77f-4301-bcb1-b5bbe95f620e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627408764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .1627408764 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1763753998 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 128348767 ps |
| CPU time | 8.02 seconds |
| Started | Jul 27 08:29:20 PM PDT 24 |
| Finished | Jul 27 08:29:28 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e7d1a31a-c12c-4ad0-8a9b-eb2a98da8a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763753998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1763753998 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2503239356 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 300080274 ps |
| CPU time | 31.58 seconds |
| Started | Jul 27 08:29:13 PM PDT 24 |
| Finished | Jul 27 08:29:45 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-db1704e2-d273-426b-9cbf-fdf777c5527d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503239356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2503239356 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1217064563 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 39228863471 ps |
| CPU time | 421.72 seconds |
| Started | Jul 27 08:29:20 PM PDT 24 |
| Finished | Jul 27 08:36:22 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5d8e3901-b61b-403a-84be-1e1403d3da3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217064563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1217064563 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1914303110 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 63547278948 ps |
| CPU time | 1158.26 seconds |
| Started | Jul 27 08:29:23 PM PDT 24 |
| Finished | Jul 27 08:48:41 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-df8c1079-151f-4d32-bd98-9813830ce00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914303110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1914303110 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2288414667 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 133400619 ps |
| CPU time | 16.71 seconds |
| Started | Jul 27 08:29:11 PM PDT 24 |
| Finished | Jul 27 08:29:28 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1e905ad4-0f38-44c9-8ac4-c0671552ebf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288414667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2288414667 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.3139796449 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 127263943 ps |
| CPU time | 14.35 seconds |
| Started | Jul 27 08:29:22 PM PDT 24 |
| Finished | Jul 27 08:29:37 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-7133164a-9477-4a9a-9cc2-7b004f95417f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139796449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3139796449 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.3069670410 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 58323914 ps |
| CPU time | 7.41 seconds |
| Started | Jul 27 08:29:08 PM PDT 24 |
| Finished | Jul 27 08:29:16 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-38fd0c4d-da16-4d52-9ee1-dea301300697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069670410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3069670410 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.1769476164 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 10534656235 ps |
| CPU time | 112.62 seconds |
| Started | Jul 27 08:29:13 PM PDT 24 |
| Finished | Jul 27 08:31:06 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e3cabe72-accb-4e40-84f0-c4c82f8cc023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769476164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1769476164 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3537253025 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 5717498676 ps |
| CPU time | 101.24 seconds |
| Started | Jul 27 08:29:13 PM PDT 24 |
| Finished | Jul 27 08:30:54 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-9a5194ba-4df7-4fe7-93fc-58a30174138b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537253025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3537253025 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1223633850 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 41908205 ps |
| CPU time | 6.91 seconds |
| Started | Jul 27 08:29:04 PM PDT 24 |
| Finished | Jul 27 08:29:11 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-2f785787-0df8-4531-8117-53b0f618bf3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223633850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .1223633850 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2346598081 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 9460268023 ps |
| CPU time | 424.32 seconds |
| Started | Jul 27 08:29:35 PM PDT 24 |
| Finished | Jul 27 08:36:40 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-c63375e7-63c0-4ee8-a617-dbdeef279e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346598081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2346598081 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3111201994 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 10301716655 ps |
| CPU time | 419.48 seconds |
| Started | Jul 27 08:29:40 PM PDT 24 |
| Finished | Jul 27 08:36:39 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-15060aa6-5faa-42cc-9001-1d71a3735d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111201994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3111201994 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4155546798 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 1270448745 ps |
| CPU time | 374.68 seconds |
| Started | Jul 27 08:29:36 PM PDT 24 |
| Finished | Jul 27 08:35:51 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-5c07d24a-52f3-452b-9578-4155917be9bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155546798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.4155546798 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.996036278 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 86568037 ps |
| CPU time | 7.66 seconds |
| Started | Jul 27 08:29:30 PM PDT 24 |
| Finished | Jul 27 08:29:38 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-5fb3ea7a-a452-4f3f-8684-50a1ecde30ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996036278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.996036278 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2926475664 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 1522470111 ps |
| CPU time | 69.75 seconds |
| Started | Jul 27 08:42:40 PM PDT 24 |
| Finished | Jul 27 08:43:50 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-785bdda8-91ff-4e0a-9d46-c15ed4a47ee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926475664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2926475664 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1977410059 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 141542214881 ps |
| CPU time | 2317.38 seconds |
| Started | Jul 27 08:42:39 PM PDT 24 |
| Finished | Jul 27 09:21:17 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-dcd11cff-3d49-4563-8355-056e552344a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977410059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1977410059 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1869458887 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 964198018 ps |
| CPU time | 42.5 seconds |
| Started | Jul 27 08:42:40 PM PDT 24 |
| Finished | Jul 27 08:43:23 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-085b6df0-1da9-4f84-ad65-69ca275b5f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869458887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1869458887 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.1683382324 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 2068209961 ps |
| CPU time | 73.93 seconds |
| Started | Jul 27 08:42:37 PM PDT 24 |
| Finished | Jul 27 08:43:51 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e82c321b-26ff-4dce-baf4-a6640c6fb0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683382324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1683382324 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.4156372213 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 540471876 ps |
| CPU time | 20.65 seconds |
| Started | Jul 27 08:42:39 PM PDT 24 |
| Finished | Jul 27 08:43:00 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-2acee8cf-eacf-4c71-8a80-40fd5ab1f4a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156372213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.4156372213 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2345112293 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 83511448091 ps |
| CPU time | 931.65 seconds |
| Started | Jul 27 08:42:37 PM PDT 24 |
| Finished | Jul 27 08:58:09 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-01de58ca-03d3-4285-8c20-95fddf9d6c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345112293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2345112293 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.4202010277 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 10720785576 ps |
| CPU time | 189.52 seconds |
| Started | Jul 27 08:42:41 PM PDT 24 |
| Finished | Jul 27 08:45:50 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-10cbc8be-b12a-4936-a355-83183741837c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202010277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.4202010277 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1910513416 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 224502513 ps |
| CPU time | 24.52 seconds |
| Started | Jul 27 08:42:38 PM PDT 24 |
| Finished | Jul 27 08:43:03 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-a1ab9754-7697-43f5-bf8b-023867ee43e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910513416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.1910513416 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.949006691 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 2546856611 ps |
| CPU time | 89.57 seconds |
| Started | Jul 27 08:42:37 PM PDT 24 |
| Finished | Jul 27 08:44:07 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-5d506420-7200-4294-84c9-9fd7fff4ca1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949006691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.949006691 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1908682320 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 53341829 ps |
| CPU time | 7.5 seconds |
| Started | Jul 27 08:42:33 PM PDT 24 |
| Finished | Jul 27 08:42:40 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-1cffac04-cdff-44bc-8fba-59aa09e8acd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908682320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1908682320 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3674398864 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 7051921466 ps |
| CPU time | 79.35 seconds |
| Started | Jul 27 08:42:38 PM PDT 24 |
| Finished | Jul 27 08:43:58 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-4f06d6a6-a7b6-4d6a-ae0d-25d38f8f505d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674398864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3674398864 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2108935737 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 4451963074 ps |
| CPU time | 81.75 seconds |
| Started | Jul 27 08:42:39 PM PDT 24 |
| Finished | Jul 27 08:44:00 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e69352d0-8b13-40be-971e-1e945aadaeef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108935737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.2108935737 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3577461813 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 51961605 ps |
| CPU time | 6.96 seconds |
| Started | Jul 27 08:42:36 PM PDT 24 |
| Finished | Jul 27 08:42:43 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-8ee671cb-90ae-4553-ae1f-2e287a011bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577461813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3577461813 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.3283765758 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 7522804266 ps |
| CPU time | 331.04 seconds |
| Started | Jul 27 08:42:37 PM PDT 24 |
| Finished | Jul 27 08:48:08 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-ecf451d9-52f6-4435-9456-82478fe752d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283765758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3283765758 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1668596630 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 1463941544 ps |
| CPU time | 44.71 seconds |
| Started | Jul 27 08:42:37 PM PDT 24 |
| Finished | Jul 27 08:43:22 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-df6f0ac7-1015-4c5c-b75a-6ae17df2cbd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668596630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1668596630 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.574632964 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 16801834635 ps |
| CPU time | 808.52 seconds |
| Started | Jul 27 08:42:37 PM PDT 24 |
| Finished | Jul 27 08:56:06 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-6aab41c6-5518-4e77-87ef-5bd3a8224db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574632964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.574632964 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2276779254 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 8107010540 ps |
| CPU time | 341.61 seconds |
| Started | Jul 27 08:42:38 PM PDT 24 |
| Finished | Jul 27 08:48:19 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-89007f17-2652-46a5-87db-daadb427880b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276779254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2276779254 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.4294330402 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 317440925 ps |
| CPU time | 17.81 seconds |
| Started | Jul 27 08:42:35 PM PDT 24 |
| Finished | Jul 27 08:42:53 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-c591bdaf-0480-460e-827b-0743ad920f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294330402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.4294330402 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1217284226 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 380804534 ps |
| CPU time | 32.73 seconds |
| Started | Jul 27 08:42:51 PM PDT 24 |
| Finished | Jul 27 08:43:24 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-9b300ab1-edde-432e-acd7-e7415e94a24e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217284226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .1217284226 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1185056975 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 52383141674 ps |
| CPU time | 908.98 seconds |
| Started | Jul 27 08:42:45 PM PDT 24 |
| Finished | Jul 27 08:57:54 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-705760df-31bd-4d25-b6cf-1665cf0ace20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185056975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1185056975 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3126627465 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 268652193 ps |
| CPU time | 29.21 seconds |
| Started | Jul 27 08:42:53 PM PDT 24 |
| Finished | Jul 27 08:43:22 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-69ee541f-90ef-4f04-88d4-f0f6b17d7df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126627465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3126627465 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.2490085884 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 272830241 ps |
| CPU time | 13.93 seconds |
| Started | Jul 27 08:42:53 PM PDT 24 |
| Finished | Jul 27 08:43:07 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-e37d6476-4dac-4a91-b62e-8850e170fa8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490085884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.2490085884 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.193163210 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 143579275 ps |
| CPU time | 16.44 seconds |
| Started | Jul 27 08:42:48 PM PDT 24 |
| Finished | Jul 27 08:43:04 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-a173a346-5444-454b-82d2-538ac7ce96ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193163210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.193163210 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.659668957 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 31140721743 ps |
| CPU time | 334.19 seconds |
| Started | Jul 27 08:42:46 PM PDT 24 |
| Finished | Jul 27 08:48:20 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-8d8a65e3-e765-4d5b-9cb7-b27bb82b3430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659668957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.659668957 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.481881709 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 44506027750 ps |
| CPU time | 766.15 seconds |
| Started | Jul 27 08:42:51 PM PDT 24 |
| Finished | Jul 27 08:55:37 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-6a89678a-62a6-47b2-b1f7-496d6a2596b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481881709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.481881709 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2945186425 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 249167079 ps |
| CPU time | 24.63 seconds |
| Started | Jul 27 08:42:46 PM PDT 24 |
| Finished | Jul 27 08:43:10 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-69923ed6-fae9-49b4-b263-b56b6e648028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945186425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.2945186425 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2018478 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 213271421 ps |
| CPU time | 17.82 seconds |
| Started | Jul 27 08:42:55 PM PDT 24 |
| Finished | Jul 27 08:43:13 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-b367fb64-2cf1-42a2-b7ab-27121b799740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2018478 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.4287346610 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 174628538 ps |
| CPU time | 8.88 seconds |
| Started | Jul 27 08:42:38 PM PDT 24 |
| Finished | Jul 27 08:42:47 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-a8048466-0baf-4449-b92b-21e21dc0027c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287346610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.4287346610 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2299996769 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 7703989618 ps |
| CPU time | 82.7 seconds |
| Started | Jul 27 08:42:38 PM PDT 24 |
| Finished | Jul 27 08:44:00 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-97d8d18a-c2ff-4cd7-bd87-278c12a91295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299996769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2299996769 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.493809520 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 6717032876 ps |
| CPU time | 114.28 seconds |
| Started | Jul 27 08:42:44 PM PDT 24 |
| Finished | Jul 27 08:44:39 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-f2863189-1a50-4926-8a07-d1882d93be54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493809520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.493809520 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3392727330 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 40343240 ps |
| CPU time | 6.05 seconds |
| Started | Jul 27 08:42:39 PM PDT 24 |
| Finished | Jul 27 08:42:45 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-23950a3b-3196-4442-a071-5e505d4733ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392727330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3392727330 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.2764927174 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 791280409 ps |
| CPU time | 71.63 seconds |
| Started | Jul 27 08:42:51 PM PDT 24 |
| Finished | Jul 27 08:44:03 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-e284f692-70ed-42b7-bf8e-cca76aba81c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764927174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.2764927174 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3146269432 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1176138265 ps |
| CPU time | 99.57 seconds |
| Started | Jul 27 08:43:28 PM PDT 24 |
| Finished | Jul 27 08:45:08 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-7220cf28-b5ad-4fab-9466-bf4a970ac04e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146269432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3146269432 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2878206301 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 5690472912 ps |
| CPU time | 208.08 seconds |
| Started | Jul 27 08:42:52 PM PDT 24 |
| Finished | Jul 27 08:46:20 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-dc9de460-120a-49a2-a31c-f9cb791628dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878206301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.2878206301 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3574854984 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 7400671967 ps |
| CPU time | 416.03 seconds |
| Started | Jul 27 08:42:53 PM PDT 24 |
| Finished | Jul 27 08:49:50 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-898999cc-8c3e-49a8-a775-ae385f51855c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574854984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3574854984 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1446560562 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 312848917 ps |
| CPU time | 33.51 seconds |
| Started | Jul 27 08:42:56 PM PDT 24 |
| Finished | Jul 27 08:43:29 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-498a0930-96c3-4854-980a-59c26760e3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446560562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1446560562 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.868292174 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 529002671 ps |
| CPU time | 46.83 seconds |
| Started | Jul 27 08:43:00 PM PDT 24 |
| Finished | Jul 27 08:43:46 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-5dbe0d15-cbd5-4b76-9a4b-3ba0468ce3a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868292174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 868292174 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1252516181 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 10752301865 ps |
| CPU time | 194.8 seconds |
| Started | Jul 27 08:43:00 PM PDT 24 |
| Finished | Jul 27 08:46:15 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-c12425c4-b2ea-47bf-bc73-58d72fbe9500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252516181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1252516181 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1716304097 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 313934446 ps |
| CPU time | 41 seconds |
| Started | Jul 27 08:43:01 PM PDT 24 |
| Finished | Jul 27 08:43:42 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-51a1038a-0857-4470-9f8c-84b41618ed89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716304097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.1716304097 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1535126201 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 188196029 ps |
| CPU time | 20.66 seconds |
| Started | Jul 27 08:43:03 PM PDT 24 |
| Finished | Jul 27 08:43:24 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ec5b8b3e-caa0-4938-a1b2-d7d4ebee9cfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535126201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1535126201 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.497365857 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 90122452 ps |
| CPU time | 11.95 seconds |
| Started | Jul 27 08:43:03 PM PDT 24 |
| Finished | Jul 27 08:43:15 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-85ce886d-02fa-46bc-85b7-a838bb058bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497365857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.497365857 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1270349829 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 115359966004 ps |
| CPU time | 1201.55 seconds |
| Started | Jul 27 08:43:00 PM PDT 24 |
| Finished | Jul 27 09:03:02 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-b61633d2-459f-4a18-bba1-b4cdf75397f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270349829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1270349829 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2187000877 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 3637230614 ps |
| CPU time | 60 seconds |
| Started | Jul 27 08:42:59 PM PDT 24 |
| Finished | Jul 27 08:43:59 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-408d04e0-e50e-4e2c-b9f4-26f091d3f02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187000877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2187000877 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.1632569727 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 235109701 ps |
| CPU time | 24.52 seconds |
| Started | Jul 27 08:43:01 PM PDT 24 |
| Finished | Jul 27 08:43:25 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-0038cd6f-04a7-4554-9da8-79e2f6cf8e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632569727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.1632569727 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2509107095 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 519782834 ps |
| CPU time | 40.89 seconds |
| Started | Jul 27 08:43:02 PM PDT 24 |
| Finished | Jul 27 08:43:43 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-885161ed-bbd8-485e-8413-0ab4e9d8167d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509107095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2509107095 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.4257753277 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 212346358 ps |
| CPU time | 8.83 seconds |
| Started | Jul 27 08:43:02 PM PDT 24 |
| Finished | Jul 27 08:43:11 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-88d562ae-f896-4fea-af60-19063be09a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257753277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.4257753277 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.698971185 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 8579877640 ps |
| CPU time | 90.91 seconds |
| Started | Jul 27 08:42:58 PM PDT 24 |
| Finished | Jul 27 08:44:29 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-2d27f5ae-9d75-498f-93c3-735452babc53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698971185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.698971185 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.988599322 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 4949524702 ps |
| CPU time | 80.27 seconds |
| Started | Jul 27 08:43:00 PM PDT 24 |
| Finished | Jul 27 08:44:20 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-d7c8eaad-7f97-4a49-8372-741c4b37630a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988599322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.988599322 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1796084789 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 43292058 ps |
| CPU time | 6 seconds |
| Started | Jul 27 08:43:03 PM PDT 24 |
| Finished | Jul 27 08:43:09 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-ed16fea1-07a0-43da-af98-33a5acdf5f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796084789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1796084789 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.1549561011 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 8008247487 ps |
| CPU time | 332.87 seconds |
| Started | Jul 27 08:43:07 PM PDT 24 |
| Finished | Jul 27 08:48:40 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-73b3b75e-afb9-485e-ba35-fae47edcc572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549561011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1549561011 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.593879635 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 6690351141 ps |
| CPU time | 290.18 seconds |
| Started | Jul 27 08:43:08 PM PDT 24 |
| Finished | Jul 27 08:47:58 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-9fa39a63-e175-460b-b353-07f63f2eca8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593879635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.593879635 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.467380635 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 2560935822 ps |
| CPU time | 341.87 seconds |
| Started | Jul 27 08:43:08 PM PDT 24 |
| Finished | Jul 27 08:48:50 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-5ec804ce-2b44-490c-a840-1406da21fecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467380635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_ with_rand_reset.467380635 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2947334105 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 6798557648 ps |
| CPU time | 421.77 seconds |
| Started | Jul 27 08:43:11 PM PDT 24 |
| Finished | Jul 27 08:50:13 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-256f05f4-f762-430e-bfdc-61adb7b2f8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947334105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2947334105 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1170624754 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 924329013 ps |
| CPU time | 42.52 seconds |
| Started | Jul 27 08:43:00 PM PDT 24 |
| Finished | Jul 27 08:43:43 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-82a9adad-4d8c-4c9e-bd31-14a539263046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170624754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1170624754 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3040205453 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 3112110711 ps |
| CPU time | 138.67 seconds |
| Started | Jul 27 08:43:17 PM PDT 24 |
| Finished | Jul 27 08:45:36 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-4938311e-596d-4a6e-8fd4-e113b367151d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040205453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .3040205453 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2080123032 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 501299730 ps |
| CPU time | 22.05 seconds |
| Started | Jul 27 08:43:17 PM PDT 24 |
| Finished | Jul 27 08:43:39 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-e90b9ef3-6302-4113-9b05-a438c539c527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080123032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.2080123032 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2641017358 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 899242278 ps |
| CPU time | 35.06 seconds |
| Started | Jul 27 08:43:15 PM PDT 24 |
| Finished | Jul 27 08:43:50 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-cdf99deb-681d-42cd-91c0-b217fd483b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641017358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2641017358 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2721259039 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 1795813554 ps |
| CPU time | 72.9 seconds |
| Started | Jul 27 08:43:17 PM PDT 24 |
| Finished | Jul 27 08:44:30 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-3798c8c7-8f42-4bd1-b4eb-00a9d14f5084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721259039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2721259039 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3881141255 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 3398110052 ps |
| CPU time | 36 seconds |
| Started | Jul 27 08:43:20 PM PDT 24 |
| Finished | Jul 27 08:43:56 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-c72d3947-8a40-469b-96fd-acdbe3f233d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881141255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3881141255 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3329276218 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 29338184916 ps |
| CPU time | 478.24 seconds |
| Started | Jul 27 08:43:16 PM PDT 24 |
| Finished | Jul 27 08:51:15 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-629cf5f0-d6c9-4fe3-8593-3e855593f7e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329276218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3329276218 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1322765981 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 42938441 ps |
| CPU time | 7.66 seconds |
| Started | Jul 27 08:43:15 PM PDT 24 |
| Finished | Jul 27 08:43:23 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-96bd12b7-8281-40ac-9ad0-c8ea988ae1cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322765981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1322765981 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.734819447 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1227999985 ps |
| CPU time | 39.91 seconds |
| Started | Jul 27 08:43:16 PM PDT 24 |
| Finished | Jul 27 08:43:56 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-5e6c2001-1e56-4541-a603-65108423842c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734819447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.734819447 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.3410315132 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 59865569 ps |
| CPU time | 7.65 seconds |
| Started | Jul 27 08:43:07 PM PDT 24 |
| Finished | Jul 27 08:43:15 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-3779df21-6ab2-47ed-8f17-6124871eb808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410315132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.3410315132 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1349387125 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 9130995703 ps |
| CPU time | 91.47 seconds |
| Started | Jul 27 08:43:12 PM PDT 24 |
| Finished | Jul 27 08:44:44 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-d72a45af-7fa8-4931-95a6-c927c7d51417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349387125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1349387125 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1688991140 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 4204871751 ps |
| CPU time | 73.21 seconds |
| Started | Jul 27 08:43:12 PM PDT 24 |
| Finished | Jul 27 08:44:25 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5918160c-d684-4fcd-8eb1-6f58a833bb7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688991140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1688991140 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2561595761 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 41090292 ps |
| CPU time | 6.46 seconds |
| Started | Jul 27 08:43:10 PM PDT 24 |
| Finished | Jul 27 08:43:17 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-66403e2c-4cb8-4a72-8279-7395109a2e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561595761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.2561595761 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3674161852 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 9209315580 ps |
| CPU time | 328.66 seconds |
| Started | Jul 27 08:43:17 PM PDT 24 |
| Finished | Jul 27 08:48:46 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-0186f6cb-690f-482e-8f8f-cd2035b6ae10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674161852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3674161852 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3272854542 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2078923429 ps |
| CPU time | 184.49 seconds |
| Started | Jul 27 08:43:16 PM PDT 24 |
| Finished | Jul 27 08:46:21 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d18da60b-9dc5-4546-8329-fd21d3744db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272854542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3272854542 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3848137865 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 6444510539 ps |
| CPU time | 712.47 seconds |
| Started | Jul 27 08:43:14 PM PDT 24 |
| Finished | Jul 27 08:55:07 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-0ca38723-5afc-4cfb-96c2-5e92580bda00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848137865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3848137865 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1112923474 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 4543068599 ps |
| CPU time | 372.86 seconds |
| Started | Jul 27 08:43:17 PM PDT 24 |
| Finished | Jul 27 08:49:30 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-f470cd7a-aa28-4425-9056-ddfa8c6dea84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112923474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1112923474 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1711581775 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 295712947 ps |
| CPU time | 35.23 seconds |
| Started | Jul 27 08:43:15 PM PDT 24 |
| Finished | Jul 27 08:43:51 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-62955481-84d7-4e25-9407-a61e3a66a569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711581775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1711581775 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1557939680 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 2196977225 ps |
| CPU time | 85.22 seconds |
| Started | Jul 27 08:43:24 PM PDT 24 |
| Finished | Jul 27 08:44:49 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-4f17a86f-5e8f-4a62-b4b8-6978d5338d55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557939680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1557939680 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3087783103 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 98857397 ps |
| CPU time | 14.3 seconds |
| Started | Jul 27 08:43:25 PM PDT 24 |
| Finished | Jul 27 08:43:40 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-8ed605bc-b0f3-48ed-9d09-46ecffc9bdc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087783103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3087783103 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.1990499566 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 1047368477 ps |
| CPU time | 37.41 seconds |
| Started | Jul 27 08:43:22 PM PDT 24 |
| Finished | Jul 27 08:43:59 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-7be82408-31d4-4dcc-a23c-32c0808fa4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990499566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.1990499566 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.2720591442 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 1571750242 ps |
| CPU time | 60.02 seconds |
| Started | Jul 27 08:43:16 PM PDT 24 |
| Finished | Jul 27 08:44:16 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ec91137e-25dc-4aa3-83a3-2b74cfced1ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720591442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2720591442 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.232483681 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 91090120805 ps |
| CPU time | 964.07 seconds |
| Started | Jul 27 08:43:25 PM PDT 24 |
| Finished | Jul 27 08:59:29 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-96bb590b-5e94-4baa-8064-4bf96eb51e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232483681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.232483681 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.3205082015 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 3853117352 ps |
| CPU time | 69.42 seconds |
| Started | Jul 27 08:43:24 PM PDT 24 |
| Finished | Jul 27 08:44:34 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-566f8c3a-a102-4c75-bf91-99144cb76fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205082015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.3205082015 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2792293818 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 125057227 ps |
| CPU time | 13.32 seconds |
| Started | Jul 27 08:43:24 PM PDT 24 |
| Finished | Jul 27 08:43:37 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-874937b6-deb5-484f-9968-4bf25be7bcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792293818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2792293818 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2872145971 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 303236336 ps |
| CPU time | 25.29 seconds |
| Started | Jul 27 08:43:26 PM PDT 24 |
| Finished | Jul 27 08:43:51 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-1fb404f6-18c1-4246-b806-3ccb001e6486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872145971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2872145971 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.2876987583 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 44718385 ps |
| CPU time | 6.67 seconds |
| Started | Jul 27 08:43:17 PM PDT 24 |
| Finished | Jul 27 08:43:23 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-1cac6a27-9f49-4bb1-a33e-5eff8c5043b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876987583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.2876987583 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1140661304 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 6248728264 ps |
| CPU time | 62.86 seconds |
| Started | Jul 27 08:43:16 PM PDT 24 |
| Finished | Jul 27 08:44:19 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-15c3670a-1b48-4da5-a943-65d7f32cb880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140661304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1140661304 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2188993194 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 6447926630 ps |
| CPU time | 113.94 seconds |
| Started | Jul 27 08:43:15 PM PDT 24 |
| Finished | Jul 27 08:45:09 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-16b259c1-678a-46fb-8bf0-8d65a3bf0753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188993194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2188993194 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.4060147171 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 53115709 ps |
| CPU time | 6.99 seconds |
| Started | Jul 27 08:43:15 PM PDT 24 |
| Finished | Jul 27 08:43:22 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-baba6171-142f-461a-82d0-fcfd89f3483c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060147171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.4060147171 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.944354059 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4045004626 ps |
| CPU time | 346.34 seconds |
| Started | Jul 27 08:43:25 PM PDT 24 |
| Finished | Jul 27 08:49:12 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-189dc0fe-4e61-4e01-a3a6-2c0871528a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944354059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.944354059 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.555432097 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 5872959640 ps |
| CPU time | 229.01 seconds |
| Started | Jul 27 08:43:28 PM PDT 24 |
| Finished | Jul 27 08:47:17 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-d292b699-37ea-4efa-ab5e-9b9543bcfc5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555432097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.555432097 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1586562528 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 3424558701 ps |
| CPU time | 417.97 seconds |
| Started | Jul 27 08:43:25 PM PDT 24 |
| Finished | Jul 27 08:50:24 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-d61c038e-0077-41e5-bc16-f2649d75521f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586562528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.1586562528 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1828639818 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 522572397 ps |
| CPU time | 185.53 seconds |
| Started | Jul 27 08:43:24 PM PDT 24 |
| Finished | Jul 27 08:46:29 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-64e6589b-f48f-4801-9345-af044c2f0d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828639818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.1828639818 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.4130835196 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 1361715975 ps |
| CPU time | 58.9 seconds |
| Started | Jul 27 08:43:30 PM PDT 24 |
| Finished | Jul 27 08:44:29 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-03b3a25a-af6e-4dbe-bddd-362cbc2864c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130835196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.4130835196 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.258688368 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 379969389 ps |
| CPU time | 31.84 seconds |
| Started | Jul 27 08:43:33 PM PDT 24 |
| Finished | Jul 27 08:44:05 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-847b5568-4229-4372-9feb-8a08a58702ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258688368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device. 258688368 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3592588063 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 134017929062 ps |
| CPU time | 2271.17 seconds |
| Started | Jul 27 08:43:35 PM PDT 24 |
| Finished | Jul 27 09:21:27 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-4fc237b5-1f0a-4182-bee8-c00a70aa977b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592588063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3592588063 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.3410656997 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 1092361049 ps |
| CPU time | 43.04 seconds |
| Started | Jul 27 08:43:32 PM PDT 24 |
| Finished | Jul 27 08:44:15 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-3767c342-112b-4b2f-82b9-5a47b0bf7a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410656997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.3410656997 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2936626282 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 867678119 ps |
| CPU time | 34.72 seconds |
| Started | Jul 27 08:43:34 PM PDT 24 |
| Finished | Jul 27 08:44:08 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-2e79b518-8a26-4fbe-bdf5-cdca6f7eadd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936626282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2936626282 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.3491630466 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 337725978 ps |
| CPU time | 31.98 seconds |
| Started | Jul 27 08:43:30 PM PDT 24 |
| Finished | Jul 27 08:44:02 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-ff2ccbc0-1c7e-4095-bc76-6630147430d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491630466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3491630466 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.4210223839 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 73771809225 ps |
| CPU time | 805.44 seconds |
| Started | Jul 27 08:43:31 PM PDT 24 |
| Finished | Jul 27 08:56:56 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-70b6b187-a801-4038-91e5-c5446dfefb1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210223839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.4210223839 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.4180670047 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 25069834584 ps |
| CPU time | 444.9 seconds |
| Started | Jul 27 08:43:34 PM PDT 24 |
| Finished | Jul 27 08:50:59 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-7f68bb4d-75fb-4204-8acc-f5eb6b6d4f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180670047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.4180670047 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.2686983293 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 271552569 ps |
| CPU time | 29.65 seconds |
| Started | Jul 27 08:43:33 PM PDT 24 |
| Finished | Jul 27 08:44:02 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-aa972003-f35e-4e6c-bd6f-d555618ebe51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686983293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.2686983293 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.2736704227 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 578571573 ps |
| CPU time | 41.15 seconds |
| Started | Jul 27 08:43:31 PM PDT 24 |
| Finished | Jul 27 08:44:12 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0087ee50-c157-47af-a51c-e0f4dd4b4193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736704227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2736704227 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.4019005762 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 47879736 ps |
| CPU time | 6.93 seconds |
| Started | Jul 27 08:43:23 PM PDT 24 |
| Finished | Jul 27 08:43:30 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-bb3edb6c-3757-4a8f-a014-ae472d8ecd35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019005762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.4019005762 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.1316286729 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 9930850142 ps |
| CPU time | 103.07 seconds |
| Started | Jul 27 08:43:30 PM PDT 24 |
| Finished | Jul 27 08:45:13 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-9da03f99-8075-4129-ad8a-fd7b94374e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316286729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.1316286729 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.4162574816 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 4779669578 ps |
| CPU time | 85.36 seconds |
| Started | Jul 27 08:43:33 PM PDT 24 |
| Finished | Jul 27 08:44:59 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-a1ae9b4b-162a-4369-a131-96eff87c4586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162574816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.4162574816 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.410812779 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 48202608 ps |
| CPU time | 6.95 seconds |
| Started | Jul 27 08:43:24 PM PDT 24 |
| Finished | Jul 27 08:43:31 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-867be768-62f0-4a84-8cb0-ddffbdb76797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410812779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays .410812779 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3693359052 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 3034468724 ps |
| CPU time | 258.91 seconds |
| Started | Jul 27 08:43:32 PM PDT 24 |
| Finished | Jul 27 08:47:51 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-bbbd8082-cb27-4b93-9293-cdb5ace5c5a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693359052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3693359052 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.2532467018 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 13249606546 ps |
| CPU time | 492.83 seconds |
| Started | Jul 27 08:43:32 PM PDT 24 |
| Finished | Jul 27 08:51:45 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-7fb25c34-ab7a-4e26-9c07-a2e40556160a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532467018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.2532467018 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.4146056375 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 5735478746 ps |
| CPU time | 447.81 seconds |
| Started | Jul 27 08:43:34 PM PDT 24 |
| Finished | Jul 27 08:51:02 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3d0bf26d-2a58-49ec-a25f-a1ecf7b38dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146056375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.4146056375 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1696304253 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 72411689 ps |
| CPU time | 35.5 seconds |
| Started | Jul 27 08:43:31 PM PDT 24 |
| Finished | Jul 27 08:44:07 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-42034822-205c-4e2d-bef4-36d1da22242c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696304253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1696304253 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.2731252339 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 1256143349 ps |
| CPU time | 53.2 seconds |
| Started | Jul 27 08:43:32 PM PDT 24 |
| Finished | Jul 27 08:44:26 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-b3b99100-ac78-483b-80e0-e2f9706f30f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731252339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.2731252339 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.1382534120 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 847040579 ps |
| CPU time | 63.41 seconds |
| Started | Jul 27 08:43:45 PM PDT 24 |
| Finished | Jul 27 08:44:49 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-b5bff4ff-3e06-4a72-8631-3c42364a3f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382534120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .1382534120 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.274295400 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 54698489944 ps |
| CPU time | 1011.16 seconds |
| Started | Jul 27 08:43:39 PM PDT 24 |
| Finished | Jul 27 09:00:31 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-7c891791-e896-404f-a8f3-928adabd8350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274295400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.274295400 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.4184436473 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 751853851 ps |
| CPU time | 32.58 seconds |
| Started | Jul 27 08:43:40 PM PDT 24 |
| Finished | Jul 27 08:44:12 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ec560482-fa84-4782-ab34-68e4a57cda66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184436473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.4184436473 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.2933572390 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 95927642 ps |
| CPU time | 11.33 seconds |
| Started | Jul 27 08:43:40 PM PDT 24 |
| Finished | Jul 27 08:43:52 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-e8ffacbc-ccc5-4027-bb88-c1c56d79b6a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933572390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2933572390 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.3983589173 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 580877928 ps |
| CPU time | 50.41 seconds |
| Started | Jul 27 08:43:39 PM PDT 24 |
| Finished | Jul 27 08:44:30 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-71d8713d-f9f1-4e50-94f3-9f1f6599586e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983589173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.3983589173 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.489106247 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 74645557994 ps |
| CPU time | 845.32 seconds |
| Started | Jul 27 08:43:42 PM PDT 24 |
| Finished | Jul 27 08:57:47 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d14e62e7-7a68-4ff2-9c9e-8140c801d431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489106247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.489106247 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.2427780151 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 11675924183 ps |
| CPU time | 196.92 seconds |
| Started | Jul 27 08:43:38 PM PDT 24 |
| Finished | Jul 27 08:46:55 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-f0cb3fa2-2c90-4115-90db-6b89cc621cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427780151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.2427780151 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3246732074 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 425753518 ps |
| CPU time | 39.57 seconds |
| Started | Jul 27 08:43:40 PM PDT 24 |
| Finished | Jul 27 08:44:20 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a9629341-8543-4f4b-8f67-cba4c8cd1510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246732074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3246732074 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.1279305868 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 240532791 ps |
| CPU time | 20.95 seconds |
| Started | Jul 27 08:43:45 PM PDT 24 |
| Finished | Jul 27 08:44:06 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-62dc1f63-4b84-41ef-bac5-6e6a8920889e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279305868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1279305868 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.3185535170 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 207233479 ps |
| CPU time | 10.59 seconds |
| Started | Jul 27 08:43:44 PM PDT 24 |
| Finished | Jul 27 08:43:54 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-ad80a7ea-01bc-4f6f-bc32-e91ad7e32144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185535170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3185535170 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3720189855 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 7620480887 ps |
| CPU time | 78.12 seconds |
| Started | Jul 27 08:43:39 PM PDT 24 |
| Finished | Jul 27 08:44:57 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-bc6cefb0-08d5-4ad7-bf50-0b778f0e3d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720189855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3720189855 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3449128366 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 6049793198 ps |
| CPU time | 105.19 seconds |
| Started | Jul 27 08:43:40 PM PDT 24 |
| Finished | Jul 27 08:45:25 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-5536fbc5-8688-41f3-9ade-632c3a6635ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449128366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3449128366 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3899155278 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 32937403 ps |
| CPU time | 5.86 seconds |
| Started | Jul 27 08:43:38 PM PDT 24 |
| Finished | Jul 27 08:43:44 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-8a72dac9-67f8-43b1-9193-9a4ddf735858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899155278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.3899155278 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.3320764640 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5873180287 ps |
| CPU time | 239.93 seconds |
| Started | Jul 27 08:43:48 PM PDT 24 |
| Finished | Jul 27 08:47:48 PM PDT 24 |
| Peak memory | 576048 kb |
| Host | smart-4131f3ae-c550-4c19-93e2-cccecf0bbfd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320764640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.3320764640 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.1593449769 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 511869777 ps |
| CPU time | 55.26 seconds |
| Started | Jul 27 08:43:52 PM PDT 24 |
| Finished | Jul 27 08:44:47 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-efafc329-02d8-4e78-b10d-8a46d13104ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593449769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.1593449769 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3938565047 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 8813437251 ps |
| CPU time | 466.4 seconds |
| Started | Jul 27 08:43:49 PM PDT 24 |
| Finished | Jul 27 08:51:36 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-1f097b03-74b8-4299-8bee-ea152eca7fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938565047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.3938565047 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.304841082 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 10690795196 ps |
| CPU time | 609.38 seconds |
| Started | Jul 27 08:43:47 PM PDT 24 |
| Finished | Jul 27 08:53:57 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-31c83c3e-3a54-461f-93c2-52dd22461f80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304841082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.304841082 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1568722859 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 1006897508 ps |
| CPU time | 43.33 seconds |
| Started | Jul 27 08:43:42 PM PDT 24 |
| Finished | Jul 27 08:44:25 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b915fdcf-09ee-4439-9a6e-978fa4f7b639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568722859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1568722859 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1315421170 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 101533090 ps |
| CPU time | 9.85 seconds |
| Started | Jul 27 08:43:55 PM PDT 24 |
| Finished | Jul 27 08:44:04 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-e796ec9d-621f-4292-be7c-01db0beed75c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315421170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1315421170 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3549189167 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 79945444964 ps |
| CPU time | 1397.88 seconds |
| Started | Jul 27 08:44:00 PM PDT 24 |
| Finished | Jul 27 09:07:18 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-77ba90ef-08df-4560-82f2-29421a883c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549189167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.3549189167 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3242928511 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1348942273 ps |
| CPU time | 61.82 seconds |
| Started | Jul 27 08:44:01 PM PDT 24 |
| Finished | Jul 27 08:45:03 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-d0d66b3b-e77f-4996-b808-c9ca08b27a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242928511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3242928511 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.1433522265 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 228493603 ps |
| CPU time | 22.48 seconds |
| Started | Jul 27 08:44:02 PM PDT 24 |
| Finished | Jul 27 08:44:25 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-38fa19bb-3fc6-4914-9bb2-1999014fb89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433522265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.1433522265 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1601746689 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1923538936 ps |
| CPU time | 75.48 seconds |
| Started | Jul 27 08:43:51 PM PDT 24 |
| Finished | Jul 27 08:45:07 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-a336694b-5fd1-4509-8c3c-9e1927f1336f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601746689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1601746689 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.345940979 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 83168775552 ps |
| CPU time | 878.22 seconds |
| Started | Jul 27 08:43:51 PM PDT 24 |
| Finished | Jul 27 08:58:29 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-76da6510-1bd2-409b-a7ca-af145f854a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345940979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.345940979 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1843031143 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 15506327257 ps |
| CPU time | 284.34 seconds |
| Started | Jul 27 08:43:54 PM PDT 24 |
| Finished | Jul 27 08:48:38 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-26de4013-e91d-478a-873a-ae329e31a463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843031143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.1843031143 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.50428634 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 322246128 ps |
| CPU time | 29.62 seconds |
| Started | Jul 27 08:43:48 PM PDT 24 |
| Finished | Jul 27 08:44:18 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-0a344656-ce8d-46b5-baa5-e8595f82c7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50428634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delay s.50428634 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.1689246386 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 1121081479 ps |
| CPU time | 37.24 seconds |
| Started | Jul 27 08:44:00 PM PDT 24 |
| Finished | Jul 27 08:44:38 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-4b61625c-0bca-4289-8be4-c040c3e41f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689246386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1689246386 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.133785495 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 199571623 ps |
| CPU time | 9.67 seconds |
| Started | Jul 27 08:43:49 PM PDT 24 |
| Finished | Jul 27 08:43:59 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-db358d62-a235-404f-a246-cc0f9251ed42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133785495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.133785495 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.4211807284 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 10080377540 ps |
| CPU time | 110.79 seconds |
| Started | Jul 27 08:43:51 PM PDT 24 |
| Finished | Jul 27 08:45:42 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-03772a59-d363-44f1-914a-62864cd9b599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211807284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.4211807284 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3351019105 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 5561994662 ps |
| CPU time | 98.2 seconds |
| Started | Jul 27 08:43:48 PM PDT 24 |
| Finished | Jul 27 08:45:26 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-2a804b78-9fda-4d7d-bf89-1ab4b48ae432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351019105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3351019105 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1053325966 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 47519377 ps |
| CPU time | 6.59 seconds |
| Started | Jul 27 08:43:51 PM PDT 24 |
| Finished | Jul 27 08:43:57 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-2e7b07f8-ccf6-40d8-8c5e-cf0668e0901a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053325966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1053325966 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.350186747 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3487155623 ps |
| CPU time | 295.65 seconds |
| Started | Jul 27 08:44:01 PM PDT 24 |
| Finished | Jul 27 08:48:57 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-bf379820-9956-49d5-b267-5ce356d430bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350186747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.350186747 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1870849606 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 2131088085 ps |
| CPU time | 79.65 seconds |
| Started | Jul 27 08:44:01 PM PDT 24 |
| Finished | Jul 27 08:45:21 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-ed21acdf-246d-49d4-8649-3849d2ec0b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870849606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1870849606 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3017949452 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 61654510 ps |
| CPU time | 20.93 seconds |
| Started | Jul 27 08:44:01 PM PDT 24 |
| Finished | Jul 27 08:44:22 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-8b7e60f7-d03f-4bf0-a1d3-3817ede7c851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017949452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3017949452 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1463258243 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 3633115564 ps |
| CPU time | 321.78 seconds |
| Started | Jul 27 08:43:59 PM PDT 24 |
| Finished | Jul 27 08:49:21 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-1596fafa-6051-4c1d-85b1-5970f3c3e8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463258243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1463258243 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1035013017 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 308173445 ps |
| CPU time | 17.71 seconds |
| Started | Jul 27 08:44:02 PM PDT 24 |
| Finished | Jul 27 08:44:20 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ab24b357-c919-48cf-9c3c-018d61d84e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035013017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1035013017 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1708071329 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 941701468 ps |
| CPU time | 81.5 seconds |
| Started | Jul 27 08:44:12 PM PDT 24 |
| Finished | Jul 27 08:45:34 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-d0341a54-57e5-400a-ac98-09f9606864db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708071329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1708071329 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3673664242 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 136819825544 ps |
| CPU time | 2352.25 seconds |
| Started | Jul 27 08:44:12 PM PDT 24 |
| Finished | Jul 27 09:23:24 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-2d5a36a4-4c2e-4340-b21a-919bce5c1492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673664242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3673664242 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.977038961 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 823935646 ps |
| CPU time | 35.21 seconds |
| Started | Jul 27 08:44:09 PM PDT 24 |
| Finished | Jul 27 08:44:44 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-d5696206-0d8a-4335-9341-1f990a84c3d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977038961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .977038961 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.1529548179 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 126017479 ps |
| CPU time | 7.78 seconds |
| Started | Jul 27 08:44:11 PM PDT 24 |
| Finished | Jul 27 08:44:19 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-3963f3eb-dc1a-490d-9caf-5275b3f28690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529548179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1529548179 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1979321779 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1246032815 ps |
| CPU time | 50.57 seconds |
| Started | Jul 27 08:44:18 PM PDT 24 |
| Finished | Jul 27 08:45:08 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-aae4f4cd-b552-43cc-812f-86fed35e77e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979321779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1979321779 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3502995335 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 112299627031 ps |
| CPU time | 1220.07 seconds |
| Started | Jul 27 08:44:12 PM PDT 24 |
| Finished | Jul 27 09:04:32 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-57caca41-448c-4312-be1b-d691c0d57d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502995335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3502995335 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.204310442 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 18741707291 ps |
| CPU time | 323.26 seconds |
| Started | Jul 27 08:44:12 PM PDT 24 |
| Finished | Jul 27 08:49:36 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-80b70d75-36b6-4c8c-8180-cb7b06808adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204310442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.204310442 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.615503606 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 276959378 ps |
| CPU time | 26.2 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 08:44:45 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-fb04f21e-8128-4c69-a72a-b213d229395f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615503606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.615503606 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1509975794 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 1762323063 ps |
| CPU time | 55.25 seconds |
| Started | Jul 27 08:44:11 PM PDT 24 |
| Finished | Jul 27 08:45:07 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-e395c06c-6008-4396-aae5-c73735be640a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509975794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1509975794 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.609728062 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 53685058 ps |
| CPU time | 7.1 seconds |
| Started | Jul 27 08:44:02 PM PDT 24 |
| Finished | Jul 27 08:44:09 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-a7334a3f-56df-4b31-aed0-0c1840d03978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609728062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.609728062 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.4138256886 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 7479370905 ps |
| CPU time | 79.06 seconds |
| Started | Jul 27 08:44:03 PM PDT 24 |
| Finished | Jul 27 08:45:22 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-d2c060d3-d152-4b98-80dd-0448986f66d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138256886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.4138256886 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.4285682695 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 6022344214 ps |
| CPU time | 106.24 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 08:46:05 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-7465c740-d713-4b6d-aee1-9f7011d514de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285682695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.4285682695 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2027802616 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 57143591 ps |
| CPU time | 7.18 seconds |
| Started | Jul 27 08:44:02 PM PDT 24 |
| Finished | Jul 27 08:44:09 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-5c725ef4-a18c-4286-8782-f85ec526d773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027802616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2027802616 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3011321364 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 3111406081 ps |
| CPU time | 242.4 seconds |
| Started | Jul 27 08:44:11 PM PDT 24 |
| Finished | Jul 27 08:48:13 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-cb86852d-013b-4f6e-8a9c-91d7a8a1a070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011321364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3011321364 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3679714347 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 1834540653 ps |
| CPU time | 202.18 seconds |
| Started | Jul 27 08:44:10 PM PDT 24 |
| Finished | Jul 27 08:47:32 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-60ef5b74-ff06-4738-9f22-af117b68a62f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679714347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3679714347 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.1544591697 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 1004225179 ps |
| CPU time | 148.55 seconds |
| Started | Jul 27 08:44:08 PM PDT 24 |
| Finished | Jul 27 08:46:37 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-66ebc77f-a00f-42f6-a859-6ddc51c554a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544591697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.1544591697 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2162033661 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 83984333 ps |
| CPU time | 13.36 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 08:44:32 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-0c0b0ddd-9fb2-4bac-b9ec-bf39d08e2b40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162033661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2162033661 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.263484080 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 3636363786 ps |
| CPU time | 173.63 seconds |
| Started | Jul 27 08:44:16 PM PDT 24 |
| Finished | Jul 27 08:47:10 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-a02861fe-0c61-4eee-a315-d3c3667b46c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263484080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 263484080 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2190643121 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 9678911504 ps |
| CPU time | 169.3 seconds |
| Started | Jul 27 08:44:17 PM PDT 24 |
| Finished | Jul 27 08:47:06 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-5cddd93e-aa7a-4d1c-bd3a-743e10d470df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190643121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2190643121 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.29433839 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 149747617 ps |
| CPU time | 17.2 seconds |
| Started | Jul 27 08:44:25 PM PDT 24 |
| Finished | Jul 27 08:44:42 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-8a0077b1-5f4f-4e09-97ba-0afef24b187e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29433839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr.29433839 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3389912895 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 1345196221 ps |
| CPU time | 47.35 seconds |
| Started | Jul 27 08:44:17 PM PDT 24 |
| Finished | Jul 27 08:45:04 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-3286aeef-be56-4d6b-ae4f-ade2a4696936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389912895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3389912895 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2052450502 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 388954234 ps |
| CPU time | 16.01 seconds |
| Started | Jul 27 08:44:16 PM PDT 24 |
| Finished | Jul 27 08:44:32 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-f147e93d-edb4-4e41-ba62-18a67343fe6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052450502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2052450502 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.1155587268 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 23358982177 ps |
| CPU time | 267.28 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 08:48:46 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-68d22952-9b0a-4e3c-80fd-2b5a0efa79b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155587268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.1155587268 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.4020925413 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 63808204137 ps |
| CPU time | 1069.06 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 09:02:08 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-9a1bb28b-7c62-4333-9178-8327572851b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020925413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.4020925413 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.152321815 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 235742070 ps |
| CPU time | 23.04 seconds |
| Started | Jul 27 08:44:22 PM PDT 24 |
| Finished | Jul 27 08:44:45 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-678f227b-f3a7-4dad-b4bb-0fe7e76cc96c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152321815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.152321815 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.496758487 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 323283731 ps |
| CPU time | 26.1 seconds |
| Started | Jul 27 08:44:16 PM PDT 24 |
| Finished | Jul 27 08:44:42 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-2b199b07-fc66-4d3e-9600-8268f59af55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496758487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.496758487 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.24469926 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 44879154 ps |
| CPU time | 6.54 seconds |
| Started | Jul 27 08:44:17 PM PDT 24 |
| Finished | Jul 27 08:44:24 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-f36653b4-1f47-4615-ab79-a0798c5dd104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24469926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.24469926 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3110812061 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 7721161578 ps |
| CPU time | 84.84 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 08:45:44 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-cc56876c-b583-4aa0-b109-04882e36c4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110812061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3110812061 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.2302651574 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 3813141626 ps |
| CPU time | 66.39 seconds |
| Started | Jul 27 08:44:21 PM PDT 24 |
| Finished | Jul 27 08:45:28 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-f187ca47-b0dc-445b-aff6-9a4c1d689ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302651574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.2302651574 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3640921437 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 58357249 ps |
| CPU time | 6.54 seconds |
| Started | Jul 27 08:44:19 PM PDT 24 |
| Finished | Jul 27 08:44:26 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-977276a0-d178-460d-b67e-f4f6548c6d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640921437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.3640921437 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.4069283559 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 7378095959 ps |
| CPU time | 291.23 seconds |
| Started | Jul 27 08:44:28 PM PDT 24 |
| Finished | Jul 27 08:49:19 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-9b93b053-7503-4a39-9e56-4f631c608a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069283559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.4069283559 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.2436840878 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 5220121523 ps |
| CPU time | 174.8 seconds |
| Started | Jul 27 08:44:30 PM PDT 24 |
| Finished | Jul 27 08:47:25 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-b49c4332-4335-4e1f-bce2-da13bb9de34e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436840878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.2436840878 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.4227876972 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 77380981 ps |
| CPU time | 19.12 seconds |
| Started | Jul 27 08:44:25 PM PDT 24 |
| Finished | Jul 27 08:44:45 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-62dc7482-2b9f-4763-a19f-41c1edaad950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227876972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.4227876972 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2298631692 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 1226700770 ps |
| CPU time | 53.04 seconds |
| Started | Jul 27 08:44:17 PM PDT 24 |
| Finished | Jul 27 08:45:10 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-57bf4218-4454-40ed-96af-64c3c9814c92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298631692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2298631692 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1077634997 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 7076111775 ps |
| CPU time | 502.53 seconds |
| Started | Jul 27 08:30:12 PM PDT 24 |
| Finished | Jul 27 08:38:34 PM PDT 24 |
| Peak memory | 637308 kb |
| Host | smart-5c3f43b9-8f09-40de-a384-56f3f19e1f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077634997 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1077634997 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.1707473763 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 6480136510 ps |
| CPU time | 704.07 seconds |
| Started | Jul 27 08:30:12 PM PDT 24 |
| Finished | Jul 27 08:41:56 PM PDT 24 |
| Peak memory | 598788 kb |
| Host | smart-c1ffc4a0-3aef-44ea-ad57-20961e3a8a25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707473763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1707473763 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1420949838 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 16012753622 ps |
| CPU time | 1952.06 seconds |
| Started | Jul 27 08:29:38 PM PDT 24 |
| Finished | Jul 27 09:02:10 PM PDT 24 |
| Peak memory | 592916 kb |
| Host | smart-924f2de5-a0ba-459d-af37-1a73e3dea982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420949838 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1420949838 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.206114014 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 604281404 ps |
| CPU time | 78.07 seconds |
| Started | Jul 27 08:29:49 PM PDT 24 |
| Finished | Jul 27 08:31:07 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-4627432d-02f7-4774-b57c-c8739bb8b23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206114014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.206114014 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.1346831173 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 4284328172 ps |
| CPU time | 79.36 seconds |
| Started | Jul 27 08:29:47 PM PDT 24 |
| Finished | Jul 27 08:31:07 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-e1bcbdea-2e01-4f74-858c-d1bb5af9ca93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346831173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.1346831173 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1646026688 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 1400924777 ps |
| CPU time | 67.95 seconds |
| Started | Jul 27 08:29:56 PM PDT 24 |
| Finished | Jul 27 08:31:04 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-0f2ed3d6-ab72-4161-9ab5-4dfeb9f9c3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646026688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1646026688 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.654980001 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 2287741420 ps |
| CPU time | 97.14 seconds |
| Started | Jul 27 08:29:56 PM PDT 24 |
| Finished | Jul 27 08:31:33 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-509caf21-0732-4d92-98c9-98d8e2d9027f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654980001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.654980001 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3964469777 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 1520015357 ps |
| CPU time | 64.17 seconds |
| Started | Jul 27 08:29:47 PM PDT 24 |
| Finished | Jul 27 08:30:51 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-c7058439-7a04-4dc5-8608-8f44cf3429e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964469777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3964469777 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2454291006 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 34941627362 ps |
| CPU time | 372.02 seconds |
| Started | Jul 27 08:29:46 PM PDT 24 |
| Finished | Jul 27 08:35:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-caff64e4-3c3c-4cde-a993-ce9bfc914cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454291006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2454291006 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2395815087 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 54707400530 ps |
| CPU time | 907.12 seconds |
| Started | Jul 27 08:29:48 PM PDT 24 |
| Finished | Jul 27 08:44:55 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-d3b99dca-799f-4bd0-8b19-6a36329c9846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395815087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2395815087 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1131594727 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 394459153 ps |
| CPU time | 38.19 seconds |
| Started | Jul 27 08:29:49 PM PDT 24 |
| Finished | Jul 27 08:30:27 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-a148dae0-0f3e-42c5-aa73-d36da69011ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131594727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.1131594727 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.3823748147 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1471058505 ps |
| CPU time | 52.55 seconds |
| Started | Jul 27 08:29:49 PM PDT 24 |
| Finished | Jul 27 08:30:42 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-986d1869-8a47-4948-9b97-9704d44aef1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823748147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3823748147 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.2385273077 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 48188397 ps |
| CPU time | 7.14 seconds |
| Started | Jul 27 08:29:40 PM PDT 24 |
| Finished | Jul 27 08:29:47 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-17d3c6df-fd00-4718-9efb-c108dfa43c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385273077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2385273077 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1615302732 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 8767408492 ps |
| CPU time | 91.03 seconds |
| Started | Jul 27 08:29:46 PM PDT 24 |
| Finished | Jul 27 08:31:18 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-39a99a10-1903-4f51-a62d-4720f577bef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615302732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1615302732 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4192940036 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 4502419336 ps |
| CPU time | 80.5 seconds |
| Started | Jul 27 08:29:55 PM PDT 24 |
| Finished | Jul 27 08:31:16 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-058c448d-c87a-415f-acaa-42b42f0ad158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192940036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4192940036 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.393196332 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 37872972 ps |
| CPU time | 5.95 seconds |
| Started | Jul 27 08:29:36 PM PDT 24 |
| Finished | Jul 27 08:29:42 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-f31e3f21-a24b-42ec-afba-8273f2ca9138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393196332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 393196332 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.204363874 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 11103391069 ps |
| CPU time | 554.79 seconds |
| Started | Jul 27 08:29:56 PM PDT 24 |
| Finished | Jul 27 08:39:11 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-346b0224-cb6a-4ca2-ad9b-da12783e539a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204363874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.204363874 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.3607926399 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 9509644415 ps |
| CPU time | 285.72 seconds |
| Started | Jul 27 08:30:03 PM PDT 24 |
| Finished | Jul 27 08:34:49 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-076bd770-9856-4803-a843-3f1c031bb2c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607926399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3607926399 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2037691363 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 7286147 ps |
| CPU time | 18.48 seconds |
| Started | Jul 27 08:30:10 PM PDT 24 |
| Finished | Jul 27 08:30:29 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-f9628239-0840-4961-a15f-62a7aafb08e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037691363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.2037691363 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.80522171 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 967511158 ps |
| CPU time | 188.21 seconds |
| Started | Jul 27 08:30:11 PM PDT 24 |
| Finished | Jul 27 08:33:19 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-74545681-a249-4bf4-ad66-90598d6a977c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80522171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_reset_error.80522171 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3063102691 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 22523117 ps |
| CPU time | 6.06 seconds |
| Started | Jul 27 08:29:56 PM PDT 24 |
| Finished | Jul 27 08:30:02 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-b1cbfc06-fea9-4bd5-9d5f-42ace79ad367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063102691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3063102691 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3419907836 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 3205701664 ps |
| CPU time | 152.1 seconds |
| Started | Jul 27 08:44:29 PM PDT 24 |
| Finished | Jul 27 08:47:01 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e9efb119-4a95-4b34-9bb2-09a3d13860cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419907836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3419907836 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2665208087 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 81829864674 ps |
| CPU time | 1332.86 seconds |
| Started | Jul 27 08:44:29 PM PDT 24 |
| Finished | Jul 27 09:06:42 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ba5afe9b-b045-4d9c-8702-0af3f60e63fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665208087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2665208087 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2256746766 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 346123887 ps |
| CPU time | 42 seconds |
| Started | Jul 27 08:44:35 PM PDT 24 |
| Finished | Jul 27 08:45:17 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-a89d644b-d0db-48e7-97da-deea88135c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256746766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2256746766 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.1154407344 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 589288866 ps |
| CPU time | 47.9 seconds |
| Started | Jul 27 08:44:30 PM PDT 24 |
| Finished | Jul 27 08:45:18 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-922e6c37-cfbc-4388-8229-c12d066ca410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154407344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.1154407344 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.907447611 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 310421901 ps |
| CPU time | 31.47 seconds |
| Started | Jul 27 08:44:26 PM PDT 24 |
| Finished | Jul 27 08:44:58 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-1cc4a627-4e7c-466e-8276-7ecbaa4c6772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907447611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.907447611 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.836187717 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 56280695499 ps |
| CPU time | 578.22 seconds |
| Started | Jul 27 08:44:31 PM PDT 24 |
| Finished | Jul 27 08:54:09 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-45c7dcd9-6ba6-49fd-9499-78b76748e8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836187717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.836187717 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.4204458535 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 62160320908 ps |
| CPU time | 1078.25 seconds |
| Started | Jul 27 08:44:26 PM PDT 24 |
| Finished | Jul 27 09:02:24 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-48d755ad-047a-42ec-8924-37ab9549a937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204458535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.4204458535 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2258345545 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 308473489 ps |
| CPU time | 29.6 seconds |
| Started | Jul 27 08:44:29 PM PDT 24 |
| Finished | Jul 27 08:44:59 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-2367a64e-3ee6-427f-92c6-2ebb2c1557ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258345545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.2258345545 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.340898737 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 427131996 ps |
| CPU time | 34.57 seconds |
| Started | Jul 27 08:44:26 PM PDT 24 |
| Finished | Jul 27 08:45:01 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-982deefe-9e53-4ac0-a98c-3ff3c0e69739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340898737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.340898737 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.2145164542 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 44516232 ps |
| CPU time | 6.52 seconds |
| Started | Jul 27 08:44:27 PM PDT 24 |
| Finished | Jul 27 08:44:34 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b73b8cd0-f29a-4e22-ba84-a85341e41f36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145164542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2145164542 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1693034208 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 5476670957 ps |
| CPU time | 61.03 seconds |
| Started | Jul 27 08:44:26 PM PDT 24 |
| Finished | Jul 27 08:45:27 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-4eb87bb0-ccfb-4444-8bd7-418df2bb2858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693034208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.1693034208 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.224340529 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 6124040402 ps |
| CPU time | 106.99 seconds |
| Started | Jul 27 08:44:26 PM PDT 24 |
| Finished | Jul 27 08:46:13 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-973b79a6-22b9-4286-8f4e-d493a841915f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224340529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.224340529 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.423950108 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 48373888 ps |
| CPU time | 6.8 seconds |
| Started | Jul 27 08:44:25 PM PDT 24 |
| Finished | Jul 27 08:44:32 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-c75c9c75-7dcd-4c9d-a7c6-566bde294593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423950108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays .423950108 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.4130718639 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 4627117420 ps |
| CPU time | 202.49 seconds |
| Started | Jul 27 08:44:36 PM PDT 24 |
| Finished | Jul 27 08:47:59 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-1d1020d9-8c8b-45bb-812b-32ee3e7e3e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130718639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.4130718639 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2041450970 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 4532545381 ps |
| CPU time | 171.9 seconds |
| Started | Jul 27 08:44:36 PM PDT 24 |
| Finished | Jul 27 08:47:28 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-254b997b-ed88-40c4-a4f0-5b6597f25242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041450970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2041450970 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2511435735 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5155495061 ps |
| CPU time | 577.68 seconds |
| Started | Jul 27 08:44:36 PM PDT 24 |
| Finished | Jul 27 08:54:14 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-03f588a6-5a7e-4bdd-bfb8-7002877ef1b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511435735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2511435735 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2769185135 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 77353772 ps |
| CPU time | 38.34 seconds |
| Started | Jul 27 08:44:34 PM PDT 24 |
| Finished | Jul 27 08:45:13 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-f06666cd-f6ef-4aee-8d2f-f85567d36de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769185135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2769185135 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2408679879 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 236286571 ps |
| CPU time | 12.34 seconds |
| Started | Jul 27 08:44:34 PM PDT 24 |
| Finished | Jul 27 08:44:47 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-c841b014-38ba-4448-a68a-d87e9f27dcae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408679879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2408679879 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3432385486 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1173417819 ps |
| CPU time | 94.73 seconds |
| Started | Jul 27 08:44:37 PM PDT 24 |
| Finished | Jul 27 08:46:11 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-22bf0b09-e5d5-4e2c-a5d3-8e1fcfadb644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432385486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3432385486 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.713609762 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 63007265741 ps |
| CPU time | 1193.74 seconds |
| Started | Jul 27 08:44:37 PM PDT 24 |
| Finished | Jul 27 09:04:31 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-0505ae37-5221-4f75-9152-3750aab753a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713609762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d evice_slow_rsp.713609762 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.1978896889 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 1410959836 ps |
| CPU time | 52.03 seconds |
| Started | Jul 27 08:44:42 PM PDT 24 |
| Finished | Jul 27 08:45:35 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-3ea6ad42-4a9d-4580-93ca-d8464ca5fb3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978896889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.1978896889 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.4253727586 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 1613970151 ps |
| CPU time | 60.23 seconds |
| Started | Jul 27 08:44:46 PM PDT 24 |
| Finished | Jul 27 08:45:46 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-1306eea4-75d6-4478-8db3-8de3c5f667bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253727586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.4253727586 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.3804667979 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 1452540185 ps |
| CPU time | 50.95 seconds |
| Started | Jul 27 08:44:40 PM PDT 24 |
| Finished | Jul 27 08:45:31 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-3d831540-f2f7-4e31-b2cc-47d4412b938e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804667979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3804667979 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2106250264 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 17357799516 ps |
| CPU time | 173.25 seconds |
| Started | Jul 27 08:44:37 PM PDT 24 |
| Finished | Jul 27 08:47:30 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-1b97cbdd-1953-4762-a49d-38d4bc9e78df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106250264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2106250264 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2120816165 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 13244107679 ps |
| CPU time | 238.84 seconds |
| Started | Jul 27 08:44:43 PM PDT 24 |
| Finished | Jul 27 08:48:42 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-976d3de4-98ec-4e94-9103-efce2260b92e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120816165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2120816165 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1092388988 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 297686711 ps |
| CPU time | 33.86 seconds |
| Started | Jul 27 08:44:36 PM PDT 24 |
| Finished | Jul 27 08:45:09 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-edabb53b-6c06-4c87-b3e8-bf9471cfee00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092388988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1092388988 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.2503601404 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 2623976670 ps |
| CPU time | 85.47 seconds |
| Started | Jul 27 08:44:40 PM PDT 24 |
| Finished | Jul 27 08:46:06 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-5f1ae68a-837b-4f56-8c34-4fa50d444805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503601404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2503601404 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.795968563 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 202186325 ps |
| CPU time | 9.38 seconds |
| Started | Jul 27 08:44:38 PM PDT 24 |
| Finished | Jul 27 08:44:47 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-24f0308d-7aa3-474a-a3d4-2920ffbc5d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795968563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.795968563 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2382854184 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 9373993274 ps |
| CPU time | 101.21 seconds |
| Started | Jul 27 08:44:36 PM PDT 24 |
| Finished | Jul 27 08:46:17 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-f51d3b57-441f-4bdd-8531-8e1b1e29333a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382854184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2382854184 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.498784598 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 5209425434 ps |
| CPU time | 88.97 seconds |
| Started | Jul 27 08:44:37 PM PDT 24 |
| Finished | Jul 27 08:46:06 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-22ced244-7f43-4789-83c3-02259c649257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498784598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.498784598 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2648450588 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 43750258 ps |
| CPU time | 6.94 seconds |
| Started | Jul 27 08:44:37 PM PDT 24 |
| Finished | Jul 27 08:44:44 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-6da3920f-e38f-4aad-9f15-06c848451ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648450588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2648450588 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.76649543 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2418237788 ps |
| CPU time | 230.22 seconds |
| Started | Jul 27 08:44:49 PM PDT 24 |
| Finished | Jul 27 08:48:39 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-974c48e0-7d7d-4b2f-850e-0a47606af111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76649543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.76649543 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.592552683 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 13513183828 ps |
| CPU time | 477.3 seconds |
| Started | Jul 27 08:44:42 PM PDT 24 |
| Finished | Jul 27 08:52:40 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-33bb5194-1c3f-4593-86b3-22a783c7db76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592552683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.592552683 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1499233524 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 10207580945 ps |
| CPU time | 514.4 seconds |
| Started | Jul 27 08:44:49 PM PDT 24 |
| Finished | Jul 27 08:53:24 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a4377a81-df67-4c81-a385-d6ad602c4891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499233524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1499233524 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2541194639 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 19619288393 ps |
| CPU time | 872.82 seconds |
| Started | Jul 27 08:44:43 PM PDT 24 |
| Finished | Jul 27 08:59:16 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-9fcca68d-d9a7-4ad3-bee7-d60ab3774199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541194639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2541194639 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1107826887 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1178964058 ps |
| CPU time | 50.09 seconds |
| Started | Jul 27 08:44:44 PM PDT 24 |
| Finished | Jul 27 08:45:34 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-324b01d6-0aea-450d-81ba-f551922c8d07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107826887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1107826887 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.1389856948 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 3404488725 ps |
| CPU time | 158.99 seconds |
| Started | Jul 27 08:44:51 PM PDT 24 |
| Finished | Jul 27 08:47:30 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-5814c0c7-fbd3-48be-9e47-21d6196e15dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389856948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .1389856948 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4231969909 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 46667510196 ps |
| CPU time | 766.3 seconds |
| Started | Jul 27 08:44:51 PM PDT 24 |
| Finished | Jul 27 08:57:38 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-cc1f6490-cb99-401e-a745-fdb54166b281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231969909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.4231969909 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2457564210 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 369892748 ps |
| CPU time | 17.5 seconds |
| Started | Jul 27 08:44:53 PM PDT 24 |
| Finished | Jul 27 08:45:11 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-c0b9dc2c-54b7-42f9-bab9-230f4e7b273b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457564210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2457564210 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.4111308418 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 971672135 ps |
| CPU time | 38.36 seconds |
| Started | Jul 27 08:44:52 PM PDT 24 |
| Finished | Jul 27 08:45:31 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ac374119-a65f-421e-966d-bc93c1bd5924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111308418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.4111308418 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1062703667 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 2534731254 ps |
| CPU time | 107.56 seconds |
| Started | Jul 27 08:44:43 PM PDT 24 |
| Finished | Jul 27 08:46:30 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-21032e39-ad45-4b80-846b-6569767ff1de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062703667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1062703667 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1129059180 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 34626896210 ps |
| CPU time | 358.24 seconds |
| Started | Jul 27 08:44:45 PM PDT 24 |
| Finished | Jul 27 08:50:44 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4baeffef-daf0-40df-9c0e-1e7fb7d833d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129059180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1129059180 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3740613613 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 54618096374 ps |
| CPU time | 945.63 seconds |
| Started | Jul 27 08:44:44 PM PDT 24 |
| Finished | Jul 27 09:00:30 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-9885aea1-82cb-44c6-98b9-bd1e344e8ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740613613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3740613613 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3295629368 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 447583898 ps |
| CPU time | 37.62 seconds |
| Started | Jul 27 08:44:45 PM PDT 24 |
| Finished | Jul 27 08:45:23 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d0f818e0-611a-4bb2-875e-0a2f1074096f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295629368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3295629368 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.197966990 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 517659868 ps |
| CPU time | 38.9 seconds |
| Started | Jul 27 08:44:54 PM PDT 24 |
| Finished | Jul 27 08:45:33 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-8100d01a-a9bf-464e-afbf-563016930da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197966990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.197966990 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.3177796388 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 191233329 ps |
| CPU time | 9.84 seconds |
| Started | Jul 27 08:44:49 PM PDT 24 |
| Finished | Jul 27 08:44:59 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-2e9607bd-56c1-495b-8765-3ae1f929073d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177796388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3177796388 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1708436266 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 8795356685 ps |
| CPU time | 94.06 seconds |
| Started | Jul 27 08:44:45 PM PDT 24 |
| Finished | Jul 27 08:46:20 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-52194233-b123-4bbb-b05b-0342b9bbdcc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708436266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1708436266 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1321389766 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 6515338352 ps |
| CPU time | 104.33 seconds |
| Started | Jul 27 08:44:45 PM PDT 24 |
| Finished | Jul 27 08:46:29 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-2ba7af2a-8c16-4151-b36b-cdcc85c1607e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321389766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1321389766 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.893261200 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 51179431 ps |
| CPU time | 7.13 seconds |
| Started | Jul 27 08:44:46 PM PDT 24 |
| Finished | Jul 27 08:44:53 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-f6122f7c-5df4-4992-b27f-0fed35805e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893261200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .893261200 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.1741038804 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 10148679048 ps |
| CPU time | 350.34 seconds |
| Started | Jul 27 08:44:52 PM PDT 24 |
| Finished | Jul 27 08:50:42 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-25b3f245-e965-4085-bc84-f3d8784856e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741038804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.1741038804 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2165583677 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 5033978984 ps |
| CPU time | 170.83 seconds |
| Started | Jul 27 08:44:54 PM PDT 24 |
| Finished | Jul 27 08:47:44 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-1b4fb770-aabc-432e-9a96-beeac45656c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165583677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2165583677 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.128474494 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 8335723710 ps |
| CPU time | 517.29 seconds |
| Started | Jul 27 08:44:53 PM PDT 24 |
| Finished | Jul 27 08:53:30 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-cc1bd6c8-a94c-42b7-a02a-08d90a2e62ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128474494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_ with_rand_reset.128474494 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.1800764646 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 262612590 ps |
| CPU time | 60.29 seconds |
| Started | Jul 27 08:44:53 PM PDT 24 |
| Finished | Jul 27 08:45:53 PM PDT 24 |
| Peak memory | 576260 kb |
| Host | smart-060ea190-245d-4e12-9809-f05ab0177e2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800764646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.1800764646 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2244328280 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 275613829 ps |
| CPU time | 34.75 seconds |
| Started | Jul 27 08:44:54 PM PDT 24 |
| Finished | Jul 27 08:45:29 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-24a5e019-148b-4d52-a209-40774029af96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244328280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2244328280 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.460715206 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 457832537 ps |
| CPU time | 20.7 seconds |
| Started | Jul 27 08:45:00 PM PDT 24 |
| Finished | Jul 27 08:45:20 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-b5962f5c-4b67-4d8d-854c-02fd8887b6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460715206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device. 460715206 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.773035612 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 81274032920 ps |
| CPU time | 1404.43 seconds |
| Started | Jul 27 08:45:01 PM PDT 24 |
| Finished | Jul 27 09:08:26 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-27953c75-8021-4a57-a599-84f0b27cccb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773035612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_d evice_slow_rsp.773035612 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.769947149 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 17193090 ps |
| CPU time | 5.64 seconds |
| Started | Jul 27 08:45:01 PM PDT 24 |
| Finished | Jul 27 08:45:06 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-d94e2513-7a69-4114-9189-dcb8a413ac86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769947149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .769947149 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.1241098680 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 2181655379 ps |
| CPU time | 70.65 seconds |
| Started | Jul 27 08:45:03 PM PDT 24 |
| Finished | Jul 27 08:46:14 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-9b74eb54-b017-4354-8ef4-6fe6c51bd2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241098680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1241098680 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.298959832 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 176603362 ps |
| CPU time | 9.97 seconds |
| Started | Jul 27 08:45:02 PM PDT 24 |
| Finished | Jul 27 08:45:12 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-f023d4da-9c77-4872-95ee-94076a27e0c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298959832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.298959832 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1988839569 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 2447756891 ps |
| CPU time | 26.21 seconds |
| Started | Jul 27 08:45:03 PM PDT 24 |
| Finished | Jul 27 08:45:29 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-fdfae5b1-6ea6-4aa5-b702-d3f05b12ada1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988839569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1988839569 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.3538152895 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 42930814354 ps |
| CPU time | 762.87 seconds |
| Started | Jul 27 08:45:03 PM PDT 24 |
| Finished | Jul 27 08:57:46 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-82d53453-02f8-436f-a045-d6566e80811c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538152895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.3538152895 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2798420731 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 153891992 ps |
| CPU time | 17.21 seconds |
| Started | Jul 27 08:45:00 PM PDT 24 |
| Finished | Jul 27 08:45:17 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-12f29e8d-1096-45ff-a6f8-9c0d1655f37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798420731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.2798420731 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2498017844 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 1432061615 ps |
| CPU time | 42.94 seconds |
| Started | Jul 27 08:44:59 PM PDT 24 |
| Finished | Jul 27 08:45:42 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-88dff3d0-23f7-475a-ad1a-3598ee8ed91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498017844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2498017844 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.523290000 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 206172721 ps |
| CPU time | 9.6 seconds |
| Started | Jul 27 08:44:54 PM PDT 24 |
| Finished | Jul 27 08:45:03 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-fda87446-492e-4f98-91cc-dab564ec4de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523290000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.523290000 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.196269746 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 9511686303 ps |
| CPU time | 101.04 seconds |
| Started | Jul 27 08:45:00 PM PDT 24 |
| Finished | Jul 27 08:46:41 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-9078042e-c049-4e38-9f02-d6bbbb8e2c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196269746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.196269746 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2140531899 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 4993804823 ps |
| CPU time | 90.6 seconds |
| Started | Jul 27 08:45:00 PM PDT 24 |
| Finished | Jul 27 08:46:31 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-290a595f-4b85-47a6-bebd-5d4557d90a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140531899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2140531899 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.184619746 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 41821974 ps |
| CPU time | 6.7 seconds |
| Started | Jul 27 08:44:52 PM PDT 24 |
| Finished | Jul 27 08:44:59 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-354023c4-ca8b-4788-9c90-43c11725d2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184619746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .184619746 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3395684224 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 2603508091 ps |
| CPU time | 215.01 seconds |
| Started | Jul 27 08:45:03 PM PDT 24 |
| Finished | Jul 27 08:48:38 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-6a3c8f8e-87da-40de-94ee-431393e4fb18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395684224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3395684224 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.4221572514 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 3506506365 ps |
| CPU time | 269.1 seconds |
| Started | Jul 27 08:45:01 PM PDT 24 |
| Finished | Jul 27 08:49:30 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-2b90f68a-81bb-4f97-9a33-518457b989a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221572514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.4221572514 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3900609663 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 5875431309 ps |
| CPU time | 398.03 seconds |
| Started | Jul 27 08:45:04 PM PDT 24 |
| Finished | Jul 27 08:51:42 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-2f7b1c4d-08c5-4060-bca4-e55fd123706a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900609663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3900609663 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3022864647 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 2757996269 ps |
| CPU time | 251.3 seconds |
| Started | Jul 27 08:45:01 PM PDT 24 |
| Finished | Jul 27 08:49:13 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-045e85b6-43c3-4f0a-b73b-5fcc57d0123b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022864647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3022864647 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.32174526 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 318956131 ps |
| CPU time | 39.44 seconds |
| Started | Jul 27 08:44:59 PM PDT 24 |
| Finished | Jul 27 08:45:39 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-38f65205-76b7-4506-b56d-92b341232345 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32174526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.32174526 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.930611247 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2419889245 ps |
| CPU time | 113.71 seconds |
| Started | Jul 27 08:45:08 PM PDT 24 |
| Finished | Jul 27 08:47:01 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-4bb72854-7b1e-49c8-9f13-62f8e8b3ac9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930611247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device. 930611247 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1976095162 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 25773559972 ps |
| CPU time | 451.9 seconds |
| Started | Jul 27 08:45:10 PM PDT 24 |
| Finished | Jul 27 08:52:43 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-35a97301-b9ae-4ad6-b955-c9a63e9acba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976095162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.1976095162 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2821826379 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 223820452 ps |
| CPU time | 11.65 seconds |
| Started | Jul 27 08:45:08 PM PDT 24 |
| Finished | Jul 27 08:45:20 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b20cd0d7-a2d0-4a43-b9d7-f8b06603bb61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821826379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2821826379 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.1004493426 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 163115762 ps |
| CPU time | 14.29 seconds |
| Started | Jul 27 08:45:14 PM PDT 24 |
| Finished | Jul 27 08:45:29 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-b6bd645f-7411-4e11-8503-52a259fda6c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004493426 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.1004493426 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.628892580 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 1099564509 ps |
| CPU time | 47.96 seconds |
| Started | Jul 27 08:45:08 PM PDT 24 |
| Finished | Jul 27 08:45:56 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-9ba5eb9f-c6dd-4f9a-8169-692c3926a0e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628892580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.628892580 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1955212239 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 20387774528 ps |
| CPU time | 205.97 seconds |
| Started | Jul 27 08:45:12 PM PDT 24 |
| Finished | Jul 27 08:48:38 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-37cd1be8-5252-48b3-a719-de139149b5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955212239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1955212239 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.2328626968 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 22601855093 ps |
| CPU time | 406.78 seconds |
| Started | Jul 27 08:45:14 PM PDT 24 |
| Finished | Jul 27 08:52:01 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-49f7582f-5309-4fdc-ab71-01113e3b2ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328626968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.2328626968 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.3751391272 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 588391323 ps |
| CPU time | 56.67 seconds |
| Started | Jul 27 08:45:09 PM PDT 24 |
| Finished | Jul 27 08:46:06 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-f9409665-2e09-4b59-8945-edae85020877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751391272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.3751391272 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.3623850669 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 2135510378 ps |
| CPU time | 61.13 seconds |
| Started | Jul 27 08:45:09 PM PDT 24 |
| Finished | Jul 27 08:46:10 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-73804352-d97f-4c3f-af0f-50cf72643143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623850669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3623850669 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1141516904 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 50632613 ps |
| CPU time | 6.8 seconds |
| Started | Jul 27 08:44:59 PM PDT 24 |
| Finished | Jul 27 08:45:06 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-27d4a6c7-92f5-437b-a0b4-d32a034a1fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141516904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1141516904 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2093161959 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 7563436371 ps |
| CPU time | 78.22 seconds |
| Started | Jul 27 08:45:01 PM PDT 24 |
| Finished | Jul 27 08:46:19 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-24c89043-1219-4e51-980b-ea7c4833f814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093161959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2093161959 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.4099055246 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 5709118008 ps |
| CPU time | 94.45 seconds |
| Started | Jul 27 08:45:14 PM PDT 24 |
| Finished | Jul 27 08:46:49 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-7fc9862a-f460-4563-a31d-3b55b5136d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099055246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.4099055246 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1743071638 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 56396028 ps |
| CPU time | 7.31 seconds |
| Started | Jul 27 08:45:00 PM PDT 24 |
| Finished | Jul 27 08:45:07 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-f1292749-accf-472f-99de-802e5b825ab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743071638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1743071638 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2444377516 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 3650847051 ps |
| CPU time | 325 seconds |
| Started | Jul 27 08:45:11 PM PDT 24 |
| Finished | Jul 27 08:50:37 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-cdb9dc57-7021-479a-a6e0-4f914f1c3409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444377516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2444377516 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.884586365 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 593543282 ps |
| CPU time | 44.78 seconds |
| Started | Jul 27 08:45:09 PM PDT 24 |
| Finished | Jul 27 08:45:54 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-57810f99-94c2-4dbf-aaf1-0a5af7709770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884586365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.884586365 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.4224303040 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 4112954596 ps |
| CPU time | 474.21 seconds |
| Started | Jul 27 08:45:08 PM PDT 24 |
| Finished | Jul 27 08:53:02 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-11001c80-4698-4dae-bc66-8d8d092599bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224303040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.4224303040 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.2829827990 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 1275635407 ps |
| CPU time | 55.93 seconds |
| Started | Jul 27 08:45:07 PM PDT 24 |
| Finished | Jul 27 08:46:03 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-d8b13925-6095-4037-b453-c83312729f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829827990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2829827990 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.8415532 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 102417671 ps |
| CPU time | 12.3 seconds |
| Started | Jul 27 08:45:16 PM PDT 24 |
| Finished | Jul 27 08:45:29 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-850d4608-05c5-4759-bed1-b36427cf6b6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8415532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device.8415532 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3403743337 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 87390605668 ps |
| CPU time | 1434.16 seconds |
| Started | Jul 27 08:45:21 PM PDT 24 |
| Finished | Jul 27 09:09:15 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-0a8101a2-aa34-421b-8cb0-1d82b7c6a3ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403743337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3403743337 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.4143570721 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 940426313 ps |
| CPU time | 41.36 seconds |
| Started | Jul 27 08:45:24 PM PDT 24 |
| Finished | Jul 27 08:46:06 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6bd02ddd-8857-4ba8-af35-a76bfad6c4bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143570721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.4143570721 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2315424055 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 355086979 ps |
| CPU time | 29.47 seconds |
| Started | Jul 27 08:45:16 PM PDT 24 |
| Finished | Jul 27 08:45:46 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-33b59600-4ff1-4a32-8c04-e748f314d25f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315424055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2315424055 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.1417875804 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 1783054587 ps |
| CPU time | 69.14 seconds |
| Started | Jul 27 08:45:18 PM PDT 24 |
| Finished | Jul 27 08:46:27 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-985abe91-705a-4766-90d8-9ce10fc2a888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417875804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.1417875804 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2611542090 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 21886049037 ps |
| CPU time | 226.71 seconds |
| Started | Jul 27 08:45:17 PM PDT 24 |
| Finished | Jul 27 08:49:04 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-6ae92b88-556c-4254-937a-f48f45532046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611542090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2611542090 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.2251873102 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 7554422670 ps |
| CPU time | 129.86 seconds |
| Started | Jul 27 08:45:18 PM PDT 24 |
| Finished | Jul 27 08:47:28 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-6eec9a65-1409-4797-94d0-2453e1913ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251873102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.2251873102 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3406217687 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 376472154 ps |
| CPU time | 31.17 seconds |
| Started | Jul 27 08:45:16 PM PDT 24 |
| Finished | Jul 27 08:45:48 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-96ce88c1-e934-44e5-ad68-a489807459ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406217687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3406217687 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.599541735 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 1823502144 ps |
| CPU time | 56.46 seconds |
| Started | Jul 27 08:45:16 PM PDT 24 |
| Finished | Jul 27 08:46:12 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-d3ac231b-f550-4438-8b05-ce82ca8d70ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599541735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.599541735 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.2462158727 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 203666890 ps |
| CPU time | 9.23 seconds |
| Started | Jul 27 08:45:09 PM PDT 24 |
| Finished | Jul 27 08:45:18 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-d9802a67-61d4-4e41-8be1-4f9c194af812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462158727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2462158727 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2365673710 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 6466295614 ps |
| CPU time | 64.34 seconds |
| Started | Jul 27 08:45:17 PM PDT 24 |
| Finished | Jul 27 08:46:22 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-2e5fdedd-9d89-4eeb-b95a-686d7671c1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365673710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2365673710 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1576439440 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 5054405160 ps |
| CPU time | 87.09 seconds |
| Started | Jul 27 08:45:21 PM PDT 24 |
| Finished | Jul 27 08:46:48 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-7048ec13-e503-46e0-b8e0-8d3142058756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576439440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1576439440 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.273319917 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 45818296 ps |
| CPU time | 6.75 seconds |
| Started | Jul 27 08:45:17 PM PDT 24 |
| Finished | Jul 27 08:45:24 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5156c523-52cd-4fd9-8e97-d760b894e43e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273319917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays .273319917 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3519962962 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 5015551600 ps |
| CPU time | 474.45 seconds |
| Started | Jul 27 08:45:25 PM PDT 24 |
| Finished | Jul 27 08:53:19 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-5798c5ae-f84a-4621-a198-0d533fa8116d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519962962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3519962962 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.594216234 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 208243540 ps |
| CPU time | 125.71 seconds |
| Started | Jul 27 08:45:24 PM PDT 24 |
| Finished | Jul 27 08:47:30 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-83cef4cb-8868-46dc-8bb5-4abdb0661c3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594216234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.594216234 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3156571975 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 1359708130 ps |
| CPU time | 70.26 seconds |
| Started | Jul 27 08:45:25 PM PDT 24 |
| Finished | Jul 27 08:46:35 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-c7a0277c-e8a1-4d7f-81dc-69e848ba6eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156571975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.3156571975 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2873756048 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 1245336035 ps |
| CPU time | 56.84 seconds |
| Started | Jul 27 08:45:27 PM PDT 24 |
| Finished | Jul 27 08:46:24 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-b502d6ef-0e88-45bd-a879-87b9807bb880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873756048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2873756048 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.305925127 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 977466446 ps |
| CPU time | 79.21 seconds |
| Started | Jul 27 08:45:36 PM PDT 24 |
| Finished | Jul 27 08:46:56 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-caa654e7-2b11-4922-8e3f-88bd520297d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305925127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device. 305925127 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.4136349325 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 138885982627 ps |
| CPU time | 2279.34 seconds |
| Started | Jul 27 08:45:36 PM PDT 24 |
| Finished | Jul 27 09:23:36 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ca0af72c-b00f-4b4e-806f-66b401deb051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136349325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.4136349325 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2712845340 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 275494057 ps |
| CPU time | 28.91 seconds |
| Started | Jul 27 08:45:36 PM PDT 24 |
| Finished | Jul 27 08:46:05 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-84f3622b-5721-4244-a4c0-4b285da45a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712845340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2712845340 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.728623803 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 198731816 ps |
| CPU time | 17.84 seconds |
| Started | Jul 27 08:45:34 PM PDT 24 |
| Finished | Jul 27 08:45:52 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-4b66ad4e-5e6c-41e4-a32b-6497f377fc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728623803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.728623803 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2213527097 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 230776120 ps |
| CPU time | 20.19 seconds |
| Started | Jul 27 08:45:23 PM PDT 24 |
| Finished | Jul 27 08:45:43 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-2f3f6863-cc76-4e72-aab5-eda031e38c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213527097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2213527097 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3140728206 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 37664327510 ps |
| CPU time | 436.44 seconds |
| Started | Jul 27 08:45:26 PM PDT 24 |
| Finished | Jul 27 08:52:43 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-13aeda40-c13a-47c4-9362-6f6813e73332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140728206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3140728206 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3393847443 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 31250543741 ps |
| CPU time | 541.28 seconds |
| Started | Jul 27 08:45:24 PM PDT 24 |
| Finished | Jul 27 08:54:25 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-e457128d-d9ee-4b7b-830a-4626a864ecaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393847443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3393847443 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.441919038 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 264426511 ps |
| CPU time | 27 seconds |
| Started | Jul 27 08:45:26 PM PDT 24 |
| Finished | Jul 27 08:45:53 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-18a20c37-48e3-41e6-9c3d-2bfd8abca785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441919038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.441919038 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.470160458 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 218354274 ps |
| CPU time | 9.69 seconds |
| Started | Jul 27 08:45:34 PM PDT 24 |
| Finished | Jul 27 08:45:44 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-af07ff5d-9399-401e-af22-ec1a611256c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470160458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.470160458 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.1242326782 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 137117189 ps |
| CPU time | 6.78 seconds |
| Started | Jul 27 08:45:26 PM PDT 24 |
| Finished | Jul 27 08:45:33 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0b4e3223-5f86-4e14-b437-8feb02681007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242326782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1242326782 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3406373027 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 10089395834 ps |
| CPU time | 103.84 seconds |
| Started | Jul 27 08:45:26 PM PDT 24 |
| Finished | Jul 27 08:47:10 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-71bb1b11-bab1-4092-841f-521630479381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406373027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.3406373027 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3401633932 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 5639265276 ps |
| CPU time | 95.87 seconds |
| Started | Jul 27 08:45:27 PM PDT 24 |
| Finished | Jul 27 08:47:03 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8683cc46-a7bc-49c3-b4ce-771c2fd91cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401633932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3401633932 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1929638588 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 50085989 ps |
| CPU time | 6.56 seconds |
| Started | Jul 27 08:45:24 PM PDT 24 |
| Finished | Jul 27 08:45:31 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-94188e22-1d38-46fa-a5ba-26b2384d4312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929638588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.1929638588 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.4247051227 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2307365365 ps |
| CPU time | 231.79 seconds |
| Started | Jul 27 08:45:37 PM PDT 24 |
| Finished | Jul 27 08:49:29 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-997ae359-f23c-4c7a-8938-48721aa57282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247051227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.4247051227 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.2631639223 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 14560752602 ps |
| CPU time | 527.8 seconds |
| Started | Jul 27 08:45:34 PM PDT 24 |
| Finished | Jul 27 08:54:22 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-725e286f-c901-4504-941c-835f48b6158a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631639223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.2631639223 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3337700138 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 5439950769 ps |
| CPU time | 256.16 seconds |
| Started | Jul 27 08:45:35 PM PDT 24 |
| Finished | Jul 27 08:49:51 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-4cb3549d-ba2f-41a3-aa81-800ba876c6f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337700138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.3337700138 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3611447729 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 3750005620 ps |
| CPU time | 184.45 seconds |
| Started | Jul 27 08:45:32 PM PDT 24 |
| Finished | Jul 27 08:48:37 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-96cf9309-dd2e-4f87-bc5a-215bd5af8d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611447729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.3611447729 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1756461642 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 1226209369 ps |
| CPU time | 54.79 seconds |
| Started | Jul 27 08:45:35 PM PDT 24 |
| Finished | Jul 27 08:46:29 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-491f8a68-d11c-406d-adda-c2e5d908a1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756461642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1756461642 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1957370249 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 2019609579 ps |
| CPU time | 82.13 seconds |
| Started | Jul 27 08:45:47 PM PDT 24 |
| Finished | Jul 27 08:47:10 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-5ca1eb50-4f72-4680-8aa2-e8586b3f70d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957370249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1957370249 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3168600741 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 59446866639 ps |
| CPU time | 1070.3 seconds |
| Started | Jul 27 08:45:43 PM PDT 24 |
| Finished | Jul 27 09:03:33 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-d10e3217-112c-4954-a5c9-d618b1543d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168600741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3168600741 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2504899658 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 1167227247 ps |
| CPU time | 47.59 seconds |
| Started | Jul 27 08:45:44 PM PDT 24 |
| Finished | Jul 27 08:46:31 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-69656721-4c41-4f49-bbb0-4ed90c9040b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504899658 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2504899658 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3099431733 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 139087581 ps |
| CPU time | 7.93 seconds |
| Started | Jul 27 08:45:42 PM PDT 24 |
| Finished | Jul 27 08:45:50 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-43a218fc-94c1-409f-b27b-1f0b649c7379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099431733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3099431733 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.3979484985 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 401441929 ps |
| CPU time | 17.24 seconds |
| Started | Jul 27 08:45:41 PM PDT 24 |
| Finished | Jul 27 08:45:58 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-15610999-ac4e-424d-923a-692b21185f2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979484985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3979484985 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.2360418952 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 18920589088 ps |
| CPU time | 196.65 seconds |
| Started | Jul 27 08:45:42 PM PDT 24 |
| Finished | Jul 27 08:48:59 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-36f8be79-d5d2-4a2d-8cd1-da0fb935f1f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360418952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2360418952 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3893184216 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 49594583295 ps |
| CPU time | 856.45 seconds |
| Started | Jul 27 08:45:46 PM PDT 24 |
| Finished | Jul 27 09:00:03 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-d0e4392c-afb6-45ac-9336-a9e03f58b8f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893184216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3893184216 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3233862932 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 540480440 ps |
| CPU time | 45.25 seconds |
| Started | Jul 27 08:45:44 PM PDT 24 |
| Finished | Jul 27 08:46:30 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-c24d2dd6-e4b4-4233-8a7e-e90f758f34d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233862932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3233862932 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1100695999 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 1556817641 ps |
| CPU time | 42.6 seconds |
| Started | Jul 27 08:45:45 PM PDT 24 |
| Finished | Jul 27 08:46:27 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-aca1a4c9-9182-4736-b934-c64e3a65614a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100695999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1100695999 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3829821727 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 41225673 ps |
| CPU time | 6.1 seconds |
| Started | Jul 27 08:45:35 PM PDT 24 |
| Finished | Jul 27 08:45:41 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-3e895042-ddb9-4716-acb8-f2e9ffabca2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829821727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3829821727 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3078656543 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 7575428171 ps |
| CPU time | 86.28 seconds |
| Started | Jul 27 08:45:35 PM PDT 24 |
| Finished | Jul 27 08:47:01 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-c69a52cb-f103-4f43-b1a5-943a5d64631c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078656543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3078656543 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.441080924 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 4609314824 ps |
| CPU time | 82.72 seconds |
| Started | Jul 27 08:45:33 PM PDT 24 |
| Finished | Jul 27 08:46:56 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-84f0fbc0-9db9-4458-b2f5-a3a68f0d66eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441080924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.441080924 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4206563310 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 62369225 ps |
| CPU time | 7.89 seconds |
| Started | Jul 27 08:45:35 PM PDT 24 |
| Finished | Jul 27 08:45:43 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-f25286ea-aa00-44fc-88fb-b2570e1efdff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206563310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.4206563310 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.2347069768 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 1077959899 ps |
| CPU time | 88.44 seconds |
| Started | Jul 27 08:45:43 PM PDT 24 |
| Finished | Jul 27 08:47:11 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-4f7e7e47-36bd-4623-a7d8-30e7321090d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347069768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2347069768 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2815383910 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 1822592682 ps |
| CPU time | 70.23 seconds |
| Started | Jul 27 08:45:46 PM PDT 24 |
| Finished | Jul 27 08:46:56 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-17da45bd-cb76-4ef2-8091-402d102727f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815383910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2815383910 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3005804268 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 300812204 ps |
| CPU time | 146.92 seconds |
| Started | Jul 27 08:45:47 PM PDT 24 |
| Finished | Jul 27 08:48:14 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-41774145-9bee-40d2-ba97-9adf97254237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005804268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3005804268 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2784144575 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 236671468 ps |
| CPU time | 87.86 seconds |
| Started | Jul 27 08:45:44 PM PDT 24 |
| Finished | Jul 27 08:47:12 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-edbbf91a-9a8c-4748-a69b-70ab3a295c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784144575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2784144575 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3436115690 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 957723993 ps |
| CPU time | 46.35 seconds |
| Started | Jul 27 08:45:46 PM PDT 24 |
| Finished | Jul 27 08:46:33 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-12b19ce8-9d49-4a58-bd10-c1227a5f9b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436115690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3436115690 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1216580441 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1897993161 ps |
| CPU time | 81.16 seconds |
| Started | Jul 27 08:45:55 PM PDT 24 |
| Finished | Jul 27 08:47:16 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-812ae87e-7035-4df0-b000-c6da5094ee4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216580441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1216580441 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.4291226244 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 45658595132 ps |
| CPU time | 790.57 seconds |
| Started | Jul 27 08:45:50 PM PDT 24 |
| Finished | Jul 27 08:59:01 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-6ec95174-ae0a-49f3-bdee-9d94c1880fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291226244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.4291226244 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.4197095661 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 1033918214 ps |
| CPU time | 39.99 seconds |
| Started | Jul 27 08:45:52 PM PDT 24 |
| Finished | Jul 27 08:46:32 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-aacd4e32-de30-4a8e-84c7-164f5d5c4c58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197095661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.4197095661 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3113256558 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 140351703 ps |
| CPU time | 7.94 seconds |
| Started | Jul 27 08:45:54 PM PDT 24 |
| Finished | Jul 27 08:46:02 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-78ead04e-d9d3-4f1b-81a0-a2e94ef3ed33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113256558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3113256558 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2820730626 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 86585434 ps |
| CPU time | 11.74 seconds |
| Started | Jul 27 08:45:50 PM PDT 24 |
| Finished | Jul 27 08:46:02 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-b73a1f16-c639-4c20-9252-2ff07288aa6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820730626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2820730626 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1066893908 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 6267379638 ps |
| CPU time | 63.87 seconds |
| Started | Jul 27 08:45:50 PM PDT 24 |
| Finished | Jul 27 08:46:54 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-c45a0720-9807-4bad-9f8b-4aa3588a22f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066893908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1066893908 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.2966919190 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 27427328049 ps |
| CPU time | 471.57 seconds |
| Started | Jul 27 08:45:53 PM PDT 24 |
| Finished | Jul 27 08:53:45 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-06c19187-f0ca-4882-b62f-f90d7a09f854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966919190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.2966919190 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.254007836 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 197096965 ps |
| CPU time | 19.64 seconds |
| Started | Jul 27 08:45:52 PM PDT 24 |
| Finished | Jul 27 08:46:12 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-d5bfe560-9b28-4984-a4a2-106fcf69ef10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254007836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_dela ys.254007836 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3151268706 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 244393254 ps |
| CPU time | 19.29 seconds |
| Started | Jul 27 08:45:53 PM PDT 24 |
| Finished | Jul 27 08:46:12 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-835cd65b-8dd6-47c4-943e-83406cb639fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151268706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3151268706 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1286913486 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 35686186 ps |
| CPU time | 5.77 seconds |
| Started | Jul 27 08:45:43 PM PDT 24 |
| Finished | Jul 27 08:45:48 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-bf7fca97-d02d-43d0-9c04-d7fc0645628f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286913486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1286913486 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.669138152 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 10261401921 ps |
| CPU time | 108 seconds |
| Started | Jul 27 08:45:50 PM PDT 24 |
| Finished | Jul 27 08:47:38 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-36f629f7-c161-4e07-820d-737adac16cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669138152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.669138152 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3800610741 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 4488369794 ps |
| CPU time | 75.25 seconds |
| Started | Jul 27 08:45:51 PM PDT 24 |
| Finished | Jul 27 08:47:07 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-ee874d21-4708-4043-871c-74d8ab868d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800610741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3800610741 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2154478564 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 36944116 ps |
| CPU time | 6.04 seconds |
| Started | Jul 27 08:45:43 PM PDT 24 |
| Finished | Jul 27 08:45:49 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-d61f445d-1016-461e-a7a9-dbdd9ac816c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154478564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2154478564 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1182560982 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 10069508283 ps |
| CPU time | 343.11 seconds |
| Started | Jul 27 08:45:50 PM PDT 24 |
| Finished | Jul 27 08:51:33 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-cf50d145-6b1a-414e-b0a1-098ab490878e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182560982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1182560982 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.926736772 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 1766138415 ps |
| CPU time | 67.72 seconds |
| Started | Jul 27 08:45:51 PM PDT 24 |
| Finished | Jul 27 08:46:59 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f742181a-acd1-4050-a30e-03ebd1cca982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926736772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.926736772 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.4112384129 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 404990012 ps |
| CPU time | 129.51 seconds |
| Started | Jul 27 08:45:52 PM PDT 24 |
| Finished | Jul 27 08:48:02 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-df3e8bde-86f7-4663-90e1-abe5199625a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112384129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.4112384129 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3102986974 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 165402270 ps |
| CPU time | 23.14 seconds |
| Started | Jul 27 08:45:55 PM PDT 24 |
| Finished | Jul 27 08:46:18 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-4b4b4e78-ace1-47e6-92a2-62ab5863710c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102986974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3102986974 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3245365080 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 482190227 ps |
| CPU time | 22.6 seconds |
| Started | Jul 27 08:45:49 PM PDT 24 |
| Finished | Jul 27 08:46:11 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-0939664b-49e5-45a1-996d-d0f03072ef20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245365080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3245365080 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2787080091 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 2709448314 ps |
| CPU time | 119.39 seconds |
| Started | Jul 27 08:46:10 PM PDT 24 |
| Finished | Jul 27 08:48:09 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-792a46cd-b74e-4f9e-87de-d8ce1785f2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787080091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2787080091 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1764984110 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 136984672852 ps |
| CPU time | 2460.8 seconds |
| Started | Jul 27 08:46:11 PM PDT 24 |
| Finished | Jul 27 09:27:12 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-79cb085c-fd84-464f-9bf0-5da9ade0c0d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764984110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1764984110 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1860594078 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 1217247256 ps |
| CPU time | 57.85 seconds |
| Started | Jul 27 08:46:11 PM PDT 24 |
| Finished | Jul 27 08:47:09 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-263fdb85-703b-4bc2-9d6b-217f3ef93dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860594078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1860594078 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3020139202 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 2428419541 ps |
| CPU time | 79.51 seconds |
| Started | Jul 27 08:46:08 PM PDT 24 |
| Finished | Jul 27 08:47:28 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-bc2a73a8-3136-4f7e-aa1d-68b65c7b61ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020139202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3020139202 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.2350728543 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 745423161 ps |
| CPU time | 28.38 seconds |
| Started | Jul 27 08:46:02 PM PDT 24 |
| Finished | Jul 27 08:46:30 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-3c052168-761c-4660-bcdb-689cb77d45ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350728543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2350728543 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3643636046 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 90024144342 ps |
| CPU time | 934.49 seconds |
| Started | Jul 27 08:45:58 PM PDT 24 |
| Finished | Jul 27 09:01:33 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-31663826-2a9f-453b-90e1-381a236b5d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643636046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3643636046 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1298961796 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 17286320516 ps |
| CPU time | 305.45 seconds |
| Started | Jul 27 08:45:58 PM PDT 24 |
| Finished | Jul 27 08:51:03 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-c94f39be-0a98-4cc0-9aef-69d560ad9aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298961796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1298961796 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1756184756 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 518190134 ps |
| CPU time | 47.19 seconds |
| Started | Jul 27 08:45:58 PM PDT 24 |
| Finished | Jul 27 08:46:45 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-244bb0f9-86cf-4d32-b2a0-66e534c448b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756184756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.1756184756 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.802425248 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 873886767 ps |
| CPU time | 26.67 seconds |
| Started | Jul 27 08:46:10 PM PDT 24 |
| Finished | Jul 27 08:46:37 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-961adb34-4bfd-4dd0-95fc-3da586a875af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802425248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.802425248 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.97101016 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 177340836 ps |
| CPU time | 8.5 seconds |
| Started | Jul 27 08:45:59 PM PDT 24 |
| Finished | Jul 27 08:46:08 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c1d90758-bd02-4fcb-9be1-16d1b9ae9793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97101016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.97101016 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1401598748 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 5043750086 ps |
| CPU time | 53.83 seconds |
| Started | Jul 27 08:45:57 PM PDT 24 |
| Finished | Jul 27 08:46:51 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-ee548695-bb7f-423a-be23-c1fbf3234b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401598748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1401598748 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3842741915 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 5605221751 ps |
| CPU time | 93.66 seconds |
| Started | Jul 27 08:45:57 PM PDT 24 |
| Finished | Jul 27 08:47:31 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-e4deb565-add4-4513-8d73-3a31621d0bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842741915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3842741915 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3259051587 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 44184774 ps |
| CPU time | 6.55 seconds |
| Started | Jul 27 08:45:58 PM PDT 24 |
| Finished | Jul 27 08:46:05 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-069cbf8d-eed3-4935-bc96-84904ffe9607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259051587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3259051587 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.2481109737 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 3126774453 ps |
| CPU time | 262.71 seconds |
| Started | Jul 27 08:46:13 PM PDT 24 |
| Finished | Jul 27 08:50:36 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-bb89be05-b45b-471c-8fda-33c66875c264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481109737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.2481109737 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.4173377748 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 11725655091 ps |
| CPU time | 429.89 seconds |
| Started | Jul 27 08:46:10 PM PDT 24 |
| Finished | Jul 27 08:53:20 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-6a13711e-c965-4d2b-bb7d-3284dbaa91fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173377748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.4173377748 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1744396808 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 2323737690 ps |
| CPU time | 106.82 seconds |
| Started | Jul 27 08:46:12 PM PDT 24 |
| Finished | Jul 27 08:47:58 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-75195c6a-095e-4efc-a168-80ddfecac263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744396808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1744396808 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2354975367 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 265452476 ps |
| CPU time | 13.07 seconds |
| Started | Jul 27 08:46:10 PM PDT 24 |
| Finished | Jul 27 08:46:23 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-5b08eb2a-ae11-40a2-adc8-5dc7eb2f038f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354975367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2354975367 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1967822588 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 11520734710 ps |
| CPU time | 1001.38 seconds |
| Started | Jul 27 08:30:44 PM PDT 24 |
| Finished | Jul 27 08:47:25 PM PDT 24 |
| Peak memory | 648828 kb |
| Host | smart-efdf63ca-729c-410a-9288-920c77fd9a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967822588 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.1967822588 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.4273573089 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4829515765 ps |
| CPU time | 362.52 seconds |
| Started | Jul 27 08:30:42 PM PDT 24 |
| Finished | Jul 27 08:36:44 PM PDT 24 |
| Peak memory | 597296 kb |
| Host | smart-f750d2f6-2af9-4634-b8aa-8e666d28486b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273573089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.4273573089 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2314826961 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 14589439853 ps |
| CPU time | 2153.21 seconds |
| Started | Jul 27 08:30:12 PM PDT 24 |
| Finished | Jul 27 09:06:06 PM PDT 24 |
| Peak memory | 593228 kb |
| Host | smart-23258ff7-3a3e-4ff6-814b-3dc4ba1659f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314826961 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2314826961 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.776880085 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3239520665 ps |
| CPU time | 252.91 seconds |
| Started | Jul 27 08:30:12 PM PDT 24 |
| Finished | Jul 27 08:34:26 PM PDT 24 |
| Peak memory | 603420 kb |
| Host | smart-515c0f2f-0b55-40c8-924c-99e5456b5427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776880085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.776880085 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.1080382832 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 884367675 ps |
| CPU time | 39.64 seconds |
| Started | Jul 27 08:30:28 PM PDT 24 |
| Finished | Jul 27 08:31:08 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-00607812-4f37-4631-9ce6-370865c7ccaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080382832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 1080382832 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.437268182 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 67005955460 ps |
| CPU time | 1186.45 seconds |
| Started | Jul 27 08:30:30 PM PDT 24 |
| Finished | Jul 27 08:50:17 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-e20cea1f-d9e3-49fe-82dd-30c24eac3472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437268182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.437268182 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1999127261 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 835698886 ps |
| CPU time | 39.08 seconds |
| Started | Jul 27 08:30:41 PM PDT 24 |
| Finished | Jul 27 08:31:20 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8f588beb-09b8-46c0-b000-9cf59f2a93ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999127261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .1999127261 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.2709822511 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 300797817 ps |
| CPU time | 32.99 seconds |
| Started | Jul 27 08:30:30 PM PDT 24 |
| Finished | Jul 27 08:31:03 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-88c91aca-5fbe-43f5-9806-202220df0aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709822511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2709822511 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.3290546304 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 1638367199 ps |
| CPU time | 66.46 seconds |
| Started | Jul 27 08:30:23 PM PDT 24 |
| Finished | Jul 27 08:31:30 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-8f9e0101-141f-477f-941d-b8b75696a86c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290546304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3290546304 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.596453953 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 85786975031 ps |
| CPU time | 957.92 seconds |
| Started | Jul 27 08:30:20 PM PDT 24 |
| Finished | Jul 27 08:46:18 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-2e95f617-05d6-4e7f-9358-fee016298855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596453953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.596453953 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1906769312 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 14051477729 ps |
| CPU time | 246.9 seconds |
| Started | Jul 27 08:30:28 PM PDT 24 |
| Finished | Jul 27 08:34:35 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-430464d2-dfb4-4cf1-b7da-5cf7c63cc0b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906769312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1906769312 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4256807949 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 434910098 ps |
| CPU time | 46.79 seconds |
| Started | Jul 27 08:30:23 PM PDT 24 |
| Finished | Jul 27 08:31:10 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-6c301112-65a6-40d3-b38a-b54f414e5abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256807949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.4256807949 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.502691099 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 410032182 ps |
| CPU time | 33.82 seconds |
| Started | Jul 27 08:30:29 PM PDT 24 |
| Finished | Jul 27 08:31:03 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-4347b939-ed12-4c44-a836-b614bd6f3efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502691099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.502691099 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.845653431 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 53852158 ps |
| CPU time | 7.06 seconds |
| Started | Jul 27 08:30:14 PM PDT 24 |
| Finished | Jul 27 08:30:21 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c3aee335-215d-49cd-b946-3c16b7682b11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845653431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.845653431 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.1521596750 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 7802388310 ps |
| CPU time | 85.09 seconds |
| Started | Jul 27 08:30:21 PM PDT 24 |
| Finished | Jul 27 08:31:47 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-d8b952d7-f92c-49f8-921e-0151b3888e79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521596750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1521596750 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2996574398 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 4261190184 ps |
| CPU time | 69.99 seconds |
| Started | Jul 27 08:30:18 PM PDT 24 |
| Finished | Jul 27 08:31:28 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-540e7b6a-2071-419b-b427-1d3055bb222e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996574398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2996574398 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3197796315 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 49839421 ps |
| CPU time | 7.08 seconds |
| Started | Jul 27 08:30:20 PM PDT 24 |
| Finished | Jul 27 08:30:28 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-6d6b6868-00a5-4f12-979c-70cb8a5c1ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197796315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3197796315 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1512609223 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 3058502640 ps |
| CPU time | 267 seconds |
| Started | Jul 27 08:30:40 PM PDT 24 |
| Finished | Jul 27 08:35:07 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-31b980ca-90e3-4da4-8c4a-92f317b99621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512609223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1512609223 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.342849414 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 16333494661 ps |
| CPU time | 756.51 seconds |
| Started | Jul 27 08:30:44 PM PDT 24 |
| Finished | Jul 27 08:43:20 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-3c7c4398-d1ed-44d9-b6bc-cb20c33f3815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342849414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.342849414 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.304597052 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 8065690227 ps |
| CPU time | 350.68 seconds |
| Started | Jul 27 08:30:42 PM PDT 24 |
| Finished | Jul 27 08:36:33 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-8ee743b7-7339-4317-bdc8-4414f37a92c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304597052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.304597052 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2798905940 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 689919774 ps |
| CPU time | 138.88 seconds |
| Started | Jul 27 08:30:41 PM PDT 24 |
| Finished | Jul 27 08:33:00 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-3f53b7e9-dc5c-4dbb-a670-e348cc0b81d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798905940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.2798905940 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.192743676 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 311355624 ps |
| CPU time | 35.63 seconds |
| Started | Jul 27 08:30:29 PM PDT 24 |
| Finished | Jul 27 08:31:05 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-328b470f-1d8f-4452-b23c-07c4a4efb93a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192743676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.192743676 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.3300451566 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 585356651 ps |
| CPU time | 55.86 seconds |
| Started | Jul 27 08:46:25 PM PDT 24 |
| Finished | Jul 27 08:47:21 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b1352303-bd73-460e-8b82-8cb83cfffd8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300451566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .3300451566 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.468770153 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 155270723334 ps |
| CPU time | 2497.25 seconds |
| Started | Jul 27 08:46:21 PM PDT 24 |
| Finished | Jul 27 09:27:59 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-6b835773-9a8c-48ef-abfc-c04234536363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468770153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_d evice_slow_rsp.468770153 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.164633670 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 53698377 ps |
| CPU time | 5.91 seconds |
| Started | Jul 27 08:46:25 PM PDT 24 |
| Finished | Jul 27 08:46:31 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-bf866099-61ca-49e9-9b18-0edb0320f65a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164633670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .164633670 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.2556816366 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2318716355 ps |
| CPU time | 84.54 seconds |
| Started | Jul 27 08:46:22 PM PDT 24 |
| Finished | Jul 27 08:47:46 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-19563578-e750-4683-a1a1-3a5eda1b52e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556816366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2556816366 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.3135625705 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 234899189 ps |
| CPU time | 22.96 seconds |
| Started | Jul 27 08:46:10 PM PDT 24 |
| Finished | Jul 27 08:46:33 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-38e058c1-122e-40a8-ad8f-105ecfc23801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135625705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3135625705 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.3436926094 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 75981486786 ps |
| CPU time | 858.58 seconds |
| Started | Jul 27 08:46:20 PM PDT 24 |
| Finished | Jul 27 09:00:38 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-565ec0e8-f854-46fa-aeac-d96190538f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436926094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.3436926094 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.420258 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 12727235405 ps |
| CPU time | 221.45 seconds |
| Started | Jul 27 08:46:20 PM PDT 24 |
| Finished | Jul 27 08:50:02 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-070371ee-dabc-46b9-9ff8-63c7a6800a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.420258 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.557853607 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 323811145 ps |
| CPU time | 30.4 seconds |
| Started | Jul 27 08:46:12 PM PDT 24 |
| Finished | Jul 27 08:46:42 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-6015831c-69c8-4933-9159-f7481f28557b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557853607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_dela ys.557853607 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.1993217882 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1516298474 ps |
| CPU time | 51.22 seconds |
| Started | Jul 27 08:46:22 PM PDT 24 |
| Finished | Jul 27 08:47:13 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3bcb550c-5bda-40db-bcfb-65f48412f727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993217882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.1993217882 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.4172771816 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 198425240 ps |
| CPU time | 9.67 seconds |
| Started | Jul 27 08:46:07 PM PDT 24 |
| Finished | Jul 27 08:46:17 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-ffdc62b3-b255-493f-82e1-52da0059f0d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172771816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.4172771816 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2210830993 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 8841925166 ps |
| CPU time | 93.99 seconds |
| Started | Jul 27 08:46:11 PM PDT 24 |
| Finished | Jul 27 08:47:45 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-39b96be3-999a-4197-bc1a-edd10ca76248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210830993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2210830993 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.306357933 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 4616598389 ps |
| CPU time | 82.79 seconds |
| Started | Jul 27 08:46:11 PM PDT 24 |
| Finished | Jul 27 08:47:34 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-ee8a366a-9ec7-4055-aa4f-51ea84724667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306357933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.306357933 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3199608107 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 52296681 ps |
| CPU time | 6.91 seconds |
| Started | Jul 27 08:46:09 PM PDT 24 |
| Finished | Jul 27 08:46:16 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-89a067e8-4144-4a5b-995c-578ba366df23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199608107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.3199608107 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.424798892 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 154629790 ps |
| CPU time | 15.46 seconds |
| Started | Jul 27 08:46:23 PM PDT 24 |
| Finished | Jul 27 08:46:39 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-cfe88e8f-1f13-4e34-a5af-a4244385c61e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424798892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.424798892 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1561993363 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 4291895165 ps |
| CPU time | 154.01 seconds |
| Started | Jul 27 08:46:19 PM PDT 24 |
| Finished | Jul 27 08:48:53 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-5598f10e-a935-4c6e-9679-3c0bf1a8fab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561993363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1561993363 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3071090006 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 4567063415 ps |
| CPU time | 377.79 seconds |
| Started | Jul 27 08:46:21 PM PDT 24 |
| Finished | Jul 27 08:52:39 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-f7b39819-7c0b-476d-a359-d2240c15c78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071090006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.3071090006 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2430845879 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 9379688379 ps |
| CPU time | 441.29 seconds |
| Started | Jul 27 08:46:21 PM PDT 24 |
| Finished | Jul 27 08:53:42 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-793ad492-d10a-44a8-809b-ba45b66b8091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430845879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2430845879 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3596673976 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 216876957 ps |
| CPU time | 26.75 seconds |
| Started | Jul 27 08:46:22 PM PDT 24 |
| Finished | Jul 27 08:46:49 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-d53f393e-4eff-49ab-810d-59d605d52e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596673976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3596673976 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.2268756413 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 133595622 ps |
| CPU time | 9.33 seconds |
| Started | Jul 27 08:46:27 PM PDT 24 |
| Finished | Jul 27 08:46:36 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-827c90e3-ab27-49f3-9fac-ff94906872bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268756413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .2268756413 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.445734997 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 39076607098 ps |
| CPU time | 673.05 seconds |
| Started | Jul 27 08:46:28 PM PDT 24 |
| Finished | Jul 27 08:57:41 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-4f56ac04-f6bc-43d0-857d-5f91f59f3b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445734997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_d evice_slow_rsp.445734997 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.940163771 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 1183840906 ps |
| CPU time | 45.3 seconds |
| Started | Jul 27 08:46:25 PM PDT 24 |
| Finished | Jul 27 08:47:11 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-b8dc239c-f340-4388-b68d-588887153584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940163771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr .940163771 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.179485924 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 252375284 ps |
| CPU time | 24.09 seconds |
| Started | Jul 27 08:46:29 PM PDT 24 |
| Finished | Jul 27 08:46:53 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-a27bd46b-9574-4471-93a9-96a377b5d077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179485924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.179485924 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.107856083 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 1779496779 ps |
| CPU time | 68.78 seconds |
| Started | Jul 27 08:46:28 PM PDT 24 |
| Finished | Jul 27 08:47:37 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-21e8357e-b06e-4667-a6bf-96d42e76ae85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107856083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.107856083 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.944452025 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 38522602890 ps |
| CPU time | 393.03 seconds |
| Started | Jul 27 08:46:27 PM PDT 24 |
| Finished | Jul 27 08:53:00 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-8f8d871a-653e-46e5-a520-7a98d8c61f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944452025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.944452025 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.2827839089 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 26875450075 ps |
| CPU time | 490.54 seconds |
| Started | Jul 27 08:46:26 PM PDT 24 |
| Finished | Jul 27 08:54:37 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-83f6b9b6-3137-4e2c-b9f5-a87cbbfa3164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827839089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.2827839089 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3718977807 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 639923901 ps |
| CPU time | 55.96 seconds |
| Started | Jul 27 08:46:29 PM PDT 24 |
| Finished | Jul 27 08:47:26 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-0b590358-6b51-40fa-8df3-81fa3033773c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718977807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3718977807 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1718488765 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 2194823955 ps |
| CPU time | 68.57 seconds |
| Started | Jul 27 08:46:30 PM PDT 24 |
| Finished | Jul 27 08:47:39 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-90f2bd40-585e-469f-912f-2d0d260498b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718488765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1718488765 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.3370047959 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 46191431 ps |
| CPU time | 6.99 seconds |
| Started | Jul 27 08:46:21 PM PDT 24 |
| Finished | Jul 27 08:46:28 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d79ba4dd-3b70-4467-9bfa-25d26cf7a5b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370047959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3370047959 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2169863382 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 8934933079 ps |
| CPU time | 88.33 seconds |
| Started | Jul 27 08:46:21 PM PDT 24 |
| Finished | Jul 27 08:47:49 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-6b7b3840-3001-4dcb-92d8-7d967f205179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169863382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2169863382 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2067087829 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 4145318646 ps |
| CPU time | 70.71 seconds |
| Started | Jul 27 08:46:28 PM PDT 24 |
| Finished | Jul 27 08:47:38 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-01a3bd9c-04f5-407d-a1d0-7ec36371bad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067087829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2067087829 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2771034539 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 51189404 ps |
| CPU time | 6.71 seconds |
| Started | Jul 27 08:46:22 PM PDT 24 |
| Finished | Jul 27 08:46:29 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-2f9f55b0-6f4d-4a11-9dcd-fea5d15a9767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771034539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2771034539 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.1028590912 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 10644313130 ps |
| CPU time | 409.92 seconds |
| Started | Jul 27 08:46:28 PM PDT 24 |
| Finished | Jul 27 08:53:18 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-567e4710-d8ab-48cc-b47e-172a79b40081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028590912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1028590912 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.2437330784 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 3472768140 ps |
| CPU time | 244.18 seconds |
| Started | Jul 27 08:46:30 PM PDT 24 |
| Finished | Jul 27 08:50:35 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-5fc806a3-bc56-45d0-807d-264ffe6f71b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437330784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.2437330784 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.271477481 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 232305618 ps |
| CPU time | 136.99 seconds |
| Started | Jul 27 08:46:30 PM PDT 24 |
| Finished | Jul 27 08:48:47 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-a60cb3d0-9b86-4896-861b-df127cd071f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271477481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_ with_rand_reset.271477481 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.4225900782 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 1719234340 ps |
| CPU time | 173.18 seconds |
| Started | Jul 27 08:46:37 PM PDT 24 |
| Finished | Jul 27 08:49:31 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-144a3347-de08-4fbb-bfa0-12cc4933c514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225900782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.4225900782 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2364680692 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 477219985 ps |
| CPU time | 25.18 seconds |
| Started | Jul 27 08:46:31 PM PDT 24 |
| Finished | Jul 27 08:46:56 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-82da5571-9e5f-42fb-bfff-7a63946489b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364680692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2364680692 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3616395814 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 575692771 ps |
| CPU time | 43.79 seconds |
| Started | Jul 27 08:46:37 PM PDT 24 |
| Finished | Jul 27 08:47:21 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-78273e4e-bb73-44ab-b28c-8152ea6149eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616395814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3616395814 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1144217927 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 10073390051 ps |
| CPU time | 169.92 seconds |
| Started | Jul 27 08:46:34 PM PDT 24 |
| Finished | Jul 27 08:49:24 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-335f782e-fe50-4c23-8238-41aa3093d741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144217927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1144217927 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3987102757 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 131607652 ps |
| CPU time | 18.63 seconds |
| Started | Jul 27 08:46:38 PM PDT 24 |
| Finished | Jul 27 08:46:57 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-707e0865-edce-4261-a94e-e0f37ccf68f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987102757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3987102757 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.4153313734 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1034654762 ps |
| CPU time | 37.63 seconds |
| Started | Jul 27 08:46:38 PM PDT 24 |
| Finished | Jul 27 08:47:16 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-084ea295-12ac-4bd9-9d8f-73cd110e8f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153313734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.4153313734 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.551278062 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 1449122216 ps |
| CPU time | 55.56 seconds |
| Started | Jul 27 08:46:39 PM PDT 24 |
| Finished | Jul 27 08:47:35 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-6465db01-042c-4378-bccf-25d07ca4df4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551278062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.551278062 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2392022046 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 78341659667 ps |
| CPU time | 857.99 seconds |
| Started | Jul 27 08:46:38 PM PDT 24 |
| Finished | Jul 27 09:00:56 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-bb9908bb-d6a8-477a-8d10-dc1ec78614ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392022046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2392022046 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.1751187455 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 16977050668 ps |
| CPU time | 278.7 seconds |
| Started | Jul 27 08:46:37 PM PDT 24 |
| Finished | Jul 27 08:51:16 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-56388b0f-7708-42ab-9e1e-298e95c7b4f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751187455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.1751187455 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.540836779 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 300952571 ps |
| CPU time | 29.89 seconds |
| Started | Jul 27 08:46:36 PM PDT 24 |
| Finished | Jul 27 08:47:06 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-16e9cf8d-9ca3-49a1-a394-5eb060350cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540836779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.540836779 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2348587647 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 192522657 ps |
| CPU time | 16.96 seconds |
| Started | Jul 27 08:46:38 PM PDT 24 |
| Finished | Jul 27 08:46:55 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f2ef06fc-2daf-4077-8aae-bdf625fa5bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348587647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2348587647 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3556228651 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 153661203 ps |
| CPU time | 8.14 seconds |
| Started | Jul 27 08:46:36 PM PDT 24 |
| Finished | Jul 27 08:46:44 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-a5d98478-53c1-4fad-a74c-ad32b754c6a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556228651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3556228651 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.2446971034 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 8519061839 ps |
| CPU time | 87.55 seconds |
| Started | Jul 27 08:46:36 PM PDT 24 |
| Finished | Jul 27 08:48:04 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-66be9481-5301-4d1e-a458-a772c2f0347d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446971034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.2446971034 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.910825739 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 6254621889 ps |
| CPU time | 101.93 seconds |
| Started | Jul 27 08:46:36 PM PDT 24 |
| Finished | Jul 27 08:48:18 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-65ad14bc-be44-4217-88f5-21824af6745e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910825739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.910825739 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.177481548 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 47725529 ps |
| CPU time | 5.84 seconds |
| Started | Jul 27 08:46:35 PM PDT 24 |
| Finished | Jul 27 08:46:40 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-12a01f99-1b56-472a-9fc7-2787afaa8274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177481548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .177481548 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.4221660104 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 3824190934 ps |
| CPU time | 172.1 seconds |
| Started | Jul 27 08:46:43 PM PDT 24 |
| Finished | Jul 27 08:49:35 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-02004350-d08e-474e-944e-2f8135a70f2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221660104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.4221660104 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.831299435 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 7468209672 ps |
| CPU time | 272.19 seconds |
| Started | Jul 27 08:46:43 PM PDT 24 |
| Finished | Jul 27 08:51:15 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-a7456f91-d7e3-482f-b5c1-9f23f6f37ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831299435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.831299435 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.7840880 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 6212299198 ps |
| CPU time | 336.32 seconds |
| Started | Jul 27 08:46:48 PM PDT 24 |
| Finished | Jul 27 08:52:25 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-1f24eb9e-1d08-40c5-89c6-4e9712eace5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7840880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_wi th_rand_reset.7840880 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2436375249 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 1605515794 ps |
| CPU time | 243.96 seconds |
| Started | Jul 27 08:46:45 PM PDT 24 |
| Finished | Jul 27 08:50:49 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-cf959fec-fe4a-4ebb-b812-072206c83135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436375249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2436375249 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1742335528 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 758929583 ps |
| CPU time | 36.07 seconds |
| Started | Jul 27 08:46:34 PM PDT 24 |
| Finished | Jul 27 08:47:10 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-5b897128-3ff7-4b10-8d3f-9a7c94f9c702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742335528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1742335528 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.633683362 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 133306731 ps |
| CPU time | 13.75 seconds |
| Started | Jul 27 08:46:51 PM PDT 24 |
| Finished | Jul 27 08:47:05 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4fa6aed1-c1b8-4f1f-b73e-17cbf7324834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633683362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 633683362 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2721040400 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 113481241003 ps |
| CPU time | 2002.86 seconds |
| Started | Jul 27 08:46:51 PM PDT 24 |
| Finished | Jul 27 09:20:14 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-d65e1115-d96d-41c8-8b37-54aaf94cbd0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721040400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2721040400 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3062380665 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 704496475 ps |
| CPU time | 34.31 seconds |
| Started | Jul 27 08:46:52 PM PDT 24 |
| Finished | Jul 27 08:47:26 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c4f4584b-536b-4607-aff1-9ce11baebf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062380665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3062380665 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.4058293149 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 552871718 ps |
| CPU time | 44.2 seconds |
| Started | Jul 27 08:46:53 PM PDT 24 |
| Finished | Jul 27 08:47:37 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-c65dfe12-973a-4044-9862-2e7db861b46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058293149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.4058293149 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.120280510 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1725453520 ps |
| CPU time | 67.04 seconds |
| Started | Jul 27 08:46:53 PM PDT 24 |
| Finished | Jul 27 08:48:00 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-f882e443-5df1-41ed-8db0-4d067bd978de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120280510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.120280510 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.903007173 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 12031967745 ps |
| CPU time | 127.97 seconds |
| Started | Jul 27 08:46:51 PM PDT 24 |
| Finished | Jul 27 08:48:59 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-235c64dd-794e-47d8-9885-fae62a2c2b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903007173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.903007173 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3321375315 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 11215917602 ps |
| CPU time | 198.84 seconds |
| Started | Jul 27 08:46:50 PM PDT 24 |
| Finished | Jul 27 08:50:09 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-6bc5057e-0724-4771-b459-fa07286bb2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321375315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3321375315 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1046254202 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 511044212 ps |
| CPU time | 50.77 seconds |
| Started | Jul 27 08:46:53 PM PDT 24 |
| Finished | Jul 27 08:47:44 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-8573d9d2-ec8f-4e67-b733-2f9102b02e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046254202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1046254202 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3760683653 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 192255496 ps |
| CPU time | 16.81 seconds |
| Started | Jul 27 08:46:52 PM PDT 24 |
| Finished | Jul 27 08:47:09 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-62d91d74-fe6c-4d4f-9b01-f6f7732debc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760683653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3760683653 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.3067629175 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 178424366 ps |
| CPU time | 8.61 seconds |
| Started | Jul 27 08:46:44 PM PDT 24 |
| Finished | Jul 27 08:46:53 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-68aece21-de8d-4931-aa7d-4940704834f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067629175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.3067629175 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1525665376 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 7680588714 ps |
| CPU time | 87.14 seconds |
| Started | Jul 27 08:46:48 PM PDT 24 |
| Finished | Jul 27 08:48:15 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fd31a097-56c5-43e3-98fe-8832c1cdcb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525665376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1525665376 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2469290731 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 4517164521 ps |
| CPU time | 74.65 seconds |
| Started | Jul 27 08:46:45 PM PDT 24 |
| Finished | Jul 27 08:48:00 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-e7127fb8-5aa7-4d50-9e35-6e3136606038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469290731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2469290731 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2214420108 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 50275607 ps |
| CPU time | 6.58 seconds |
| Started | Jul 27 08:46:49 PM PDT 24 |
| Finished | Jul 27 08:46:55 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-47c9e248-797c-4f45-9b8a-4226e13835b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214420108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.2214420108 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3709337627 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 534485208 ps |
| CPU time | 56.98 seconds |
| Started | Jul 27 08:46:53 PM PDT 24 |
| Finished | Jul 27 08:47:50 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-5cd99456-0bed-44b8-9415-6c80856295c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709337627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3709337627 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2975964244 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 351708100 ps |
| CPU time | 31.06 seconds |
| Started | Jul 27 08:46:50 PM PDT 24 |
| Finished | Jul 27 08:47:22 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-cc2c8e5c-604b-4178-8d0b-51d725893fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975964244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2975964244 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.2988193579 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 9908420554 ps |
| CPU time | 563.24 seconds |
| Started | Jul 27 08:46:57 PM PDT 24 |
| Finished | Jul 27 08:56:20 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-e579f9de-3737-4de8-9247-c2704276973b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988193579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.2988193579 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.4257972002 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 773618790 ps |
| CPU time | 290.55 seconds |
| Started | Jul 27 08:46:53 PM PDT 24 |
| Finished | Jul 27 08:51:44 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-c555ab1d-d92b-4e88-b0d1-97e9539b2640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257972002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.4257972002 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3929365960 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 637022396 ps |
| CPU time | 29.28 seconds |
| Started | Jul 27 08:46:51 PM PDT 24 |
| Finished | Jul 27 08:47:20 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-dfecb64e-463b-4992-9d44-dbffe14765d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929365960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3929365960 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3235222636 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 302306793 ps |
| CPU time | 18.13 seconds |
| Started | Jul 27 08:46:58 PM PDT 24 |
| Finished | Jul 27 08:47:17 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-c4e563a9-0734-4e12-8989-eb1ce830c4c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235222636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3235222636 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.1345604194 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 36295583712 ps |
| CPU time | 667.62 seconds |
| Started | Jul 27 08:47:10 PM PDT 24 |
| Finished | Jul 27 08:58:18 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-ca83a9ec-7104-4e7d-9146-a45d54bf942d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345604194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.1345604194 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.394500315 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 48644298 ps |
| CPU time | 8.55 seconds |
| Started | Jul 27 08:47:00 PM PDT 24 |
| Finished | Jul 27 08:47:09 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-ea08a43e-46bc-4981-8bda-509744bca098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394500315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_addr .394500315 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2519136795 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 648728626 ps |
| CPU time | 25.13 seconds |
| Started | Jul 27 08:47:07 PM PDT 24 |
| Finished | Jul 27 08:47:32 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-4ea014e2-9989-4220-a35b-f40767cd8710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519136795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2519136795 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.664479528 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 258667077 ps |
| CPU time | 12.5 seconds |
| Started | Jul 27 08:47:02 PM PDT 24 |
| Finished | Jul 27 08:47:15 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-656f20fc-1f42-4bc2-b61e-17d9df17c540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664479528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.664479528 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.928162987 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 86371434336 ps |
| CPU time | 901.86 seconds |
| Started | Jul 27 08:47:02 PM PDT 24 |
| Finished | Jul 27 09:02:04 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-a9db02d7-ed17-43ba-92f7-18b994077d12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928162987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.928162987 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3881209523 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 36024377311 ps |
| CPU time | 635.75 seconds |
| Started | Jul 27 08:47:07 PM PDT 24 |
| Finished | Jul 27 08:57:42 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-137e00cf-bbd3-4e43-8818-7603fb88e4fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881209523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3881209523 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.126669903 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 472935624 ps |
| CPU time | 49.7 seconds |
| Started | Jul 27 08:47:05 PM PDT 24 |
| Finished | Jul 27 08:47:55 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-163f621b-fa00-4b8b-97c7-15f7c379503b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126669903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.126669903 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.2644568078 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 85920193 ps |
| CPU time | 10 seconds |
| Started | Jul 27 08:47:03 PM PDT 24 |
| Finished | Jul 27 08:47:13 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-1f661ddd-7a4c-4d52-a856-72953de382fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644568078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2644568078 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.2585686259 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 128197989 ps |
| CPU time | 7.45 seconds |
| Started | Jul 27 08:46:58 PM PDT 24 |
| Finished | Jul 27 08:47:05 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-ea4dea92-0333-4a51-8894-9c0b471d2449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585686259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2585686259 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.327790261 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 10031441170 ps |
| CPU time | 105.04 seconds |
| Started | Jul 27 08:47:03 PM PDT 24 |
| Finished | Jul 27 08:48:48 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-686112d8-9b9e-4728-a3ff-d6e595eb55f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327790261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.327790261 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2616716416 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 4924026865 ps |
| CPU time | 88.33 seconds |
| Started | Jul 27 08:47:05 PM PDT 24 |
| Finished | Jul 27 08:48:33 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-02c7c23b-b07b-4c6e-a63a-e9f7c7594a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616716416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2616716416 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1532597305 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 48144886 ps |
| CPU time | 6.21 seconds |
| Started | Jul 27 08:46:53 PM PDT 24 |
| Finished | Jul 27 08:46:59 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-6beb71d6-bd17-4e6f-8205-b3aaa897f1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532597305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.1532597305 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.3253561291 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 3726680053 ps |
| CPU time | 301.33 seconds |
| Started | Jul 27 08:47:05 PM PDT 24 |
| Finished | Jul 27 08:52:06 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-074ac58b-b249-4ea9-bc26-f4ede02ccbf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253561291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3253561291 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2496138697 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 7212971691 ps |
| CPU time | 271.26 seconds |
| Started | Jul 27 08:47:11 PM PDT 24 |
| Finished | Jul 27 08:51:42 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-dc1509ae-f8ba-44fb-93b6-a47dc8a79d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496138697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2496138697 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.673945011 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 636821370 ps |
| CPU time | 234.29 seconds |
| Started | Jul 27 08:47:21 PM PDT 24 |
| Finished | Jul 27 08:51:15 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-984f3495-d08f-4f13-86b8-0a09711ddd76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673945011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_rand_reset.673945011 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1764826906 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 551093309 ps |
| CPU time | 195.5 seconds |
| Started | Jul 27 08:47:23 PM PDT 24 |
| Finished | Jul 27 08:50:38 PM PDT 24 |
| Peak memory | 576756 kb |
| Host | smart-0e31bb92-42b2-46d3-9c73-471fed93528d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764826906 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.1764826906 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3523953486 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 1203130485 ps |
| CPU time | 54.3 seconds |
| Started | Jul 27 08:47:04 PM PDT 24 |
| Finished | Jul 27 08:47:58 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-45b16490-5de6-42bd-bc2b-1bb415381b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523953486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3523953486 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.822960626 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 738790594 ps |
| CPU time | 51.5 seconds |
| Started | Jul 27 08:47:09 PM PDT 24 |
| Finished | Jul 27 08:48:01 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-085d4325-b7f2-4f3d-856c-a15c914ea88b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822960626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device. 822960626 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.4256745426 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 106281326445 ps |
| CPU time | 1795.29 seconds |
| Started | Jul 27 08:47:22 PM PDT 24 |
| Finished | Jul 27 09:17:18 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-3f6c4906-8117-477b-8585-a204e629a837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256745426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.4256745426 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1863873856 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 381098502 ps |
| CPU time | 20.3 seconds |
| Started | Jul 27 08:47:18 PM PDT 24 |
| Finished | Jul 27 08:47:38 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-c32c1503-87b2-4ebb-ae6d-ed5e0ce86321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863873856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1863873856 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2107755504 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 551071418 ps |
| CPU time | 47.56 seconds |
| Started | Jul 27 08:47:16 PM PDT 24 |
| Finished | Jul 27 08:48:03 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-86464c6c-70fe-4b95-8203-ccb20fd07cc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107755504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2107755504 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.2270980787 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 307235302 ps |
| CPU time | 28.34 seconds |
| Started | Jul 27 08:47:10 PM PDT 24 |
| Finished | Jul 27 08:47:39 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-622d9c0e-b913-4781-9af5-39a53e545892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270980787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.2270980787 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1066757679 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 60829465208 ps |
| CPU time | 632.15 seconds |
| Started | Jul 27 08:47:22 PM PDT 24 |
| Finished | Jul 27 08:57:54 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-027718d5-a41a-42f1-86eb-7fc7f458ce90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066757679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1066757679 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3058758461 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 29193743559 ps |
| CPU time | 488.48 seconds |
| Started | Jul 27 08:47:22 PM PDT 24 |
| Finished | Jul 27 08:55:30 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-0ae6304b-5be6-41f7-8c92-9827e421af0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058758461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3058758461 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.318386350 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 145174623 ps |
| CPU time | 14.13 seconds |
| Started | Jul 27 08:47:08 PM PDT 24 |
| Finished | Jul 27 08:47:22 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-13c63fea-fba0-4790-a5e2-726d070517e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318386350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.318386350 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1547531351 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 548381470 ps |
| CPU time | 45.56 seconds |
| Started | Jul 27 08:47:10 PM PDT 24 |
| Finished | Jul 27 08:47:55 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-383de579-0aaf-4f68-9b13-3212a3ecbc60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547531351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1547531351 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1604390297 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 213987216 ps |
| CPU time | 9.56 seconds |
| Started | Jul 27 08:47:12 PM PDT 24 |
| Finished | Jul 27 08:47:21 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-25da8727-8a0e-4cae-8653-e28b4245d64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604390297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1604390297 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.4222897201 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 7497726464 ps |
| CPU time | 78.22 seconds |
| Started | Jul 27 08:47:12 PM PDT 24 |
| Finished | Jul 27 08:48:30 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-e3cdd7a6-26df-4fa7-871d-29fd9d0aea35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222897201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.4222897201 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2995116967 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4756500822 ps |
| CPU time | 86.57 seconds |
| Started | Jul 27 08:47:08 PM PDT 24 |
| Finished | Jul 27 08:48:35 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-c4830f93-2cf1-49c3-8f73-8e70703ccca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995116967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2995116967 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1208483767 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 57024870 ps |
| CPU time | 7.22 seconds |
| Started | Jul 27 08:47:22 PM PDT 24 |
| Finished | Jul 27 08:47:29 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-226e488f-07d9-4e9a-87de-439e6be5da35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208483767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.1208483767 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.2602900478 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 14459064471 ps |
| CPU time | 553.38 seconds |
| Started | Jul 27 08:47:18 PM PDT 24 |
| Finished | Jul 27 08:56:31 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-f1e4a05b-4fb6-45f4-9267-b5193bf82292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602900478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.2602900478 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3841647952 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 6181547271 ps |
| CPU time | 216.04 seconds |
| Started | Jul 27 08:47:16 PM PDT 24 |
| Finished | Jul 27 08:50:52 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-dcdcff66-033d-4c2f-9718-ebc7f6f8398e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841647952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3841647952 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.486248823 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 137826363 ps |
| CPU time | 34.79 seconds |
| Started | Jul 27 08:47:15 PM PDT 24 |
| Finished | Jul 27 08:47:50 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-b338f788-bf30-4863-a19f-d6a2f04a7131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486248823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.486248823 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3000860699 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 230632584 ps |
| CPU time | 63.21 seconds |
| Started | Jul 27 08:47:15 PM PDT 24 |
| Finished | Jul 27 08:48:19 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-680f3e08-e1a7-462e-aad5-38d2a8d98176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000860699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3000860699 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3752867340 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 246373158 ps |
| CPU time | 31.1 seconds |
| Started | Jul 27 08:47:15 PM PDT 24 |
| Finished | Jul 27 08:47:46 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-e2bd1ec5-0a6e-4ec8-b77f-42b908f5c4e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752867340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3752867340 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.1058271625 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 178715022 ps |
| CPU time | 16.02 seconds |
| Started | Jul 27 08:47:25 PM PDT 24 |
| Finished | Jul 27 08:47:41 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-b7817e69-1e36-403b-8c12-7767c880f497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058271625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .1058271625 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2214788830 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 53573023189 ps |
| CPU time | 1090.59 seconds |
| Started | Jul 27 08:47:30 PM PDT 24 |
| Finished | Jul 27 09:05:40 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-3f6bfba8-9b9c-45d1-a781-34ba42c6c277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214788830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.2214788830 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2694843364 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 285973662 ps |
| CPU time | 33.52 seconds |
| Started | Jul 27 08:47:25 PM PDT 24 |
| Finished | Jul 27 08:47:59 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-6bf3739b-939d-42c7-80ad-a0c750ec5f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694843364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2694843364 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2222075493 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 1316127303 ps |
| CPU time | 53.97 seconds |
| Started | Jul 27 08:47:23 PM PDT 24 |
| Finished | Jul 27 08:48:17 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-fd844d1f-065b-47bf-835e-c77d6e38a69e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222075493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2222075493 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.854643486 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 1516853176 ps |
| CPU time | 57.83 seconds |
| Started | Jul 27 08:47:24 PM PDT 24 |
| Finished | Jul 27 08:48:22 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-d7ec4f52-25ba-4f61-84c4-d46ac7aff5f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854643486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.854643486 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3161179715 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 83178129321 ps |
| CPU time | 792.42 seconds |
| Started | Jul 27 08:47:24 PM PDT 24 |
| Finished | Jul 27 09:00:36 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e8e0ae42-18d2-4a0e-aec8-8bb25a2f5393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161179715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3161179715 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3091695380 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 48827483244 ps |
| CPU time | 857.52 seconds |
| Started | Jul 27 08:47:28 PM PDT 24 |
| Finished | Jul 27 09:01:46 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-5ebe3a10-ba10-41c8-ab02-7d92ca66e7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091695380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3091695380 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.804858865 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 197271489 ps |
| CPU time | 19.2 seconds |
| Started | Jul 27 08:47:25 PM PDT 24 |
| Finished | Jul 27 08:47:44 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-e14948ed-6481-4f99-bf2f-5cd9a6566ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804858865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_dela ys.804858865 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.4264394304 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 2388008159 ps |
| CPU time | 81.82 seconds |
| Started | Jul 27 08:47:27 PM PDT 24 |
| Finished | Jul 27 08:48:49 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-d6c31c15-bb02-4ca3-87cf-4fc0c8d6ea17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264394304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.4264394304 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.1780835113 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 258687589 ps |
| CPU time | 10.83 seconds |
| Started | Jul 27 08:47:16 PM PDT 24 |
| Finished | Jul 27 08:47:26 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-caad2872-f26f-4796-8eea-5999cc1b5a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780835113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1780835113 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3299586867 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 7934916073 ps |
| CPU time | 82.2 seconds |
| Started | Jul 27 08:47:18 PM PDT 24 |
| Finished | Jul 27 08:48:40 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-2ecd0a1e-5de6-448e-b7e7-f8b0873b8bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299586867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3299586867 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2279716507 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 5502754136 ps |
| CPU time | 102.22 seconds |
| Started | Jul 27 08:47:24 PM PDT 24 |
| Finished | Jul 27 08:49:06 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-bfdd35fc-a2da-45ea-9c75-6608c287b7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279716507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2279716507 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.869743589 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 42275377 ps |
| CPU time | 5.36 seconds |
| Started | Jul 27 08:47:15 PM PDT 24 |
| Finished | Jul 27 08:47:21 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-08febf00-2b6e-46a1-a5cc-b4d9b47dc14e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869743589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays .869743589 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2720335606 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 4171238622 ps |
| CPU time | 361.74 seconds |
| Started | Jul 27 08:47:25 PM PDT 24 |
| Finished | Jul 27 08:53:27 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-b3412d9f-8849-4b29-9d67-740f29bc9982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720335606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2720335606 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2341484052 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 13456828804 ps |
| CPU time | 481.21 seconds |
| Started | Jul 27 08:47:36 PM PDT 24 |
| Finished | Jul 27 08:55:38 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-dd494e41-2daa-4c6d-a746-0414757b9d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341484052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2341484052 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.366398788 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 416326107 ps |
| CPU time | 127.29 seconds |
| Started | Jul 27 08:47:25 PM PDT 24 |
| Finished | Jul 27 08:49:33 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-dbaecdce-92bb-4b71-950a-d167ddf3e466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366398788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.366398788 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2025557341 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 308462579 ps |
| CPU time | 46.63 seconds |
| Started | Jul 27 08:47:34 PM PDT 24 |
| Finished | Jul 27 08:48:21 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-97a29f73-66c1-46be-94ca-6d4ebb751ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025557341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.2025557341 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.2094919123 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 1194088280 ps |
| CPU time | 49.26 seconds |
| Started | Jul 27 08:47:23 PM PDT 24 |
| Finished | Jul 27 08:48:13 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-77ba76a3-d230-4cef-b93c-b1d672ead732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094919123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.2094919123 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.4009659546 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 1113348511 ps |
| CPU time | 49.34 seconds |
| Started | Jul 27 08:47:35 PM PDT 24 |
| Finished | Jul 27 08:48:24 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-1ec30378-6a26-4824-b9c5-7e5de9213d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009659546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .4009659546 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.289711081 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 252479672 ps |
| CPU time | 32.59 seconds |
| Started | Jul 27 08:47:36 PM PDT 24 |
| Finished | Jul 27 08:48:09 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-57417e6d-d6f4-4b03-925d-2fad3223f26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289711081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .289711081 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1299516885 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 2308597478 ps |
| CPU time | 85.88 seconds |
| Started | Jul 27 08:47:34 PM PDT 24 |
| Finished | Jul 27 08:49:00 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-bd7efd38-becc-4c87-ba3b-c421774f1c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299516885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1299516885 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.3878650983 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 284389292 ps |
| CPU time | 29.08 seconds |
| Started | Jul 27 08:47:36 PM PDT 24 |
| Finished | Jul 27 08:48:05 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-44dbafb6-ead0-45a3-89dd-bcf5eba5bf2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878650983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3878650983 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.915177845 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 29142609998 ps |
| CPU time | 493.9 seconds |
| Started | Jul 27 08:47:35 PM PDT 24 |
| Finished | Jul 27 08:55:49 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-173361e6-f35f-4cef-b8a6-0491218a3298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915177845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.915177845 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2743358632 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 67803148 ps |
| CPU time | 8.41 seconds |
| Started | Jul 27 08:47:34 PM PDT 24 |
| Finished | Jul 27 08:47:42 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-d36de6ec-b7e0-4a4f-a93b-58134e3710f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743358632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2743358632 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3616240663 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 316450377 ps |
| CPU time | 24.16 seconds |
| Started | Jul 27 08:47:35 PM PDT 24 |
| Finished | Jul 27 08:47:59 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-b085d54f-b2e2-41ad-9045-fb4dadb57ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616240663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3616240663 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2071043397 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 206788330 ps |
| CPU time | 9.39 seconds |
| Started | Jul 27 08:47:35 PM PDT 24 |
| Finished | Jul 27 08:47:44 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-dba2a880-7c3b-4e32-be23-78c8db1d8d3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071043397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2071043397 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3277128712 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 7457341404 ps |
| CPU time | 82.6 seconds |
| Started | Jul 27 08:47:35 PM PDT 24 |
| Finished | Jul 27 08:48:58 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-61d8296e-714e-4490-ad19-e1980588ea29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277128712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3277128712 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.614501250 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 6142373722 ps |
| CPU time | 113.93 seconds |
| Started | Jul 27 08:47:37 PM PDT 24 |
| Finished | Jul 27 08:49:31 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-f34220e6-77a6-4cd6-bfaf-89cec3f2a4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614501250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.614501250 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3335455407 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 39517659 ps |
| CPU time | 5.72 seconds |
| Started | Jul 27 08:47:38 PM PDT 24 |
| Finished | Jul 27 08:47:43 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-193f3065-b007-4906-a5a7-47d2ce131da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335455407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3335455407 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.444462897 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 648689326 ps |
| CPU time | 62.24 seconds |
| Started | Jul 27 08:47:36 PM PDT 24 |
| Finished | Jul 27 08:48:39 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-6cce6f5d-fd83-4f99-98c5-988bc1390791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444462897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.444462897 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.4274470996 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 1165626992 ps |
| CPU time | 47.42 seconds |
| Started | Jul 27 08:47:49 PM PDT 24 |
| Finished | Jul 27 08:48:36 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-3c0f1c1c-0b55-45dd-b5a4-f8a5b7eb9603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274470996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.4274470996 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2385263187 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 185302242 ps |
| CPU time | 105.26 seconds |
| Started | Jul 27 08:47:34 PM PDT 24 |
| Finished | Jul 27 08:49:19 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-32264ccf-c624-4fd9-b756-b190669dbda8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385263187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.2385263187 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.723474548 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 3786873277 ps |
| CPU time | 456.19 seconds |
| Started | Jul 27 08:47:44 PM PDT 24 |
| Finished | Jul 27 08:55:20 PM PDT 24 |
| Peak memory | 577684 kb |
| Host | smart-6c96130e-493e-4d38-9471-51f78c2f50b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723474548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.723474548 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1932047722 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 923817876 ps |
| CPU time | 38.52 seconds |
| Started | Jul 27 08:47:34 PM PDT 24 |
| Finished | Jul 27 08:48:12 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-bd83dd36-45ba-4d19-906f-a942f847292c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932047722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1932047722 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1900462815 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 722058812 ps |
| CPU time | 64.64 seconds |
| Started | Jul 27 08:47:51 PM PDT 24 |
| Finished | Jul 27 08:48:56 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b20c9bfb-3d13-43c2-98ec-a454cab7f428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900462815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .1900462815 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2220094039 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 69704091974 ps |
| CPU time | 1270.94 seconds |
| Started | Jul 27 08:47:55 PM PDT 24 |
| Finished | Jul 27 09:09:06 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-765fa833-c71e-45db-9b92-2418bed61122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220094039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2220094039 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2106560967 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 212107041 ps |
| CPU time | 25.81 seconds |
| Started | Jul 27 08:47:57 PM PDT 24 |
| Finished | Jul 27 08:48:23 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-efc0ea21-18c6-41c6-b0c7-fc5210ccb618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106560967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2106560967 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1100084855 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2101531649 ps |
| CPU time | 74.25 seconds |
| Started | Jul 27 08:47:53 PM PDT 24 |
| Finished | Jul 27 08:49:07 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-f97ff637-39a6-4977-9c30-5b725cb299ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100084855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1100084855 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2455129331 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1679488346 ps |
| CPU time | 61.68 seconds |
| Started | Jul 27 08:47:49 PM PDT 24 |
| Finished | Jul 27 08:48:51 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-e7321a8b-a37a-4123-9c01-cf644b48192f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455129331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2455129331 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3358410886 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 11029445909 ps |
| CPU time | 107.22 seconds |
| Started | Jul 27 08:47:42 PM PDT 24 |
| Finished | Jul 27 08:49:29 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-1d04045f-63c9-4894-8e17-b7812b48abea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358410886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3358410886 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2804259375 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 52222636383 ps |
| CPU time | 931.82 seconds |
| Started | Jul 27 08:47:44 PM PDT 24 |
| Finished | Jul 27 09:03:16 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-0092f22d-393b-47ff-8a9b-3851cfd8af53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804259375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.2804259375 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.2696377127 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 467393720 ps |
| CPU time | 46.03 seconds |
| Started | Jul 27 08:47:48 PM PDT 24 |
| Finished | Jul 27 08:48:34 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-063cc90e-7c81-4d6f-8f75-4f44212359a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696377127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.2696377127 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.2782579594 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 395283849 ps |
| CPU time | 31.99 seconds |
| Started | Jul 27 08:47:51 PM PDT 24 |
| Finished | Jul 27 08:48:24 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-e4e259dd-373b-43ce-a80c-1f553e8eaf0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782579594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.2782579594 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.2024872650 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 250861662 ps |
| CPU time | 11.13 seconds |
| Started | Jul 27 08:47:43 PM PDT 24 |
| Finished | Jul 27 08:47:54 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-de45b07b-2a94-4642-aea4-f6a13bded0f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024872650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2024872650 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.4095406420 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 10762272550 ps |
| CPU time | 122.29 seconds |
| Started | Jul 27 08:47:44 PM PDT 24 |
| Finished | Jul 27 08:49:46 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-0e6b1639-b4b9-4585-b177-68b72f6b674c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095406420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.4095406420 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.2641155829 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 4806839971 ps |
| CPU time | 80.53 seconds |
| Started | Jul 27 08:47:48 PM PDT 24 |
| Finished | Jul 27 08:49:08 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-a514f4c2-c61e-4f3b-bdb1-17a5749f7b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641155829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.2641155829 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.4139352515 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 46927791 ps |
| CPU time | 6.34 seconds |
| Started | Jul 27 08:47:47 PM PDT 24 |
| Finished | Jul 27 08:47:54 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-605cca2f-ea2a-4629-ae2a-c071c5c2c10d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139352515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.4139352515 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2119408409 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 2801714031 ps |
| CPU time | 247.65 seconds |
| Started | Jul 27 08:47:55 PM PDT 24 |
| Finished | Jul 27 08:52:03 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-d7c7b9b2-1f0d-4e42-ae86-388dcd4b5735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119408409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2119408409 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.4287449545 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 2304004572 ps |
| CPU time | 200.92 seconds |
| Started | Jul 27 08:47:51 PM PDT 24 |
| Finished | Jul 27 08:51:12 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-a2b2e9e1-7d09-4727-8068-0bf8e582b478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287449545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.4287449545 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.109446149 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 1347938305 ps |
| CPU time | 177.52 seconds |
| Started | Jul 27 08:47:53 PM PDT 24 |
| Finished | Jul 27 08:50:50 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-0559969d-b590-47eb-b7b1-258f38c94348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109446149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_ with_rand_reset.109446149 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.488808418 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 2749999932 ps |
| CPU time | 234 seconds |
| Started | Jul 27 08:47:52 PM PDT 24 |
| Finished | Jul 27 08:51:46 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-d0385427-24c2-476e-b85c-6ee87ea3569b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488808418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_reset_error.488808418 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2154905121 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 1199969369 ps |
| CPU time | 53.16 seconds |
| Started | Jul 27 08:47:52 PM PDT 24 |
| Finished | Jul 27 08:48:45 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-b29c7fb1-c597-46f7-b472-d2c077e1797d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154905121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2154905121 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1436817564 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 734672491 ps |
| CPU time | 58.39 seconds |
| Started | Jul 27 08:48:01 PM PDT 24 |
| Finished | Jul 27 08:48:59 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-448a2c3b-f9de-4f69-812f-4a686fc70a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436817564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1436817564 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3218034958 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 26785576457 ps |
| CPU time | 467.21 seconds |
| Started | Jul 27 08:48:01 PM PDT 24 |
| Finished | Jul 27 08:55:49 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-5900f014-2141-4842-8bf3-99da344a561c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218034958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.3218034958 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.4081518457 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 69194878 ps |
| CPU time | 10.45 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 08:48:13 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-37b8243a-3807-4aea-aee0-eaac40d39fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081518457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.4081518457 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.1378242029 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 198560065 ps |
| CPU time | 19.49 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 08:48:22 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d0691a94-80a2-4117-8004-e695f836e67b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378242029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1378242029 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.143155859 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1159890729 ps |
| CPU time | 49.71 seconds |
| Started | Jul 27 08:48:03 PM PDT 24 |
| Finished | Jul 27 08:48:53 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-73da452e-d5ed-44a2-bd67-ad52f57346b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143155859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.143155859 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.2429351349 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 98968341323 ps |
| CPU time | 1018.69 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 09:05:01 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-eea7613a-6f44-4705-9a6e-8a970f8de6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429351349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.2429351349 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3089219859 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 3665003171 ps |
| CPU time | 59.38 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 08:49:02 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-ad157b83-ac55-4aa6-823e-2eee45708944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089219859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3089219859 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3820634074 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 372157077 ps |
| CPU time | 31.7 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 08:48:34 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-96531436-a1c1-4eb3-b686-78027d806ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820634074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3820634074 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.462760197 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 884385587 ps |
| CPU time | 28.4 seconds |
| Started | Jul 27 08:48:00 PM PDT 24 |
| Finished | Jul 27 08:48:29 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-dbdb1654-47ef-4b32-a0c6-3ee25b8626db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462760197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.462760197 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3646129400 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 33467506 ps |
| CPU time | 6.04 seconds |
| Started | Jul 27 08:48:00 PM PDT 24 |
| Finished | Jul 27 08:48:06 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-5a6d2637-506b-40b4-8945-ca5980954844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646129400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3646129400 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.1908550590 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 7186863157 ps |
| CPU time | 73 seconds |
| Started | Jul 27 08:48:03 PM PDT 24 |
| Finished | Jul 27 08:49:16 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0e8d4bb9-de8f-4d36-9db9-5124d8fa9cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908550590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1908550590 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3095476808 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 7437476116 ps |
| CPU time | 122.8 seconds |
| Started | Jul 27 08:48:05 PM PDT 24 |
| Finished | Jul 27 08:50:07 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-95a03bc5-4110-423a-9ea5-a841c6b9749c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095476808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3095476808 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1846807136 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 48728179 ps |
| CPU time | 7.01 seconds |
| Started | Jul 27 08:48:01 PM PDT 24 |
| Finished | Jul 27 08:48:09 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-14f6693c-5871-4a72-9173-331260c7eb86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846807136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1846807136 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.977298625 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 5654687422 ps |
| CPU time | 233.69 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 08:51:55 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-523cced4-529e-4593-ba03-2a61607a5e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977298625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.977298625 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.1548351177 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 6455090829 ps |
| CPU time | 248.17 seconds |
| Started | Jul 27 08:48:02 PM PDT 24 |
| Finished | Jul 27 08:52:11 PM PDT 24 |
| Peak memory | 576076 kb |
| Host | smart-5a97dfcd-8295-4be1-8f46-212a770361ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548351177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.1548351177 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2693020753 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 9849613273 ps |
| CPU time | 426.09 seconds |
| Started | Jul 27 08:48:03 PM PDT 24 |
| Finished | Jul 27 08:55:09 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-88ff7deb-fde3-4cc5-a5fe-cf62b0b8e312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693020753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2693020753 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.1324679227 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 3374434585 ps |
| CPU time | 358.61 seconds |
| Started | Jul 27 08:48:07 PM PDT 24 |
| Finished | Jul 27 08:54:06 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8712f962-0dc6-44ea-aee8-5cfc359b3846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324679227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.1324679227 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1403927918 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 158758212 ps |
| CPU time | 20.67 seconds |
| Started | Jul 27 08:48:01 PM PDT 24 |
| Finished | Jul 27 08:48:22 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-32c04f4b-edfe-4356-8c1d-a6c028b6d578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403927918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1403927918 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3238043397 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 9475824393 ps |
| CPU time | 997.24 seconds |
| Started | Jul 27 08:30:59 PM PDT 24 |
| Finished | Jul 27 08:47:36 PM PDT 24 |
| Peak memory | 652628 kb |
| Host | smart-ceb3bebe-52e4-4d20-96d0-48a8a8142ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238043397 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.3238043397 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.2423427009 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 6577785516 ps |
| CPU time | 842.94 seconds |
| Started | Jul 27 08:30:59 PM PDT 24 |
| Finished | Jul 27 08:45:02 PM PDT 24 |
| Peak memory | 597708 kb |
| Host | smart-094d6e5a-6aa6-4985-9ef0-2cac6d1926f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423427009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.2423427009 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3648667637 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 14480363167 ps |
| CPU time | 1809.54 seconds |
| Started | Jul 27 08:30:40 PM PDT 24 |
| Finished | Jul 27 09:00:49 PM PDT 24 |
| Peak memory | 593028 kb |
| Host | smart-8c3527ae-7581-4e21-bec8-cf37e3bb2e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648667637 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3648667637 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.1057552843 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 4456134700 ps |
| CPU time | 345.61 seconds |
| Started | Jul 27 08:30:48 PM PDT 24 |
| Finished | Jul 27 08:36:34 PM PDT 24 |
| Peak memory | 603416 kb |
| Host | smart-187cf0e9-8e8e-40d4-b362-45135828ac06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057552843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.1057552843 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.3051530109 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 1488199472 ps |
| CPU time | 117.6 seconds |
| Started | Jul 27 08:30:51 PM PDT 24 |
| Finished | Jul 27 08:32:49 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-c4332f90-a9cb-47dd-9ff4-78bd6cbbd506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051530109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 3051530109 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3750065702 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 87598036675 ps |
| CPU time | 1589.92 seconds |
| Started | Jul 27 08:30:53 PM PDT 24 |
| Finished | Jul 27 08:57:23 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-4c7322d6-051e-4885-8f64-4452dce977a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750065702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.3750065702 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3562929181 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 1366634376 ps |
| CPU time | 62.72 seconds |
| Started | Jul 27 08:30:52 PM PDT 24 |
| Finished | Jul 27 08:31:55 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-e693d42e-f8fc-4ae9-9a53-2a4e0a1b33c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562929181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .3562929181 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.183623410 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 1836567321 ps |
| CPU time | 65.28 seconds |
| Started | Jul 27 08:30:52 PM PDT 24 |
| Finished | Jul 27 08:31:58 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-d3b26e10-cee0-427b-b786-0d20a9de252b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183623410 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.183623410 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.3197339609 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 1609801370 ps |
| CPU time | 67.52 seconds |
| Started | Jul 27 08:30:50 PM PDT 24 |
| Finished | Jul 27 08:31:57 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-5a5f8e1e-3549-403a-a039-e37ffcbc41b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197339609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3197339609 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1770633653 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 34799438535 ps |
| CPU time | 361.21 seconds |
| Started | Jul 27 08:30:49 PM PDT 24 |
| Finished | Jul 27 08:36:50 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-20c17706-1fe0-4a3a-9b27-511255efb097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770633653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1770633653 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1515665916 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 5475180724 ps |
| CPU time | 97.18 seconds |
| Started | Jul 27 08:30:49 PM PDT 24 |
| Finished | Jul 27 08:32:26 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-f6cf4085-eae3-4bb0-8623-4e9b0a89a15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515665916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1515665916 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2507371032 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 210314161 ps |
| CPU time | 23.1 seconds |
| Started | Jul 27 08:30:49 PM PDT 24 |
| Finished | Jul 27 08:31:12 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-4cfa271a-eba3-48fe-b36b-0459adb9a64b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507371032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2507371032 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1780654847 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 331170268 ps |
| CPU time | 14.24 seconds |
| Started | Jul 27 08:30:53 PM PDT 24 |
| Finished | Jul 27 08:31:07 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-d0cf1afb-fa5b-4cec-a7d0-cd5d21b84e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780654847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1780654847 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.122625451 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 40053990 ps |
| CPU time | 6.47 seconds |
| Started | Jul 27 08:30:43 PM PDT 24 |
| Finished | Jul 27 08:30:50 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-6355989c-6b89-4fd5-8822-bcd281dd4b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122625451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.122625451 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3663232706 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 6529950109 ps |
| CPU time | 69.3 seconds |
| Started | Jul 27 08:30:41 PM PDT 24 |
| Finished | Jul 27 08:31:51 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-8920cc77-3494-4229-980f-832bf5d941b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663232706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3663232706 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.926149051 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 5188037541 ps |
| CPU time | 89.11 seconds |
| Started | Jul 27 08:30:48 PM PDT 24 |
| Finished | Jul 27 08:32:17 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-ef334d85-9494-4b19-a76e-3b967f7d3571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926149051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.926149051 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1880766612 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 48670325 ps |
| CPU time | 6.88 seconds |
| Started | Jul 27 08:30:43 PM PDT 24 |
| Finished | Jul 27 08:30:50 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-40aa2563-e1d5-4d5d-b1f8-90fcf079bd5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880766612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .1880766612 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.3552063109 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3498921175 ps |
| CPU time | 295.84 seconds |
| Started | Jul 27 08:31:00 PM PDT 24 |
| Finished | Jul 27 08:35:56 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-90dbdd28-8786-4fee-9634-0ffd4bb0b9a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552063109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3552063109 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.998532420 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 18294749966 ps |
| CPU time | 779.01 seconds |
| Started | Jul 27 08:30:58 PM PDT 24 |
| Finished | Jul 27 08:43:57 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-266bb7d6-f3e4-49c8-be80-3d204245453c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998532420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.998532420 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1782550277 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 6793341788 ps |
| CPU time | 348.77 seconds |
| Started | Jul 27 08:30:59 PM PDT 24 |
| Finished | Jul 27 08:36:48 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-760c7560-0a88-4ddf-a93d-dd72950b6bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782550277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1782550277 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.459907482 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 522193189 ps |
| CPU time | 166.28 seconds |
| Started | Jul 27 08:30:59 PM PDT 24 |
| Finished | Jul 27 08:33:45 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-dbd98938-65f1-4daf-82a0-99deac997d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459907482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.459907482 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.716130897 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 1582632126 ps |
| CPU time | 71.38 seconds |
| Started | Jul 27 08:30:49 PM PDT 24 |
| Finished | Jul 27 08:32:00 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-504c4fd3-c6a9-48a6-a975-779651677667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716130897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.716130897 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2916774830 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 2062031080 ps |
| CPU time | 89.21 seconds |
| Started | Jul 27 08:48:14 PM PDT 24 |
| Finished | Jul 27 08:49:43 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-1264d452-d3ee-454c-a002-061a7af4166d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916774830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2916774830 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.154444755 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 127561304806 ps |
| CPU time | 2124.25 seconds |
| Started | Jul 27 08:48:07 PM PDT 24 |
| Finished | Jul 27 09:23:32 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-6471c483-b339-4644-8d05-69a572045dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154444755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.154444755 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.4200799660 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 394697057 ps |
| CPU time | 17.57 seconds |
| Started | Jul 27 08:48:11 PM PDT 24 |
| Finished | Jul 27 08:48:29 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-163014f1-5117-4bba-9e9d-e8447ab6dc0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200799660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.4200799660 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1384359022 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 581523094 ps |
| CPU time | 45.88 seconds |
| Started | Jul 27 08:48:11 PM PDT 24 |
| Finished | Jul 27 08:48:57 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-09955199-5f60-4f78-8a86-89a0db1099d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384359022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1384359022 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.1821204224 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 1835566213 ps |
| CPU time | 67.57 seconds |
| Started | Jul 27 08:48:07 PM PDT 24 |
| Finished | Jul 27 08:49:14 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-d68eb26d-cd9e-42e8-a252-b2144c4e9832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821204224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.1821204224 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2623164820 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 93188936398 ps |
| CPU time | 964.23 seconds |
| Started | Jul 27 08:48:10 PM PDT 24 |
| Finished | Jul 27 09:04:14 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-167afd07-4b9a-4fee-b912-e00270835648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623164820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2623164820 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.385643743 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 30456207300 ps |
| CPU time | 525.47 seconds |
| Started | Jul 27 08:48:11 PM PDT 24 |
| Finished | Jul 27 08:56:57 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-36147142-c4b3-4530-bd74-67dd22dd2cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385643743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.385643743 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.184306798 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 564287778 ps |
| CPU time | 50.89 seconds |
| Started | Jul 27 08:48:07 PM PDT 24 |
| Finished | Jul 27 08:48:58 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-12ed74f5-4061-4bf7-b2c1-3f671a0b1a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184306798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_dela ys.184306798 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.3068678421 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 2188816760 ps |
| CPU time | 65.05 seconds |
| Started | Jul 27 08:48:12 PM PDT 24 |
| Finished | Jul 27 08:49:17 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-ab8c8a80-7caa-472a-8dbb-a2811467e040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068678421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3068678421 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.377843593 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 136051181 ps |
| CPU time | 8.07 seconds |
| Started | Jul 27 08:48:08 PM PDT 24 |
| Finished | Jul 27 08:48:16 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-01af1dcc-aa42-45ed-89de-40cb63eacffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377843593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.377843593 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2349337433 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 8946909372 ps |
| CPU time | 99.88 seconds |
| Started | Jul 27 08:48:11 PM PDT 24 |
| Finished | Jul 27 08:49:51 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-a15eab54-4e54-48d6-8b35-6b9fee6f19c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349337433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2349337433 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3269480447 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 4145167634 ps |
| CPU time | 70.63 seconds |
| Started | Jul 27 08:48:10 PM PDT 24 |
| Finished | Jul 27 08:49:21 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-d3cce907-a668-4ac7-8349-4fb78a026290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269480447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3269480447 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.863667072 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 46295252 ps |
| CPU time | 6.06 seconds |
| Started | Jul 27 08:48:08 PM PDT 24 |
| Finished | Jul 27 08:48:14 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-6b814406-e9c8-4ad0-b1b6-86319f73f0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863667072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays .863667072 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.3918497506 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 1417449829 ps |
| CPU time | 126.95 seconds |
| Started | Jul 27 08:48:17 PM PDT 24 |
| Finished | Jul 27 08:50:24 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-52fbe043-e587-4bc7-8d20-e7298d64e355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918497506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.3918497506 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3710307126 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 12672410598 ps |
| CPU time | 458.29 seconds |
| Started | Jul 27 08:48:12 PM PDT 24 |
| Finished | Jul 27 08:55:50 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-d778173c-d73f-4e13-9858-2a423d024ba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710307126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3710307126 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2513982673 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 6936251 ps |
| CPU time | 12.38 seconds |
| Started | Jul 27 08:48:13 PM PDT 24 |
| Finished | Jul 27 08:48:26 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-64ed8797-4c63-41c3-a763-bf9a030f835d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513982673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.2513982673 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1331042198 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 546083682 ps |
| CPU time | 137.23 seconds |
| Started | Jul 27 08:48:12 PM PDT 24 |
| Finished | Jul 27 08:50:29 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-a844ad29-23bd-4f6f-b3a8-f06c381da9cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331042198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.1331042198 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2451948224 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1110521208 ps |
| CPU time | 51.48 seconds |
| Started | Jul 27 08:48:09 PM PDT 24 |
| Finished | Jul 27 08:49:01 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-af7e5e67-cce6-498c-a954-e09f3f9fbed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451948224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2451948224 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.534227515 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 520612796 ps |
| CPU time | 47.92 seconds |
| Started | Jul 27 08:48:20 PM PDT 24 |
| Finished | Jul 27 08:49:08 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-57b9ab6f-4a02-45f4-844a-298888e700ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534227515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device. 534227515 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3248325654 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 23415840138 ps |
| CPU time | 411.44 seconds |
| Started | Jul 27 08:48:20 PM PDT 24 |
| Finished | Jul 27 08:55:11 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-46c6c90c-a4db-4a06-89a4-69ae7d1e95f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248325654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3248325654 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2174134369 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 176115874 ps |
| CPU time | 21.59 seconds |
| Started | Jul 27 08:48:21 PM PDT 24 |
| Finished | Jul 27 08:48:43 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-fb944826-aada-4240-80ee-67f3b0c48061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174134369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2174134369 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.1244774232 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 75885913 ps |
| CPU time | 10.01 seconds |
| Started | Jul 27 08:48:21 PM PDT 24 |
| Finished | Jul 27 08:48:31 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-50f925f5-6566-4ebc-831c-806a92d0da87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244774232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1244774232 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.2892641323 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 2085440408 ps |
| CPU time | 77.87 seconds |
| Started | Jul 27 08:48:13 PM PDT 24 |
| Finished | Jul 27 08:49:31 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-2399c826-94c6-49a0-bc31-9d2d87c79145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892641323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2892641323 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.238717960 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 63948214032 ps |
| CPU time | 697.43 seconds |
| Started | Jul 27 08:48:15 PM PDT 24 |
| Finished | Jul 27 08:59:53 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-df440b89-218f-46a4-b673-67a4c6a8cd80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238717960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.238717960 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.66322113 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 3990039083 ps |
| CPU time | 67.14 seconds |
| Started | Jul 27 08:48:18 PM PDT 24 |
| Finished | Jul 27 08:49:26 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-32dbaf14-2eb8-4653-87aa-977075b2c6cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66322113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.66322113 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1974104755 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 601853359 ps |
| CPU time | 55.05 seconds |
| Started | Jul 27 08:48:13 PM PDT 24 |
| Finished | Jul 27 08:49:08 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b1fd8823-747e-4580-891f-523fea5f617e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974104755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.1974104755 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.2609203043 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 200510010 ps |
| CPU time | 16.11 seconds |
| Started | Jul 27 08:48:19 PM PDT 24 |
| Finished | Jul 27 08:48:35 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-09fa2425-05fd-4a19-861f-22dddfa9d209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609203043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.2609203043 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.1645224536 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 227614386 ps |
| CPU time | 10.31 seconds |
| Started | Jul 27 08:48:12 PM PDT 24 |
| Finished | Jul 27 08:48:23 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-187055b8-7e12-45d4-8a42-cecb68ca122a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645224536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1645224536 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.3970113322 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 9254703102 ps |
| CPU time | 98.11 seconds |
| Started | Jul 27 08:48:13 PM PDT 24 |
| Finished | Jul 27 08:49:52 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-38bf4eff-16c5-4ed2-8132-4c78ce6b9597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970113322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.3970113322 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.4179108128 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 4013352264 ps |
| CPU time | 68.39 seconds |
| Started | Jul 27 08:48:13 PM PDT 24 |
| Finished | Jul 27 08:49:21 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-a81ec824-c5d0-4e60-855a-7ab7fdeb0180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179108128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.4179108128 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.3062575050 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 53098643 ps |
| CPU time | 6.48 seconds |
| Started | Jul 27 08:48:13 PM PDT 24 |
| Finished | Jul 27 08:48:20 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-fb6ea43e-6b6f-4961-b827-8ef08dccd83d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062575050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.3062575050 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.821525264 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 2954525296 ps |
| CPU time | 222 seconds |
| Started | Jul 27 08:48:33 PM PDT 24 |
| Finished | Jul 27 08:52:15 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-0625c9aa-d883-4492-bc9a-1833d2cebb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821525264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.821525264 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.918552802 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 8520148011 ps |
| CPU time | 306.15 seconds |
| Started | Jul 27 08:48:30 PM PDT 24 |
| Finished | Jul 27 08:53:36 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-7f54690c-3fbb-49b4-9067-902b6d7c3074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918552802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.918552802 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2345178188 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2450385775 ps |
| CPU time | 286.56 seconds |
| Started | Jul 27 08:48:33 PM PDT 24 |
| Finished | Jul 27 08:53:19 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-5867d6e0-4699-4af9-a6d1-ef153bd9a992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345178188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.2345178188 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2500725405 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 2407701459 ps |
| CPU time | 209.67 seconds |
| Started | Jul 27 08:48:30 PM PDT 24 |
| Finished | Jul 27 08:51:59 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-534fb880-dc8e-4af0-81bc-08b856d98ff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500725405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2500725405 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1098833878 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 65834908 ps |
| CPU time | 11.8 seconds |
| Started | Jul 27 08:48:20 PM PDT 24 |
| Finished | Jul 27 08:48:32 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-ffbd234e-43d3-47ae-a75a-8356ece43836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098833878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1098833878 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1234992980 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 15773058 ps |
| CPU time | 6.35 seconds |
| Started | Jul 27 08:48:38 PM PDT 24 |
| Finished | Jul 27 08:48:45 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-1729d9aa-8719-4d66-bef2-0c8a3b7d64d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234992980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1234992980 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.382152962 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 12862642800 ps |
| CPU time | 233.05 seconds |
| Started | Jul 27 08:48:36 PM PDT 24 |
| Finished | Jul 27 08:52:29 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-100ddcaf-e370-4b94-a85e-0510a4817cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382152962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.382152962 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3306368603 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 935021687 ps |
| CPU time | 39.11 seconds |
| Started | Jul 27 08:48:37 PM PDT 24 |
| Finished | Jul 27 08:49:16 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d8b912a6-8969-4a18-a334-2ead4ee125f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306368603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.3306368603 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.3989177230 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 563441711 ps |
| CPU time | 45.59 seconds |
| Started | Jul 27 08:48:40 PM PDT 24 |
| Finished | Jul 27 08:49:25 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-84b65cf7-2043-43e4-a95b-f99cf38b0c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989177230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.3989177230 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.3911363142 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 1160775049 ps |
| CPU time | 43.67 seconds |
| Started | Jul 27 08:48:29 PM PDT 24 |
| Finished | Jul 27 08:49:12 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-82565eb7-784b-4120-a8e4-2952bd02f47b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911363142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.3911363142 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.766951407 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 5305148587 ps |
| CPU time | 55.66 seconds |
| Started | Jul 27 08:48:32 PM PDT 24 |
| Finished | Jul 27 08:49:27 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-53656247-4485-416a-807e-b6e11cb28e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766951407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.766951407 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1299502498 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 55611938613 ps |
| CPU time | 955.33 seconds |
| Started | Jul 27 08:48:35 PM PDT 24 |
| Finished | Jul 27 09:04:31 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-ac2a9ce4-b9b4-4c4c-9494-dbe28abc2db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299502498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1299502498 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2042822488 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 402243582 ps |
| CPU time | 39.13 seconds |
| Started | Jul 27 08:48:29 PM PDT 24 |
| Finished | Jul 27 08:49:08 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-ff186ed7-05aa-48ee-b407-7dd1ea8cdc7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042822488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2042822488 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3406829843 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 254567938 ps |
| CPU time | 19.04 seconds |
| Started | Jul 27 08:48:35 PM PDT 24 |
| Finished | Jul 27 08:48:54 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-c2a02cdb-c033-49da-9df8-65578af62fb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406829843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3406829843 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.816811096 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 61271539 ps |
| CPU time | 7.74 seconds |
| Started | Jul 27 08:48:30 PM PDT 24 |
| Finished | Jul 27 08:48:38 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-06b9a471-16b1-4dde-8e7d-0bb1049d3787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816811096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.816811096 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3478140994 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 8283952980 ps |
| CPU time | 83.41 seconds |
| Started | Jul 27 08:48:29 PM PDT 24 |
| Finished | Jul 27 08:49:53 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-84fe1fdc-5065-468d-a213-e6e31df516aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478140994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3478140994 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.1936967837 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 5760231730 ps |
| CPU time | 95.61 seconds |
| Started | Jul 27 08:48:34 PM PDT 24 |
| Finished | Jul 27 08:50:09 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-7a8350f2-3f81-4226-b29b-12a987bd77e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936967837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.1936967837 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3298619269 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 51412427 ps |
| CPU time | 7.02 seconds |
| Started | Jul 27 08:48:29 PM PDT 24 |
| Finished | Jul 27 08:48:36 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-4a6d7490-fe4e-4904-9523-e2dc212d8aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298619269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3298619269 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2756629013 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 11624542833 ps |
| CPU time | 411.77 seconds |
| Started | Jul 27 08:48:37 PM PDT 24 |
| Finished | Jul 27 08:55:29 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-49be9480-e3dc-445d-9c58-2517f64937d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756629013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2756629013 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2155743929 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 6769126839 ps |
| CPU time | 239.47 seconds |
| Started | Jul 27 08:48:35 PM PDT 24 |
| Finished | Jul 27 08:52:35 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-1b003b22-67d6-48a0-94c1-427ee50bf5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155743929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2155743929 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2131574366 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 3337225693 ps |
| CPU time | 448.06 seconds |
| Started | Jul 27 08:48:37 PM PDT 24 |
| Finished | Jul 27 08:56:05 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-5e87ffbb-a7f1-4525-a8e3-1ba97e5d3c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131574366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2131574366 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2577521941 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 2233955961 ps |
| CPU time | 371.4 seconds |
| Started | Jul 27 08:48:36 PM PDT 24 |
| Finished | Jul 27 08:54:47 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-16fb1da1-756e-42eb-a63e-4577956b9576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577521941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2577521941 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2825979731 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 617360353 ps |
| CPU time | 28.07 seconds |
| Started | Jul 27 08:48:35 PM PDT 24 |
| Finished | Jul 27 08:49:04 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-7c146789-b1d8-4b13-8a97-cf96c87bbd77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825979731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2825979731 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.1260190778 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 2560711349 ps |
| CPU time | 99.93 seconds |
| Started | Jul 27 08:48:49 PM PDT 24 |
| Finished | Jul 27 08:50:29 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-9700a77a-9319-4f9c-b9b3-86f5ffab8e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260190778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .1260190778 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1795333726 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 121943554736 ps |
| CPU time | 2063.93 seconds |
| Started | Jul 27 08:48:48 PM PDT 24 |
| Finished | Jul 27 09:23:12 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-48101c15-49fb-4a4b-b99b-734278726d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795333726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.1795333726 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2519778120 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 73417500 ps |
| CPU time | 11.29 seconds |
| Started | Jul 27 08:48:50 PM PDT 24 |
| Finished | Jul 27 08:49:01 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-d16b913c-399b-4230-9748-4b067a05d0ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519778120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2519778120 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.629705519 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 550087655 ps |
| CPU time | 40.32 seconds |
| Started | Jul 27 08:48:46 PM PDT 24 |
| Finished | Jul 27 08:49:27 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d936510f-9d58-4b87-87f9-f40fba2e55bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629705519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.629705519 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3481478415 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 410132154 ps |
| CPU time | 35.01 seconds |
| Started | Jul 27 08:48:47 PM PDT 24 |
| Finished | Jul 27 08:49:22 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-2e428af2-85ba-4c75-9514-038034153111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481478415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3481478415 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.4202781664 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 17324216433 ps |
| CPU time | 188.34 seconds |
| Started | Jul 27 08:48:47 PM PDT 24 |
| Finished | Jul 27 08:51:55 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-0c633c8a-c0d8-48c5-b6e4-c021d39df851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202781664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.4202781664 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3000361409 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 29329101965 ps |
| CPU time | 533.72 seconds |
| Started | Jul 27 08:48:48 PM PDT 24 |
| Finished | Jul 27 08:57:42 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-70e8f4a7-1498-4d50-a1fd-d1ec7b89e98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000361409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3000361409 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.200195504 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 515648955 ps |
| CPU time | 39.43 seconds |
| Started | Jul 27 08:48:51 PM PDT 24 |
| Finished | Jul 27 08:49:31 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-e994b466-a855-45aa-9c81-1a8df9542269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200195504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela ys.200195504 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.1100773495 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 421381778 ps |
| CPU time | 33.63 seconds |
| Started | Jul 27 08:48:49 PM PDT 24 |
| Finished | Jul 27 08:49:23 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-57a4d0aa-f867-4177-bf5d-ebe66f0dcc17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100773495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.1100773495 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3370090750 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 274884361 ps |
| CPU time | 11.53 seconds |
| Started | Jul 27 08:48:36 PM PDT 24 |
| Finished | Jul 27 08:48:48 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-ab6c9d5b-55cb-43be-a7cd-a4188f66d7d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370090750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3370090750 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1096941044 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 7102274151 ps |
| CPU time | 69.34 seconds |
| Started | Jul 27 08:48:34 PM PDT 24 |
| Finished | Jul 27 08:49:43 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-b093a3d4-8e08-40f1-8b13-a515abf5c52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096941044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1096941044 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3441077759 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 5103682086 ps |
| CPU time | 88.67 seconds |
| Started | Jul 27 08:48:36 PM PDT 24 |
| Finished | Jul 27 08:50:04 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-893bbce7-261b-4c2b-a6d4-ddef2e00538b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441077759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3441077759 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2112723440 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 45608190 ps |
| CPU time | 6.33 seconds |
| Started | Jul 27 08:48:36 PM PDT 24 |
| Finished | Jul 27 08:48:42 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-e07f37c9-7b3f-4256-a26e-764877af6ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112723440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2112723440 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.1640222242 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 14190342307 ps |
| CPU time | 492.36 seconds |
| Started | Jul 27 08:48:52 PM PDT 24 |
| Finished | Jul 27 08:57:04 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-bc4b6787-73ef-46a9-ab73-a069ddb22052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640222242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1640222242 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3099037239 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 11873125411 ps |
| CPU time | 413.13 seconds |
| Started | Jul 27 08:48:58 PM PDT 24 |
| Finished | Jul 27 08:55:52 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-9882a6a4-f806-4141-978a-61f9192ea2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099037239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3099037239 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1038698555 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 8553255769 ps |
| CPU time | 934.2 seconds |
| Started | Jul 27 08:48:47 PM PDT 24 |
| Finished | Jul 27 09:04:22 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-65a656cf-e0dd-49f7-bfa4-dba5c5b6f829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038698555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1038698555 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2522392247 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 1095532855 ps |
| CPU time | 92.72 seconds |
| Started | Jul 27 08:48:57 PM PDT 24 |
| Finished | Jul 27 08:50:30 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-4f82994d-049b-4034-ac17-d179a75eb132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522392247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2522392247 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.183507011 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 495618133 ps |
| CPU time | 25.37 seconds |
| Started | Jul 27 08:48:47 PM PDT 24 |
| Finished | Jul 27 08:49:12 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-3494ddda-b797-421e-9a79-6797f71a63ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183507011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.183507011 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1083345946 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 2936498828 ps |
| CPU time | 141.47 seconds |
| Started | Jul 27 08:48:53 PM PDT 24 |
| Finished | Jul 27 08:51:14 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-57646c73-5f82-4cb3-bcee-09298b7ebb5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083345946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1083345946 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.654433507 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 306844236 ps |
| CPU time | 31.74 seconds |
| Started | Jul 27 08:48:54 PM PDT 24 |
| Finished | Jul 27 08:49:26 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-da1e96a8-a17f-4004-a4f8-ef52a7d58e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654433507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr .654433507 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.4163830690 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 31221689 ps |
| CPU time | 6.3 seconds |
| Started | Jul 27 08:48:55 PM PDT 24 |
| Finished | Jul 27 08:49:01 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-cb65b379-2721-4b23-bdc0-78b83a9b1bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163830690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.4163830690 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.1731856631 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 227836875 ps |
| CPU time | 24.06 seconds |
| Started | Jul 27 08:48:54 PM PDT 24 |
| Finished | Jul 27 08:49:18 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f9e20173-6272-4703-ba94-2af63106f143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731856631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.1731856631 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3014058862 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 4364062112 ps |
| CPU time | 46.72 seconds |
| Started | Jul 27 08:48:56 PM PDT 24 |
| Finished | Jul 27 08:49:42 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-bbc055bc-d0fe-449d-88e3-ea8d52eb6812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014058862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3014058862 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3566427840 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 7916392082 ps |
| CPU time | 138.06 seconds |
| Started | Jul 27 08:48:59 PM PDT 24 |
| Finished | Jul 27 08:51:17 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-e0c93276-21d7-433d-b92f-d7a4806ddd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566427840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3566427840 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.579877251 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 397270008 ps |
| CPU time | 35.63 seconds |
| Started | Jul 27 08:48:56 PM PDT 24 |
| Finished | Jul 27 08:49:32 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-e2044ad2-241f-47db-9019-c8571984333e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579877251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_dela ys.579877251 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3054207165 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 1063011625 ps |
| CPU time | 35.44 seconds |
| Started | Jul 27 08:49:00 PM PDT 24 |
| Finished | Jul 27 08:49:35 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-0bf451b0-2a0f-40e7-a05d-0116c8f4de79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054207165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3054207165 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.2290369651 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 186739491 ps |
| CPU time | 9.78 seconds |
| Started | Jul 27 08:48:55 PM PDT 24 |
| Finished | Jul 27 08:49:05 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-71a4a6b9-d505-4895-b575-a9a1c1384be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290369651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2290369651 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3586627299 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 8455528682 ps |
| CPU time | 93.65 seconds |
| Started | Jul 27 08:48:58 PM PDT 24 |
| Finished | Jul 27 08:50:32 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-1ebd66bd-0094-4de3-bd20-0f1599d703f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586627299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3586627299 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3085833965 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 3118848599 ps |
| CPU time | 55.35 seconds |
| Started | Jul 27 08:48:59 PM PDT 24 |
| Finished | Jul 27 08:49:55 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-45a3426b-8a92-443b-9f96-0706686071fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085833965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3085833965 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.383996657 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 48199996 ps |
| CPU time | 6.96 seconds |
| Started | Jul 27 08:48:52 PM PDT 24 |
| Finished | Jul 27 08:48:59 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-c26381ec-cb61-4d92-a273-a491b1883ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383996657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .383996657 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.2628013724 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 1102421949 ps |
| CPU time | 86.87 seconds |
| Started | Jul 27 08:48:56 PM PDT 24 |
| Finished | Jul 27 08:50:23 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-fa768640-bd18-4ef3-b65a-f6a0f4482e4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628013724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.2628013724 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2233795793 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 1731893844 ps |
| CPU time | 113.73 seconds |
| Started | Jul 27 08:48:56 PM PDT 24 |
| Finished | Jul 27 08:50:50 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-25f5375e-759e-4fca-a0b3-b3784db7f51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233795793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2233795793 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.1311896476 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 412924266 ps |
| CPU time | 142.67 seconds |
| Started | Jul 27 08:48:57 PM PDT 24 |
| Finished | Jul 27 08:51:19 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-e5d17afe-14db-4027-8706-171a095b1195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311896476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.1311896476 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.499368369 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 4202794530 ps |
| CPU time | 392.01 seconds |
| Started | Jul 27 08:49:10 PM PDT 24 |
| Finished | Jul 27 08:55:42 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-9ccf465c-252e-4414-91e5-eaf17285d6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499368369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.499368369 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1764727199 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 183315940 ps |
| CPU time | 23.91 seconds |
| Started | Jul 27 08:48:55 PM PDT 24 |
| Finished | Jul 27 08:49:19 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-af373a32-edad-4f03-ad81-2bd855576478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764727199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1764727199 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2799963079 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 590053667 ps |
| CPU time | 47.14 seconds |
| Started | Jul 27 08:49:03 PM PDT 24 |
| Finished | Jul 27 08:49:50 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-503d63be-9095-42be-aa18-3169171fdac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799963079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2799963079 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.88528414 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 59505105752 ps |
| CPU time | 1057.91 seconds |
| Started | Jul 27 08:49:03 PM PDT 24 |
| Finished | Jul 27 09:06:41 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-570d687c-e142-4526-b65e-837e65c4a6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88528414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_de vice_slow_rsp.88528414 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2928609030 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 1122162503 ps |
| CPU time | 37.32 seconds |
| Started | Jul 27 08:49:10 PM PDT 24 |
| Finished | Jul 27 08:49:48 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-215fe434-370a-44f6-8614-2b7f7eeb8098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928609030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2928609030 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3496917863 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 146309053 ps |
| CPU time | 8.39 seconds |
| Started | Jul 27 08:49:01 PM PDT 24 |
| Finished | Jul 27 08:49:10 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-3872a320-a80e-4eda-9a67-75117e72e060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496917863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3496917863 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1680574374 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 1688901488 ps |
| CPU time | 70.78 seconds |
| Started | Jul 27 08:49:03 PM PDT 24 |
| Finished | Jul 27 08:50:14 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-598bc033-18c6-40ff-8e27-f4d8f783bfe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680574374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1680574374 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.484003225 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 66351040920 ps |
| CPU time | 746.11 seconds |
| Started | Jul 27 08:49:04 PM PDT 24 |
| Finished | Jul 27 09:01:30 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c7582933-a8e8-4c15-8135-c403723b5897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484003225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.484003225 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.3574934981 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 60761147296 ps |
| CPU time | 1075.92 seconds |
| Started | Jul 27 08:49:03 PM PDT 24 |
| Finished | Jul 27 09:06:59 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-6fd81a98-1560-44ee-bffd-1f0200052537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574934981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.3574934981 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2957831640 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 358528941 ps |
| CPU time | 29.63 seconds |
| Started | Jul 27 08:49:07 PM PDT 24 |
| Finished | Jul 27 08:49:37 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-fbba97eb-5102-4328-9219-5c153e038541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957831640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2957831640 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.3885962671 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 457384693 ps |
| CPU time | 37.14 seconds |
| Started | Jul 27 08:49:05 PM PDT 24 |
| Finished | Jul 27 08:49:42 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-032666ab-ea03-4c96-9b33-211cc7842af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885962671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3885962671 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.3887710810 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 37649082 ps |
| CPU time | 6.39 seconds |
| Started | Jul 27 08:49:02 PM PDT 24 |
| Finished | Jul 27 08:49:09 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-6bf503c3-c011-4750-99bd-88e74a20ed2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887710810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3887710810 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.398463000 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 6864768495 ps |
| CPU time | 73.5 seconds |
| Started | Jul 27 08:49:03 PM PDT 24 |
| Finished | Jul 27 08:50:16 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-1b71ed8b-9547-4569-ad22-8aa7f49bd002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398463000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.398463000 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2048736923 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 5809382091 ps |
| CPU time | 101.1 seconds |
| Started | Jul 27 08:49:07 PM PDT 24 |
| Finished | Jul 27 08:50:48 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-c9e68125-5d52-44b0-b287-dc3cb03e049a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048736923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2048736923 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.236014652 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 45621167 ps |
| CPU time | 6.62 seconds |
| Started | Jul 27 08:49:04 PM PDT 24 |
| Finished | Jul 27 08:49:11 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-f84468a2-f51c-42e3-82a8-8f26d48fb7f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236014652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays .236014652 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1730682066 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 8241608650 ps |
| CPU time | 305.02 seconds |
| Started | Jul 27 08:49:03 PM PDT 24 |
| Finished | Jul 27 08:54:08 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-0d026331-ad8e-414e-a62d-50ba92c188d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730682066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1730682066 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.488838401 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 10215168027 ps |
| CPU time | 391.82 seconds |
| Started | Jul 27 08:49:10 PM PDT 24 |
| Finished | Jul 27 08:55:42 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-f279c445-72e5-44af-b4b5-be2eac0b1691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488838401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.488838401 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1095090953 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 300168224 ps |
| CPU time | 147.12 seconds |
| Started | Jul 27 08:49:02 PM PDT 24 |
| Finished | Jul 27 08:51:30 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-204c1cc2-a18e-48d7-a6d0-63d16e6ee9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095090953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1095090953 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.751706154 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 6349208407 ps |
| CPU time | 499.74 seconds |
| Started | Jul 27 08:49:12 PM PDT 24 |
| Finished | Jul 27 08:57:31 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-998456ee-9dc3-4e52-826c-f97db50105e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751706154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_reset_error.751706154 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.3790969322 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 250632125 ps |
| CPU time | 28.46 seconds |
| Started | Jul 27 08:49:01 PM PDT 24 |
| Finished | Jul 27 08:49:30 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-b89db642-9eee-4789-8804-967e4c4fbfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790969322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.3790969322 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1821104892 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 708495669 ps |
| CPU time | 61.09 seconds |
| Started | Jul 27 08:49:20 PM PDT 24 |
| Finished | Jul 27 08:50:21 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-092bc24e-39e4-4507-ad8d-938cb787a4de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821104892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1821104892 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2842593046 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 110067967413 ps |
| CPU time | 1667.9 seconds |
| Started | Jul 27 08:49:25 PM PDT 24 |
| Finished | Jul 27 09:17:14 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-123882ad-2937-436e-9111-c71e74384190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842593046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2842593046 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.879614857 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 453565210 ps |
| CPU time | 21.21 seconds |
| Started | Jul 27 08:49:22 PM PDT 24 |
| Finished | Jul 27 08:49:43 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-323a714d-b86f-4315-9b1c-32da33e6e9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879614857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr .879614857 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.1705763837 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 2103942133 ps |
| CPU time | 69.72 seconds |
| Started | Jul 27 08:49:24 PM PDT 24 |
| Finished | Jul 27 08:50:34 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-c07f3d0a-a19d-4ab8-a420-addf0ef94efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705763837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1705763837 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1833756813 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 263455007 ps |
| CPU time | 13.63 seconds |
| Started | Jul 27 08:49:12 PM PDT 24 |
| Finished | Jul 27 08:49:25 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-4eef091f-96b3-4e6c-b69e-752c8a242e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833756813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1833756813 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2573570061 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 89312351432 ps |
| CPU time | 917.21 seconds |
| Started | Jul 27 08:49:20 PM PDT 24 |
| Finished | Jul 27 09:04:37 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-6c01f7a7-3872-44dd-bf0d-e1c35df4bc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573570061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2573570061 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3284681623 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 19347948116 ps |
| CPU time | 344.44 seconds |
| Started | Jul 27 08:49:20 PM PDT 24 |
| Finished | Jul 27 08:55:05 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-60c7240c-0c51-4db1-9a6f-090a366da088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284681623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.3284681623 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2773009476 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 367747039 ps |
| CPU time | 36.4 seconds |
| Started | Jul 27 08:49:13 PM PDT 24 |
| Finished | Jul 27 08:49:49 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-ea0903c2-dd40-4a15-a2e8-56109be574fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773009476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2773009476 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3185936874 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 129313417 ps |
| CPU time | 12.71 seconds |
| Started | Jul 27 08:49:24 PM PDT 24 |
| Finished | Jul 27 08:49:37 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-deb6f05e-2268-4676-8e56-0a67c65200b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185936874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3185936874 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.1157648107 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 217285883 ps |
| CPU time | 9.85 seconds |
| Started | Jul 27 08:49:12 PM PDT 24 |
| Finished | Jul 27 08:49:22 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-9f5c9c5a-5777-4c04-a894-29e1c05ce1f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157648107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.1157648107 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2071384775 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 9295891836 ps |
| CPU time | 100.85 seconds |
| Started | Jul 27 08:49:10 PM PDT 24 |
| Finished | Jul 27 08:50:51 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-3d142521-6aaf-4d42-b7b2-e0d213594f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071384775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2071384775 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.561064547 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4654108558 ps |
| CPU time | 78.12 seconds |
| Started | Jul 27 08:49:13 PM PDT 24 |
| Finished | Jul 27 08:50:31 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-8d550d17-f0fb-4c16-8f6e-618b404438d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561064547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.561064547 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2410921308 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 50398880 ps |
| CPU time | 6.86 seconds |
| Started | Jul 27 08:49:13 PM PDT 24 |
| Finished | Jul 27 08:49:19 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-aee73829-0f0a-4ee2-b581-37a3901658b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410921308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.2410921308 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.1160849903 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 6291271162 ps |
| CPU time | 300.34 seconds |
| Started | Jul 27 08:49:25 PM PDT 24 |
| Finished | Jul 27 08:54:26 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-4be92460-4c59-460f-8a77-7fa602a365a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160849903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1160849903 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.523962354 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 256817653 ps |
| CPU time | 25.32 seconds |
| Started | Jul 27 08:49:19 PM PDT 24 |
| Finished | Jul 27 08:49:44 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-b6af7ef9-0c16-430f-9c12-6d648324a605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523962354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.523962354 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3874808207 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 183730887 ps |
| CPU time | 92.63 seconds |
| Started | Jul 27 08:49:21 PM PDT 24 |
| Finished | Jul 27 08:50:54 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-f7947c81-28e7-46c8-8551-b82673ce9130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874808207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3874808207 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1756046360 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 1379443995 ps |
| CPU time | 50.29 seconds |
| Started | Jul 27 08:49:25 PM PDT 24 |
| Finished | Jul 27 08:50:15 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-b4ef32b0-eb67-4e5d-9bf3-8eeed7715c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756046360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1756046360 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2821522930 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 603856148 ps |
| CPU time | 43.18 seconds |
| Started | Jul 27 08:49:29 PM PDT 24 |
| Finished | Jul 27 08:50:12 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-cb3b40c1-0735-43cd-b307-dc0675982cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821522930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2821522930 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.2278517310 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 148102726213 ps |
| CPU time | 2452.71 seconds |
| Started | Jul 27 08:49:33 PM PDT 24 |
| Finished | Jul 27 09:30:26 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-6af7d73d-05fd-4d84-8b3f-e687f6e394ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278517310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.2278517310 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1929333562 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 572101321 ps |
| CPU time | 25 seconds |
| Started | Jul 27 08:49:33 PM PDT 24 |
| Finished | Jul 27 08:49:58 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-752e711e-5863-4312-976e-540d368008b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929333562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1929333562 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2597534089 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 235535088 ps |
| CPU time | 21.79 seconds |
| Started | Jul 27 08:49:30 PM PDT 24 |
| Finished | Jul 27 08:49:52 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-82804461-d4cb-400e-a7b4-91aa3071660b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597534089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2597534089 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.4138294623 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 241575788 ps |
| CPU time | 23.83 seconds |
| Started | Jul 27 08:49:28 PM PDT 24 |
| Finished | Jul 27 08:49:51 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-13fe1fc5-dc8d-4673-9051-2f3f55f33dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138294623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.4138294623 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1961328212 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 43924169624 ps |
| CPU time | 479.98 seconds |
| Started | Jul 27 08:49:31 PM PDT 24 |
| Finished | Jul 27 08:57:31 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-04bc5832-1b8a-4983-a2a9-c824a5e49de6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961328212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1961328212 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.4261590257 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 32516041392 ps |
| CPU time | 556.98 seconds |
| Started | Jul 27 08:49:32 PM PDT 24 |
| Finished | Jul 27 08:58:49 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-bfdc5ad8-7ed0-4f7c-a1a6-4c31c29f8bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261590257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.4261590257 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.695059488 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 380809586 ps |
| CPU time | 34.19 seconds |
| Started | Jul 27 08:49:31 PM PDT 24 |
| Finished | Jul 27 08:50:05 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-69b4fde6-bf20-4e53-af36-f28aa11288b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695059488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.695059488 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.403218121 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1220165009 ps |
| CPU time | 35.48 seconds |
| Started | Jul 27 08:49:28 PM PDT 24 |
| Finished | Jul 27 08:50:03 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-8900a743-23ef-4518-bfcb-0660ef5d683f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403218121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.403218121 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.1447313325 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 164583386 ps |
| CPU time | 7.94 seconds |
| Started | Jul 27 08:49:20 PM PDT 24 |
| Finished | Jul 27 08:49:28 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-796d1141-08d8-4cde-9657-1864cff6b0e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447313325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1447313325 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1307885814 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 10840816629 ps |
| CPU time | 112.73 seconds |
| Started | Jul 27 08:49:27 PM PDT 24 |
| Finished | Jul 27 08:51:19 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-7c8f1fe7-3aa4-455d-a5c8-298573cc2851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307885814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1307885814 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.102506897 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 3869328501 ps |
| CPU time | 67.54 seconds |
| Started | Jul 27 08:49:31 PM PDT 24 |
| Finished | Jul 27 08:50:39 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-e85bdf46-980f-40ca-a2ce-9bb64732870a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102506897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.102506897 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2335508126 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 44339881 ps |
| CPU time | 5.8 seconds |
| Started | Jul 27 08:49:25 PM PDT 24 |
| Finished | Jul 27 08:49:31 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-a56fd3c8-953f-42c3-9f5a-8f1445e7eaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335508126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2335508126 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.4263276493 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 11949730150 ps |
| CPU time | 443.63 seconds |
| Started | Jul 27 08:49:33 PM PDT 24 |
| Finished | Jul 27 08:56:56 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-5f5efc27-55ce-4023-b4d3-eef9b5aef07b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263276493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.4263276493 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.924993796 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 3460188770 ps |
| CPU time | 276.71 seconds |
| Started | Jul 27 08:49:33 PM PDT 24 |
| Finished | Jul 27 08:54:10 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-bfc0af3a-c242-4181-838b-f8b4ff0807ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924993796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.924993796 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1053652786 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 1674031895 ps |
| CPU time | 71.85 seconds |
| Started | Jul 27 08:49:35 PM PDT 24 |
| Finished | Jul 27 08:50:47 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-bce49d26-c9f1-481e-875d-759d6843f101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053652786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1053652786 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3374390879 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 978184135 ps |
| CPU time | 42.54 seconds |
| Started | Jul 27 08:49:28 PM PDT 24 |
| Finished | Jul 27 08:50:11 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-3681310f-200c-4684-a42d-8913af9cbacc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374390879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3374390879 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.2194693107 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 649715477 ps |
| CPU time | 50.76 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 08:50:34 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-9bc5adce-0faf-4ec3-8378-1d886191a7a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194693107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2194693107 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1180629933 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 16773940018 ps |
| CPU time | 283.35 seconds |
| Started | Jul 27 08:49:36 PM PDT 24 |
| Finished | Jul 27 08:54:19 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-dca62e98-6890-4644-9906-ed735d5701fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180629933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.1180629933 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1483526022 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 339627812 ps |
| CPU time | 42.66 seconds |
| Started | Jul 27 08:49:48 PM PDT 24 |
| Finished | Jul 27 08:50:31 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-daf0c240-3163-4288-9cb8-d87e77b1005e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483526022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.1483526022 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.2295416995 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 100890284 ps |
| CPU time | 12.77 seconds |
| Started | Jul 27 08:49:44 PM PDT 24 |
| Finished | Jul 27 08:49:57 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-2d773bd6-96af-4fb9-91c7-aa7023567c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295416995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2295416995 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.2925191183 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 1399974537 ps |
| CPU time | 49.02 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 08:50:33 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-7522884f-18da-4bcb-b839-76f3f9a63d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925191183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.2925191183 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.476306102 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 6201577224 ps |
| CPU time | 66.14 seconds |
| Started | Jul 27 08:49:38 PM PDT 24 |
| Finished | Jul 27 08:50:45 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-0d202933-cbf5-4fe7-8ced-86197ca762ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476306102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.476306102 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1847747932 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 58673307251 ps |
| CPU time | 991.76 seconds |
| Started | Jul 27 08:49:36 PM PDT 24 |
| Finished | Jul 27 09:06:08 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-e161ceec-034f-4d7c-937e-a9354032696b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847747932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1847747932 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1302605082 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 466943445 ps |
| CPU time | 46.93 seconds |
| Started | Jul 27 08:49:44 PM PDT 24 |
| Finished | Jul 27 08:50:31 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-7af7f83d-6d88-450e-8d6a-f2e365eae1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302605082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1302605082 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.2170562481 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 460364474 ps |
| CPU time | 37.51 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 08:50:21 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-6865e62f-17af-410d-97ec-47d12a5aa145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170562481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.2170562481 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3349035275 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 157181154 ps |
| CPU time | 7.91 seconds |
| Started | Jul 27 08:49:42 PM PDT 24 |
| Finished | Jul 27 08:49:50 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-b2374491-30b5-4731-8f5d-1a06d92b8df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349035275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3349035275 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.2671588713 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 9067339399 ps |
| CPU time | 95.99 seconds |
| Started | Jul 27 08:49:38 PM PDT 24 |
| Finished | Jul 27 08:51:14 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-9251d567-071c-418f-9583-b2db06ec3c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671588713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.2671588713 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1605635876 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 4964656699 ps |
| CPU time | 87.83 seconds |
| Started | Jul 27 08:49:36 PM PDT 24 |
| Finished | Jul 27 08:51:04 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-14cf31ea-993a-43c3-bc57-08423b81ef46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605635876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1605635876 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2961557696 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 49798641 ps |
| CPU time | 6.66 seconds |
| Started | Jul 27 08:49:41 PM PDT 24 |
| Finished | Jul 27 08:49:48 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-6bc3e0cb-e881-4177-85c2-db53687d93da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961557696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2961557696 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.803701955 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3097005557 ps |
| CPU time | 229.52 seconds |
| Started | Jul 27 08:49:47 PM PDT 24 |
| Finished | Jul 27 08:53:36 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-fe8d0e67-f26a-49cc-8349-bd25fab6aa5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803701955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.803701955 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.685755840 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 14112983573 ps |
| CPU time | 499.21 seconds |
| Started | Jul 27 08:49:47 PM PDT 24 |
| Finished | Jul 27 08:58:06 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-3bedd5ed-fe1b-4903-ad93-b5affd4dd7b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685755840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.685755840 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2505796981 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 944576214 ps |
| CPU time | 186.76 seconds |
| Started | Jul 27 08:49:44 PM PDT 24 |
| Finished | Jul 27 08:52:51 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-b425706f-6fab-4608-87f9-a6273840730f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505796981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2505796981 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.2669321966 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 151792441 ps |
| CPU time | 22.3 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 08:50:06 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-5f734455-8a1d-4e7b-add1-de277f3e7ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669321966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.2669321966 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.2568682169 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 843288664 ps |
| CPU time | 42.48 seconds |
| Started | Jul 27 08:49:49 PM PDT 24 |
| Finished | Jul 27 08:50:31 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-9eacf06d-7086-44a2-b39e-c650b5b4358c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568682169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .2568682169 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.4039124602 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 141419922674 ps |
| CPU time | 2493.77 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 09:31:17 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-96252ed1-6865-49b2-92e3-182812d8df64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039124602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.4039124602 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.4031309434 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 914839670 ps |
| CPU time | 42.01 seconds |
| Started | Jul 27 08:49:45 PM PDT 24 |
| Finished | Jul 27 08:50:27 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-0c24b973-78fe-4d91-b560-75c12768dba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031309434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.4031309434 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1631232331 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 1027956745 ps |
| CPU time | 34.37 seconds |
| Started | Jul 27 08:49:44 PM PDT 24 |
| Finished | Jul 27 08:50:19 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-358dfdd1-73ec-4a44-b939-b06275e432ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631232331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1631232331 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.1846035696 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1559680494 ps |
| CPU time | 60.77 seconds |
| Started | Jul 27 08:49:50 PM PDT 24 |
| Finished | Jul 27 08:50:50 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-425ea529-9f8d-4287-b4c4-66eb7e90705b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846035696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1846035696 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2512576917 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 88497070217 ps |
| CPU time | 888.3 seconds |
| Started | Jul 27 08:49:48 PM PDT 24 |
| Finished | Jul 27 09:04:37 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-c2d9e2bc-ff3f-41b0-a0aa-9896f3d09f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512576917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2512576917 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2919013001 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 45326936165 ps |
| CPU time | 835.53 seconds |
| Started | Jul 27 08:49:44 PM PDT 24 |
| Finished | Jul 27 09:03:40 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-3d4467bc-44b1-4ec4-8e99-175a4c58c138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919013001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2919013001 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1531471179 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 167435522 ps |
| CPU time | 15.4 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 08:49:59 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-2b0e9778-d5f3-4e6f-be5e-7839b6dc20af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531471179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1531471179 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.2561434634 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 284010334 ps |
| CPU time | 11.31 seconds |
| Started | Jul 27 08:49:47 PM PDT 24 |
| Finished | Jul 27 08:49:59 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-407b6336-92a7-496c-8dc7-5cdc6c5a8c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561434634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2561434634 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.583478388 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 153437626 ps |
| CPU time | 8.44 seconds |
| Started | Jul 27 08:49:45 PM PDT 24 |
| Finished | Jul 27 08:49:54 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-1a13bbb9-b18b-474d-ae44-f4344b62a16b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583478388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.583478388 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2306043655 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 8799614119 ps |
| CPU time | 97.67 seconds |
| Started | Jul 27 08:49:44 PM PDT 24 |
| Finished | Jul 27 08:51:22 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-2c83764b-6a6f-4ee0-bcaa-006b012ae8c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306043655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2306043655 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.207017444 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 5392321419 ps |
| CPU time | 100.26 seconds |
| Started | Jul 27 08:49:45 PM PDT 24 |
| Finished | Jul 27 08:51:25 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-ada57303-157b-46c1-b2ba-a618893d4279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207017444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.207017444 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3738697560 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 50546115 ps |
| CPU time | 6.53 seconds |
| Started | Jul 27 08:49:47 PM PDT 24 |
| Finished | Jul 27 08:49:53 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-b08f662a-40c9-466e-9e40-df17cab8275b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738697560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.3738697560 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.903390605 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 708377397 ps |
| CPU time | 65.94 seconds |
| Started | Jul 27 08:49:52 PM PDT 24 |
| Finished | Jul 27 08:50:58 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-00c300b4-ab61-4649-9c7a-e09d88686032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903390605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.903390605 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.2065091838 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 4658437013 ps |
| CPU time | 184.78 seconds |
| Started | Jul 27 08:50:04 PM PDT 24 |
| Finished | Jul 27 08:53:09 PM PDT 24 |
| Peak memory | 576044 kb |
| Host | smart-acc9efd4-3094-4962-911e-891e3bec808e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065091838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.2065091838 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2746959158 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 13309490671 ps |
| CPU time | 662.03 seconds |
| Started | Jul 27 08:49:51 PM PDT 24 |
| Finished | Jul 27 09:00:53 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-e391e03b-82c8-476e-aa93-1f77a538841f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746959158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.2746959158 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.350480485 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 3810890352 ps |
| CPU time | 465.22 seconds |
| Started | Jul 27 08:49:51 PM PDT 24 |
| Finished | Jul 27 08:57:36 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-13377589-fe2b-4768-99cd-cbd104b82f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350480485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.350480485 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3016476136 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 1251126542 ps |
| CPU time | 54.1 seconds |
| Started | Jul 27 08:49:43 PM PDT 24 |
| Finished | Jul 27 08:50:37 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-2b7bd808-a6bb-4277-b13e-2892a8511863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016476136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3016476136 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3620425405 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4115752348 ps |
| CPU time | 489.91 seconds |
| Started | Jul 27 07:52:33 PM PDT 24 |
| Finished | Jul 27 08:00:44 PM PDT 24 |
| Peak memory | 620520 kb |
| Host | smart-1ad2edbc-1187-45b7-888f-ab72a68b7e3e |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 620425405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3620425405 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.774075186 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3082048484 ps |
| CPU time | 262.55 seconds |
| Started | Jul 27 07:52:13 PM PDT 24 |
| Finished | Jul 27 07:56:36 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-67b91f3b-49f3-4fb1-a801-f7263a153e32 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=774075186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.774075186 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.3660306978 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2223947640 ps |
| CPU time | 262.77 seconds |
| Started | Jul 27 07:52:16 PM PDT 24 |
| Finished | Jul 27 07:56:39 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-1e14480f-bde9-47f7-b7da-fbf93cc5389d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660306978 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.3660306978 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1441202612 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2069684110 ps |
| CPU time | 233.38 seconds |
| Started | Jul 27 07:57:02 PM PDT 24 |
| Finished | Jul 27 08:00:56 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-f3ce3dc4-6521-490f-9eea-cd10163430d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441 202612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1441202612 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2688980223 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 3341418719 ps |
| CPU time | 281.13 seconds |
| Started | Jul 27 07:54:11 PM PDT 24 |
| Finished | Jul 27 07:58:53 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-35d70b3c-a074-45a0-ab78-b922e4efa60a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688980223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2688980223 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.2857728173 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3205754502 ps |
| CPU time | 296.86 seconds |
| Started | Jul 27 07:53:14 PM PDT 24 |
| Finished | Jul 27 07:58:11 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-56db675d-0090-4dac-8fd7-fa55d1c2229d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857728173 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.2857728173 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.785731362 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 3443299026 ps |
| CPU time | 255.41 seconds |
| Started | Jul 27 07:55:31 PM PDT 24 |
| Finished | Jul 27 07:59:48 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-193c2258-ff93-4af8-84aa-f96299ccb50c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785731362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.785731362 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2058364108 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 2895725045 ps |
| CPU time | 327.3 seconds |
| Started | Jul 27 07:55:57 PM PDT 24 |
| Finished | Jul 27 08:01:25 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-2eef357b-5d31-43a8-9483-33e0ae2b52c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058364108 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2058364108 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.1635046640 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 2884360794 ps |
| CPU time | 326.5 seconds |
| Started | Jul 27 07:52:24 PM PDT 24 |
| Finished | Jul 27 07:57:51 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-02ecfdff-2c8e-4258-8cc2-8b0be7d287d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635046640 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1635046640 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2780277443 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 2847868765 ps |
| CPU time | 247.53 seconds |
| Started | Jul 27 07:54:55 PM PDT 24 |
| Finished | Jul 27 07:59:03 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-b04e1acb-2733-44fa-8fd9-0e06a5739e17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2780277443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.2780277443 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1766403224 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5759590032 ps |
| CPU time | 527.78 seconds |
| Started | Jul 27 07:53:26 PM PDT 24 |
| Finished | Jul 27 08:02:15 PM PDT 24 |
| Peak memory | 624324 kb |
| Host | smart-9fc0f0d1-a9b1-4ff0-af50-6a88d60cf5fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1766403224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1766403224 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2923145087 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5437412904 ps |
| CPU time | 1042.61 seconds |
| Started | Jul 27 07:57:19 PM PDT 24 |
| Finished | Jul 27 08:14:43 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-159e3c33-cd79-4357-8f46-fb672adca622 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2923145087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2923145087 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1316640905 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 8406258648 ps |
| CPU time | 1961.4 seconds |
| Started | Jul 27 07:51:05 PM PDT 24 |
| Finished | Jul 27 08:23:46 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-a431e519-e236-436f-9871-515646b60517 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316640905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.1316640905 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2820170106 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 12481949320 ps |
| CPU time | 1182.55 seconds |
| Started | Jul 27 07:51:39 PM PDT 24 |
| Finished | Jul 27 08:11:22 PM PDT 24 |
| Peak memory | 611416 kb |
| Host | smart-a621a4a6-38c0-4079-a23a-07fac07769fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820170106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2820170106 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4224268287 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 4669492726 ps |
| CPU time | 577.05 seconds |
| Started | Jul 27 07:53:24 PM PDT 24 |
| Finished | Jul 27 08:03:01 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-445afdac-016d-45e0-bc3a-edc7113e4b45 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4224268287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.4224268287 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4052014556 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 255957460752 ps |
| CPU time | 13204.7 seconds |
| Started | Jul 27 07:55:31 PM PDT 24 |
| Finished | Jul 27 11:35:38 PM PDT 24 |
| Peak memory | 611276 kb |
| Host | smart-cb371565-6056-4228-8aa7-5c1c078a7194 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052014556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4052014556 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.1827115508 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3005233496 ps |
| CPU time | 260.32 seconds |
| Started | Jul 27 07:54:33 PM PDT 24 |
| Finished | Jul 27 07:58:54 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-9690f0cf-2828-4cfa-a6d3-90628f59b4eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827115508 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1827115508 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.2856336214 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3572447786 ps |
| CPU time | 280.69 seconds |
| Started | Jul 27 07:52:40 PM PDT 24 |
| Finished | Jul 27 07:57:21 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-26f21919-99b1-43b5-acde-877224a83be4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856336214 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2856336214 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2003155194 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 7164589736 ps |
| CPU time | 365.68 seconds |
| Started | Jul 27 07:53:32 PM PDT 24 |
| Finished | Jul 27 07:59:38 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-19c1ad8b-8d82-4f4e-92e2-2a3b30fd61cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2003155194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2003155194 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.972501906 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3599268310 ps |
| CPU time | 289.01 seconds |
| Started | Jul 27 07:56:05 PM PDT 24 |
| Finished | Jul 27 08:00:54 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-48ff733f-6cd4-45b9-81fd-5a5e3417c5c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972501906 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.972501906 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2785285732 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 10309981332 ps |
| CPU time | 760.71 seconds |
| Started | Jul 27 07:52:52 PM PDT 24 |
| Finished | Jul 27 08:05:34 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-eb69b4f6-fafc-435b-84c5-72b568102f09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2785285732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2785285732 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3027012773 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 5314996456 ps |
| CPU time | 512.37 seconds |
| Started | Jul 27 07:53:39 PM PDT 24 |
| Finished | Jul 27 08:02:12 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-daf290e6-7188-455b-bb55-ef6d28c65204 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3027012773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3027012773 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2141096141 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 6437876144 ps |
| CPU time | 1049.6 seconds |
| Started | Jul 27 07:54:31 PM PDT 24 |
| Finished | Jul 27 08:12:01 PM PDT 24 |
| Peak memory | 617924 kb |
| Host | smart-1e31f5c8-ca42-4186-82ce-c44468b71943 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141096141 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2141096141 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1080158727 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 12669876495 ps |
| CPU time | 1195.31 seconds |
| Started | Jul 27 07:55:21 PM PDT 24 |
| Finished | Jul 27 08:15:17 PM PDT 24 |
| Peak memory | 621064 kb |
| Host | smart-4cc8e5fb-0480-4db2-abf2-02e4b22b51ba |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1080158727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1080158727 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.300972893 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 4452056850 ps |
| CPU time | 626.52 seconds |
| Started | Jul 27 07:56:36 PM PDT 24 |
| Finished | Jul 27 08:07:03 PM PDT 24 |
| Peak memory | 612648 kb |
| Host | smart-0313e327-8528-43b0-adff-4d79467b55f0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300972893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.300972893 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1683332381 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 4468754536 ps |
| CPU time | 485.02 seconds |
| Started | Jul 27 07:55:36 PM PDT 24 |
| Finished | Jul 27 08:03:41 PM PDT 24 |
| Peak memory | 613396 kb |
| Host | smart-30541fc4-84bb-4165-90db-681be94fedbf |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683332381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1683332381 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2075097247 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 5181340890 ps |
| CPU time | 915.88 seconds |
| Started | Jul 27 07:57:37 PM PDT 24 |
| Finished | Jul 27 08:12:54 PM PDT 24 |
| Peak memory | 612672 kb |
| Host | smart-d9461864-3c8d-44a8-bb89-4ee27368ff88 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075097247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2075097247 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2163285036 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5342285280 ps |
| CPU time | 672.15 seconds |
| Started | Jul 27 07:56:16 PM PDT 24 |
| Finished | Jul 27 08:07:28 PM PDT 24 |
| Peak memory | 612608 kb |
| Host | smart-a19b687f-9082-4eb8-967e-fef37c859d99 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163285036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2163285036 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3732800854 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4298953650 ps |
| CPU time | 610.7 seconds |
| Started | Jul 27 07:54:04 PM PDT 24 |
| Finished | Jul 27 08:04:15 PM PDT 24 |
| Peak memory | 613720 kb |
| Host | smart-1f9c055d-4a64-4d8d-9090-94d7b238d5bb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732800854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3732800854 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1155933004 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 2985764048 ps |
| CPU time | 286.13 seconds |
| Started | Jul 27 07:54:01 PM PDT 24 |
| Finished | Jul 27 07:58:48 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-8c27e6f5-5428-499d-88fd-6cfb60ac2c2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155933004 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1155933004 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.67492708 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 3048241552 ps |
| CPU time | 505.04 seconds |
| Started | Jul 27 07:53:51 PM PDT 24 |
| Finished | Jul 27 08:02:17 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-9aced07f-364b-4e63-8bbd-17ef04e1caef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67492708 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.67492708 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.477129815 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2356061573 ps |
| CPU time | 212.66 seconds |
| Started | Jul 27 07:55:16 PM PDT 24 |
| Finished | Jul 27 07:58:49 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-207a94d1-d983-45d6-b355-9b8fe668d5f7 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477129815 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.477129815 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.803414255 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5682621328 ps |
| CPU time | 464.07 seconds |
| Started | Jul 27 07:53:30 PM PDT 24 |
| Finished | Jul 27 08:01:14 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-58d561ed-343a-45ca-8b27-3a321f863687 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803414255 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.803414255 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4081068291 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 5282344716 ps |
| CPU time | 511.35 seconds |
| Started | Jul 27 07:56:38 PM PDT 24 |
| Finished | Jul 27 08:05:10 PM PDT 24 |
| Peak memory | 611024 kb |
| Host | smart-0dc34825-7cf5-4db4-9b08-27b76945bfcc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081068291 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.4081068291 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1352589458 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 4032932372 ps |
| CPU time | 389.48 seconds |
| Started | Jul 27 07:58:33 PM PDT 24 |
| Finished | Jul 27 08:05:03 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-45fefec3-9f7b-4c27-a7cc-2f8856d50202 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352589458 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1352589458 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2936853043 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 6083240704 ps |
| CPU time | 504.48 seconds |
| Started | Jul 27 07:51:30 PM PDT 24 |
| Finished | Jul 27 07:59:54 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-6577863d-1031-4e85-9939-12e893b1430b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936853043 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2936853043 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.835016092 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 11537185600 ps |
| CPU time | 1486.4 seconds |
| Started | Jul 27 07:59:04 PM PDT 24 |
| Finished | Jul 27 08:23:51 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-979d36bd-295a-4137-99b8-6bf199baa5bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835016092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.835016092 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2834441203 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3243642430 ps |
| CPU time | 331.22 seconds |
| Started | Jul 27 07:56:01 PM PDT 24 |
| Finished | Jul 27 08:01:32 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-52f35c28-2cda-46a0-85a0-fbcf9cdfcfc5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834441203 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2834441203 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.450556442 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 3958177686 ps |
| CPU time | 512.13 seconds |
| Started | Jul 27 07:52:43 PM PDT 24 |
| Finished | Jul 27 08:01:15 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-17eba39c-4e25-4009-97b2-9c145d56e7f7 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450556442 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.450556442 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1533773665 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3160907084 ps |
| CPU time | 322.65 seconds |
| Started | Jul 27 07:55:20 PM PDT 24 |
| Finished | Jul 27 08:00:43 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-faff6e2c-a761-497c-bb20-c5fac35b8b4c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533773665 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.1533773665 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.699564374 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 72258487070 ps |
| CPU time | 16043.7 seconds |
| Started | Jul 27 07:54:43 PM PDT 24 |
| Finished | Jul 28 12:22:09 AM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-38fd55bf-f021-4216-8ed6-549c01632a5a |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=699564374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.699564374 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1681128236 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 34314496152 ps |
| CPU time | 8351.38 seconds |
| Started | Jul 27 07:53:23 PM PDT 24 |
| Finished | Jul 27 10:12:36 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-b31b75d7-d81d-4669-bad3-9e457482c8c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681128236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1681128236 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1768739110 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 21059942652 ps |
| CPU time | 4610.34 seconds |
| Started | Jul 27 07:54:34 PM PDT 24 |
| Finished | Jul 27 09:11:25 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-680934da-b183-4dd1-b7af-8088923b614d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1768739110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1768739110 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2560077454 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 3996021304 ps |
| CPU time | 493.31 seconds |
| Started | Jul 27 07:56:48 PM PDT 24 |
| Finished | Jul 27 08:05:02 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-e015facb-5b70-4b60-afd0-852f1d6829e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25600 77454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.2560077454 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.2663385648 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 2600511600 ps |
| CPU time | 302.68 seconds |
| Started | Jul 27 07:57:06 PM PDT 24 |
| Finished | Jul 27 08:02:09 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-57cd12dc-0773-4cb4-96f5-6296e0307e3c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663385648 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2663385648 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2237306667 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 6379500569 ps |
| CPU time | 668.58 seconds |
| Started | Jul 27 07:53:02 PM PDT 24 |
| Finished | Jul 27 08:04:11 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-35d8a58f-5ef9-4500-897d-d220af996505 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237306667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2237306667 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.4050874927 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2935090502 ps |
| CPU time | 305.31 seconds |
| Started | Jul 27 07:58:06 PM PDT 24 |
| Finished | Jul 27 08:03:11 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-7aa9ec79-e809-431b-86e9-6806e8e771e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050874927 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.4050874927 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.1107783439 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4353233528 ps |
| CPU time | 958.53 seconds |
| Started | Jul 27 07:54:38 PM PDT 24 |
| Finished | Jul 27 08:10:37 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-9ddc1864-153d-4ef0-abfe-029bb00988c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107783439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.1107783439 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2432629986 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 5770921024 ps |
| CPU time | 1038.44 seconds |
| Started | Jul 27 07:54:42 PM PDT 24 |
| Finished | Jul 27 08:12:01 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-978d24ea-8ca6-468c-ba4d-ba88bbb90e63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2432629986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2432629986 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2203919147 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 6920746875 ps |
| CPU time | 1115.32 seconds |
| Started | Jul 27 07:53:18 PM PDT 24 |
| Finished | Jul 27 08:11:54 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-0c82e0a4-507c-44e5-ac27-67b282f1d16e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203919147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2203919147 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.267685326 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3455394392 ps |
| CPU time | 602.67 seconds |
| Started | Jul 27 07:53:35 PM PDT 24 |
| Finished | Jul 27 08:03:38 PM PDT 24 |
| Peak memory | 616756 kb |
| Host | smart-9dfb00e0-a741-45f1-9dd4-6cbcd79a7596 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267685326 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_edn_kat.267685326 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.2387812804 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 9992781596 ps |
| CPU time | 2354.56 seconds |
| Started | Jul 27 07:52:58 PM PDT 24 |
| Finished | Jul 27 08:32:14 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-54edafba-8b7a-4775-822e-a8567e70ec5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387812804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2387812804 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3903791807 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3122344860 ps |
| CPU time | 273.29 seconds |
| Started | Jul 27 07:52:55 PM PDT 24 |
| Finished | Jul 27 07:57:28 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-60aee459-4a51-4be8-91e0-c20dbd4c386f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39 03791807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3903791807 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4102675286 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2063708422 ps |
| CPU time | 233.99 seconds |
| Started | Jul 27 07:53:14 PM PDT 24 |
| Finished | Jul 27 07:57:09 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-0855f7b9-2f66-47fe-a4c3-388d40cbb26c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102675286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.4102675286 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.415821717 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 3391156642 ps |
| CPU time | 718.28 seconds |
| Started | Jul 27 07:57:16 PM PDT 24 |
| Finished | Jul 27 08:09:14 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-d79c9105-f060-4ff0-8622-e33c964bcba1 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=415821717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.415821717 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.3305086690 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 3053648292 ps |
| CPU time | 262.91 seconds |
| Started | Jul 27 07:51:28 PM PDT 24 |
| Finished | Jul 27 07:55:51 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-4b836c3b-7e2f-4a65-bb9a-96c39ae64fe4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305086690 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.3305086690 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.1662279529 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 2803010140 ps |
| CPU time | 147.24 seconds |
| Started | Jul 27 07:52:07 PM PDT 24 |
| Finished | Jul 27 07:54:34 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-f126cb06-ae01-4bf9-9bb8-954d9a29b5b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662279529 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.1662279529 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.246141721 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 2172720360 ps |
| CPU time | 182.43 seconds |
| Started | Jul 27 07:53:04 PM PDT 24 |
| Finished | Jul 27 07:56:07 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-799a0f73-cac8-498a-98cc-217183bf948d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246141721 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_example_manufacturer.246141721 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.3770157373 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 2308077902 ps |
| CPU time | 157.42 seconds |
| Started | Jul 27 07:54:13 PM PDT 24 |
| Finished | Jul 27 07:56:52 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-66950255-7f5a-47aa-a14b-12bcd1ffe1a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770157373 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.3770157373 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.4144545135 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 57983844214 ps |
| CPU time | 12246.5 seconds |
| Started | Jul 27 07:54:09 PM PDT 24 |
| Finished | Jul 27 11:18:17 PM PDT 24 |
| Peak memory | 625384 kb |
| Host | smart-79b0c242-31f2-4ff5-8002-72c98846f061 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4144545135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.4144545135 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.1721110122 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 4567125196 ps |
| CPU time | 541.42 seconds |
| Started | Jul 27 07:55:22 PM PDT 24 |
| Finished | Jul 27 08:04:24 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-e04b6d75-990a-4872-b56b-27ed481dd9cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1721110122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1721110122 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1662657262 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5536315570 ps |
| CPU time | 1049.35 seconds |
| Started | Jul 27 07:53:17 PM PDT 24 |
| Finished | Jul 27 08:10:46 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-92122f61-1dde-4f28-a8a5-3ecf99e5fd96 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662657262 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1662657262 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1070366541 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5392717758 ps |
| CPU time | 1076.7 seconds |
| Started | Jul 27 07:53:31 PM PDT 24 |
| Finished | Jul 27 08:11:28 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-8b0432ae-feea-4f95-a98a-c6bbca766121 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070366541 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1070366541 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2537039269 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 7810232680 ps |
| CPU time | 1329.23 seconds |
| Started | Jul 27 07:53:51 PM PDT 24 |
| Finished | Jul 27 08:16:01 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-b42879e9-b4d7-4da0-9c13-f8c2995c7a6f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537039269 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2537039269 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3070897858 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 6014659706 ps |
| CPU time | 1223.67 seconds |
| Started | Jul 27 07:55:27 PM PDT 24 |
| Finished | Jul 27 08:15:53 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-5882919c-f5bc-4a47-a23a-927ad4f4a084 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070897858 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3070897858 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3060671449 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3279440686 ps |
| CPU time | 373.79 seconds |
| Started | Jul 27 07:57:04 PM PDT 24 |
| Finished | Jul 27 08:03:19 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-8f719f1c-8aff-47ee-b5bc-eb00ece47290 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060671449 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3060671449 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3906436992 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 5453879280 ps |
| CPU time | 1118.09 seconds |
| Started | Jul 27 07:53:20 PM PDT 24 |
| Finished | Jul 27 08:11:59 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-18a41131-aa42-4e99-809b-4d063f3b18d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906436992 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3906436992 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.117138972 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 4566138529 ps |
| CPU time | 595.07 seconds |
| Started | Jul 27 07:53:02 PM PDT 24 |
| Finished | Jul 27 08:02:58 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-a62cb890-429e-4409-b646-c62c69fa623c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=117138972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.117138972 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1788563877 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 5557618271 ps |
| CPU time | 730.6 seconds |
| Started | Jul 27 07:57:20 PM PDT 24 |
| Finished | Jul 27 08:09:33 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-26e33a59-b541-4101-b278-095b713801fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1788563877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1788563877 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.4018484543 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3269796250 ps |
| CPU time | 325.41 seconds |
| Started | Jul 27 07:53:22 PM PDT 24 |
| Finished | Jul 27 07:58:48 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-ae21c909-e4ca-421d-9d1b-dccbd130b985 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018484 543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.4018484543 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.3648292028 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 23726780968 ps |
| CPU time | 2183.85 seconds |
| Started | Jul 27 07:51:29 PM PDT 24 |
| Finished | Jul 27 08:27:54 PM PDT 24 |
| Peak memory | 613984 kb |
| Host | smart-6c807ab6-d6f6-4fdf-a7bf-80446cdb2fad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648292028 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3648292028 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2146090778 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 21912185217 ps |
| CPU time | 2023.47 seconds |
| Started | Jul 27 07:57:01 PM PDT 24 |
| Finished | Jul 27 08:30:46 PM PDT 24 |
| Peak memory | 618344 kb |
| Host | smart-8300375c-36ea-4a63-87ba-853c376c4db7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2146090778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2146090778 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2950798441 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 2793768648 ps |
| CPU time | 281.14 seconds |
| Started | Jul 27 07:59:12 PM PDT 24 |
| Finished | Jul 27 08:03:53 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-f382b529-7958-4069-b032-c3850f5f48ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2950798441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2950798441 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1331827505 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4530448448 ps |
| CPU time | 488.07 seconds |
| Started | Jul 27 07:57:34 PM PDT 24 |
| Finished | Jul 27 08:05:42 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-408896ef-f9df-4083-9979-5968d4535aec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331827505 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1331827505 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.1059330533 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3084707820 ps |
| CPU time | 315.87 seconds |
| Started | Jul 27 07:59:08 PM PDT 24 |
| Finished | Jul 27 08:04:24 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-7da6023f-fd40-4ba7-8618-6f99dc89d0c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059330533 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.1059330533 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.717263594 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 2920599420 ps |
| CPU time | 235.48 seconds |
| Started | Jul 27 07:56:26 PM PDT 24 |
| Finished | Jul 27 08:00:22 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-d0c42544-30fa-494e-99f4-fdf567c2172d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717263594 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.717263594 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1685454827 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 3056142468 ps |
| CPU time | 322.91 seconds |
| Started | Jul 27 07:53:11 PM PDT 24 |
| Finished | Jul 27 07:58:34 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-7c278116-d573-4fe9-a3b9-9fc124189d1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685454827 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.1685454827 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3459453649 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 3102816404 ps |
| CPU time | 189.49 seconds |
| Started | Jul 27 07:55:52 PM PDT 24 |
| Finished | Jul 27 07:59:01 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-313879ba-9ea5-451c-bcb1-3e4b2faca38c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459453649 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3459453649 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.3316368639 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 7893543996 ps |
| CPU time | 2112.57 seconds |
| Started | Jul 27 07:54:14 PM PDT 24 |
| Finished | Jul 27 08:29:27 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-808ab06d-fef7-4f3e-968d-0d382b196b2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316368639 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.3316368639 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.570845559 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 2930897360 ps |
| CPU time | 366.28 seconds |
| Started | Jul 27 07:57:09 PM PDT 24 |
| Finished | Jul 27 08:03:15 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-6105f883-45bc-45ea-9b62-7b5295a89477 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570845559 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.570845559 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.1289428246 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 3071868380 ps |
| CPU time | 345.7 seconds |
| Started | Jul 27 07:54:26 PM PDT 24 |
| Finished | Jul 27 08:00:12 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-1e981d5b-b9c1-461b-940c-b0f450aa9ec3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289428246 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1289428246 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.895864415 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3933762140 ps |
| CPU time | 376.89 seconds |
| Started | Jul 27 07:51:48 PM PDT 24 |
| Finished | Jul 27 07:58:05 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-71de054d-04dd-4d0f-9a52-808f547825c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895864415 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.895864415 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4241183062 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5115635250 ps |
| CPU time | 826.66 seconds |
| Started | Jul 27 07:53:23 PM PDT 24 |
| Finished | Jul 27 08:07:10 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-d7caf293-33d2-483f-99a0-cda55339d1ac |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241183062 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.4241183062 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.537232397 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 63784462064 ps |
| CPU time | 12190.1 seconds |
| Started | Jul 27 07:52:08 PM PDT 24 |
| Finished | Jul 27 11:15:19 PM PDT 24 |
| Peak memory | 625320 kb |
| Host | smart-a8d92790-16ca-45a5-b895-1bf14ea08bd6 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=537232397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.537232397 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.390339526 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 11200544872 ps |
| CPU time | 1966.68 seconds |
| Started | Jul 27 07:53:08 PM PDT 24 |
| Finished | Jul 27 08:25:55 PM PDT 24 |
| Peak memory | 618420 kb |
| Host | smart-4fcb06a3-aa16-4903-bd16-5ac05fa6246a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903 39526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.390339526 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3158670468 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 10682786612 ps |
| CPU time | 2290.85 seconds |
| Started | Jul 27 07:58:28 PM PDT 24 |
| Finished | Jul 27 08:36:40 PM PDT 24 |
| Peak memory | 618520 kb |
| Host | smart-196c479d-2867-4a87-b44d-d6a7f478dc43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3158670468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3158670468 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1875583829 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 11741442423 ps |
| CPU time | 1830.47 seconds |
| Started | Jul 27 07:55:24 PM PDT 24 |
| Finished | Jul 27 08:25:55 PM PDT 24 |
| Peak memory | 618444 kb |
| Host | smart-c7fef351-1e46-4e81-8f9c-cb7fbfaa84ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1875583829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1875583829 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.374294981 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 11268245016 ps |
| CPU time | 2437.2 seconds |
| Started | Jul 27 07:53:58 PM PDT 24 |
| Finished | Jul 27 08:34:35 PM PDT 24 |
| Peak memory | 617184 kb |
| Host | smart-b2a28058-000e-4732-8314-d19af8aad215 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=374294981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.374294981 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2273175648 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 6710507640 ps |
| CPU time | 1400.34 seconds |
| Started | Jul 27 07:53:39 PM PDT 24 |
| Finished | Jul 27 08:16:59 PM PDT 24 |
| Peak memory | 611944 kb |
| Host | smart-181becf0-7547-404e-ae29-00a513773080 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227317 5648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2273175648 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3022626090 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 8027611856 ps |
| CPU time | 1446.64 seconds |
| Started | Jul 27 07:53:34 PM PDT 24 |
| Finished | Jul 27 08:17:41 PM PDT 24 |
| Peak memory | 611356 kb |
| Host | smart-113831ed-4675-48eb-a398-0cdefa26ae71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226 26090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3022626090 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.246140677 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2000600216 ps |
| CPU time | 156.8 seconds |
| Started | Jul 27 07:54:08 PM PDT 24 |
| Finished | Jul 27 07:56:45 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-eb4f25bf-6661-4f10-842e-93eba2bd8883 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246140677 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.246140677 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.3179075461 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 2414364700 ps |
| CPU time | 309.2 seconds |
| Started | Jul 27 07:54:47 PM PDT 24 |
| Finished | Jul 27 07:59:57 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-4940a8f2-d813-44b5-b0a5-dda2f1ebb6b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179075461 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3179075461 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.820014939 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2648053736 ps |
| CPU time | 175.97 seconds |
| Started | Jul 27 07:53:08 PM PDT 24 |
| Finished | Jul 27 07:56:04 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-d05b6851-1f9a-4f11-97d2-eafda2642467 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820014939 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_idle.820014939 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3623610418 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2604089408 ps |
| CPU time | 302.15 seconds |
| Started | Jul 27 07:57:42 PM PDT 24 |
| Finished | Jul 27 08:02:44 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-32aa5d8c-d701-48b8-becd-0ff2b1140b1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623610418 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3623610418 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2869562016 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3526840152 ps |
| CPU time | 396.43 seconds |
| Started | Jul 27 07:58:31 PM PDT 24 |
| Finished | Jul 27 08:05:08 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-1beff4f5-d31d-458c-b191-df06ebf74921 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869562016 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.2869562016 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2655504082 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2831888118 ps |
| CPU time | 307.14 seconds |
| Started | Jul 27 07:55:54 PM PDT 24 |
| Finished | Jul 27 08:01:02 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-a26c54b6-41a0-401b-9b0b-78a9f984c636 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655504082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2655504082 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3353811376 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2719676905 ps |
| CPU time | 235.21 seconds |
| Started | Jul 27 07:52:24 PM PDT 24 |
| Finished | Jul 27 07:56:19 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-2d19d23d-a483-4d81-8f18-fdbf471d052b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33538113 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3353811376 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.244778656 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2684073056 ps |
| CPU time | 269.74 seconds |
| Started | Jul 27 07:55:03 PM PDT 24 |
| Finished | Jul 27 07:59:33 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-ec4dc710-f68d-4929-80c6-261797ccfb93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244778656 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_smoketest.244778656 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.22246257 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3075611064 ps |
| CPU time | 331.59 seconds |
| Started | Jul 27 07:50:25 PM PDT 24 |
| Finished | Jul 27 07:55:57 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-39f6ec55-be04-4d73-9fc2-f15b064855c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246257 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.22246257 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2032803003 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3258394848 ps |
| CPU time | 181.61 seconds |
| Started | Jul 27 07:56:10 PM PDT 24 |
| Finished | Jul 27 07:59:12 PM PDT 24 |
| Peak memory | 620240 kb |
| Host | smart-c946ad95-11d1-42b4-bf10-14c2733558dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032803003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2032803003 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1260137999 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 2929610911 ps |
| CPU time | 290.02 seconds |
| Started | Jul 27 07:54:09 PM PDT 24 |
| Finished | Jul 27 07:58:59 PM PDT 24 |
| Peak memory | 622276 kb |
| Host | smart-396aa87a-28b6-443f-ae0a-04f03acb34b6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260137999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1260137999 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2705085159 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2786866140 ps |
| CPU time | 140.54 seconds |
| Started | Jul 27 07:53:27 PM PDT 24 |
| Finished | Jul 27 07:55:48 PM PDT 24 |
| Peak memory | 620636 kb |
| Host | smart-f570ac63-254b-4590-b210-b3d5867e09f7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705085159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2705085159 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2743408372 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 7033108377 ps |
| CPU time | 331.73 seconds |
| Started | Jul 27 07:52:24 PM PDT 24 |
| Finished | Jul 27 07:57:58 PM PDT 24 |
| Peak memory | 621068 kb |
| Host | smart-b184d5c9-77cf-45ef-a6da-0412b8855ba7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743408372 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2743408372 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.421780554 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2450522457 ps |
| CPU time | 126.69 seconds |
| Started | Jul 27 07:55:31 PM PDT 24 |
| Finished | Jul 27 07:57:38 PM PDT 24 |
| Peak memory | 618308 kb |
| Host | smart-8528becf-77f1-41c6-9f54-ab486ec3c6be |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=421780554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.421780554 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1433157194 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 2319296045 ps |
| CPU time | 100.72 seconds |
| Started | Jul 27 07:54:42 PM PDT 24 |
| Finished | Jul 27 07:56:23 PM PDT 24 |
| Peak memory | 623668 kb |
| Host | smart-c305708f-ca6c-4a77-98fa-a3f8020cf9b0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433157194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1433157194 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.788523251 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 49786609504 ps |
| CPU time | 6101.12 seconds |
| Started | Jul 27 07:54:52 PM PDT 24 |
| Finished | Jul 27 09:36:35 PM PDT 24 |
| Peak memory | 621304 kb |
| Host | smart-bd469033-4781-4172-a1e6-065d28426a50 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788523251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.788523251 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.203322121 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 9758875409 ps |
| CPU time | 1087.39 seconds |
| Started | Jul 27 07:53:09 PM PDT 24 |
| Finished | Jul 27 08:11:17 PM PDT 24 |
| Peak memory | 620556 kb |
| Host | smart-c7d1859e-f28e-4519-825c-028be9974844 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=203322121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.203322121 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3795698302 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 47891857140 ps |
| CPU time | 6045.06 seconds |
| Started | Jul 27 07:52:20 PM PDT 24 |
| Finished | Jul 27 09:33:06 PM PDT 24 |
| Peak memory | 620736 kb |
| Host | smart-936938c4-31e9-464c-93c2-6f790029ab73 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795698302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3795698302 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1920516083 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 21472571336 ps |
| CPU time | 2375.7 seconds |
| Started | Jul 27 07:53:13 PM PDT 24 |
| Finished | Jul 27 08:32:49 PM PDT 24 |
| Peak memory | 621772 kb |
| Host | smart-eb1c53c1-c80f-445b-aecf-551e1fae4a38 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1920516083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.1920516083 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1820208363 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 18645836887 ps |
| CPU time | 4058.71 seconds |
| Started | Jul 27 07:53:46 PM PDT 24 |
| Finished | Jul 27 09:01:25 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-fcb0d810-dd3c-4419-b3ae-2aed3b7621a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1820208363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1820208363 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2703836877 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 25502117430 ps |
| CPU time | 4316.36 seconds |
| Started | Jul 27 07:57:19 PM PDT 24 |
| Finished | Jul 27 09:09:16 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-91d07eec-0fab-4c6c-97f3-da6cf49acf13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703836877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2703836877 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2699276198 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 3885728404 ps |
| CPU time | 573.54 seconds |
| Started | Jul 27 07:55:29 PM PDT 24 |
| Finished | Jul 27 08:05:04 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-21dc0d05-4fc3-4086-adfc-ccd577a99559 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699276198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2699276198 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.102484597 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5918786932 ps |
| CPU time | 1009.8 seconds |
| Started | Jul 27 07:56:59 PM PDT 24 |
| Finished | Jul 27 08:13:49 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-773c2c77-9832-498e-a4be-4f05061f8c5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=102484597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.102484597 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.483440772 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5196969400 ps |
| CPU time | 898.49 seconds |
| Started | Jul 27 07:54:34 PM PDT 24 |
| Finished | Jul 27 08:09:33 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-b0197b3c-5414-499c-8034-9bf6001cf0dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483440772 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.483440772 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.562231688 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 26899245440 ps |
| CPU time | 5681.92 seconds |
| Started | Jul 27 07:52:53 PM PDT 24 |
| Finished | Jul 27 09:27:36 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-416f8b09-acb1-42d6-b38f-4e3ae14f9b65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562231 688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.562231688 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.401556469 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 2663189428 ps |
| CPU time | 229.37 seconds |
| Started | Jul 27 07:55:08 PM PDT 24 |
| Finished | Jul 27 07:58:58 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-91d0be67-3c7a-4503-b93b-6f075bdad6f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401556469 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.401556469 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.947234342 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 8913537380 ps |
| CPU time | 1403.84 seconds |
| Started | Jul 27 07:52:58 PM PDT 24 |
| Finished | Jul 27 08:16:23 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-8cca86a6-9afe-4300-bdd6-ed8e54609c96 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=947234342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.947234342 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1640584362 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7858372850 ps |
| CPU time | 1228.97 seconds |
| Started | Jul 27 07:52:45 PM PDT 24 |
| Finished | Jul 27 08:13:14 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-2ce31fc7-b578-478f-b965-d8272c6b9091 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1640584362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1640584362 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2130078616 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 9332089384 ps |
| CPU time | 1659.28 seconds |
| Started | Jul 27 07:56:35 PM PDT 24 |
| Finished | Jul 27 08:24:16 PM PDT 24 |
| Peak memory | 611324 kb |
| Host | smart-e8ec4e81-5b00-4a7c-947c-ae835ff3c10f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2130078616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2130078616 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2680752855 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 5045645896 ps |
| CPU time | 799.17 seconds |
| Started | Jul 27 07:51:46 PM PDT 24 |
| Finished | Jul 27 08:05:06 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-7125f7b5-d3af-48a9-9b10-d445ac5ba290 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2680752855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2680752855 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2177119099 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 3556293428 ps |
| CPU time | 323.3 seconds |
| Started | Jul 27 07:59:17 PM PDT 24 |
| Finished | Jul 27 08:04:40 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-7126b88d-72ed-4a4e-a5a6-70ba0a014f1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177119099 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.2177119099 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.3932664197 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3477559080 ps |
| CPU time | 306.42 seconds |
| Started | Jul 27 07:54:18 PM PDT 24 |
| Finished | Jul 27 07:59:28 PM PDT 24 |
| Peak memory | 612024 kb |
| Host | smart-4b044e0a-166c-474e-b991-7f7a571c1d12 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932664197 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3932664197 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.3933161933 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 4597586786 ps |
| CPU time | 762.08 seconds |
| Started | Jul 27 07:55:26 PM PDT 24 |
| Finished | Jul 27 08:08:09 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-dbadf51a-2350-4135-8477-458a9428c16f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933161933 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3933161933 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.3188090227 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4734214500 ps |
| CPU time | 346.43 seconds |
| Started | Jul 27 07:52:36 PM PDT 24 |
| Finished | Jul 27 07:58:23 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-517b889b-aebe-448f-ab23-53897cc5cde7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188090227 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.3188090227 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.1066714236 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6158974506 ps |
| CPU time | 1826.28 seconds |
| Started | Jul 27 07:58:03 PM PDT 24 |
| Finished | Jul 27 08:28:30 PM PDT 24 |
| Peak memory | 625544 kb |
| Host | smart-69e86d36-6189-4e67-9ea8-2250908f9e95 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1066714236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1066714236 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4147331701 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 11708692473 ps |
| CPU time | 1527.83 seconds |
| Started | Jul 27 07:54:42 PM PDT 24 |
| Finished | Jul 27 08:20:10 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-b8456d97-0734-41d9-a661-227e8f5a8327 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147 331701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.4147331701 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.236260139 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 24078792730 ps |
| CPU time | 1974.25 seconds |
| Started | Jul 27 07:59:08 PM PDT 24 |
| Finished | Jul 27 08:32:03 PM PDT 24 |
| Peak memory | 611496 kb |
| Host | smart-fd7e0c9a-5284-4462-9b7b-cb53af04191a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236 260139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.236260139 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.626796379 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 13488915523 ps |
| CPU time | 1076.8 seconds |
| Started | Jul 27 07:53:11 PM PDT 24 |
| Finished | Jul 27 08:11:08 PM PDT 24 |
| Peak memory | 611836 kb |
| Host | smart-09c1df44-21d2-4de4-a3d4-d1eb3c0af2c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=626796379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.626796379 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3070746667 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 21125101720 ps |
| CPU time | 1386.91 seconds |
| Started | Jul 27 07:52:26 PM PDT 24 |
| Finished | Jul 27 08:15:34 PM PDT 24 |
| Peak memory | 611572 kb |
| Host | smart-a288777a-32a1-46a7-a669-22e152735fda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3070746667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3070746667 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.536627938 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 7534265860 ps |
| CPU time | 545.43 seconds |
| Started | Jul 27 07:52:00 PM PDT 24 |
| Finished | Jul 27 08:01:05 PM PDT 24 |
| Peak memory | 611504 kb |
| Host | smart-9db764c5-dee6-4730-99a5-7e2fceae14ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536627938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.536627938 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3607391178 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3485246216 ps |
| CPU time | 422.7 seconds |
| Started | Jul 27 07:53:34 PM PDT 24 |
| Finished | Jul 27 08:00:36 PM PDT 24 |
| Peak memory | 616792 kb |
| Host | smart-5ce0ad96-9c94-46f2-bb66-c4334d3e2748 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3607391178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3607391178 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2873138870 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 12408437806 ps |
| CPU time | 1550.98 seconds |
| Started | Jul 27 07:53:32 PM PDT 24 |
| Finished | Jul 27 08:19:23 PM PDT 24 |
| Peak memory | 612100 kb |
| Host | smart-e8819ca9-f690-45da-96c4-c742efc427b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873138870 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2873138870 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2659008167 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8277146280 ps |
| CPU time | 488.8 seconds |
| Started | Jul 27 07:56:26 PM PDT 24 |
| Finished | Jul 27 08:04:35 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-f0177c03-7554-4fb2-bee9-a1c2e1543065 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659008167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2659008167 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3501781345 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 6336507323 ps |
| CPU time | 494.58 seconds |
| Started | Jul 27 07:52:18 PM PDT 24 |
| Finished | Jul 27 08:00:33 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-428ace66-5dd8-4e16-8f25-1085bbbe7a83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501781345 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3501781345 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.720856307 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 28515547593 ps |
| CPU time | 3128.7 seconds |
| Started | Jul 27 07:55:21 PM PDT 24 |
| Finished | Jul 27 08:47:30 PM PDT 24 |
| Peak memory | 612100 kb |
| Host | smart-9f86484b-55f6-495f-b62f-a0fe5b81a02d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=720856307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.720856307 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.632602916 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 23471490322 ps |
| CPU time | 1825.97 seconds |
| Started | Jul 27 07:51:47 PM PDT 24 |
| Finished | Jul 27 08:22:13 PM PDT 24 |
| Peak memory | 611384 kb |
| Host | smart-5f9dc221-a33f-4984-8150-5776599f0dd6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=632602916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.632602916 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1387047945 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 34223450863 ps |
| CPU time | 3574.44 seconds |
| Started | Jul 27 07:53:21 PM PDT 24 |
| Finished | Jul 27 08:52:56 PM PDT 24 |
| Peak memory | 612280 kb |
| Host | smart-9276bf1c-4939-4344-9f72-5b9621b4ae93 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387047945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1387047945 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.502343261 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3243889688 ps |
| CPU time | 254.92 seconds |
| Started | Jul 27 07:54:22 PM PDT 24 |
| Finished | Jul 27 07:58:37 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-f16ba1c6-a8aa-4280-960e-7b27b989f0df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502343261 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.502343261 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.422121363 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 4915426609 ps |
| CPU time | 516.62 seconds |
| Started | Jul 27 07:53:22 PM PDT 24 |
| Finished | Jul 27 08:01:59 PM PDT 24 |
| Peak memory | 618104 kb |
| Host | smart-e82f0e4f-629b-4e94-8b82-fd22e7baa43b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=422121363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.422121363 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.390810160 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 6005460446 ps |
| CPU time | 514.88 seconds |
| Started | Jul 27 07:53:11 PM PDT 24 |
| Finished | Jul 27 08:01:46 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-e2b38d38-b421-4d8b-b500-93fcc2e18182 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=390810160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.390810160 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.730122646 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 5011213170 ps |
| CPU time | 361.74 seconds |
| Started | Jul 27 07:54:54 PM PDT 24 |
| Finished | Jul 27 08:00:56 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-9ed4e9fe-8928-4a06-beab-649956b359f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730122646 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.730122646 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.984572115 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 9252248920 ps |
| CPU time | 1384.37 seconds |
| Started | Jul 27 07:56:05 PM PDT 24 |
| Finished | Jul 27 08:19:10 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-cbc288d4-cf4a-42a5-ae08-52dd278d7127 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984572115 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.984572115 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3535986095 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5003596952 ps |
| CPU time | 609.92 seconds |
| Started | Jul 27 07:52:28 PM PDT 24 |
| Finished | Jul 27 08:02:38 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-36946711-fe73-45f1-99c1-5b025a268893 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535986095 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3535986095 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.461806896 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 5386895256 ps |
| CPU time | 315.34 seconds |
| Started | Jul 27 07:53:34 PM PDT 24 |
| Finished | Jul 27 07:58:50 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-e4baffc1-da9a-43f6-a3cb-119400b0a7f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461806896 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.461806896 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4000214972 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 4527355670 ps |
| CPU time | 624.57 seconds |
| Started | Jul 27 07:56:26 PM PDT 24 |
| Finished | Jul 27 08:06:52 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-dc699347-4dfa-43fc-9b5a-7ac3eaf6f08f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400 0214972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.4000214972 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4137817798 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 9945473244 ps |
| CPU time | 394.92 seconds |
| Started | Jul 27 07:53:44 PM PDT 24 |
| Finished | Jul 27 08:00:20 PM PDT 24 |
| Peak memory | 625408 kb |
| Host | smart-da117479-32ea-4d8e-8810-d6b694c5621d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137817798 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.4137817798 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.889891023 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 13274254930 ps |
| CPU time | 2079.68 seconds |
| Started | Jul 27 07:55:52 PM PDT 24 |
| Finished | Jul 27 08:30:32 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-56cb3a0a-3c9f-41d5-b4a9-db90170f213b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=889891023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.889891023 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.370025209 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 7179284648 ps |
| CPU time | 514.19 seconds |
| Started | Jul 27 07:53:05 PM PDT 24 |
| Finished | Jul 27 08:01:39 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-7787ab26-915a-4d0c-a6e8-6558eaebc36b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370025209 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_rstmgr_cpu_info.370025209 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1506426872 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 6386987464 ps |
| CPU time | 560.29 seconds |
| Started | Jul 27 07:53:56 PM PDT 24 |
| Finished | Jul 27 08:03:17 PM PDT 24 |
| Peak memory | 643312 kb |
| Host | smart-8e46a7ac-9a87-4cc0-a8b4-e67334055e9b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1506426872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1506426872 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3314422847 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3039423592 ps |
| CPU time | 162.29 seconds |
| Started | Jul 27 07:55:16 PM PDT 24 |
| Finished | Jul 27 07:57:59 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-cdf198ba-c091-46cf-90be-6abda8373624 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314422847 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.3314422847 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.59219412 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 4181158440 ps |
| CPU time | 529.71 seconds |
| Started | Jul 27 07:51:28 PM PDT 24 |
| Finished | Jul 27 08:00:18 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-3bee3a9f-a5cd-46b1-bf2d-21487b22fedf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59219412 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_sw_req.59219412 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.647607652 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3097326750 ps |
| CPU time | 395.49 seconds |
| Started | Jul 27 07:55:51 PM PDT 24 |
| Finished | Jul 27 08:02:27 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-3dc5bba7-f27b-477b-bde3-cb55c58c49c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647607652 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.647607652 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1474004958 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3328730770 ps |
| CPU time | 221.32 seconds |
| Started | Jul 27 07:52:41 PM PDT 24 |
| Finished | Jul 27 07:56:23 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-a09d370e-f290-4fe1-8050-d8f5d94c6c3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474004958 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1474004958 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1241940205 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 5628334700 ps |
| CPU time | 1022.67 seconds |
| Started | Jul 27 07:55:54 PM PDT 24 |
| Finished | Jul 27 08:12:58 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-09386fde-149b-4072-9c1a-a96827bc6988 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1241940205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1241940205 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4111246665 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 5551121142 ps |
| CPU time | 569.64 seconds |
| Started | Jul 27 07:57:26 PM PDT 24 |
| Finished | Jul 27 08:06:56 PM PDT 24 |
| Peak memory | 620456 kb |
| Host | smart-dd9d60ba-963f-47f9-bedf-9df24830c2a5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111246665 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.4111246665 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2911693045 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2652671368 ps |
| CPU time | 224.81 seconds |
| Started | Jul 27 07:58:54 PM PDT 24 |
| Finished | Jul 27 08:02:39 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-158db224-e4c1-4fb4-b0f7-11ea9be066da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911693045 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2911693045 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.3765505915 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2734557850 ps |
| CPU time | 323.45 seconds |
| Started | Jul 27 07:57:34 PM PDT 24 |
| Finished | Jul 27 08:02:58 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-e844d224-54e3-42db-a8b4-28bbe69cad48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765505915 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.3765505915 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1482845999 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 2431764008 ps |
| CPU time | 184.5 seconds |
| Started | Jul 27 07:54:04 PM PDT 24 |
| Finished | Jul 27 07:57:09 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-29336441-d9c9-4a15-b676-c660c67405f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482845999 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1482845999 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1353587136 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2486704738 ps |
| CPU time | 190.35 seconds |
| Started | Jul 27 07:55:17 PM PDT 24 |
| Finished | Jul 27 07:58:28 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-4f2a0aff-b689-4dde-9e66-e29ac5b7718e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353587 136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1353587136 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.117694284 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 6207363994 ps |
| CPU time | 567.43 seconds |
| Started | Jul 27 07:54:03 PM PDT 24 |
| Finished | Jul 27 08:03:30 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-26497a23-d97b-4c7a-ab7c-6307f72b7c4e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117694284 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.117694284 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3173350918 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 10178730872 ps |
| CPU time | 1168.43 seconds |
| Started | Jul 27 07:54:22 PM PDT 24 |
| Finished | Jul 27 08:13:51 PM PDT 24 |
| Peak memory | 611408 kb |
| Host | smart-0e95240b-b4d5-4dde-b11f-dffc5ddca181 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173350918 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3173350918 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1587444952 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 8530756712 ps |
| CPU time | 722.24 seconds |
| Started | Jul 27 07:54:03 PM PDT 24 |
| Finished | Jul 27 08:06:05 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-7786047e-c462-4b33-b505-26ab57913801 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587444952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1587444952 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3448583793 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 8155664894 ps |
| CPU time | 840.15 seconds |
| Started | Jul 27 07:54:31 PM PDT 24 |
| Finished | Jul 27 08:08:32 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-54831fb0-f9e1-40b8-b2af-7f6338306572 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448583793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.3448583793 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3808922766 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 7375989250 ps |
| CPU time | 723.1 seconds |
| Started | Jul 27 07:53:37 PM PDT 24 |
| Finished | Jul 27 08:05:41 PM PDT 24 |
| Peak memory | 625456 kb |
| Host | smart-75aa136d-40af-4897-a53c-da865197c1e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808922766 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3808922766 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2917033210 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3932448400 ps |
| CPU time | 565.85 seconds |
| Started | Jul 27 07:55:23 PM PDT 24 |
| Finished | Jul 27 08:04:49 PM PDT 24 |
| Peak memory | 625424 kb |
| Host | smart-367d3ead-ea85-4ac2-81fb-4f05d205f475 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917033210 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2917033210 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3433407908 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3530438461 ps |
| CPU time | 370.43 seconds |
| Started | Jul 27 07:51:59 PM PDT 24 |
| Finished | Jul 27 07:58:09 PM PDT 24 |
| Peak memory | 619708 kb |
| Host | smart-f259b4d8-1e99-4db3-9b74-22070b376b54 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433407908 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.3433407908 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2712180742 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3398376798 ps |
| CPU time | 368.47 seconds |
| Started | Jul 27 07:52:49 PM PDT 24 |
| Finished | Jul 27 07:58:57 PM PDT 24 |
| Peak memory | 620280 kb |
| Host | smart-59ef62c4-704b-4f3e-8152-7e89a8f443bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712180742 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2712180742 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2010918145 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4801593180 ps |
| CPU time | 653.34 seconds |
| Started | Jul 27 07:52:26 PM PDT 24 |
| Finished | Jul 27 08:03:20 PM PDT 24 |
| Peak memory | 611324 kb |
| Host | smart-e47a3222-09ba-4797-bbe4-3cccccdb447a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010918145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2010918145 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2386368639 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4149377757 ps |
| CPU time | 724.35 seconds |
| Started | Jul 27 07:56:14 PM PDT 24 |
| Finished | Jul 27 08:08:20 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-61289c15-8986-48ba-987c-49037907baca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386368639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2386368639 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1154513993 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4502130303 ps |
| CPU time | 506.53 seconds |
| Started | Jul 27 07:51:57 PM PDT 24 |
| Finished | Jul 27 08:00:25 PM PDT 24 |
| Peak memory | 611636 kb |
| Host | smart-de98151d-1239-47cb-90e6-ba0cedafbbe1 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154513993 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1154513993 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1108193580 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 2914727600 ps |
| CPU time | 197.1 seconds |
| Started | Jul 27 07:56:39 PM PDT 24 |
| Finished | Jul 27 07:59:56 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-2117b8ef-e609-4e29-8621-65c9c7a28a37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108193580 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1108193580 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1929003140 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 20932982877 ps |
| CPU time | 3922.76 seconds |
| Started | Jul 27 07:52:18 PM PDT 24 |
| Finished | Jul 27 08:57:41 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-2a241ab1-e2f0-4c11-8621-c12e07e4e4a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929003140 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1929003140 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.206078387 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 5318325583 ps |
| CPU time | 607.86 seconds |
| Started | Jul 27 07:57:31 PM PDT 24 |
| Finished | Jul 27 08:07:41 PM PDT 24 |
| Peak memory | 614496 kb |
| Host | smart-192eb136-8877-4fa4-abe0-af1f9582e412 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206078387 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.206078387 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.511777571 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2575222145 ps |
| CPU time | 325.69 seconds |
| Started | Jul 27 07:56:17 PM PDT 24 |
| Finished | Jul 27 08:01:44 PM PDT 24 |
| Peak memory | 613780 kb |
| Host | smart-cd7ed3a1-90c3-4303-a070-2f908344c996 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511777571 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.511777571 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3251387489 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4941874896 ps |
| CPU time | 396.26 seconds |
| Started | Jul 27 07:52:26 PM PDT 24 |
| Finished | Jul 27 07:59:03 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-0bd688c8-fd00-4edd-89d4-04f382f46e0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251387489 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3251387489 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.433805820 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 7888291878 ps |
| CPU time | 1808.39 seconds |
| Started | Jul 27 07:52:44 PM PDT 24 |
| Finished | Jul 27 08:22:55 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-e1973dfe-e61c-43b3-8e8e-b6ec88ef2435 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=433805820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.433805820 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.655834529 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3491835500 ps |
| CPU time | 262.31 seconds |
| Started | Jul 27 07:55:47 PM PDT 24 |
| Finished | Jul 27 08:00:10 PM PDT 24 |
| Peak memory | 617792 kb |
| Host | smart-fc62f21f-faa3-47bf-b673-4ea8bbd82f1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655834529 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.655834529 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.84218960 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 4018660300 ps |
| CPU time | 600.67 seconds |
| Started | Jul 27 07:51:33 PM PDT 24 |
| Finished | Jul 27 08:01:34 PM PDT 24 |
| Peak memory | 625328 kb |
| Host | smart-260fd917-6282-47be-881c-8b16a99bcefa |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84218960 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.84218960 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.750814766 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8442065342 ps |
| CPU time | 1930 seconds |
| Started | Jul 27 07:56:04 PM PDT 24 |
| Finished | Jul 27 08:28:16 PM PDT 24 |
| Peak memory | 625284 kb |
| Host | smart-1b9735a4-c7db-4abb-873c-78d70c346bcb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750814766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.750814766 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.733780322 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 8474795458 ps |
| CPU time | 1133.36 seconds |
| Started | Jul 27 07:53:20 PM PDT 24 |
| Finished | Jul 27 08:12:14 PM PDT 24 |
| Peak memory | 625276 kb |
| Host | smart-1fa171ee-f952-473c-9847-5b84402d79bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733780322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.733780322 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.189183549 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 78362166754 ps |
| CPU time | 15892.9 seconds |
| Started | Jul 27 07:52:13 PM PDT 24 |
| Finished | Jul 28 12:17:07 AM PDT 24 |
| Peak memory | 636656 kb |
| Host | smart-792159b0-8fae-4dc5-980e-84637f3f8aa0 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=189183549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.189183549 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1962938528 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 5009794560 ps |
| CPU time | 677.42 seconds |
| Started | Jul 27 07:53:00 PM PDT 24 |
| Finished | Jul 27 08:04:18 PM PDT 24 |
| Peak memory | 625340 kb |
| Host | smart-c49211c1-046b-403b-9737-48c61f157617 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962938528 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1962938528 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1380636478 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 4197855872 ps |
| CPU time | 572.71 seconds |
| Started | Jul 27 07:52:01 PM PDT 24 |
| Finished | Jul 27 08:01:34 PM PDT 24 |
| Peak memory | 625268 kb |
| Host | smart-975423e2-bfd5-4560-b764-3f7304be5b54 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380636478 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1380636478 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3052815909 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 3367392230 ps |
| CPU time | 300.72 seconds |
| Started | Jul 27 07:58:55 PM PDT 24 |
| Finished | Jul 27 08:03:55 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-bb8950b3-891a-4ebd-94cf-9c524ec192d3 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052815909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3052815909 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.2482959228 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8122766400 ps |
| CPU time | 1867.81 seconds |
| Started | Jul 27 07:52:58 PM PDT 24 |
| Finished | Jul 27 08:24:07 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-b4286971-0826-4f93-9a9f-be14cd08d0e2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829 59228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2482959228 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2614400107 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12441311884 ps |
| CPU time | 3085.52 seconds |
| Started | Jul 27 07:52:34 PM PDT 24 |
| Finished | Jul 27 08:44:01 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-102ff646-eaa5-4c58-80a7-d4419b5abfd8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2614400107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2614400107 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.1573951726 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2340312208 ps |
| CPU time | 253.98 seconds |
| Started | Jul 27 07:52:37 PM PDT 24 |
| Finished | Jul 27 07:56:52 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-dd033c27-346f-4f3f-8008-9cceb03f1c71 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573951726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1573951726 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1456482051 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3227681166 ps |
| CPU time | 542.84 seconds |
| Started | Jul 27 07:54:09 PM PDT 24 |
| Finished | Jul 27 08:03:13 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-2a7d9f27-0d08-4474-8e87-f23106ab1b09 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145648205 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1456482051 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3293489935 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 18254379608 ps |
| CPU time | 5032.75 seconds |
| Started | Jul 27 07:53:03 PM PDT 24 |
| Finished | Jul 27 09:16:56 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-c5f47228-fa9e-4fa4-9e26-0324968c55ed |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3293489935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3293489935 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3306219885 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3085346174 ps |
| CPU time | 332.32 seconds |
| Started | Jul 27 07:55:34 PM PDT 24 |
| Finished | Jul 27 08:01:07 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-cf86472a-618d-4284-ac7e-fe89bf0ed112 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306219885 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3306219885 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.1844490973 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2646122884 ps |
| CPU time | 161.53 seconds |
| Started | Jul 27 07:57:02 PM PDT 24 |
| Finished | Jul 27 07:59:44 PM PDT 24 |
| Peak memory | 622136 kb |
| Host | smart-80894d09-31d6-4b2b-b52a-501fe096a0de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1844490973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1844490973 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.3416886046 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3132994911 ps |
| CPU time | 169.49 seconds |
| Started | Jul 27 07:52:14 PM PDT 24 |
| Finished | Jul 27 07:55:04 PM PDT 24 |
| Peak memory | 622968 kb |
| Host | smart-23415991-b1cd-4f1c-a6d0-a4a959a06084 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416886046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3416886046 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3191633063 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 15847677524 ps |
| CPU time | 4384.33 seconds |
| Started | Jul 27 07:58:54 PM PDT 24 |
| Finished | Jul 27 09:11:59 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-fe528cf9-c932-40ad-a9c5-2b3754e54c87 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191633063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3191633063 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.4140257248 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 15178036882 ps |
| CPU time | 4111.43 seconds |
| Started | Jul 27 07:59:01 PM PDT 24 |
| Finished | Jul 27 09:07:33 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-9e736033-00e5-417e-a78d-999aaaac47af |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140257248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.4140257248 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2808247080 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 15574287450 ps |
| CPU time | 4243.42 seconds |
| Started | Jul 27 07:55:43 PM PDT 24 |
| Finished | Jul 27 09:06:27 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-04bfed2f-4ae9-4196-9d63-7854884aa369 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808247080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2808247080 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.412886485 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 14961980712 ps |
| CPU time | 4150.96 seconds |
| Started | Jul 27 07:58:48 PM PDT 24 |
| Finished | Jul 27 09:07:59 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-87c0d3bf-720f-49ca-97e1-014e41df031b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412886485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_rma.412886485 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4045503775 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 11088136570 ps |
| CPU time | 3255.89 seconds |
| Started | Jul 27 07:58:55 PM PDT 24 |
| Finished | Jul 27 08:53:11 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-73202f83-17d1-4b27-a200-1b4f5f525215 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045503775 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.4045503775 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.128352759 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 24102405230 ps |
| CPU time | 6504.74 seconds |
| Started | Jul 27 07:58:58 PM PDT 24 |
| Finished | Jul 27 09:47:24 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-73e248d5-ad5b-4eb5-8f0d-03a64690ff1a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=128352759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.128352759 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3546701670 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 23803301160 ps |
| CPU time | 7400.35 seconds |
| Started | Jul 27 08:10:33 PM PDT 24 |
| Finished | Jul 27 10:13:54 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-d3281b87-8779-4d64-b405-a4a9421cc14d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3546701670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3546701670 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2871751705 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 24241424616 ps |
| CPU time | 6488.4 seconds |
| Started | Jul 27 08:10:32 PM PDT 24 |
| Finished | Jul 27 09:58:41 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-5bd7c73b-6a88-46b3-ac2a-e1fcf03ca36e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2871751705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2871751705 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2896551583 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 18829407976 ps |
| CPU time | 4841.85 seconds |
| Started | Jul 27 08:01:54 PM PDT 24 |
| Finished | Jul 27 09:22:37 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-264ed62d-f587-45a1-8d87-a67105ee614d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896551583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2896551583 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1476973884 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 15080934296 ps |
| CPU time | 4346.69 seconds |
| Started | Jul 27 07:56:52 PM PDT 24 |
| Finished | Jul 27 09:09:20 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-4d843c52-fbea-49eb-9581-3be971936005 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1476973884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1476973884 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2573665515 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 15755523040 ps |
| CPU time | 3801.52 seconds |
| Started | Jul 27 08:04:02 PM PDT 24 |
| Finished | Jul 27 09:07:24 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-7ec6badc-3dbd-4f1b-bec5-0df572a4dab7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2573665515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2573665515 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1385887310 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 15729143030 ps |
| CPU time | 4589.28 seconds |
| Started | Jul 27 07:58:14 PM PDT 24 |
| Finished | Jul 27 09:14:44 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-3ac9fc95-d590-486c-bb85-5c55ba570ecb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1385887310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1385887310 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2433099814 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13954529870 ps |
| CPU time | 3955.02 seconds |
| Started | Jul 27 08:01:23 PM PDT 24 |
| Finished | Jul 27 09:07:18 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-7888e73f-3e9a-404d-9024-fdb2bf61a844 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2433099814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2433099814 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3450475643 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 12219719660 ps |
| CPU time | 3339.24 seconds |
| Started | Jul 27 08:03:26 PM PDT 24 |
| Finished | Jul 27 08:59:06 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-1afc3f78-dd67-4bac-8fb6-9b645f23fe2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450475643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3450475643 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3014798398 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 15074568380 ps |
| CPU time | 4541.11 seconds |
| Started | Jul 27 08:00:34 PM PDT 24 |
| Finished | Jul 27 09:16:16 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-b05c04f4-ab81-444a-9eff-a4fb6e0da534 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014798398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3014798398 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.404445936 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 15165620280 ps |
| CPU time | 4488.41 seconds |
| Started | Jul 27 07:55:51 PM PDT 24 |
| Finished | Jul 27 09:10:41 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-4199137f-078e-4b75-8d05-7e9903237f0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404445936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.404445936 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2504659545 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 15749277230 ps |
| CPU time | 3967.13 seconds |
| Started | Jul 27 07:58:02 PM PDT 24 |
| Finished | Jul 27 09:04:10 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-91965981-22e8-4405-a3a5-adcdbb1688f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250465 9545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2504659545 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1225500564 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 15393496500 ps |
| CPU time | 4283.38 seconds |
| Started | Jul 27 08:01:09 PM PDT 24 |
| Finished | Jul 27 09:12:33 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-22727cbe-2dc6-40d0-bfc2-f26a7ad387e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225500564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1225500564 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2223712574 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 11883393544 ps |
| CPU time | 3137.5 seconds |
| Started | Jul 27 07:58:10 PM PDT 24 |
| Finished | Jul 27 08:50:28 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-240439c8-01ba-4763-a5fc-33e19733fa18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2223712574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2223712574 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3113251375 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 10665936435 ps |
| CPU time | 1693.57 seconds |
| Started | Jul 27 07:52:46 PM PDT 24 |
| Finished | Jul 27 08:21:01 PM PDT 24 |
| Peak memory | 624944 kb |
| Host | smart-9da5d794-057d-4fce-9a85-d8a2cdc2adc0 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132 51375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3113251375 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3242105864 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 11584228273 ps |
| CPU time | 2140.11 seconds |
| Started | Jul 27 07:55:34 PM PDT 24 |
| Finished | Jul 27 08:31:16 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-83be1e88-b96e-4f0c-91c6-883540d90db3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421 05864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3242105864 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.240825481 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 10791162455 ps |
| CPU time | 1989.69 seconds |
| Started | Jul 27 07:56:28 PM PDT 24 |
| Finished | Jul 27 08:29:38 PM PDT 24 |
| Peak memory | 624792 kb |
| Host | smart-8cf59134-e4da-4086-bde9-d9ab24464651 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=240825481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.240825481 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3311260363 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 25644381517 ps |
| CPU time | 2975.2 seconds |
| Started | Jul 27 07:52:01 PM PDT 24 |
| Finished | Jul 27 08:41:37 PM PDT 24 |
| Peak memory | 622344 kb |
| Host | smart-8c61b148-f98b-4551-ae8c-f9fc898658bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3311260363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3311260363 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.325173911 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 26447555996 ps |
| CPU time | 3042.47 seconds |
| Started | Jul 27 07:54:13 PM PDT 24 |
| Finished | Jul 27 08:44:56 PM PDT 24 |
| Peak memory | 622372 kb |
| Host | smart-f87acc40-f365-40c1-9f74-b9e7b1977f21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=325173911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.325173911 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4119738629 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 24408957016 ps |
| CPU time | 3693.35 seconds |
| Started | Jul 27 07:54:30 PM PDT 24 |
| Finished | Jul 27 08:56:04 PM PDT 24 |
| Peak memory | 622092 kb |
| Host | smart-3c48a2cb-e1a8-4de6-9e4b-1a89e66e84cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119738629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.4119738629 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3589505530 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 14745271512 ps |
| CPU time | 4252.48 seconds |
| Started | Jul 27 07:59:02 PM PDT 24 |
| Finished | Jul 27 09:09:55 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-6a72f632-5392-4ccd-90dd-a0f0fd0fc4ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589505530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3589505530 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2381671532 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 14979346760 ps |
| CPU time | 4105.3 seconds |
| Started | Jul 27 07:59:13 PM PDT 24 |
| Finished | Jul 27 09:07:40 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-e0e6e16f-1825-4d77-be9f-4dd1920ed9ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381671532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.2381671532 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1306102548 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 15170186850 ps |
| CPU time | 3801.73 seconds |
| Started | Jul 27 07:58:35 PM PDT 24 |
| Finished | Jul 27 09:01:57 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-e59f5e02-3f42-4b55-bcf9-52a848b363c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306102548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1306102548 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.1737179698 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 26040171306 ps |
| CPU time | 5994.65 seconds |
| Started | Jul 27 08:02:34 PM PDT 24 |
| Finished | Jul 27 09:42:29 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-512856d0-bff9-4756-9fe4-d3ec61aa9796 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737179698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.1737179698 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3051949329 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 14679158120 ps |
| CPU time | 3908.4 seconds |
| Started | Jul 27 08:02:10 PM PDT 24 |
| Finished | Jul 27 09:07:19 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-7f2fab20-8b6d-43c9-b660-5d303e9655c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051949329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3051949329 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.530718154 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 28754957580 ps |
| CPU time | 3816.81 seconds |
| Started | Jul 27 07:57:07 PM PDT 24 |
| Finished | Jul 27 09:00:45 PM PDT 24 |
| Peak memory | 611972 kb |
| Host | smart-94f9aec4-fcd9-4148-a227-08b25938d413 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530718154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.530718154 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1594364746 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 23596307729 ps |
| CPU time | 7198.23 seconds |
| Started | Jul 27 08:10:28 PM PDT 24 |
| Finished | Jul 27 10:10:27 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-04cd553c-ad5e-4123-93a2-33ba42f31276 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1594364746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.1594364746 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3509974600 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 23879954484 ps |
| CPU time | 7079.7 seconds |
| Started | Jul 27 08:09:21 PM PDT 24 |
| Finished | Jul 27 10:07:23 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-bda6a777-e560-4c76-8765-6be543cedbba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3509974600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3509974600 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2639644240 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 23842899080 ps |
| CPU time | 6213.83 seconds |
| Started | Jul 27 08:00:02 PM PDT 24 |
| Finished | Jul 27 09:43:40 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-2652a777-e344-4d34-9112-6bd0827094ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2639644240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.2639644240 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.860226940 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 22792542556 ps |
| CPU time | 5384.87 seconds |
| Started | Jul 27 07:59:15 PM PDT 24 |
| Finished | Jul 27 09:29:00 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-45b3d842-53e7-4ab4-8d76-96036788c421 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=860226940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_ bad_rma.860226940 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.763411449 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 17534865430 ps |
| CPU time | 4946.03 seconds |
| Started | Jul 27 07:59:36 PM PDT 24 |
| Finished | Jul 27 09:22:03 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-e7ebdeec-f98e-4c38-baa5-d0399ca9a4db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=763411449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_ bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alwa ys_a_bad_b_bad_test_unlocked0.763411449 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1173108087 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 15014974325 ps |
| CPU time | 4642.04 seconds |
| Started | Jul 27 08:09:52 PM PDT 24 |
| Finished | Jul 27 09:27:16 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-e3bad2d2-202c-4413-beab-231804943a31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173108087 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1173108087 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2564942218 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 14049723479 ps |
| CPU time | 4467.68 seconds |
| Started | Jul 27 08:04:38 PM PDT 24 |
| Finished | Jul 27 09:19:06 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-5f0091b4-d08f-4683-acd5-efc66da9f563 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564942218 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2564942218 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1339357605 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 14913426552 ps |
| CPU time | 4157.68 seconds |
| Started | Jul 27 07:59:01 PM PDT 24 |
| Finished | Jul 27 09:08:20 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-9e8193d2-1be7-4277-8db3-72def4222f20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339357605 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1339357605 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2812385685 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 14124539472 ps |
| CPU time | 4482.27 seconds |
| Started | Jul 27 07:57:30 PM PDT 24 |
| Finished | Jul 27 09:12:13 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-06f83d3e-251c-4bd3-9138-eb9ea96351e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812385685 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2812385685 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3924848000 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 11488784917 ps |
| CPU time | 3652.13 seconds |
| Started | Jul 27 07:58:54 PM PDT 24 |
| Finished | Jul 27 08:59:47 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-997049b3-0c4d-4aff-8eec-3c92b6d7e50a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924848000 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3924848000 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.50486609 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 14521193590 ps |
| CPU time | 4562.82 seconds |
| Started | Jul 27 07:59:41 PM PDT 24 |
| Finished | Jul 27 09:15:44 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-271a3f55-b6f8-4f19-a0b5-661569fcb25b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50486609 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.50486609 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3023505059 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 15067149640 ps |
| CPU time | 4891.3 seconds |
| Started | Jul 27 08:08:49 PM PDT 24 |
| Finished | Jul 27 09:30:22 PM PDT 24 |
| Peak memory | 610880 kb |
| Host | smart-fe65ef94-0367-45fe-af17-a9c70acd261c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023505059 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3023505059 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2353860358 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 14679544562 ps |
| CPU time | 4266.19 seconds |
| Started | Jul 27 07:58:33 PM PDT 24 |
| Finished | Jul 27 09:09:40 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-4ee1aa36-4bcd-43bd-ac58-b9e2e174e401 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353860358 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2353860358 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.617288915 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 11091484903 ps |
| CPU time | 3082.51 seconds |
| Started | Jul 27 08:02:26 PM PDT 24 |
| Finished | Jul 27 08:53:49 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-a79084fb-bf02-4e92-8bb2-7d52c5acd8f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617288915 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.617288915 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.3534321368 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 14450679498 ps |
| CPU time | 4058.83 seconds |
| Started | Jul 27 07:56:43 PM PDT 24 |
| Finished | Jul 27 09:04:22 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-76ad8a94-4fc8-4c92-8773-032d2625bb9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3534321368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.3534321368 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.3106130774 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 17131938796 ps |
| CPU time | 4724.19 seconds |
| Started | Jul 27 08:01:07 PM PDT 24 |
| Finished | Jul 27 09:19:51 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-b51314a0-dc61-488f-86f3-3c4fe104eb28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106130774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3106130774 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.4232791118 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 4039283256 ps |
| CPU time | 511.44 seconds |
| Started | Jul 27 07:52:00 PM PDT 24 |
| Finished | Jul 27 08:00:32 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-b4656d7b-9f7c-4dca-82c5-0c3216ef6191 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232791118 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.4232791118 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.2231105905 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5982867073 ps |
| CPU time | 224.52 seconds |
| Started | Jul 27 07:54:08 PM PDT 24 |
| Finished | Jul 27 07:57:52 PM PDT 24 |
| Peak memory | 623816 kb |
| Host | smart-3e0f419a-87a0-4678-aea9-69f00b39ac45 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2231105905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.2231105905 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.3120484269 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 2245170201 ps |
| CPU time | 90.78 seconds |
| Started | Jul 27 07:53:33 PM PDT 24 |
| Finished | Jul 27 07:55:04 PM PDT 24 |
| Peak memory | 618432 kb |
| Host | smart-3360d593-53c0-44a0-8bb5-5f34beca3150 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120484269 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3120484269 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.1383497337 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 13327747720 ps |
| CPU time | 1602.78 seconds |
| Started | Jul 27 07:59:07 PM PDT 24 |
| Finished | Jul 27 08:25:50 PM PDT 24 |
| Peak memory | 607384 kb |
| Host | smart-b3fe85cc-75bf-4888-8d51-1b4e2e141e1b |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383497337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1 383497337 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2114117455 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 4503169378 ps |
| CPU time | 449.89 seconds |
| Started | Jul 27 08:06:52 PM PDT 24 |
| Finished | Jul 27 08:14:22 PM PDT 24 |
| Peak memory | 620540 kb |
| Host | smart-52b1c945-d095-40f8-8fc5-2eddbd32f418 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 114117455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2114117455 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1158310453 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3285791492 ps |
| CPU time | 285.48 seconds |
| Started | Jul 27 07:55:29 PM PDT 24 |
| Finished | Jul 27 08:00:15 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-4e00d709-c1e3-48f0-8177-42ea07595cfc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1158310453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1158310453 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1418349659 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 19736852198 ps |
| CPU time | 720.71 seconds |
| Started | Jul 27 07:58:52 PM PDT 24 |
| Finished | Jul 27 08:10:54 PM PDT 24 |
| Peak memory | 619952 kb |
| Host | smart-b588a319-ae0d-4686-bf95-d3623510fd9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1418349659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1418349659 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.3790614894 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 2753917674 ps |
| CPU time | 232.62 seconds |
| Started | Jul 27 07:59:30 PM PDT 24 |
| Finished | Jul 27 08:03:23 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-a9137f2d-f790-412d-a044-e043367b1f54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790614894 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3790614894 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.410711311 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 2864552540 ps |
| CPU time | 187.76 seconds |
| Started | Jul 27 07:59:41 PM PDT 24 |
| Finished | Jul 27 08:02:49 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-ff00fa63-2f7b-48b9-891c-a1648faf3828 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107 11311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.410711311 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.110816217 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 3646058262 ps |
| CPU time | 306.22 seconds |
| Started | Jul 27 08:07:30 PM PDT 24 |
| Finished | Jul 27 08:12:37 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-84480bc1-20ab-4d16-8657-953a7d4fa5e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110816217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.110816217 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.2744740850 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2454773508 ps |
| CPU time | 257.06 seconds |
| Started | Jul 27 08:07:36 PM PDT 24 |
| Finished | Jul 27 08:11:55 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-e681fd2e-efb7-4d29-bfd1-ffb2dc756917 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744740850 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2744740850 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.1386648373 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2601360290 ps |
| CPU time | 198.34 seconds |
| Started | Jul 27 08:00:34 PM PDT 24 |
| Finished | Jul 27 08:03:52 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-2fcf255e-6af9-4aa4-a660-7a6cd7bc9669 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386648373 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1386648373 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3158687128 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 3572379681 ps |
| CPU time | 372.37 seconds |
| Started | Jul 27 07:59:17 PM PDT 24 |
| Finished | Jul 27 08:05:30 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-7c9150b1-8e4d-4f1e-aee6-f2c4f3d4ab36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158687128 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3158687128 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.3257072098 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2971447690 ps |
| CPU time | 337.88 seconds |
| Started | Jul 27 08:08:10 PM PDT 24 |
| Finished | Jul 27 08:13:48 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-d6516582-f672-4cd3-bffa-529b7a36555d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257072098 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.3257072098 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.457507324 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2861354252 ps |
| CPU time | 279.9 seconds |
| Started | Jul 27 08:02:05 PM PDT 24 |
| Finished | Jul 27 08:06:45 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-97f8c4d3-153a-41ab-82e2-374066b8d591 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=457507324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.457507324 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3266733076 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 5799226584 ps |
| CPU time | 605.45 seconds |
| Started | Jul 27 07:59:54 PM PDT 24 |
| Finished | Jul 27 08:09:59 PM PDT 24 |
| Peak memory | 624320 kb |
| Host | smart-08d54bcd-c602-4270-af16-a9a43ea55327 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3266733076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3266733076 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.101266911 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 7638374528 ps |
| CPU time | 1718.71 seconds |
| Started | Jul 27 08:00:18 PM PDT 24 |
| Finished | Jul 27 08:28:57 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-835865e9-3ef4-4adc-bdd6-037733d91d4e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=101266911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.101266911 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.80487881 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 7733147158 ps |
| CPU time | 1762.89 seconds |
| Started | Jul 27 08:01:06 PM PDT 24 |
| Finished | Jul 27 08:30:29 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-a915f045-280b-4d7f-abd0-e21134209c03 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80487881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.80487881 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1818474448 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 12442648680 ps |
| CPU time | 1559.6 seconds |
| Started | Jul 27 08:02:10 PM PDT 24 |
| Finished | Jul 27 08:28:10 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-21cb8903-5390-4d59-bab1-63125cc8602d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818474448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1818474448 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1056053120 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 8131121036 ps |
| CPU time | 1756.6 seconds |
| Started | Jul 27 08:01:15 PM PDT 24 |
| Finished | Jul 27 08:30:32 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-d661cab2-a710-4a03-a222-8508a9e7a701 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1056053120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1056053120 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2744550931 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4986807616 ps |
| CPU time | 492.6 seconds |
| Started | Jul 27 08:00:49 PM PDT 24 |
| Finished | Jul 27 08:09:02 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-a2b327a0-5ff9-4144-9686-049e2b9af1fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2744550931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.2744550931 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2760642214 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 256030681144 ps |
| CPU time | 12841.9 seconds |
| Started | Jul 27 08:00:42 PM PDT 24 |
| Finished | Jul 27 11:34:45 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-c157e17a-f6c8-4bb3-800c-3719bc676d69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760642214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2760642214 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.841017194 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4087774168 ps |
| CPU time | 517.13 seconds |
| Started | Jul 27 08:02:11 PM PDT 24 |
| Finished | Jul 27 08:10:48 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-0bf00a57-b8a9-41ae-b369-aca416e35c10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841017194 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.841017194 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1362342289 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 7743463728 ps |
| CPU time | 576.95 seconds |
| Started | Jul 27 08:00:35 PM PDT 24 |
| Finished | Jul 27 08:10:12 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-5ae1cb3b-23d3-4bf5-9a73-cd699384d753 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1362342289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1362342289 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3103633948 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3238925526 ps |
| CPU time | 279.43 seconds |
| Started | Jul 27 08:08:33 PM PDT 24 |
| Finished | Jul 27 08:13:13 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-118396e2-de55-4d78-8742-b177e01f6ca5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103633948 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3103633948 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2634581706 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 8522036554 ps |
| CPU time | 1186.48 seconds |
| Started | Jul 27 07:59:37 PM PDT 24 |
| Finished | Jul 27 08:19:23 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-4ed49233-90a0-4280-ae8a-868db6070cfa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2634581706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2634581706 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.4157454381 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 5264656820 ps |
| CPU time | 740.75 seconds |
| Started | Jul 27 08:02:45 PM PDT 24 |
| Finished | Jul 27 08:15:06 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-09c74eca-8869-4a31-a705-d0ae8d17ddaf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4157454381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.4157454381 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2343637770 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 7069233662 ps |
| CPU time | 1206.89 seconds |
| Started | Jul 27 08:08:08 PM PDT 24 |
| Finished | Jul 27 08:28:16 PM PDT 24 |
| Peak memory | 616888 kb |
| Host | smart-3f18a79d-93c1-46c6-9227-05e2d8c28bdc |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343637770 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2343637770 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1873712759 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 18233875463 ps |
| CPU time | 2235.73 seconds |
| Started | Jul 27 08:07:14 PM PDT 24 |
| Finished | Jul 27 08:44:31 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-169ac576-f242-4914-80be-f985046da67c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873712759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1873712759 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3263776884 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 7425551079 ps |
| CPU time | 546.36 seconds |
| Started | Jul 27 08:04:26 PM PDT 24 |
| Finished | Jul 27 08:13:33 PM PDT 24 |
| Peak memory | 621096 kb |
| Host | smart-3d4bac05-182f-4111-90e8-841cbc030a38 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3263776884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3263776884 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2055602797 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3560571300 ps |
| CPU time | 688.83 seconds |
| Started | Jul 27 08:06:39 PM PDT 24 |
| Finished | Jul 27 08:18:08 PM PDT 24 |
| Peak memory | 612664 kb |
| Host | smart-665098e1-305f-4ea2-a019-2921fc1e897a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055602797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2055602797 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2035742629 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3654118940 ps |
| CPU time | 703.94 seconds |
| Started | Jul 27 08:05:47 PM PDT 24 |
| Finished | Jul 27 08:17:31 PM PDT 24 |
| Peak memory | 613368 kb |
| Host | smart-40000f08-8cea-4ce2-b725-e560adf06eb5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035742629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2035742629 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.878417432 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 3586648656 ps |
| CPU time | 608.41 seconds |
| Started | Jul 27 08:05:54 PM PDT 24 |
| Finished | Jul 27 08:16:03 PM PDT 24 |
| Peak memory | 613356 kb |
| Host | smart-c1c7dee8-8398-47b0-95e3-2f7ad4355cc6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878417432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.878417432 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1589908929 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4700640080 ps |
| CPU time | 613.26 seconds |
| Started | Jul 27 08:05:47 PM PDT 24 |
| Finished | Jul 27 08:16:00 PM PDT 24 |
| Peak memory | 612668 kb |
| Host | smart-9c8b2ab3-65fe-4a0f-8387-c3f995fd6d11 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589908929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1589908929 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2988968210 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4924965700 ps |
| CPU time | 796.46 seconds |
| Started | Jul 27 08:10:51 PM PDT 24 |
| Finished | Jul 27 08:24:09 PM PDT 24 |
| Peak memory | 612680 kb |
| Host | smart-232f6024-c23c-4ee2-9549-8d38aaa93cbb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988968210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2988968210 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1536637696 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 4254303358 ps |
| CPU time | 686.96 seconds |
| Started | Jul 27 08:05:22 PM PDT 24 |
| Finished | Jul 27 08:16:50 PM PDT 24 |
| Peak memory | 613620 kb |
| Host | smart-b96674a4-120f-4b34-8125-0e781cebe2f6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536637696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1536637696 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2448593730 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2509043171 ps |
| CPU time | 195.64 seconds |
| Started | Jul 27 08:05:44 PM PDT 24 |
| Finished | Jul 27 08:09:01 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-e36964c6-5891-4845-bc29-8fc38909048e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448593730 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.2448593730 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1612838886 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3949711556 ps |
| CPU time | 456.49 seconds |
| Started | Jul 27 08:05:56 PM PDT 24 |
| Finished | Jul 27 08:13:32 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-bfaeca24-4d25-4689-94dd-080609fb30f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612838886 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1612838886 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1207546853 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 2902497935 ps |
| CPU time | 203.5 seconds |
| Started | Jul 27 08:07:36 PM PDT 24 |
| Finished | Jul 27 08:11:00 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-2f40dcd6-9b71-4127-b0ae-550515c8640f |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207546853 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1207546853 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.846573585 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 5313659928 ps |
| CPU time | 507.87 seconds |
| Started | Jul 27 08:04:35 PM PDT 24 |
| Finished | Jul 27 08:13:03 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-c52f9701-47eb-4cc4-8406-095b331c53af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846573585 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.846573585 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2434236345 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5123847340 ps |
| CPU time | 545.6 seconds |
| Started | Jul 27 08:05:33 PM PDT 24 |
| Finished | Jul 27 08:14:39 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-a30756dd-658f-4a2d-8931-1f4129266279 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434236345 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2434236345 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1149353842 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 5219771080 ps |
| CPU time | 658.54 seconds |
| Started | Jul 27 08:05:14 PM PDT 24 |
| Finished | Jul 27 08:16:14 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-eabbb041-6896-4e2a-b383-e5275e9c7a3f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149353842 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1149353842 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.943403484 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3690926920 ps |
| CPU time | 344.53 seconds |
| Started | Jul 27 08:05:15 PM PDT 24 |
| Finished | Jul 27 08:10:59 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-6445e83b-bace-449b-945d-a3527220a381 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943403484 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.943403484 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3920362134 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 10248458008 ps |
| CPU time | 1360.79 seconds |
| Started | Jul 27 08:05:22 PM PDT 24 |
| Finished | Jul 27 08:28:03 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-1d9a1878-651f-409f-82f1-1c59515d7d5d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920362134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3920362134 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.870402001 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3787917138 ps |
| CPU time | 518.1 seconds |
| Started | Jul 27 08:06:08 PM PDT 24 |
| Finished | Jul 27 08:14:46 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-fc298d47-b66f-4275-8278-434dc90e2ee4 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870402001 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.870402001 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3140994228 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4275141182 ps |
| CPU time | 805.09 seconds |
| Started | Jul 27 08:06:26 PM PDT 24 |
| Finished | Jul 27 08:19:51 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-2969c87b-d0cf-4e9e-8e74-ede10c87c0b3 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140994228 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3140994228 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2995212094 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3490121510 ps |
| CPU time | 288.86 seconds |
| Started | Jul 27 08:07:40 PM PDT 24 |
| Finished | Jul 27 08:12:29 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-c4505395-e496-4b00-97e6-eedc73decd62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995212094 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2995212094 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.257826588 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 17686811240 ps |
| CPU time | 4363.88 seconds |
| Started | Jul 27 08:01:50 PM PDT 24 |
| Finished | Jul 27 09:14:34 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-66a6b3f1-3066-4d36-9680-c6e6e19c93fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257826588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.257826588 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4247071407 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 194594143208 ps |
| CPU time | 26217.5 seconds |
| Started | Jul 27 08:08:22 PM PDT 24 |
| Finished | Jul 28 03:25:23 AM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-52f2232b-54f9-469a-aefd-6800142b9824 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4247071407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.4247071407 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.800288241 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4539124300 ps |
| CPU time | 481.72 seconds |
| Started | Jul 27 08:02:39 PM PDT 24 |
| Finished | Jul 27 08:10:41 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-a9bcbb07-90fd-4f74-9904-14624b63ff20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80028 8241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.800288241 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3417766921 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2714636372 ps |
| CPU time | 236.55 seconds |
| Started | Jul 27 08:02:33 PM PDT 24 |
| Finished | Jul 27 08:06:30 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-8ed05077-034d-4b7f-ae71-a97fa6e1644e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417766921 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3417766921 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.936280369 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 5983055056 ps |
| CPU time | 809 seconds |
| Started | Jul 27 08:02:57 PM PDT 24 |
| Finished | Jul 27 08:16:26 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-29a83447-aa3f-4f6e-afc2-23c360f157dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936280369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.936280369 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.4278713723 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3328445190 ps |
| CPU time | 289.4 seconds |
| Started | Jul 27 08:13:05 PM PDT 24 |
| Finished | Jul 27 08:17:55 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-bc53d260-9391-4acf-b54f-3c74081f0312 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278713723 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.4278713723 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.2545439185 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 4792909688 ps |
| CPU time | 995.86 seconds |
| Started | Jul 27 08:01:57 PM PDT 24 |
| Finished | Jul 27 08:18:33 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-7999d09d-25c5-46de-bd9d-697b1d689068 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545439185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2545439185 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.3415401240 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3236408190 ps |
| CPU time | 634.74 seconds |
| Started | Jul 27 08:01:22 PM PDT 24 |
| Finished | Jul 27 08:11:57 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-bc532ed3-b3e5-48b8-92e7-6b22d5d0f741 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415401240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.3415401240 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3162845316 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 6299049496 ps |
| CPU time | 1436.96 seconds |
| Started | Jul 27 08:02:58 PM PDT 24 |
| Finished | Jul 27 08:26:56 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-648ea4e9-43c2-4e65-bb3a-8172c918bc03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3162845316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3162845316 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.998713874 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 6260672233 ps |
| CPU time | 983.64 seconds |
| Started | Jul 27 08:03:07 PM PDT 24 |
| Finished | Jul 27 08:19:31 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-c1214393-e55b-4e96-84da-1656e4349107 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998713874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.998713874 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3132381745 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 2956000568 ps |
| CPU time | 585.54 seconds |
| Started | Jul 27 08:01:22 PM PDT 24 |
| Finished | Jul 27 08:11:08 PM PDT 24 |
| Peak memory | 616740 kb |
| Host | smart-7ecafb7b-1332-4e65-a102-fc6dfe3dd629 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132381745 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3132381745 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.450250865 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 8686439516 ps |
| CPU time | 2333.45 seconds |
| Started | Jul 27 08:02:55 PM PDT 24 |
| Finished | Jul 27 08:41:49 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-6bc56597-56a4-4f97-882f-b7687ba003ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450250865 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.450250865 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3361034778 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2249375290 ps |
| CPU time | 184.6 seconds |
| Started | Jul 27 08:02:59 PM PDT 24 |
| Finished | Jul 27 08:06:04 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-036a6f0b-adfc-4d49-8893-5c86f79b8214 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33 61034778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3361034778 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.5372366 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5970915908 ps |
| CPU time | 1258.24 seconds |
| Started | Jul 27 08:03:15 PM PDT 24 |
| Finished | Jul 27 08:24:13 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-5efc8d6f-9489-4815-9bdc-a9b013e132f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=5372366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.5372366 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1011322182 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 2973448290 ps |
| CPU time | 216.3 seconds |
| Started | Jul 27 08:02:11 PM PDT 24 |
| Finished | Jul 27 08:05:48 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-4eef3766-5ab9-497c-87d6-2679b2e8ca0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011322182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.1011322182 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.169909530 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 3147946168 ps |
| CPU time | 432.72 seconds |
| Started | Jul 27 08:08:46 PM PDT 24 |
| Finished | Jul 27 08:15:58 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-58527519-7fe5-41d7-8094-cafa957a3227 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=169909530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.169909530 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.3180288662 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 2509171528 ps |
| CPU time | 246.07 seconds |
| Started | Jul 27 08:00:14 PM PDT 24 |
| Finished | Jul 27 08:04:20 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-07506d63-4d72-4275-bc6c-cbea71deb36a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180288662 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.3180288662 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1136625811 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2790202564 ps |
| CPU time | 222.52 seconds |
| Started | Jul 27 07:55:51 PM PDT 24 |
| Finished | Jul 27 07:59:33 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-d3abfaa6-068a-49d6-834a-02e516d3702f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136625811 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1136625811 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.2511403486 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 3067833432 ps |
| CPU time | 272.42 seconds |
| Started | Jul 27 07:56:44 PM PDT 24 |
| Finished | Jul 27 08:01:17 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-1f76dacb-c167-44ba-83ca-b6665c37a038 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511403486 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.2511403486 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.3713678269 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 2347516200 ps |
| CPU time | 133.9 seconds |
| Started | Jul 27 07:52:40 PM PDT 24 |
| Finished | Jul 27 07:54:55 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-6967d458-d6d3-4cc1-b225-a15eb84918e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713678269 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3713678269 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.547183730 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 60094482984 ps |
| CPU time | 10551.9 seconds |
| Started | Jul 27 07:56:07 PM PDT 24 |
| Finished | Jul 27 10:52:01 PM PDT 24 |
| Peak memory | 625360 kb |
| Host | smart-d685e32c-92ce-4087-8d53-85527d4588f6 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=547183730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.547183730 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.2318496559 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5137017356 ps |
| CPU time | 835.32 seconds |
| Started | Jul 27 08:07:41 PM PDT 24 |
| Finished | Jul 27 08:21:37 PM PDT 24 |
| Peak memory | 611708 kb |
| Host | smart-922cea38-e391-4437-9a69-14f3b726f858 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2318496559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2318496559 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4214541688 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6334772410 ps |
| CPU time | 1094.98 seconds |
| Started | Jul 27 07:56:09 PM PDT 24 |
| Finished | Jul 27 08:14:25 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-648190eb-e67f-45f3-9276-1e8a7dfac2cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214541688 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.4214541688 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2170120867 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 6145988166 ps |
| CPU time | 837.91 seconds |
| Started | Jul 27 07:53:37 PM PDT 24 |
| Finished | Jul 27 08:07:35 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-1d792f6d-f54a-4d92-bb62-a95bcd677927 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170120867 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2170120867 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.127528185 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 6747232574 ps |
| CPU time | 1092.76 seconds |
| Started | Jul 27 08:07:21 PM PDT 24 |
| Finished | Jul 27 08:25:35 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-d6666d16-3c87-4f91-9c53-7df267744585 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127528185 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.127528185 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2588550434 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 6294821898 ps |
| CPU time | 880.24 seconds |
| Started | Jul 27 07:57:10 PM PDT 24 |
| Finished | Jul 27 08:11:51 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-226349ab-aecb-4dab-9802-962c148a8f7d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588550434 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2588550434 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.321863581 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3146204856 ps |
| CPU time | 303.99 seconds |
| Started | Jul 27 07:55:44 PM PDT 24 |
| Finished | Jul 27 08:00:49 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-6144d8ea-f0b7-406a-ad37-ac2d7ed2b33a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321863581 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.321863581 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1941542900 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4731705910 ps |
| CPU time | 452.51 seconds |
| Started | Jul 27 07:55:38 PM PDT 24 |
| Finished | Jul 27 08:03:10 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-48c897e6-0b89-43eb-91f2-638b8faafaf4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19 41542900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1941542900 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3672710819 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 5972897450 ps |
| CPU time | 1442.91 seconds |
| Started | Jul 27 08:10:33 PM PDT 24 |
| Finished | Jul 27 08:34:36 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-099b1a59-2760-4ecf-9f94-a9203f113f6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672710819 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.3672710819 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.587879165 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 4626778154 ps |
| CPU time | 801.73 seconds |
| Started | Jul 27 07:57:54 PM PDT 24 |
| Finished | Jul 27 08:11:16 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-582f93e3-11ee-466d-b2e1-f903fb525652 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587879165 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.587879165 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1299769286 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 4638617659 ps |
| CPU time | 733.65 seconds |
| Started | Jul 27 07:57:48 PM PDT 24 |
| Finished | Jul 27 08:10:02 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-12217d34-7fde-4313-a493-f048173fc4f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1299769286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1299769286 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.840998899 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2839937238 ps |
| CPU time | 350.15 seconds |
| Started | Jul 27 08:08:43 PM PDT 24 |
| Finished | Jul 27 08:14:34 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-c7500378-fc98-4e0b-8946-2e09059c5ae3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8409988 99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.840998899 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.888059290 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 19493801996 ps |
| CPU time | 2265.34 seconds |
| Started | Jul 27 07:57:16 PM PDT 24 |
| Finished | Jul 27 08:35:02 PM PDT 24 |
| Peak memory | 612996 kb |
| Host | smart-ef72e9f2-0d58-4067-81b0-fd5a259fd42f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888059290 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.888059290 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3031175844 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 21646932335 ps |
| CPU time | 1757.32 seconds |
| Started | Jul 27 08:06:53 PM PDT 24 |
| Finished | Jul 27 08:36:11 PM PDT 24 |
| Peak memory | 618248 kb |
| Host | smart-8e128be1-333c-458b-b3f3-e8ed960803d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3031175844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3031175844 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4000149264 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2803294468 ps |
| CPU time | 260.12 seconds |
| Started | Jul 27 08:10:45 PM PDT 24 |
| Finished | Jul 27 08:15:06 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-4e9aa446-76a1-4cbc-9864-b114c47e8687 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4000149264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.4000149264 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2798664309 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3929878638 ps |
| CPU time | 462.86 seconds |
| Started | Jul 27 07:55:09 PM PDT 24 |
| Finished | Jul 27 08:02:52 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-01fad3a9-c82d-47d7-8382-1ed63cd2d0cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798664309 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2798664309 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.515383254 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2433115790 ps |
| CPU time | 194.49 seconds |
| Started | Jul 27 08:08:25 PM PDT 24 |
| Finished | Jul 27 08:11:39 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-44adf9a7-18b6-40ba-9d4a-43e6de3dc8ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515383254 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_gpio_smoketest.515383254 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.3652123399 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 2564884024 ps |
| CPU time | 265.17 seconds |
| Started | Jul 27 08:03:32 PM PDT 24 |
| Finished | Jul 27 08:07:57 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-cd5d3d54-efcf-4f68-85f4-400ef9045b45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652123399 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3652123399 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2259224566 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3121939110 ps |
| CPU time | 304.17 seconds |
| Started | Jul 27 08:02:47 PM PDT 24 |
| Finished | Jul 27 08:07:52 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-969fdf44-ac05-4f2c-b569-e00d468d9191 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259224566 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.2259224566 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.127568994 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2948498602 ps |
| CPU time | 247.9 seconds |
| Started | Jul 27 08:03:26 PM PDT 24 |
| Finished | Jul 27 08:07:34 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-6a6e1899-7d0b-4352-ac74-610e420245a1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127568994 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.127568994 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1671766967 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3806220999 ps |
| CPU time | 294.16 seconds |
| Started | Jul 27 08:07:50 PM PDT 24 |
| Finished | Jul 27 08:12:44 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-37ebe059-dd46-41b2-8f31-5c6da957e860 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671766967 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1671766967 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.3582931731 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 7286187924 ps |
| CPU time | 1427.32 seconds |
| Started | Jul 27 08:03:24 PM PDT 24 |
| Finished | Jul 27 08:27:11 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-04e337d7-beea-45c5-9705-857bdaaa5654 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582931731 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.3582931731 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.125620956 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 3450568846 ps |
| CPU time | 372.08 seconds |
| Started | Jul 27 08:03:17 PM PDT 24 |
| Finished | Jul 27 08:09:29 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-44154200-9102-4c0a-a6b9-e4cd1fadd1c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125620956 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.125620956 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.1758500863 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3358041918 ps |
| CPU time | 347.46 seconds |
| Started | Jul 27 08:08:41 PM PDT 24 |
| Finished | Jul 27 08:14:29 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-a8fe3755-c30f-425d-b4c4-0510f117b6ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758500863 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1758500863 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3099215871 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3703489728 ps |
| CPU time | 433.57 seconds |
| Started | Jul 27 07:55:31 PM PDT 24 |
| Finished | Jul 27 08:02:46 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-da638014-ce18-4710-b669-57755a9c1f3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099215871 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3099215871 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3544532835 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 5536223696 ps |
| CPU time | 749.04 seconds |
| Started | Jul 27 07:54:57 PM PDT 24 |
| Finished | Jul 27 08:07:27 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-26be29dd-409f-4617-9dc0-8848b4cade69 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544532835 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3544532835 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3561786709 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5163199852 ps |
| CPU time | 941.01 seconds |
| Started | Jul 27 07:57:29 PM PDT 24 |
| Finished | Jul 27 08:13:11 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-8c0fb984-0e6d-483b-a436-88c7ea49ce62 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561786709 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3561786709 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1686327624 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4508625448 ps |
| CPU time | 560.87 seconds |
| Started | Jul 27 07:56:42 PM PDT 24 |
| Finished | Jul 27 08:06:03 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-6c899a22-0b46-4d1d-bbee-ae4ba0b75c4c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686327624 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1686327624 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1439876060 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 63184749492 ps |
| CPU time | 11296 seconds |
| Started | Jul 27 07:57:35 PM PDT 24 |
| Finished | Jul 27 11:05:52 PM PDT 24 |
| Peak memory | 625264 kb |
| Host | smart-48a2887d-fd7c-43ff-8b20-9209b2fa901c |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1439876060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1439876060 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3835496036 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 8079928039 ps |
| CPU time | 1645.95 seconds |
| Started | Jul 27 08:03:37 PM PDT 24 |
| Finished | Jul 27 08:31:03 PM PDT 24 |
| Peak memory | 617404 kb |
| Host | smart-5862eaa9-f32b-4db7-9f76-db2b027d3bb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3835496036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3835496036 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2267626610 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 10100094975 ps |
| CPU time | 1968.09 seconds |
| Started | Jul 27 08:06:44 PM PDT 24 |
| Finished | Jul 27 08:39:32 PM PDT 24 |
| Peak memory | 618424 kb |
| Host | smart-872acfa4-efd3-49ec-bd47-643a79d16fc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2267626610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2267626610 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2836103594 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 10429864288 ps |
| CPU time | 2532.04 seconds |
| Started | Jul 27 08:04:45 PM PDT 24 |
| Finished | Jul 27 08:46:58 PM PDT 24 |
| Peak memory | 617480 kb |
| Host | smart-c89f7cba-44f0-4061-9c2f-c0227464e9ca |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2836103594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2836103594 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2407516397 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 7671295600 ps |
| CPU time | 1714.59 seconds |
| Started | Jul 27 08:08:21 PM PDT 24 |
| Finished | Jul 27 08:36:56 PM PDT 24 |
| Peak memory | 611628 kb |
| Host | smart-cda211fd-707e-44cd-8f1d-6a9f06f272da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240751 6397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2407516397 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1602384289 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 6783240840 ps |
| CPU time | 1592.24 seconds |
| Started | Jul 27 08:05:16 PM PDT 24 |
| Finished | Jul 27 08:31:49 PM PDT 24 |
| Peak memory | 611940 kb |
| Host | smart-eb381d1c-3f43-4c64-abc9-33f30410c379 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16023 84289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1602384289 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2950249126 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 14075042152 ps |
| CPU time | 3388.31 seconds |
| Started | Jul 27 08:07:51 PM PDT 24 |
| Finished | Jul 27 09:04:20 PM PDT 24 |
| Peak memory | 611488 kb |
| Host | smart-a911212f-de6b-444d-bbec-2a7c66208bc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29502 49126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2950249126 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.3301376580 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 2307490568 ps |
| CPU time | 221.31 seconds |
| Started | Jul 27 08:04:05 PM PDT 24 |
| Finished | Jul 27 08:07:47 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-fa222589-65ef-4fcb-9006-ef4f08f995bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301376580 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3301376580 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.1375905272 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 3554213128 ps |
| CPU time | 241.77 seconds |
| Started | Jul 27 07:56:36 PM PDT 24 |
| Finished | Jul 27 08:00:38 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-4c69b241-d15e-4272-a77b-7c2884daccdb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375905272 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1375905272 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3445246335 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3133911474 ps |
| CPU time | 237.2 seconds |
| Started | Jul 27 08:08:00 PM PDT 24 |
| Finished | Jul 27 08:11:57 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-39caac60-9885-41ef-a676-76cb705f3ed9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445246335 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3445246335 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2024929179 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3260598738 ps |
| CPU time | 409.81 seconds |
| Started | Jul 27 08:06:57 PM PDT 24 |
| Finished | Jul 27 08:13:47 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-3c67388c-bbed-47a6-bc80-c8679efafad6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024929179 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2024929179 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2037488656 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3633787484 ps |
| CPU time | 294.84 seconds |
| Started | Jul 27 08:07:56 PM PDT 24 |
| Finished | Jul 27 08:12:51 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-90ccf597-06c6-4387-a55f-79ab01aa992b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037488656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2037488656 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1617174758 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 2948280137 ps |
| CPU time | 419.83 seconds |
| Started | Jul 27 08:08:30 PM PDT 24 |
| Finished | Jul 27 08:15:30 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-af4f1534-f29f-4b55-ba05-e8b6a04c8c36 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16171747 58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1617174758 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.2142938336 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 3161200838 ps |
| CPU time | 212.46 seconds |
| Started | Jul 27 08:08:00 PM PDT 24 |
| Finished | Jul 27 08:11:32 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-fa687024-7e70-4492-adf6-3bcc0e5c35e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142938336 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.2142938336 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2457053981 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 2596295248 ps |
| CPU time | 329.16 seconds |
| Started | Jul 27 07:57:10 PM PDT 24 |
| Finished | Jul 27 08:02:39 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-7c723e73-fbd9-4108-b575-6f791c8d95b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457053981 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2457053981 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3473054082 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5966471060 ps |
| CPU time | 811.91 seconds |
| Started | Jul 27 08:06:38 PM PDT 24 |
| Finished | Jul 27 08:20:10 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-6c11aeac-6907-452b-b281-c9e0178cc6c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3473054082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3473054082 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1470122737 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4069027640 ps |
| CPU time | 277.37 seconds |
| Started | Jul 27 07:56:52 PM PDT 24 |
| Finished | Jul 27 08:01:29 PM PDT 24 |
| Peak memory | 622196 kb |
| Host | smart-63973f57-307c-47de-b284-3fdbe61241ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14701227 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1470122737 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1201617608 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 11808662892 ps |
| CPU time | 1325.52 seconds |
| Started | Jul 27 07:57:51 PM PDT 24 |
| Finished | Jul 27 08:19:57 PM PDT 24 |
| Peak memory | 621548 kb |
| Host | smart-715565a9-3653-492c-867a-4cb4be6a37c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201617608 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1201617608 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3115648032 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2248993732 ps |
| CPU time | 116.68 seconds |
| Started | Jul 27 07:57:47 PM PDT 24 |
| Finished | Jul 27 07:59:44 PM PDT 24 |
| Peak memory | 618548 kb |
| Host | smart-c5a5941c-edfc-4907-9d43-33557d0040c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3115648032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3115648032 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3834387344 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 2361544204 ps |
| CPU time | 112.42 seconds |
| Started | Jul 27 07:59:34 PM PDT 24 |
| Finished | Jul 27 08:01:27 PM PDT 24 |
| Peak memory | 618524 kb |
| Host | smart-62fa7588-f166-4c76-940f-2f9b96befa7e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834387344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3834387344 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.685692780 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 47345916584 ps |
| CPU time | 5483.3 seconds |
| Started | Jul 27 07:54:25 PM PDT 24 |
| Finished | Jul 27 09:25:49 PM PDT 24 |
| Peak memory | 621032 kb |
| Host | smart-deb04615-f780-44b8-ae1c-0734ccef0a97 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685692780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.685692780 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3584958330 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 11792526410 ps |
| CPU time | 1116.94 seconds |
| Started | Jul 27 07:54:50 PM PDT 24 |
| Finished | Jul 27 08:13:27 PM PDT 24 |
| Peak memory | 620904 kb |
| Host | smart-5bb02ccf-34bc-43e8-8588-61aec95ba23c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584958330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3584958330 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3128871410 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 48897196472 ps |
| CPU time | 5161.38 seconds |
| Started | Jul 27 07:55:56 PM PDT 24 |
| Finished | Jul 27 09:21:58 PM PDT 24 |
| Peak memory | 621076 kb |
| Host | smart-f7cce0b7-3a46-4517-8f54-5dbdc03f0440 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128871410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.3128871410 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1896636844 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 17944978140 ps |
| CPU time | 3733.33 seconds |
| Started | Jul 27 08:00:37 PM PDT 24 |
| Finished | Jul 27 09:02:51 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-54e7575b-665b-4d2d-a89b-7c91fddf68f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1896636844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.1896636844 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.605010145 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 19398017679 ps |
| CPU time | 4195.53 seconds |
| Started | Jul 27 08:00:10 PM PDT 24 |
| Finished | Jul 27 09:10:06 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-df39fe6f-d9f6-48d4-a695-c5bb9caca7a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=605010145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.605010145 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1702818550 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 24611276183 ps |
| CPU time | 3865.85 seconds |
| Started | Jul 27 08:07:45 PM PDT 24 |
| Finished | Jul 27 09:12:11 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-1c00f5c4-773f-4fe8-918f-4299b5a70297 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702818550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1702818550 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3381377109 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3869985352 ps |
| CPU time | 502.78 seconds |
| Started | Jul 27 07:59:25 PM PDT 24 |
| Finished | Jul 27 08:07:48 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-0bbae8c7-75ad-4707-a4e4-3f502d52da0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381377109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3381377109 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.1849052216 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 5966828140 ps |
| CPU time | 969.09 seconds |
| Started | Jul 27 08:00:33 PM PDT 24 |
| Finished | Jul 27 08:16:43 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-ff7d9ce7-4a37-4e83-8c71-0832e90b2de7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1849052216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1849052216 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1699654054 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 8854773280 ps |
| CPU time | 2154.67 seconds |
| Started | Jul 27 08:07:44 PM PDT 24 |
| Finished | Jul 27 08:43:39 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-83b1cd1f-8feb-405e-9f25-f1e898a95dc4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699654054 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1699654054 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.38230675 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 2541216611 ps |
| CPU time | 221.46 seconds |
| Started | Jul 27 07:57:42 PM PDT 24 |
| Finished | Jul 27 08:01:24 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-b88b1a65-9e9d-4bc6-89ac-429376929656 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38230675 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.38230675 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2344826749 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 7364291560 ps |
| CPU time | 1168.03 seconds |
| Started | Jul 27 07:58:09 PM PDT 24 |
| Finished | Jul 27 08:17:37 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-3ae70abd-861d-42ae-9bf7-596226aaef84 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2344826749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2344826749 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1543674556 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 7569310668 ps |
| CPU time | 1205.6 seconds |
| Started | Jul 27 07:57:00 PM PDT 24 |
| Finished | Jul 27 08:17:06 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-4e9abf24-de2d-4d47-a335-4c23e8638b70 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1543674556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1543674556 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4089467844 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 7013015536 ps |
| CPU time | 1423.85 seconds |
| Started | Jul 27 07:56:15 PM PDT 24 |
| Finished | Jul 27 08:19:59 PM PDT 24 |
| Peak memory | 611300 kb |
| Host | smart-090e3677-63f6-42e5-b5e0-41e754a84a23 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4089467844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.4089467844 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3004626324 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 4736046156 ps |
| CPU time | 836.5 seconds |
| Started | Jul 27 07:58:10 PM PDT 24 |
| Finished | Jul 27 08:12:07 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-9c62822a-7646-48dd-b527-913f5bd8d6f9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3004626324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3004626324 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2218215894 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 3172794824 ps |
| CPU time | 414.62 seconds |
| Started | Jul 27 08:08:49 PM PDT 24 |
| Finished | Jul 27 08:15:44 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-5ad7e065-224e-4565-a464-83e7426515a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218215894 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2218215894 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.290631504 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2884325920 ps |
| CPU time | 224.19 seconds |
| Started | Jul 27 07:52:42 PM PDT 24 |
| Finished | Jul 27 07:56:26 PM PDT 24 |
| Peak memory | 612024 kb |
| Host | smart-514ce28c-3624-4e36-a220-2cf7a028eb8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290631504 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.290631504 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.2583976612 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2832035960 ps |
| CPU time | 274.12 seconds |
| Started | Jul 27 08:04:28 PM PDT 24 |
| Finished | Jul 27 08:09:02 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-e2e4d789-3db7-414f-9f90-ce72e3b0bc60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583976612 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.2583976612 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3280387330 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 4620072152 ps |
| CPU time | 803 seconds |
| Started | Jul 27 08:08:23 PM PDT 24 |
| Finished | Jul 27 08:21:47 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-a60baf8f-ee2c-4454-a7b0-0afc0606b267 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280387330 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3280387330 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.77543897 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 9728059658 ps |
| CPU time | 616.17 seconds |
| Started | Jul 27 08:07:05 PM PDT 24 |
| Finished | Jul 27 08:17:22 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-87722e11-c53f-4805-a540-0ea56ba8bcd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77543897 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.77543897 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2807687383 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 10173537139 ps |
| CPU time | 1443.82 seconds |
| Started | Jul 27 07:58:19 PM PDT 24 |
| Finished | Jul 27 08:22:23 PM PDT 24 |
| Peak memory | 611772 kb |
| Host | smart-3c4af7bd-9e89-458f-8769-eb2dcf48a048 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807 687383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2807687383 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.921669294 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 27898847840 ps |
| CPU time | 2637.29 seconds |
| Started | Jul 27 08:05:02 PM PDT 24 |
| Finished | Jul 27 08:49:00 PM PDT 24 |
| Peak memory | 611488 kb |
| Host | smart-9194eee6-124b-4846-a675-fb9751263de7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921 669294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.921669294 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3715630856 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 15199880826 ps |
| CPU time | 1293.83 seconds |
| Started | Jul 27 07:56:36 PM PDT 24 |
| Finished | Jul 27 08:18:10 PM PDT 24 |
| Peak memory | 611824 kb |
| Host | smart-cae0456a-49a1-4f9f-b004-fb134bab4f68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3715630856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3715630856 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.328532274 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 20634416660 ps |
| CPU time | 2009.81 seconds |
| Started | Jul 27 08:06:24 PM PDT 24 |
| Finished | Jul 27 08:39:54 PM PDT 24 |
| Peak memory | 611656 kb |
| Host | smart-7e44e7e5-505f-4b91-9004-73655afd3141 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 328532274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.328532274 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1701357970 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 10010235136 ps |
| CPU time | 580.94 seconds |
| Started | Jul 27 07:56:31 PM PDT 24 |
| Finished | Jul 27 08:06:12 PM PDT 24 |
| Peak memory | 611476 kb |
| Host | smart-5210c8c7-5dfc-4588-9cf3-fdaf52909dee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701357970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1701357970 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1831638859 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 7431532388 ps |
| CPU time | 367.45 seconds |
| Started | Jul 27 08:00:18 PM PDT 24 |
| Finished | Jul 27 08:06:25 PM PDT 24 |
| Peak memory | 618308 kb |
| Host | smart-51fb5084-8198-4338-a15a-587cbb738705 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1831638859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1831638859 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.966781897 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 9563843974 ps |
| CPU time | 416.34 seconds |
| Started | Jul 27 07:58:42 PM PDT 24 |
| Finished | Jul 27 08:05:39 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-68551de6-48ac-4462-9a80-43cadefacd26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966781897 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.966781897 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1204956177 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4445874785 ps |
| CPU time | 432.4 seconds |
| Started | Jul 27 07:59:21 PM PDT 24 |
| Finished | Jul 27 08:06:33 PM PDT 24 |
| Peak memory | 617820 kb |
| Host | smart-19ac32bd-a08c-4ba4-88d7-50f1ea858516 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1204956177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1204956177 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3158506547 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 10332948835 ps |
| CPU time | 1565.04 seconds |
| Started | Jul 27 07:59:22 PM PDT 24 |
| Finished | Jul 27 08:25:28 PM PDT 24 |
| Peak memory | 612092 kb |
| Host | smart-d0d02e86-0b41-455c-bcc7-aabd194389bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158506547 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3158506547 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2034766986 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 7782085986 ps |
| CPU time | 313.02 seconds |
| Started | Jul 27 08:07:33 PM PDT 24 |
| Finished | Jul 27 08:12:46 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-c29a9ca8-855c-4167-a125-181ddc7bcce2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034766986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2034766986 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.7621039 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 8098454044 ps |
| CPU time | 805.62 seconds |
| Started | Jul 27 08:01:49 PM PDT 24 |
| Finished | Jul 27 08:15:15 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-cb70d6ab-fa42-429e-afda-61d1d7aa339c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7621039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.7621039 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.258227265 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 20920033704 ps |
| CPU time | 2143.11 seconds |
| Started | Jul 27 08:02:46 PM PDT 24 |
| Finished | Jul 27 08:38:30 PM PDT 24 |
| Peak memory | 612108 kb |
| Host | smart-f5cb3bea-4658-423d-9c25-005893ae0a31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=258227265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.258227265 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2334207293 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 23966555868 ps |
| CPU time | 1568.77 seconds |
| Started | Jul 27 08:07:07 PM PDT 24 |
| Finished | Jul 27 08:33:17 PM PDT 24 |
| Peak memory | 611640 kb |
| Host | smart-ac88ea3e-347f-4a7a-b6e9-099315a4ffc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2334207293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2334207293 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3508359345 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 33915361296 ps |
| CPU time | 3149.08 seconds |
| Started | Jul 27 08:02:43 PM PDT 24 |
| Finished | Jul 27 08:55:13 PM PDT 24 |
| Peak memory | 612576 kb |
| Host | smart-70a75498-e185-4c57-b7c6-6df319a469d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508359345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3508359345 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1050386766 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6421855196 ps |
| CPU time | 520.63 seconds |
| Started | Jul 27 08:06:52 PM PDT 24 |
| Finished | Jul 27 08:15:33 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-5e428e44-e3bb-49f0-a0de-aef41159b8c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1050386766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1050386766 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3242567497 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3235327580 ps |
| CPU time | 263.46 seconds |
| Started | Jul 27 07:58:18 PM PDT 24 |
| Finished | Jul 27 08:02:42 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-feb35cae-3598-4fd7-bb47-64299a946578 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242567497 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3242567497 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1904819999 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 6871487784 ps |
| CPU time | 595.19 seconds |
| Started | Jul 27 07:59:05 PM PDT 24 |
| Finished | Jul 27 08:09:01 PM PDT 24 |
| Peak memory | 617388 kb |
| Host | smart-0d89f7c3-b9d8-413f-adca-54f81000b004 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1904819999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1904819999 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1708449454 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5213421240 ps |
| CPU time | 457.16 seconds |
| Started | Jul 27 08:05:19 PM PDT 24 |
| Finished | Jul 27 08:12:57 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-f7763207-1fa5-481f-80bd-b92311733b42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17084494 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1708449454 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4089521361 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 5915782774 ps |
| CPU time | 508.81 seconds |
| Started | Jul 27 08:06:16 PM PDT 24 |
| Finished | Jul 27 08:14:45 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-fe831f54-beaa-4a9b-b2b7-8a536de8ccb7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4089521361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.4089521361 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.758970247 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 6300524922 ps |
| CPU time | 381.96 seconds |
| Started | Jul 27 08:09:05 PM PDT 24 |
| Finished | Jul 27 08:15:27 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-bfa29b5e-634d-4ae9-8823-80a7e1a7155e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758970247 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.758970247 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.720971132 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 6787573439 ps |
| CPU time | 1079.53 seconds |
| Started | Jul 27 07:58:29 PM PDT 24 |
| Finished | Jul 27 08:16:29 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-4f32bddf-1c8c-4b48-a283-ae8b4eef7fbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720971132 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.720971132 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1937045006 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 5795540118 ps |
| CPU time | 482.71 seconds |
| Started | Jul 27 08:00:06 PM PDT 24 |
| Finished | Jul 27 08:08:09 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-ba116402-3efb-4d5a-8569-1eeac9f2b2d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937045006 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1937045006 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.560223844 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6251451296 ps |
| CPU time | 422.37 seconds |
| Started | Jul 27 08:08:33 PM PDT 24 |
| Finished | Jul 27 08:15:36 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-f6cf0ada-d1db-4279-aa9a-27a7ef14b3bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560223844 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.560223844 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2255545241 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 5145868852 ps |
| CPU time | 466.06 seconds |
| Started | Jul 27 07:58:47 PM PDT 24 |
| Finished | Jul 27 08:06:33 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-a1c229f6-e44b-4ba2-978a-01b875e5aa9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225 5545241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2255545241 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1753750032 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 8994044405 ps |
| CPU time | 431.53 seconds |
| Started | Jul 27 08:04:14 PM PDT 24 |
| Finished | Jul 27 08:11:26 PM PDT 24 |
| Peak memory | 625400 kb |
| Host | smart-14c58dc5-75c4-4a9e-8cdc-7394cfa048ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753750032 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1753750032 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1948125453 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 14272749768 ps |
| CPU time | 2067.14 seconds |
| Started | Jul 27 08:00:09 PM PDT 24 |
| Finished | Jul 27 08:34:37 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-0da59a00-f6c6-472b-b3b6-71a188c624c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1948125453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.1948125453 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3075790116 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6577471208 ps |
| CPU time | 727.68 seconds |
| Started | Jul 27 07:57:14 PM PDT 24 |
| Finished | Jul 27 08:09:22 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-81c22543-4b4d-4a46-800d-7e166204e996 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075790116 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3075790116 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.822732704 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5286502936 ps |
| CPU time | 494.62 seconds |
| Started | Jul 27 07:55:25 PM PDT 24 |
| Finished | Jul 27 08:03:40 PM PDT 24 |
| Peak memory | 641876 kb |
| Host | smart-18a967e3-f3f5-43ba-8157-0a167ac3b089 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 822732704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.822732704 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.4211054278 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2803188262 ps |
| CPU time | 290.78 seconds |
| Started | Jul 27 08:09:02 PM PDT 24 |
| Finished | Jul 27 08:13:53 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-523b81c8-c919-4a66-a1f1-ec10eb3c0d9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211054278 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.4211054278 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.14909745 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 4178617780 ps |
| CPU time | 403.38 seconds |
| Started | Jul 27 07:57:11 PM PDT 24 |
| Finished | Jul 27 08:03:55 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-9bbbc9aa-6330-4064-a565-1da2f4f46a35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14909745 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_sw_req.14909745 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3539132354 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3415143216 ps |
| CPU time | 222.75 seconds |
| Started | Jul 27 07:56:09 PM PDT 24 |
| Finished | Jul 27 07:59:52 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-89abad00-59a5-46d3-96bb-3b5f7f68fc32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539132354 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3539132354 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2261265879 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2276919544 ps |
| CPU time | 271.97 seconds |
| Started | Jul 27 08:07:04 PM PDT 24 |
| Finished | Jul 27 08:11:37 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-98d8abab-8754-44d7-90a3-4cee2c339938 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2261265879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2261265879 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.916785011 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2603061971 ps |
| CPU time | 195.53 seconds |
| Started | Jul 27 08:06:35 PM PDT 24 |
| Finished | Jul 27 08:09:51 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-5270854f-02d1-415a-bf70-679002ec30b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916785011 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.916785011 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1055558964 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4604777888 ps |
| CPU time | 717.99 seconds |
| Started | Jul 27 07:59:58 PM PDT 24 |
| Finished | Jul 27 08:11:57 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-df0b2501-f2ab-4f8c-becf-1b0e59eb372a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10555 58964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1055558964 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.600680239 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 5257599306 ps |
| CPU time | 1162.73 seconds |
| Started | Jul 27 08:00:17 PM PDT 24 |
| Finished | Jul 27 08:19:40 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-b522ec87-676c-4b1f-a598-f23aae048f18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=600680239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.600680239 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2637534977 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5514041786 ps |
| CPU time | 556.86 seconds |
| Started | Jul 27 08:06:34 PM PDT 24 |
| Finished | Jul 27 08:15:51 PM PDT 24 |
| Peak memory | 624832 kb |
| Host | smart-ce74e355-116e-494b-b381-1852ce0f4d2e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637534977 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2637534977 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.331130575 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 6873942696 ps |
| CPU time | 604.97 seconds |
| Started | Jul 27 08:05:56 PM PDT 24 |
| Finished | Jul 27 08:16:01 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-62aecc5e-0202-4819-82db-caf5ad2f7199 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331130575 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.331130575 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2029402060 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5587825610 ps |
| CPU time | 573.51 seconds |
| Started | Jul 27 08:07:11 PM PDT 24 |
| Finished | Jul 27 08:16:45 PM PDT 24 |
| Peak memory | 622120 kb |
| Host | smart-34a62975-6b3b-49cf-b8db-6ef69f5a4806 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202940 2060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2029402060 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1222256419 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2113196000 ps |
| CPU time | 224.35 seconds |
| Started | Jul 27 08:09:24 PM PDT 24 |
| Finished | Jul 27 08:13:09 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-559c2848-a0a0-46b3-be4d-26baa638f27a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222256419 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.1222256419 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.3054658447 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3413253030 ps |
| CPU time | 352.48 seconds |
| Started | Jul 27 08:00:02 PM PDT 24 |
| Finished | Jul 27 08:05:58 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-b926650a-6716-4e93-b92d-44ae45dda56b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054658447 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3054658447 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2451877158 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3168300040 ps |
| CPU time | 329.7 seconds |
| Started | Jul 27 08:09:57 PM PDT 24 |
| Finished | Jul 27 08:15:28 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-7816fa59-9b8b-4c27-b53a-79309a79481e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451877158 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2451877158 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1730633328 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3522006642 ps |
| CPU time | 319.93 seconds |
| Started | Jul 27 08:04:01 PM PDT 24 |
| Finished | Jul 27 08:09:22 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-a4cdc9b8-cdfd-4722-93c6-9cdf9c5de424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730633 328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1730633328 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1896710936 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3663633180 ps |
| CPU time | 209.58 seconds |
| Started | Jul 27 07:53:08 PM PDT 24 |
| Finished | Jul 27 07:56:38 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-fb7618ba-615e-4b3f-8111-e9fc7d605d9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896710936 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1896710936 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.247518862 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 9752763800 ps |
| CPU time | 1591.59 seconds |
| Started | Jul 27 07:57:55 PM PDT 24 |
| Finished | Jul 27 08:24:27 PM PDT 24 |
| Peak memory | 611444 kb |
| Host | smart-5c450386-449b-4ee1-826a-3805f52afe1d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247518862 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.247518862 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.490390004 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 9264990896 ps |
| CPU time | 746.27 seconds |
| Started | Jul 27 08:05:44 PM PDT 24 |
| Finished | Jul 27 08:18:10 PM PDT 24 |
| Peak memory | 611116 kb |
| Host | smart-7daa1600-8227-4c7e-bd69-c4336aef3825 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490390004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.490390004 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3262260800 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6227660004 ps |
| CPU time | 613.42 seconds |
| Started | Jul 27 07:54:35 PM PDT 24 |
| Finished | Jul 27 08:04:49 PM PDT 24 |
| Peak memory | 625452 kb |
| Host | smart-b2fee2f2-3a70-44e0-9fa5-6569ba54bd2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262260800 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3262260800 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1758413643 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4121927248 ps |
| CPU time | 476.19 seconds |
| Started | Jul 27 07:53:05 PM PDT 24 |
| Finished | Jul 27 08:01:02 PM PDT 24 |
| Peak memory | 625384 kb |
| Host | smart-02da0062-26aa-473d-abb8-af1d92179d84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758413643 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1758413643 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1287084221 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3935730551 ps |
| CPU time | 275.31 seconds |
| Started | Jul 27 07:56:42 PM PDT 24 |
| Finished | Jul 27 08:01:18 PM PDT 24 |
| Peak memory | 619680 kb |
| Host | smart-adbc95b1-ab0a-4021-ba61-826a9db5650f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287084221 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.1287084221 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1008166593 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3703295294 ps |
| CPU time | 400.49 seconds |
| Started | Jul 27 07:56:22 PM PDT 24 |
| Finished | Jul 27 08:03:03 PM PDT 24 |
| Peak memory | 620140 kb |
| Host | smart-f940766b-2639-4868-bf92-1bf5469c3777 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008166593 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1008166593 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3311784976 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3228817036 ps |
| CPU time | 259.7 seconds |
| Started | Jul 27 07:54:41 PM PDT 24 |
| Finished | Jul 27 07:59:01 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-548ae599-f8c7-4b09-917f-d43f26369264 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311784976 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3311784976 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1701598045 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5880928789 ps |
| CPU time | 512.51 seconds |
| Started | Jul 27 08:05:32 PM PDT 24 |
| Finished | Jul 27 08:14:04 PM PDT 24 |
| Peak memory | 611344 kb |
| Host | smart-dc373ea2-504d-49b2-b993-bf9532c626ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701598045 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1701598045 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4065454458 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5262564312 ps |
| CPU time | 428.98 seconds |
| Started | Jul 27 08:05:23 PM PDT 24 |
| Finished | Jul 27 08:12:33 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-5c9e0a32-3053-4f22-8c77-0af70e7e35d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065454458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.4065454458 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2819399020 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4362524640 ps |
| CPU time | 655.17 seconds |
| Started | Jul 27 08:04:17 PM PDT 24 |
| Finished | Jul 27 08:15:13 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-a28d117e-bee4-43f3-8d90-301ee86d54fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819399020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2819399020 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1290839978 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 5154860676 ps |
| CPU time | 493.95 seconds |
| Started | Jul 27 08:06:48 PM PDT 24 |
| Finished | Jul 27 08:15:03 PM PDT 24 |
| Peak memory | 611476 kb |
| Host | smart-1777c4e5-aae2-48b8-8a13-5489ecf7094a |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290839978 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1290839978 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1606768226 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 3017656460 ps |
| CPU time | 296.8 seconds |
| Started | Jul 27 08:08:36 PM PDT 24 |
| Finished | Jul 27 08:13:32 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-b5fbc1cd-195f-4f17-ab63-b834ece65e28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606768226 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1606768226 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2932684541 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 20016318103 ps |
| CPU time | 4582.41 seconds |
| Started | Jul 27 08:00:13 PM PDT 24 |
| Finished | Jul 27 09:16:36 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-955f6c67-a226-49ad-8ca7-e4b0672e84c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932684541 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2932684541 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4109100725 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4526157110 ps |
| CPU time | 765.16 seconds |
| Started | Jul 27 08:02:02 PM PDT 24 |
| Finished | Jul 27 08:14:49 PM PDT 24 |
| Peak memory | 614404 kb |
| Host | smart-d5f61fe3-58ae-4e59-ba12-92eec4a81125 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109100725 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.4109100725 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3879637693 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2716487001 ps |
| CPU time | 278.37 seconds |
| Started | Jul 27 08:02:21 PM PDT 24 |
| Finished | Jul 27 08:07:01 PM PDT 24 |
| Peak memory | 613852 kb |
| Host | smart-29ef683b-fbb5-4de7-a0a3-cb17fc3922d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879637693 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3879637693 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.178925703 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 3335109810 ps |
| CPU time | 391.14 seconds |
| Started | Jul 27 07:59:18 PM PDT 24 |
| Finished | Jul 27 08:05:49 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-47f96b53-1691-48c9-b12b-e2aeb9994932 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178925703 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.178925703 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1993127843 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 23896588680 ps |
| CPU time | 1810.67 seconds |
| Started | Jul 27 07:59:45 PM PDT 24 |
| Finished | Jul 27 08:29:56 PM PDT 24 |
| Peak memory | 614844 kb |
| Host | smart-1c5576db-16f3-489a-90e4-9b5df7e4ccfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19931278 43 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.1993127843 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3305702841 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6375876932 ps |
| CPU time | 614.19 seconds |
| Started | Jul 27 08:00:27 PM PDT 24 |
| Finished | Jul 27 08:10:42 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-0a56d7b5-2a13-4935-836d-addc60b64861 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305702841 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3305702841 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.258380578 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3833244014 ps |
| CPU time | 602.11 seconds |
| Started | Jul 27 07:53:33 PM PDT 24 |
| Finished | Jul 27 08:03:35 PM PDT 24 |
| Peak memory | 619464 kb |
| Host | smart-30747b99-af84-4d76-bb13-33a1f7010d15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=258380578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.258380578 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.862873531 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 3172403336 ps |
| CPU time | 212.84 seconds |
| Started | Jul 27 08:08:48 PM PDT 24 |
| Finished | Jul 27 08:12:21 PM PDT 24 |
| Peak memory | 617652 kb |
| Host | smart-49f498db-16af-40d0-a67f-61e22c7981b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862873531 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.862873531 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.3865035154 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4628834400 ps |
| CPU time | 815.02 seconds |
| Started | Jul 27 08:01:13 PM PDT 24 |
| Finished | Jul 27 08:14:48 PM PDT 24 |
| Peak memory | 625360 kb |
| Host | smart-e6e064e4-4103-402e-830e-9c5d19fa9731 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865035154 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.3865035154 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1506524508 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8830633940 ps |
| CPU time | 2023.64 seconds |
| Started | Jul 27 07:56:17 PM PDT 24 |
| Finished | Jul 27 08:30:01 PM PDT 24 |
| Peak memory | 625308 kb |
| Host | smart-544212ff-0b0d-487b-89a0-3934d85a832b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506524508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1506524508 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.854032067 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 4782181748 ps |
| CPU time | 505.7 seconds |
| Started | Jul 27 07:53:22 PM PDT 24 |
| Finished | Jul 27 08:01:48 PM PDT 24 |
| Peak memory | 625316 kb |
| Host | smart-8d928c8b-ea1a-4f16-9faf-cd7cd854750d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854032067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.854032067 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.62019118 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3898427960 ps |
| CPU time | 649.57 seconds |
| Started | Jul 27 07:56:39 PM PDT 24 |
| Finished | Jul 27 08:07:29 PM PDT 24 |
| Peak memory | 625340 kb |
| Host | smart-4d9d1b37-59fe-4709-ad97-2c2303b59f75 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62019118 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.62019118 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4203846224 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 3989561910 ps |
| CPU time | 456.83 seconds |
| Started | Jul 27 07:54:44 PM PDT 24 |
| Finished | Jul 27 08:02:21 PM PDT 24 |
| Peak memory | 625296 kb |
| Host | smart-3aa76d4a-c2e3-4ed4-8fce-e7a577fbaf8b |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203846224 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.4203846224 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1133423540 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3935483858 ps |
| CPU time | 663.53 seconds |
| Started | Jul 27 07:55:04 PM PDT 24 |
| Finished | Jul 27 08:06:08 PM PDT 24 |
| Peak memory | 625240 kb |
| Host | smart-9cff4632-0506-4443-a6c3-8350f8ff0d44 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133423540 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1133423540 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.985314956 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 2911958623 ps |
| CPU time | 170.63 seconds |
| Started | Jul 27 08:06:15 PM PDT 24 |
| Finished | Jul 27 08:09:06 PM PDT 24 |
| Peak memory | 623592 kb |
| Host | smart-a2228da7-5e24-4728-be66-e932b10209db |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985314956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.985314956 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.3195281788 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 15228978047 ps |
| CPU time | 4043.77 seconds |
| Started | Jul 27 08:13:10 PM PDT 24 |
| Finished | Jul 27 09:20:34 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-cb4be241-10d6-4f88-b77d-ec509db34cae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195281788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3195281788 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1633898805 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 15982404989 ps |
| CPU time | 3672.73 seconds |
| Started | Jul 27 08:12:27 PM PDT 24 |
| Finished | Jul 27 09:13:40 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-fefc4d6b-e4c6-4481-89ad-d4dde63c76b2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633898805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1633898805 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3667544074 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 14983765873 ps |
| CPU time | 3907.96 seconds |
| Started | Jul 27 08:12:07 PM PDT 24 |
| Finished | Jul 27 09:17:16 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-67087358-8b4a-44e6-8611-eb87eec6b5ac |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667544074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3667544074 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.278131303 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 14525880301 ps |
| CPU time | 4274.31 seconds |
| Started | Jul 27 08:15:22 PM PDT 24 |
| Finished | Jul 27 09:26:37 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-35d929d3-ec8e-4abe-b646-b8029bc7788f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278131303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_rma.278131303 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2466707255 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 14278240500 ps |
| CPU time | 4087.21 seconds |
| Started | Jul 27 08:17:10 PM PDT 24 |
| Finished | Jul 27 09:25:18 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-7c7d9fb0-6c4d-42bc-b61c-b3e08b1c6afa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466707255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2466707255 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1129082734 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 14422966036 ps |
| CPU time | 4405.82 seconds |
| Started | Jul 27 08:17:11 PM PDT 24 |
| Finished | Jul 27 09:30:37 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-d113a17c-3502-407e-9f96-b899f08f9ca3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129082734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1129082734 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3657750418 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 14861771224 ps |
| CPU time | 4834.93 seconds |
| Started | Jul 27 08:10:43 PM PDT 24 |
| Finished | Jul 27 09:31:18 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-34a8fe95-fd00-43af-8b02-0b086010eb93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657750418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3657750418 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.1692851132 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 26270071940 ps |
| CPU time | 6855.36 seconds |
| Started | Jul 27 08:12:25 PM PDT 24 |
| Finished | Jul 27 10:06:42 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-57f587cc-7761-4be7-bad2-e79a4fe0a230 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692851132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.1692851132 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.433837898 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 14551123405 ps |
| CPU time | 3970.7 seconds |
| Started | Jul 27 08:13:09 PM PDT 24 |
| Finished | Jul 27 09:19:20 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-6d13b961-3a09-475f-aa91-fa0ca1efb21d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433837898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s hutdown_exception_c.433837898 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1668917134 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 31343808055 ps |
| CPU time | 3734.73 seconds |
| Started | Jul 27 08:13:51 PM PDT 24 |
| Finished | Jul 27 09:16:06 PM PDT 24 |
| Peak memory | 611740 kb |
| Host | smart-60875d27-b0a3-4277-9231-7c504a82f07b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668917134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1668917134 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.3075248618 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 14718412292 ps |
| CPU time | 4175.12 seconds |
| Started | Jul 27 08:12:12 PM PDT 24 |
| Finished | Jul 27 09:21:48 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-e1ed1899-68e6-4670-95e4-d1e39e53127d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3075248618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3075248618 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3221673616 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 16654762210 ps |
| CPU time | 4525.36 seconds |
| Started | Jul 27 08:12:37 PM PDT 24 |
| Finished | Jul 27 09:28:03 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-3f3b85dc-4b43-4969-8fcc-70d3bf73dd72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221673616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3221673616 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.1204701316 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4923464144 ps |
| CPU time | 503.8 seconds |
| Started | Jul 27 08:08:26 PM PDT 24 |
| Finished | Jul 27 08:16:50 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-12be7b37-3a5c-4cdf-8a11-1a16734e4357 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204701316 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1204701316 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.1780045667 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4418049350 ps |
| CPU time | 207.87 seconds |
| Started | Jul 27 08:08:01 PM PDT 24 |
| Finished | Jul 27 08:11:30 PM PDT 24 |
| Peak memory | 620256 kb |
| Host | smart-6fb96fbd-7d99-4a06-be22-58c4e4fad9fa |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1780045667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.1780045667 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.363099011 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3127724410 ps |
| CPU time | 113.28 seconds |
| Started | Jul 27 08:08:07 PM PDT 24 |
| Finished | Jul 27 08:10:00 PM PDT 24 |
| Peak memory | 618628 kb |
| Host | smart-48823649-5ad8-487b-9266-715883163cb5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363099011 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.363099011 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2328806942 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5809145811 ps |
| CPU time | 540.01 seconds |
| Started | Jul 27 08:22:39 PM PDT 24 |
| Finished | Jul 27 08:31:39 PM PDT 24 |
| Peak memory | 621068 kb |
| Host | smart-db772e1a-735f-46a6-9f94-0fab41cde339 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328806942 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2328806942 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.395808023 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4151473476 ps |
| CPU time | 624.23 seconds |
| Started | Jul 27 08:22:17 PM PDT 24 |
| Finished | Jul 27 08:32:42 PM PDT 24 |
| Peak memory | 619500 kb |
| Host | smart-7078fcc4-4c46-44b7-991b-2f4d285ab96e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=395808023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.395808023 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.4178594505 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 6018651052 ps |
| CPU time | 699.68 seconds |
| Started | Jul 27 08:21:32 PM PDT 24 |
| Finished | Jul 27 08:33:12 PM PDT 24 |
| Peak memory | 650560 kb |
| Host | smart-9b3f7cb3-d699-4440-8ba7-c6f62dcf8888 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4178594505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4178594505 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3457260011 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 6461242706 ps |
| CPU time | 648.55 seconds |
| Started | Jul 27 08:22:54 PM PDT 24 |
| Finished | Jul 27 08:33:43 PM PDT 24 |
| Peak memory | 621016 kb |
| Host | smart-b4e278ed-91ed-448d-9bcd-4067c44e26c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457260011 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.3457260011 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1206813947 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 4036034112 ps |
| CPU time | 648.31 seconds |
| Started | Jul 27 08:22:20 PM PDT 24 |
| Finished | Jul 27 08:33:09 PM PDT 24 |
| Peak memory | 623756 kb |
| Host | smart-2b342be1-4856-40f7-8eef-07947b40a7af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1206813947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1206813947 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3286950857 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5642133640 ps |
| CPU time | 643.5 seconds |
| Started | Jul 27 08:22:09 PM PDT 24 |
| Finished | Jul 27 08:32:52 PM PDT 24 |
| Peak memory | 650524 kb |
| Host | smart-e495bc63-8201-4f26-a262-baf6b70af178 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3286950857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3286950857 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.933469524 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 9635354849 ps |
| CPU time | 741.58 seconds |
| Started | Jul 27 08:22:25 PM PDT 24 |
| Finished | Jul 27 08:34:47 PM PDT 24 |
| Peak memory | 621100 kb |
| Host | smart-677f7043-6b62-43b3-ba83-99d17029c6d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933469524 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.933469524 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.963745712 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4659491924 ps |
| CPU time | 554.87 seconds |
| Started | Jul 27 08:21:13 PM PDT 24 |
| Finished | Jul 27 08:30:29 PM PDT 24 |
| Peak memory | 623824 kb |
| Host | smart-41fa8324-fda9-44d6-b2d0-5d8cf0f89c3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=963745712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.963745712 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.698719958 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3798906666 ps |
| CPU time | 432.86 seconds |
| Started | Jul 27 08:23:24 PM PDT 24 |
| Finished | Jul 27 08:30:37 PM PDT 24 |
| Peak memory | 649464 kb |
| Host | smart-fe702e00-92c7-4776-9b72-82cfd0919f46 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698719958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_s w_alert_handler_lpg_sleep_mode_alerts.698719958 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.1058665859 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 4884175412 ps |
| CPU time | 697.62 seconds |
| Started | Jul 27 08:22:15 PM PDT 24 |
| Finished | Jul 27 08:33:53 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-bf43eb08-c015-4d58-b1be-b6636831d003 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1058665859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1058665859 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.4003444840 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6493648251 ps |
| CPU time | 547.34 seconds |
| Started | Jul 27 08:24:14 PM PDT 24 |
| Finished | Jul 27 08:33:22 PM PDT 24 |
| Peak memory | 621076 kb |
| Host | smart-e1a805a2-d5d1-46b2-9470-776e0d258d11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003444840 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.4003444840 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2387972811 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 13546387432 ps |
| CPU time | 2710.61 seconds |
| Started | Jul 27 08:23:33 PM PDT 24 |
| Finished | Jul 27 09:08:44 PM PDT 24 |
| Peak memory | 619736 kb |
| Host | smart-daf709dc-22de-455a-9427-098002ab03ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2387972811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2387972811 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.428917212 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 4008685342 ps |
| CPU time | 387.39 seconds |
| Started | Jul 27 08:23:10 PM PDT 24 |
| Finished | Jul 27 08:29:38 PM PDT 24 |
| Peak memory | 649132 kb |
| Host | smart-834dda10-3ee0-4a66-9015-5506017cef92 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428917212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.428917212 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2747070862 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 11140375073 ps |
| CPU time | 736.6 seconds |
| Started | Jul 27 08:22:38 PM PDT 24 |
| Finished | Jul 27 08:34:55 PM PDT 24 |
| Peak memory | 620976 kb |
| Host | smart-6e2e2053-0e36-4574-a367-f3f715572352 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747070862 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2747070862 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.452815136 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 7981760668 ps |
| CPU time | 1845.99 seconds |
| Started | Jul 27 08:22:37 PM PDT 24 |
| Finished | Jul 27 08:53:23 PM PDT 24 |
| Peak memory | 619504 kb |
| Host | smart-16ef3eef-089a-4fc2-a262-5b02334aea5d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=452815136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.452815136 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.561928123 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 3366925240 ps |
| CPU time | 348.89 seconds |
| Started | Jul 27 08:22:15 PM PDT 24 |
| Finished | Jul 27 08:28:05 PM PDT 24 |
| Peak memory | 619264 kb |
| Host | smart-f8f8a239-4532-4d17-b1c3-cff58a220e53 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561928123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_s w_alert_handler_lpg_sleep_mode_alerts.561928123 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.4068686563 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4863203872 ps |
| CPU time | 606.63 seconds |
| Started | Jul 27 08:22:42 PM PDT 24 |
| Finished | Jul 27 08:32:49 PM PDT 24 |
| Peak memory | 650388 kb |
| Host | smart-dac1fbd4-70b4-4419-8ccd-2790d4ae8b4b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4068686563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.4068686563 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1616162346 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 13136612412 ps |
| CPU time | 2286.59 seconds |
| Started | Jul 27 08:22:01 PM PDT 24 |
| Finished | Jul 27 09:00:08 PM PDT 24 |
| Peak memory | 619644 kb |
| Host | smart-fc5413b0-ed3a-41c8-9065-deb4dcbc8b75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1616162346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1616162346 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1806756025 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3695242638 ps |
| CPU time | 576.42 seconds |
| Started | Jul 27 08:24:20 PM PDT 24 |
| Finished | Jul 27 08:33:58 PM PDT 24 |
| Peak memory | 619504 kb |
| Host | smart-fa1eab3b-a25e-414a-b538-18654db58fdc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1806756025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1806756025 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066733362 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3245672142 ps |
| CPU time | 370.82 seconds |
| Started | Jul 27 08:23:58 PM PDT 24 |
| Finished | Jul 27 08:30:09 PM PDT 24 |
| Peak memory | 649492 kb |
| Host | smart-ffce8e48-d956-4bc9-80ff-09938aed0660 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066733362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1066733362 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3710530337 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 12785098680 ps |
| CPU time | 2558.01 seconds |
| Started | Jul 27 08:22:51 PM PDT 24 |
| Finished | Jul 27 09:05:29 PM PDT 24 |
| Peak memory | 619492 kb |
| Host | smart-1eeecefc-b34e-474b-a92f-32baa309f3ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3710530337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3710530337 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3867212908 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 4434024064 ps |
| CPU time | 915.09 seconds |
| Started | Jul 27 08:22:55 PM PDT 24 |
| Finished | Jul 27 08:38:10 PM PDT 24 |
| Peak memory | 619780 kb |
| Host | smart-7b69a935-3a34-4201-a6a5-78527c6ef2db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3867212908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3867212908 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3914524208 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 12954398574 ps |
| CPU time | 2446.5 seconds |
| Started | Jul 27 08:26:02 PM PDT 24 |
| Finished | Jul 27 09:06:49 PM PDT 24 |
| Peak memory | 623752 kb |
| Host | smart-e8a8eef4-e764-4bdb-84ee-91431b75f95f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3914524208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3914524208 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1890652593 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 13412137800 ps |
| CPU time | 1520.21 seconds |
| Started | Jul 27 08:07:11 PM PDT 24 |
| Finished | Jul 27 08:32:31 PM PDT 24 |
| Peak memory | 608324 kb |
| Host | smart-42c32024-3519-4afc-b6a7-bfc184d2d180 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890652593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 890652593 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.776130585 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3607698754 ps |
| CPU time | 383.4 seconds |
| Started | Jul 27 08:17:08 PM PDT 24 |
| Finished | Jul 27 08:23:32 PM PDT 24 |
| Peak memory | 620496 kb |
| Host | smart-9223c825-c8e6-4d52-bc43-b3e6b213b03d |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7 76130585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.776130585 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3103042943 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 2991653856 ps |
| CPU time | 334.05 seconds |
| Started | Jul 27 08:14:04 PM PDT 24 |
| Finished | Jul 27 08:19:39 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-2d6c32f7-5e12-4ef9-b732-458d751f9677 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3103042943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3103042943 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1084113391 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 17981594396 ps |
| CPU time | 504.22 seconds |
| Started | Jul 27 08:11:38 PM PDT 24 |
| Finished | Jul 27 08:20:03 PM PDT 24 |
| Peak memory | 620028 kb |
| Host | smart-76bc0401-451b-4dc1-93b4-fc71a3c43aa2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1084113391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1084113391 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.3765922199 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 3619567348 ps |
| CPU time | 284.46 seconds |
| Started | Jul 27 08:12:33 PM PDT 24 |
| Finished | Jul 27 08:17:17 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-ee0c31e6-fdff-42ba-9aef-8b087c4d122c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765922199 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3765922199 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1320597920 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 3366585329 ps |
| CPU time | 255.99 seconds |
| Started | Jul 27 08:11:47 PM PDT 24 |
| Finished | Jul 27 08:16:04 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-453d5030-75ec-4448-958e-7c2b012674fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320 597920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.1320597920 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1886090547 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3245812108 ps |
| CPU time | 272.3 seconds |
| Started | Jul 27 08:16:25 PM PDT 24 |
| Finished | Jul 27 08:20:57 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-2ef620ce-d120-48a2-9974-54cfb311b56b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886090547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1886090547 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3713251319 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3105419952 ps |
| CPU time | 276.87 seconds |
| Started | Jul 27 08:11:48 PM PDT 24 |
| Finished | Jul 27 08:16:25 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-608ad162-bb83-4e96-a2e7-b99fa1a27457 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713251319 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3713251319 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.680697632 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2694097368 ps |
| CPU time | 330.94 seconds |
| Started | Jul 27 08:11:39 PM PDT 24 |
| Finished | Jul 27 08:17:11 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-69e66563-8fe9-47e7-8e37-565ea7d6a848 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680697632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.680697632 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.469332192 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 3400734611 ps |
| CPU time | 341.36 seconds |
| Started | Jul 27 08:14:42 PM PDT 24 |
| Finished | Jul 27 08:20:24 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-4c2822ff-c124-4d1e-b5c7-43700a260a3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469332192 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.469332192 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.4136866672 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 2370994856 ps |
| CPU time | 259.06 seconds |
| Started | Jul 27 08:18:03 PM PDT 24 |
| Finished | Jul 27 08:22:22 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-14ab2345-8267-4e11-969c-adc82a15576f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136866672 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.4136866672 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2554591243 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3501697462 ps |
| CPU time | 327.52 seconds |
| Started | Jul 27 08:11:58 PM PDT 24 |
| Finished | Jul 27 08:17:25 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-b659d2bc-b931-4957-833f-7cdb5cf196b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2554591243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2554591243 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.955389789 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 5932050536 ps |
| CPU time | 723.19 seconds |
| Started | Jul 27 08:11:01 PM PDT 24 |
| Finished | Jul 27 08:23:05 PM PDT 24 |
| Peak memory | 624312 kb |
| Host | smart-de9362af-7bd3-4f4c-a1ff-7b5ed17baa32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=955389789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.955389789 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.688460412 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 7491867760 ps |
| CPU time | 1786.61 seconds |
| Started | Jul 27 08:12:29 PM PDT 24 |
| Finished | Jul 27 08:42:16 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-f227bdf3-5927-4c98-aa4b-52da10534477 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=688460412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.688460412 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4213107381 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 7605676286 ps |
| CPU time | 1440.96 seconds |
| Started | Jul 27 08:15:09 PM PDT 24 |
| Finished | Jul 27 08:39:10 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-6caeb91c-bf15-45a9-b679-0944918d5f93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213107381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.4213107381 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2476984153 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 7561810978 ps |
| CPU time | 1191.58 seconds |
| Started | Jul 27 08:13:36 PM PDT 24 |
| Finished | Jul 27 08:33:28 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-e0ad56f7-03ad-4f9c-be15-5b254ebc4d46 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2476984153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2476984153 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4128180344 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 3888167976 ps |
| CPU time | 396.83 seconds |
| Started | Jul 27 08:11:16 PM PDT 24 |
| Finished | Jul 27 08:17:53 PM PDT 24 |
| Peak memory | 609152 kb |
| Host | smart-68752b53-0d33-4777-82e7-8d48ad2654d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4128180344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.4128180344 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2965275725 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 254412443130 ps |
| CPU time | 11484.4 seconds |
| Started | Jul 27 08:14:29 PM PDT 24 |
| Finished | Jul 27 11:25:55 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-2000e0c1-dd0e-4b37-a3bd-b3d260c528f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965275725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2965275725 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.1468860903 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3104297324 ps |
| CPU time | 323.07 seconds |
| Started | Jul 27 08:12:25 PM PDT 24 |
| Finished | Jul 27 08:17:48 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-30d080b1-3cbb-4ec3-ae76-08b311cb532f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468860903 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.1468860903 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.164088438 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 4360360120 ps |
| CPU time | 483.82 seconds |
| Started | Jul 27 08:11:49 PM PDT 24 |
| Finished | Jul 27 08:19:53 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-749a7397-d8b4-490d-bf63-5404559b8b85 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164088438 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.164088438 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1469141502 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 6128452950 ps |
| CPU time | 411.49 seconds |
| Started | Jul 27 08:10:28 PM PDT 24 |
| Finished | Jul 27 08:17:20 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-90e61f1b-ae2b-4d85-a41e-cf6cfbdcb357 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1469141502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1469141502 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4265660892 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 3355971924 ps |
| CPU time | 265.1 seconds |
| Started | Jul 27 08:16:48 PM PDT 24 |
| Finished | Jul 27 08:21:13 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-1a198fba-fb5d-4d97-a2ce-db8fdf3ec50a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265660892 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.4265660892 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2036522937 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 6687693288 ps |
| CPU time | 640.9 seconds |
| Started | Jul 27 08:11:02 PM PDT 24 |
| Finished | Jul 27 08:21:43 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-b46a681b-933e-453a-bab6-82ab7c8e3036 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2036522937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2036522937 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1454671443 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 6182781774 ps |
| CPU time | 783.96 seconds |
| Started | Jul 27 08:11:27 PM PDT 24 |
| Finished | Jul 27 08:24:31 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-097e713e-9e4d-4d21-ab89-bd85e0dc6528 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1454671443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1454671443 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1942120073 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 8606929248 ps |
| CPU time | 980.37 seconds |
| Started | Jul 27 08:15:26 PM PDT 24 |
| Finished | Jul 27 08:31:47 PM PDT 24 |
| Peak memory | 617928 kb |
| Host | smart-9021cc5c-7652-4cbd-8322-4c890a5d6ee1 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942120073 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1942120073 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4171478421 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 22837470064 ps |
| CPU time | 3610.84 seconds |
| Started | Jul 27 08:16:43 PM PDT 24 |
| Finished | Jul 27 09:16:55 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-7f5ff37f-ba83-4506-8b22-2b4eea879be0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171478421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.4171478421 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2963701810 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 7259827367 ps |
| CPU time | 596.21 seconds |
| Started | Jul 27 08:13:48 PM PDT 24 |
| Finished | Jul 27 08:23:45 PM PDT 24 |
| Peak memory | 620992 kb |
| Host | smart-e87b54a9-cb4c-4686-8e20-eb0f32f2c4d8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2963701810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2963701810 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4143106550 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 4246834582 ps |
| CPU time | 592.18 seconds |
| Started | Jul 27 08:13:43 PM PDT 24 |
| Finished | Jul 27 08:23:36 PM PDT 24 |
| Peak memory | 612644 kb |
| Host | smart-a1859825-ba42-4956-ac02-d4db37483cf2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143106550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.4143106550 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2515173178 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 3965494390 ps |
| CPU time | 734.67 seconds |
| Started | Jul 27 08:14:21 PM PDT 24 |
| Finished | Jul 27 08:26:36 PM PDT 24 |
| Peak memory | 612664 kb |
| Host | smart-db7b0172-dc4b-4748-8c8c-73b586b92488 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515173178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2515173178 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.699639205 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 4334789034 ps |
| CPU time | 886.3 seconds |
| Started | Jul 27 08:14:43 PM PDT 24 |
| Finished | Jul 27 08:29:29 PM PDT 24 |
| Peak memory | 613452 kb |
| Host | smart-c8a1d743-2413-4cbd-a515-9ba57ebc3dde |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699639205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.699639205 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2234230168 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 4687151642 ps |
| CPU time | 663.15 seconds |
| Started | Jul 27 08:14:20 PM PDT 24 |
| Finished | Jul 27 08:25:24 PM PDT 24 |
| Peak memory | 612664 kb |
| Host | smart-bf90d018-901d-4f10-ae4e-1da572df5b40 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234230168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2234230168 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.866393932 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 4321812560 ps |
| CPU time | 679.63 seconds |
| Started | Jul 27 08:14:22 PM PDT 24 |
| Finished | Jul 27 08:25:42 PM PDT 24 |
| Peak memory | 613724 kb |
| Host | smart-87efedb9-9736-4ec2-8076-8e290b366009 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866393932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.866393932 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1658723285 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 5331195278 ps |
| CPU time | 821.79 seconds |
| Started | Jul 27 08:14:31 PM PDT 24 |
| Finished | Jul 27 08:28:13 PM PDT 24 |
| Peak memory | 613680 kb |
| Host | smart-6bcb00c9-973b-4b22-a5f3-6d65d14c4f67 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658723285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1658723285 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2048152777 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 2441178231 ps |
| CPU time | 226.31 seconds |
| Started | Jul 27 08:15:46 PM PDT 24 |
| Finished | Jul 27 08:19:33 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-224584f2-0469-4809-a2e5-ab79a0d53734 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048152777 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2048152777 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.108261042 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 3436365306 ps |
| CPU time | 434.64 seconds |
| Started | Jul 27 08:15:13 PM PDT 24 |
| Finished | Jul 27 08:22:28 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-ce5a9909-c0f8-401c-967b-e641f88b6657 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108261042 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.108261042 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4214818659 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 3048350754 ps |
| CPU time | 222.75 seconds |
| Started | Jul 27 08:15:25 PM PDT 24 |
| Finished | Jul 27 08:19:08 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-e74abc0f-6916-4670-aa6b-bea27f39caf8 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214818659 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.4214818659 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4041316334 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 4255849304 ps |
| CPU time | 383.71 seconds |
| Started | Jul 27 08:14:33 PM PDT 24 |
| Finished | Jul 27 08:20:57 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-9fcfbc24-1fce-4336-8675-3fbb864174fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041316334 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.4041316334 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1728386939 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 5144055114 ps |
| CPU time | 432.49 seconds |
| Started | Jul 27 08:14:18 PM PDT 24 |
| Finished | Jul 27 08:21:31 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-a3b5c784-f181-4d27-95d2-6d2bc9671b57 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728386939 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.1728386939 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3477836271 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5010142136 ps |
| CPU time | 640.1 seconds |
| Started | Jul 27 08:14:13 PM PDT 24 |
| Finished | Jul 27 08:24:53 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-7e111612-3729-4fef-810c-cfdf55a2963c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477836271 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3477836271 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1548517873 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 4845418890 ps |
| CPU time | 595.48 seconds |
| Started | Jul 27 08:15:36 PM PDT 24 |
| Finished | Jul 27 08:25:32 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-37590e45-9a77-4350-976c-b73f75e2e3a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548517873 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1548517873 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.44529359 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 10472542890 ps |
| CPU time | 1534.27 seconds |
| Started | Jul 27 08:14:42 PM PDT 24 |
| Finished | Jul 27 08:40:17 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-5b86ad73-cb08-476f-b76a-3b3e740c87a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44529359 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.44529359 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1029421730 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 4395269436 ps |
| CPU time | 482.81 seconds |
| Started | Jul 27 08:14:53 PM PDT 24 |
| Finished | Jul 27 08:22:56 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-dc2cd8d7-884f-48b8-8920-6b1652692636 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029421730 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1029421730 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2251604710 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 4973075130 ps |
| CPU time | 697.1 seconds |
| Started | Jul 27 08:15:31 PM PDT 24 |
| Finished | Jul 27 08:27:08 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-e29cc7c2-f6f8-43a0-9755-f3364a934230 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251604710 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2251604710 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1885891730 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2950692552 ps |
| CPU time | 354.23 seconds |
| Started | Jul 27 08:18:06 PM PDT 24 |
| Finished | Jul 27 08:24:00 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-d7ffb204-f561-4e3b-869f-7b51c13daabc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885891730 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.1885891730 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1574537193 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 17665017800 ps |
| CPU time | 4501.57 seconds |
| Started | Jul 27 08:12:57 PM PDT 24 |
| Finished | Jul 27 09:27:59 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-6b81649a-23d5-4cd2-9280-dd6d68711c02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574537193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1574537193 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1506364637 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 4333792736 ps |
| CPU time | 584.24 seconds |
| Started | Jul 27 08:12:23 PM PDT 24 |
| Finished | Jul 27 08:22:07 PM PDT 24 |
| Peak memory | 611456 kb |
| Host | smart-13776f19-b937-4d9d-bb54-deb945d0fb42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063 64637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1506364637 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.3627958279 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 3143188200 ps |
| CPU time | 213.69 seconds |
| Started | Jul 27 08:11:43 PM PDT 24 |
| Finished | Jul 27 08:15:17 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-dced29ed-d3c7-488a-af85-8e60ef50e3f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627958279 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3627958279 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2294583590 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 2336290532 ps |
| CPU time | 273.32 seconds |
| Started | Jul 27 08:16:36 PM PDT 24 |
| Finished | Jul 27 08:21:09 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-de2f42be-d6a0-44f2-9704-5945070e2ac8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294583590 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2294583590 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3656304073 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5226838774 ps |
| CPU time | 859.12 seconds |
| Started | Jul 27 08:09:28 PM PDT 24 |
| Finished | Jul 27 08:23:48 PM PDT 24 |
| Peak memory | 611676 kb |
| Host | smart-a5d2aefd-c9d7-491d-9cb2-9085889c03a8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3656304073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3656304073 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.141310021 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 5825852250 ps |
| CPU time | 1346.27 seconds |
| Started | Jul 27 08:12:04 PM PDT 24 |
| Finished | Jul 27 08:34:31 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-bed20946-c965-49d3-9e23-04c076568fdc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141310021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a uto_mode.141310021 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.575587968 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 3019674150 ps |
| CPU time | 539.41 seconds |
| Started | Jul 27 08:11:58 PM PDT 24 |
| Finished | Jul 27 08:20:57 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-d374ae69-1485-4f19-8477-0be6400ce316 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575587968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.575587968 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1996750182 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 5723408350 ps |
| CPU time | 966.94 seconds |
| Started | Jul 27 08:12:29 PM PDT 24 |
| Finished | Jul 27 08:28:36 PM PDT 24 |
| Peak memory | 611416 kb |
| Host | smart-f4255764-b1b5-4bee-968e-919ca2266213 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1996750182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1996750182 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.860246 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 7346024689 ps |
| CPU time | 1143.71 seconds |
| Started | Jul 27 08:12:41 PM PDT 24 |
| Finished | Jul 27 08:31:45 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-138546a3-98bc-4688-83ce-222cb9ae1ab8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.860246 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.1934171934 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3562771624 ps |
| CPU time | 559.48 seconds |
| Started | Jul 27 08:11:40 PM PDT 24 |
| Finished | Jul 27 08:20:59 PM PDT 24 |
| Peak memory | 616024 kb |
| Host | smart-050ead0b-81f4-419d-84d8-602b02996107 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934171934 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.1934171934 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2299119016 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 5776776008 ps |
| CPU time | 1076.31 seconds |
| Started | Jul 27 08:12:12 PM PDT 24 |
| Finished | Jul 27 08:30:08 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-5f7db334-75c1-46a9-8fea-9c97980be91c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299119016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2299119016 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3576881728 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 3026209666 ps |
| CPU time | 230.09 seconds |
| Started | Jul 27 08:15:29 PM PDT 24 |
| Finished | Jul 27 08:19:19 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-3e5cecae-c569-4ccd-943e-addbe95a7af0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35 76881728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3576881728 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1120468266 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 6896158424 ps |
| CPU time | 1725.81 seconds |
| Started | Jul 27 08:15:42 PM PDT 24 |
| Finished | Jul 27 08:44:28 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-77158140-a31c-4d9e-9f23-cea57557a730 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1120468266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1120468266 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2399812587 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2860569016 ps |
| CPU time | 203.92 seconds |
| Started | Jul 27 08:12:23 PM PDT 24 |
| Finished | Jul 27 08:15:48 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-0a3729c9-c0b3-4c06-854b-e69969f2a0ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399812587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2399812587 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2605645190 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 3526863350 ps |
| CPU time | 361.39 seconds |
| Started | Jul 27 08:17:07 PM PDT 24 |
| Finished | Jul 27 08:23:09 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-795507f9-ee3f-4d7f-84e6-5270db75d335 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2605645190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2605645190 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.3482728528 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3058631764 ps |
| CPU time | 238.64 seconds |
| Started | Jul 27 08:10:30 PM PDT 24 |
| Finished | Jul 27 08:14:28 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-e22cfdba-0619-41d8-88da-4b4e9b10564b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482728528 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.3482728528 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.2155470792 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 2571972450 ps |
| CPU time | 252.94 seconds |
| Started | Jul 27 08:10:37 PM PDT 24 |
| Finished | Jul 27 08:14:50 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-411534b6-c6f2-458d-86f7-4f3f9b1bbe65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155470792 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.2155470792 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.3204368724 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2809844666 ps |
| CPU time | 159.71 seconds |
| Started | Jul 27 08:09:10 PM PDT 24 |
| Finished | Jul 27 08:11:50 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-cecfd2cf-cd20-4552-84d4-4feb16862433 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204368724 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3204368724 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2670482243 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 2570296144 ps |
| CPU time | 162.26 seconds |
| Started | Jul 27 08:08:27 PM PDT 24 |
| Finished | Jul 27 08:11:09 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-ba688ddb-d384-4971-92a1-e7f125436a0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670482243 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2670482243 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2780029463 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 57372397544 ps |
| CPU time | 10577.9 seconds |
| Started | Jul 27 08:09:49 PM PDT 24 |
| Finished | Jul 27 11:06:08 PM PDT 24 |
| Peak memory | 625336 kb |
| Host | smart-4b7370dd-e50f-43d6-ab85-3b5f165fe615 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2780029463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2780029463 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.1585796551 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4625627948 ps |
| CPU time | 500.68 seconds |
| Started | Jul 27 08:14:09 PM PDT 24 |
| Finished | Jul 27 08:22:29 PM PDT 24 |
| Peak memory | 611452 kb |
| Host | smart-3eefc5b6-b844-4d9b-8b84-be5f5b8e0ecd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1585796551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.1585796551 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4066179113 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 5193507712 ps |
| CPU time | 1052.84 seconds |
| Started | Jul 27 08:10:56 PM PDT 24 |
| Finished | Jul 27 08:28:29 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-43ffe365-5142-4f33-a316-00e558ee6547 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066179113 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.4066179113 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.981649990 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 5348198053 ps |
| CPU time | 1285.7 seconds |
| Started | Jul 27 08:10:05 PM PDT 24 |
| Finished | Jul 27 08:31:31 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-14fee7e6-93cb-458b-a772-549a6ae82389 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981649990 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.981649990 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.835525146 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 8068026294 ps |
| CPU time | 1288.67 seconds |
| Started | Jul 27 08:15:30 PM PDT 24 |
| Finished | Jul 27 08:36:59 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-b3ebf36d-a7d6-4a56-b7f3-c3b28ab0cd5b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835525146 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.835525146 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.290459915 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5718082096 ps |
| CPU time | 1165.9 seconds |
| Started | Jul 27 08:09:39 PM PDT 24 |
| Finished | Jul 27 08:29:05 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-1aa47cbb-7a91-459f-9a3e-3acabaa556de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290459915 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.290459915 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2909451762 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3089779754 ps |
| CPU time | 298.33 seconds |
| Started | Jul 27 08:09:25 PM PDT 24 |
| Finished | Jul 27 08:14:23 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-71d0334a-dd9e-492c-8e6a-218c1e0ceb22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909451762 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2909451762 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3324700847 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 4775243000 ps |
| CPU time | 400.79 seconds |
| Started | Jul 27 08:08:46 PM PDT 24 |
| Finished | Jul 27 08:15:27 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-93148865-ff26-4897-ae2d-b35b9e7bc733 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33 24700847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3324700847 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2955597489 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 5835216018 ps |
| CPU time | 1156.23 seconds |
| Started | Jul 27 08:16:57 PM PDT 24 |
| Finished | Jul 27 08:36:14 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-d6062b42-fb08-4de5-8621-c860b1b4512f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955597489 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2955597489 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1183901893 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4255110148 ps |
| CPU time | 670.96 seconds |
| Started | Jul 27 08:09:52 PM PDT 24 |
| Finished | Jul 27 08:21:03 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-f388304d-e434-4aff-8bac-6e1e049fd253 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183901893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1183901893 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2916526552 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4694136168 ps |
| CPU time | 704.94 seconds |
| Started | Jul 27 08:10:29 PM PDT 24 |
| Finished | Jul 27 08:22:14 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-35606787-833a-45a8-8a7c-ad5be4f5fd92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2916526552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2916526552 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1948121976 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 5641466052 ps |
| CPU time | 672.08 seconds |
| Started | Jul 27 08:16:32 PM PDT 24 |
| Finished | Jul 27 08:27:44 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-99a3df2e-7a20-4482-b22d-9ec262ce2aa7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1948121976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1948121976 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.898830765 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3329228588 ps |
| CPU time | 335.04 seconds |
| Started | Jul 27 08:14:36 PM PDT 24 |
| Finished | Jul 27 08:20:11 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-7f6b775a-b620-4036-b489-71f714e776c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8988307 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.898830765 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.4050712338 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 19548425623 ps |
| CPU time | 1976.05 seconds |
| Started | Jul 27 08:10:18 PM PDT 24 |
| Finished | Jul 27 08:43:15 PM PDT 24 |
| Peak memory | 612220 kb |
| Host | smart-f4498ddc-53cd-4e88-a5e8-380a3823b4d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050712338 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.4050712338 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.995507379 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 22203351353 ps |
| CPU time | 2483.94 seconds |
| Started | Jul 27 08:15:56 PM PDT 24 |
| Finished | Jul 27 08:57:21 PM PDT 24 |
| Peak memory | 612312 kb |
| Host | smart-8ad2210d-16d8-42d2-903d-1f459649763c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=995507379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.995507379 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2019257610 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 2817172556 ps |
| CPU time | 249.51 seconds |
| Started | Jul 27 08:19:32 PM PDT 24 |
| Finished | Jul 27 08:23:42 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-7575100f-12ad-477b-ba97-9e2238d9ff69 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2019257610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2019257610 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.2193031929 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 3262563405 ps |
| CPU time | 310.23 seconds |
| Started | Jul 27 08:18:16 PM PDT 24 |
| Finished | Jul 27 08:23:26 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-fb121208-6eab-4fcf-8074-14d0332f23aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193031929 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2193031929 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.4117248127 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2496913936 ps |
| CPU time | 238.4 seconds |
| Started | Jul 27 08:13:54 PM PDT 24 |
| Finished | Jul 27 08:17:53 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-511da097-0ae2-4559-a591-ab07ee68ccf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117248127 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.4117248127 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2808592313 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 3128312388 ps |
| CPU time | 347.54 seconds |
| Started | Jul 27 08:12:32 PM PDT 24 |
| Finished | Jul 27 08:18:20 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-41a964dc-a0af-4c65-b9f7-fa0accef9689 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808592313 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2808592313 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1249580668 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 3436889854 ps |
| CPU time | 338.42 seconds |
| Started | Jul 27 08:15:01 PM PDT 24 |
| Finished | Jul 27 08:20:40 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-1edad888-592e-48ca-81c6-38ad1ca3c8d6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249580668 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1249580668 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3273258010 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 2968240918 ps |
| CPU time | 217.1 seconds |
| Started | Jul 27 08:15:51 PM PDT 24 |
| Finished | Jul 27 08:19:28 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-02986427-0cb6-4684-8b6b-bc7af16e614b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273258010 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3273258010 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1129582079 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 7500575512 ps |
| CPU time | 1454.42 seconds |
| Started | Jul 27 08:12:43 PM PDT 24 |
| Finished | Jul 27 08:36:58 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-a1b37476-f434-448c-ae25-c5e9fbd7f8b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129582079 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1129582079 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2458097451 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 2710647400 ps |
| CPU time | 338.04 seconds |
| Started | Jul 27 08:12:40 PM PDT 24 |
| Finished | Jul 27 08:18:18 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-e217f99f-13d2-45ba-8420-cc6216f94d70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458097451 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2458097451 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2584935698 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3176391822 ps |
| CPU time | 337.93 seconds |
| Started | Jul 27 08:17:50 PM PDT 24 |
| Finished | Jul 27 08:23:28 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-8c1b69ac-008b-4ec7-a941-bf2d9d4ffe11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584935698 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2584935698 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3796230845 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3702083216 ps |
| CPU time | 490.59 seconds |
| Started | Jul 27 08:10:11 PM PDT 24 |
| Finished | Jul 27 08:18:23 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-a975ebf0-d130-4407-a632-5280a63fc165 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796230845 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.3796230845 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1430471589 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 4830791538 ps |
| CPU time | 755.03 seconds |
| Started | Jul 27 08:09:38 PM PDT 24 |
| Finished | Jul 27 08:22:14 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-255082a4-e093-4a66-9377-b160d55e11f2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430471589 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.1430471589 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1978335141 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5402496960 ps |
| CPU time | 844.79 seconds |
| Started | Jul 27 08:10:03 PM PDT 24 |
| Finished | Jul 27 08:24:08 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-1363b149-8ce2-482c-970c-544f947e1415 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978335141 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1978335141 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2096205042 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5560543914 ps |
| CPU time | 1022.79 seconds |
| Started | Jul 27 08:08:57 PM PDT 24 |
| Finished | Jul 27 08:26:00 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-a005212c-2e82-4399-9168-2b5184e2921d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096205042 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.2096205042 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.887284226 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 65464782621 ps |
| CPU time | 11155.3 seconds |
| Started | Jul 27 08:10:26 PM PDT 24 |
| Finished | Jul 27 11:16:23 PM PDT 24 |
| Peak memory | 625292 kb |
| Host | smart-3e82b7dd-e4ce-48a3-bdc2-5eea3cdb3eec |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=887284226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.887284226 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1947307873 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 11231775192 ps |
| CPU time | 2538.4 seconds |
| Started | Jul 27 08:12:26 PM PDT 24 |
| Finished | Jul 27 08:54:45 PM PDT 24 |
| Peak memory | 618400 kb |
| Host | smart-b5853ed0-2cdc-413e-85be-dac56fa11ca1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947 307873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1947307873 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2851879661 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 11374817504 ps |
| CPU time | 2310.94 seconds |
| Started | Jul 27 08:12:31 PM PDT 24 |
| Finished | Jul 27 08:51:02 PM PDT 24 |
| Peak memory | 617448 kb |
| Host | smart-32051bff-ae63-42e2-b0b7-1792042e2909 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2851879661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2851879661 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2842282575 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 12340093260 ps |
| CPU time | 2399.26 seconds |
| Started | Jul 27 08:16:45 PM PDT 24 |
| Finished | Jul 27 08:56:44 PM PDT 24 |
| Peak memory | 618736 kb |
| Host | smart-340317ec-2996-4c43-b2b5-2296d16e81e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2842282575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2842282575 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1635257449 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7645966526 ps |
| CPU time | 1220.58 seconds |
| Started | Jul 27 08:15:33 PM PDT 24 |
| Finished | Jul 27 08:35:54 PM PDT 24 |
| Peak memory | 611608 kb |
| Host | smart-e7f3b9c3-cdb1-455f-86ab-c05e092cfb1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352 57449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1635257449 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1897608547 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 14938910312 ps |
| CPU time | 4056.08 seconds |
| Started | Jul 27 08:14:31 PM PDT 24 |
| Finished | Jul 27 09:22:08 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-0f695f51-0063-4246-b8ee-3f295ca1b65e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18976 08547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1897608547 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.1304104103 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2737030380 ps |
| CPU time | 330.48 seconds |
| Started | Jul 27 08:13:39 PM PDT 24 |
| Finished | Jul 27 08:19:10 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-8fdb7527-4302-4226-99d8-2b7e7a5a8a53 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304104103 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.1304104103 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.1659507556 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 3140446750 ps |
| CPU time | 250.15 seconds |
| Started | Jul 27 08:10:52 PM PDT 24 |
| Finished | Jul 27 08:15:03 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-94aaf122-f59b-467b-9f7d-78033d645cbe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659507556 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1659507556 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.3203761876 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 2838013200 ps |
| CPU time | 249.74 seconds |
| Started | Jul 27 08:13:41 PM PDT 24 |
| Finished | Jul 27 08:17:51 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-9343e455-4dc8-4cb4-a2c3-c25374194651 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203761876 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.3203761876 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4262184011 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 2994366200 ps |
| CPU time | 206.08 seconds |
| Started | Jul 27 08:12:36 PM PDT 24 |
| Finished | Jul 27 08:16:02 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-ff98554c-97a0-4a8a-a5be-6723d5f2caf5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262184011 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.4262184011 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1533252984 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2993848966 ps |
| CPU time | 343.58 seconds |
| Started | Jul 27 08:15:28 PM PDT 24 |
| Finished | Jul 27 08:21:12 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-d1426339-03bf-4a72-a948-0de009a08cbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533252984 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.1533252984 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2860444868 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 3270448779 ps |
| CPU time | 362.91 seconds |
| Started | Jul 27 08:13:49 PM PDT 24 |
| Finished | Jul 27 08:19:53 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-35c28e83-e47b-4d51-b312-4dc7edef930a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860444868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2860444868 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1328471570 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2819722319 ps |
| CPU time | 281.11 seconds |
| Started | Jul 27 08:14:56 PM PDT 24 |
| Finished | Jul 27 08:19:38 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-6ec47472-434a-4707-99dd-72cd7413ad3e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13284715 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1328471570 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2668937339 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2994047820 ps |
| CPU time | 336.58 seconds |
| Started | Jul 27 08:17:35 PM PDT 24 |
| Finished | Jul 27 08:23:12 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-7cdc48e9-74c4-40ce-9ea7-a0dc1d190220 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668937339 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2668937339 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1336779245 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3189759942 ps |
| CPU time | 403.5 seconds |
| Started | Jul 27 08:11:04 PM PDT 24 |
| Finished | Jul 27 08:17:47 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-a85eaf24-bf90-4746-b7a8-601594cfa3fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336779245 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1336779245 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3692977778 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4011233184 ps |
| CPU time | 433.01 seconds |
| Started | Jul 27 08:14:19 PM PDT 24 |
| Finished | Jul 27 08:21:32 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-48f85af8-81ef-42e3-bd7e-7569e46d00f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3692977778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.3692977778 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3991588991 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3608191879 ps |
| CPU time | 179 seconds |
| Started | Jul 27 08:11:07 PM PDT 24 |
| Finished | Jul 27 08:14:08 PM PDT 24 |
| Peak memory | 620612 kb |
| Host | smart-6ab34c99-885e-4dae-b27a-b4cc30b08c16 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915889 91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3991588991 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3641533376 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 6304571867 ps |
| CPU time | 423.52 seconds |
| Started | Jul 27 08:10:22 PM PDT 24 |
| Finished | Jul 27 08:17:26 PM PDT 24 |
| Peak memory | 621080 kb |
| Host | smart-31eec836-afe7-483f-ba37-2adf804e6942 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641533376 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3641533376 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1655887270 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2250360820 ps |
| CPU time | 108.6 seconds |
| Started | Jul 27 08:09:40 PM PDT 24 |
| Finished | Jul 27 08:11:29 PM PDT 24 |
| Peak memory | 618456 kb |
| Host | smart-28070325-7ccd-4c63-af08-0ecc506b3dfd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1655887270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1655887270 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2135647994 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 2453202442 ps |
| CPU time | 94.78 seconds |
| Started | Jul 27 08:09:29 PM PDT 24 |
| Finished | Jul 27 08:11:04 PM PDT 24 |
| Peak memory | 618348 kb |
| Host | smart-446ca97f-a45f-44b8-9050-63fa9332a365 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135647994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2135647994 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.478292661 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 46750242883 ps |
| CPU time | 6571.21 seconds |
| Started | Jul 27 08:10:49 PM PDT 24 |
| Finished | Jul 27 10:00:21 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-b915e2f6-c392-49c8-bfcb-ac7a150c1fb5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478292661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.478292661 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3054681991 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 9554542003 ps |
| CPU time | 868.13 seconds |
| Started | Jul 27 08:10:53 PM PDT 24 |
| Finished | Jul 27 08:25:22 PM PDT 24 |
| Peak memory | 621812 kb |
| Host | smart-3300d998-d348-4bd1-85a1-160c657137f0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054681991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3054681991 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1117749272 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 47491821220 ps |
| CPU time | 6021.21 seconds |
| Started | Jul 27 08:09:29 PM PDT 24 |
| Finished | Jul 27 09:49:51 PM PDT 24 |
| Peak memory | 620828 kb |
| Host | smart-ab78527e-8a66-4b22-8251-f199d3709d59 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117749272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1117749272 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2892385201 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 34000078490 ps |
| CPU time | 2255.21 seconds |
| Started | Jul 27 08:10:43 PM PDT 24 |
| Finished | Jul 27 08:48:19 PM PDT 24 |
| Peak memory | 621328 kb |
| Host | smart-c0064fa1-07a7-4954-9e1c-aa4718789eee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2892385201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2892385201 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1300370554 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 17031835534 ps |
| CPU time | 4054.71 seconds |
| Started | Jul 27 08:10:57 PM PDT 24 |
| Finished | Jul 27 09:18:32 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-97457b86-25c7-451f-b661-3c74595b57f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1300370554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1300370554 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3037100399 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 18315294713 ps |
| CPU time | 4112.45 seconds |
| Started | Jul 27 08:11:24 PM PDT 24 |
| Finished | Jul 27 09:19:57 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-ae234c77-6953-4bb0-8df4-a664add99bb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3037100399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3037100399 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2289886656 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 24504116197 ps |
| CPU time | 3838.75 seconds |
| Started | Jul 27 08:15:22 PM PDT 24 |
| Finished | Jul 27 09:19:22 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-888831e3-e92a-4da7-bbec-fd8c185bd93b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289886656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2289886656 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1577294368 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3542764822 ps |
| CPU time | 514.31 seconds |
| Started | Jul 27 08:11:47 PM PDT 24 |
| Finished | Jul 27 08:20:21 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-2370ad91-a2ce-48ac-9a8b-54e6720b811b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577294368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1577294368 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.3281625812 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 6206090734 ps |
| CPU time | 1080.08 seconds |
| Started | Jul 27 08:10:32 PM PDT 24 |
| Finished | Jul 27 08:28:33 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-e6897204-644b-4d07-99a2-cae7e50c2de8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3281625812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3281625812 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.3568046888 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 10464751868 ps |
| CPU time | 2189.78 seconds |
| Started | Jul 27 08:18:02 PM PDT 24 |
| Finished | Jul 27 08:54:33 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-fc564c4c-ef63-4d5c-90e1-74edcc57f2f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568046888 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.3568046888 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1621108084 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 2400949192 ps |
| CPU time | 299.08 seconds |
| Started | Jul 27 08:10:49 PM PDT 24 |
| Finished | Jul 27 08:15:49 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-4ea22455-fd21-4e80-ace8-5a0073e7d25d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621108084 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1621108084 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3714241868 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 8803369792 ps |
| CPU time | 1321.02 seconds |
| Started | Jul 27 08:10:42 PM PDT 24 |
| Finished | Jul 27 08:32:43 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-da267d68-df43-45e5-87c1-caea7168ce15 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3714241868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3714241868 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2361710524 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 8713127416 ps |
| CPU time | 1465.63 seconds |
| Started | Jul 27 08:09:23 PM PDT 24 |
| Finished | Jul 27 08:33:49 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-ad4bbe36-5980-408d-abd1-598c5a3c1050 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2361710524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2361710524 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2791797871 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 8032309824 ps |
| CPU time | 1144.21 seconds |
| Started | Jul 27 08:10:55 PM PDT 24 |
| Finished | Jul 27 08:30:00 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-d83447b2-1894-4f0b-ba74-ec3630d4b534 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2791797871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2791797871 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2179439759 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4152031340 ps |
| CPU time | 688.84 seconds |
| Started | Jul 27 08:10:48 PM PDT 24 |
| Finished | Jul 27 08:22:17 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-dd9a3719-0619-43d5-8806-b65962366f36 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2179439759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2179439759 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1881186316 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3498911984 ps |
| CPU time | 317.4 seconds |
| Started | Jul 27 08:17:28 PM PDT 24 |
| Finished | Jul 27 08:22:46 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-287c7d3d-4b6d-4dee-b8cc-3de597e2b2df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881186316 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1881186316 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1412271797 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2498389520 ps |
| CPU time | 235.33 seconds |
| Started | Jul 27 08:14:35 PM PDT 24 |
| Finished | Jul 27 08:18:30 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-761beeda-afa1-4845-a0da-f5ace0e8cf9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412271797 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1412271797 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.1775442364 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 3753861736 ps |
| CPU time | 711 seconds |
| Started | Jul 27 08:17:34 PM PDT 24 |
| Finished | Jul 27 08:29:25 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-9aa1dd3f-b91d-4a79-9158-1be1fa177856 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775442364 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1775442364 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.1221125741 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 10759908764 ps |
| CPU time | 813.23 seconds |
| Started | Jul 27 08:16:52 PM PDT 24 |
| Finished | Jul 27 08:30:26 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-d27260cd-aa54-462e-b174-a7f7bf41c5a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221125741 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1221125741 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.712731608 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5670015910 ps |
| CPU time | 1396.26 seconds |
| Started | Jul 27 08:19:12 PM PDT 24 |
| Finished | Jul 27 08:42:29 PM PDT 24 |
| Peak memory | 625576 kb |
| Host | smart-b668d003-c1a0-4c59-a3c7-215bc47375d5 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=712731608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.712731608 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.508175255 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 10569465038 ps |
| CPU time | 1872.08 seconds |
| Started | Jul 27 08:12:34 PM PDT 24 |
| Finished | Jul 27 08:43:46 PM PDT 24 |
| Peak memory | 611980 kb |
| Host | smart-651794eb-1553-4ad1-9694-6b173142f35e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5081 75255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.508175255 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.785057977 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 24584465480 ps |
| CPU time | 2252.08 seconds |
| Started | Jul 27 08:14:07 PM PDT 24 |
| Finished | Jul 27 08:51:40 PM PDT 24 |
| Peak memory | 611232 kb |
| Host | smart-ec4b5d1b-1544-461a-bd16-420b66dc969a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785 057977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.785057977 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2689040097 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 17427914402 ps |
| CPU time | 1527.92 seconds |
| Started | Jul 27 08:12:12 PM PDT 24 |
| Finished | Jul 27 08:37:40 PM PDT 24 |
| Peak memory | 612088 kb |
| Host | smart-f5fd5f0f-eace-4a38-be45-95c7eb402c47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2689040097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2689040097 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3746277487 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 20257016580 ps |
| CPU time | 1093.82 seconds |
| Started | Jul 27 08:15:22 PM PDT 24 |
| Finished | Jul 27 08:33:36 PM PDT 24 |
| Peak memory | 611628 kb |
| Host | smart-67039280-64eb-4aa5-a805-6f3af686251c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3746277487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3746277487 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2958547333 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 9119038232 ps |
| CPU time | 790.53 seconds |
| Started | Jul 27 08:09:49 PM PDT 24 |
| Finished | Jul 27 08:23:00 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-dc687acb-a16a-43a5-8a22-231dee35d1e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958547333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2958547333 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2806855721 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 6887356952 ps |
| CPU time | 361.13 seconds |
| Started | Jul 27 08:10:51 PM PDT 24 |
| Finished | Jul 27 08:16:52 PM PDT 24 |
| Peak memory | 617812 kb |
| Host | smart-24e57265-863f-47e2-97c9-c575a9bdb1ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2806855721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2806855721 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1289627755 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 7105148160 ps |
| CPU time | 461.71 seconds |
| Started | Jul 27 08:11:24 PM PDT 24 |
| Finished | Jul 27 08:19:06 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-4ace75c1-d3c8-45e3-a440-7f26d25f2a0f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289627755 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1289627755 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1602203728 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4010099880 ps |
| CPU time | 520.24 seconds |
| Started | Jul 27 08:14:31 PM PDT 24 |
| Finished | Jul 27 08:23:12 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-664760e1-8ce2-41ee-ac0c-700ae8770cc5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602203728 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1602203728 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3039026581 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 4121493074 ps |
| CPU time | 547.96 seconds |
| Started | Jul 27 08:11:08 PM PDT 24 |
| Finished | Jul 27 08:20:16 PM PDT 24 |
| Peak memory | 616796 kb |
| Host | smart-cb1bc5f7-57f6-4651-b047-8387cb13fffe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3039026581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3039026581 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3661964191 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 11945934340 ps |
| CPU time | 1560 seconds |
| Started | Jul 27 08:10:20 PM PDT 24 |
| Finished | Jul 27 08:36:20 PM PDT 24 |
| Peak memory | 612088 kb |
| Host | smart-98d5157c-004b-4ae6-87b2-4b394546c0c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661964191 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3661964191 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1715523344 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 7986482850 ps |
| CPU time | 720 seconds |
| Started | Jul 27 08:11:34 PM PDT 24 |
| Finished | Jul 27 08:23:34 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-5c282675-216e-45bc-8f60-d6ea6c820d74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715523344 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1715523344 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.112144836 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 24198663530 ps |
| CPU time | 2945.28 seconds |
| Started | Jul 27 08:11:26 PM PDT 24 |
| Finished | Jul 27 09:00:32 PM PDT 24 |
| Peak memory | 612140 kb |
| Host | smart-d3691e4f-bfc2-4299-b3ab-0d7cfb2a4261 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=112144836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.112144836 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1297547776 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 23542780202 ps |
| CPU time | 1312.15 seconds |
| Started | Jul 27 08:14:54 PM PDT 24 |
| Finished | Jul 27 08:36:46 PM PDT 24 |
| Peak memory | 611620 kb |
| Host | smart-6736973d-352a-49e6-b8bc-fe0007298e54 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1297547776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1297547776 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.625312629 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 26006764104 ps |
| CPU time | 3240.74 seconds |
| Started | Jul 27 08:12:20 PM PDT 24 |
| Finished | Jul 27 09:06:22 PM PDT 24 |
| Peak memory | 612348 kb |
| Host | smart-abc73c86-03f1-4f7b-94b1-261322458e22 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625312629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.625312629 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.361401958 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 5301913780 ps |
| CPU time | 611.22 seconds |
| Started | Jul 27 08:14:07 PM PDT 24 |
| Finished | Jul 27 08:24:19 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-d400044f-1bcb-4ee4-a410-07ab529de3dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=361401958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.361401958 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1921321237 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3365333322 ps |
| CPU time | 260.35 seconds |
| Started | Jul 27 08:10:53 PM PDT 24 |
| Finished | Jul 27 08:15:14 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-4a7ecab1-87f3-4bbe-932a-91ea5a7e2c83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921321237 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.1921321237 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3100528874 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 6489023260 ps |
| CPU time | 394.94 seconds |
| Started | Jul 27 08:12:04 PM PDT 24 |
| Finished | Jul 27 08:18:40 PM PDT 24 |
| Peak memory | 618344 kb |
| Host | smart-40b60e2a-1f29-4d6c-947a-7094cdadd6cf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3100528874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3100528874 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3065735923 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5403812614 ps |
| CPU time | 389.24 seconds |
| Started | Jul 27 08:16:22 PM PDT 24 |
| Finished | Jul 27 08:22:52 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-9af04987-3079-4e9a-9119-c3569549efcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30657359 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3065735923 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1128686395 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5851460772 ps |
| CPU time | 552.13 seconds |
| Started | Jul 27 08:16:00 PM PDT 24 |
| Finished | Jul 27 08:25:12 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-a69fcbe8-1fa4-4138-94e4-b9c5ee3ad1e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1128686395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1128686395 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2001299838 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 4352971060 ps |
| CPU time | 288.76 seconds |
| Started | Jul 27 08:18:25 PM PDT 24 |
| Finished | Jul 27 08:23:14 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-95c9a909-2bc5-49b2-b442-c37a27739fb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001299838 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.2001299838 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.806882245 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 7180184750 ps |
| CPU time | 1031.36 seconds |
| Started | Jul 27 08:10:39 PM PDT 24 |
| Finished | Jul 27 08:27:51 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-d8aab62b-fdea-46cc-9891-41cf6749ad14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806882245 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.806882245 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2418288257 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4141775550 ps |
| CPU time | 368.73 seconds |
| Started | Jul 27 08:12:17 PM PDT 24 |
| Finished | Jul 27 08:18:26 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-72b64101-cad8-4c1c-b2e7-1a23ca0272c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418288257 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2418288257 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1796508440 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 7022086252 ps |
| CPU time | 570.65 seconds |
| Started | Jul 27 08:17:55 PM PDT 24 |
| Finished | Jul 27 08:27:26 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-0545d243-1ddd-4989-82cf-57a8ec0663d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796508440 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1796508440 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1869113748 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 5412164836 ps |
| CPU time | 691.71 seconds |
| Started | Jul 27 08:11:53 PM PDT 24 |
| Finished | Jul 27 08:23:25 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-77f2d813-70fb-429e-af21-ad6b7fac98de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186 9113748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1869113748 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.578118912 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 9535672113 ps |
| CPU time | 542.41 seconds |
| Started | Jul 27 08:15:41 PM PDT 24 |
| Finished | Jul 27 08:24:44 PM PDT 24 |
| Peak memory | 625380 kb |
| Host | smart-a221594f-87e4-4e25-974e-1a74199a7201 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578118912 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.578118912 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1234130134 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 7405806766 ps |
| CPU time | 822.36 seconds |
| Started | Jul 27 08:11:20 PM PDT 24 |
| Finished | Jul 27 08:25:03 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-b2f66814-fa91-4ebd-ac96-84200f35667c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234130134 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1234130134 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1226009081 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4752722344 ps |
| CPU time | 516.19 seconds |
| Started | Jul 27 08:09:25 PM PDT 24 |
| Finished | Jul 27 08:18:01 PM PDT 24 |
| Peak memory | 642168 kb |
| Host | smart-550a7fd5-d739-4b98-8f67-842d91e6339d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1226009081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1226009081 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.322916400 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2836161700 ps |
| CPU time | 169.66 seconds |
| Started | Jul 27 08:17:30 PM PDT 24 |
| Finished | Jul 27 08:20:20 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-f16e7176-5ec2-4876-b405-84e647ed42f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322916400 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_rstmgr_smoketest.322916400 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2218801361 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3873398810 ps |
| CPU time | 602.03 seconds |
| Started | Jul 27 08:10:32 PM PDT 24 |
| Finished | Jul 27 08:20:34 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-de4cdd31-e562-445c-8560-9e5053dd39d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218801361 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2218801361 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.417188423 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2980011392 ps |
| CPU time | 227.72 seconds |
| Started | Jul 27 08:09:44 PM PDT 24 |
| Finished | Jul 27 08:13:32 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-f01e1eb6-8752-49dc-9fd5-73c80d9be421 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417188423 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.417188423 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1172747413 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3124608724 ps |
| CPU time | 476.66 seconds |
| Started | Jul 27 08:15:31 PM PDT 24 |
| Finished | Jul 27 08:23:28 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-d406c7bb-afc1-416c-9f65-54975cae3861 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1172747413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1172747413 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2159070282 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2909988977 ps |
| CPU time | 288.7 seconds |
| Started | Jul 27 08:16:10 PM PDT 24 |
| Finished | Jul 27 08:20:59 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-599ef131-1c00-46d4-b0ce-52244bb916f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159070282 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2159070282 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.93946370 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 4670704160 ps |
| CPU time | 760.64 seconds |
| Started | Jul 27 08:12:26 PM PDT 24 |
| Finished | Jul 27 08:25:07 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-04f1d677-ffd6-4c18-849a-3a18c45531cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93946 370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.93946370 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.802659576 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 6098482320 ps |
| CPU time | 1171.29 seconds |
| Started | Jul 27 08:13:01 PM PDT 24 |
| Finished | Jul 27 08:32:33 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-f0200ca1-1492-48f3-9f2b-3111693a5704 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=802659576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.802659576 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2938856826 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5743147769 ps |
| CPU time | 668.64 seconds |
| Started | Jul 27 08:15:01 PM PDT 24 |
| Finished | Jul 27 08:26:10 PM PDT 24 |
| Peak memory | 624820 kb |
| Host | smart-22e9842c-61e4-4d00-925c-d2610d17f7e5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938856826 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2938856826 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.913376735 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 5822147732 ps |
| CPU time | 432.71 seconds |
| Started | Jul 27 08:14:29 PM PDT 24 |
| Finished | Jul 27 08:21:43 PM PDT 24 |
| Peak memory | 620040 kb |
| Host | smart-804fe229-571c-4d25-9eb0-36e99ff6ae59 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913376735 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.913376735 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3929976098 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3429371880 ps |
| CPU time | 506.83 seconds |
| Started | Jul 27 08:14:58 PM PDT 24 |
| Finished | Jul 27 08:23:25 PM PDT 24 |
| Peak memory | 621796 kb |
| Host | smart-47b4a8dd-4a89-4240-acbb-eb706b57f608 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392997 6098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3929976098 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3945729210 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2117559590 ps |
| CPU time | 221.53 seconds |
| Started | Jul 27 08:17:30 PM PDT 24 |
| Finished | Jul 27 08:21:11 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-49a23837-0219-48b7-8a00-ee8cb92fe70a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945729210 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.3945729210 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.3788183632 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 2541118560 ps |
| CPU time | 281.58 seconds |
| Started | Jul 27 08:11:43 PM PDT 24 |
| Finished | Jul 27 08:16:24 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-d3aadddf-7375-40b0-8e25-74b770db828e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788183632 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3788183632 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3409047589 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2919568466 ps |
| CPU time | 343.71 seconds |
| Started | Jul 27 08:18:07 PM PDT 24 |
| Finished | Jul 27 08:23:51 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-4872c563-6cdd-48c6-88ec-3d88a34cd23c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409047589 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3409047589 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.799635102 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 2501635256 ps |
| CPU time | 229.94 seconds |
| Started | Jul 27 08:13:49 PM PDT 24 |
| Finished | Jul 27 08:17:39 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-49ba2311-5e1d-42cc-8be0-dad51e67a4bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7996351 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.799635102 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1605056982 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3380518412 ps |
| CPU time | 331.4 seconds |
| Started | Jul 27 08:10:16 PM PDT 24 |
| Finished | Jul 27 08:15:48 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-c5eb6147-06d9-4a29-b96c-9331bfa082f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605056982 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1605056982 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1154999554 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 8607831400 ps |
| CPU time | 1060.5 seconds |
| Started | Jul 27 08:08:44 PM PDT 24 |
| Finished | Jul 27 08:26:25 PM PDT 24 |
| Peak memory | 611468 kb |
| Host | smart-3f883205-71e7-4348-a8ca-c8cbeafcc528 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154999554 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1154999554 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4060036819 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 7880267866 ps |
| CPU time | 535.72 seconds |
| Started | Jul 27 08:15:07 PM PDT 24 |
| Finished | Jul 27 08:24:02 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-fbcf5492-29be-424e-ac68-64cbfdaedf83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060036819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.4060036819 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2418531358 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 7000223808 ps |
| CPU time | 676.16 seconds |
| Started | Jul 27 08:14:04 PM PDT 24 |
| Finished | Jul 27 08:25:20 PM PDT 24 |
| Peak memory | 611192 kb |
| Host | smart-1316afed-2e6c-4e45-b121-a74faed5189f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418531358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2418531358 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.712023566 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6779399862 ps |
| CPU time | 826.81 seconds |
| Started | Jul 27 08:09:21 PM PDT 24 |
| Finished | Jul 27 08:23:08 PM PDT 24 |
| Peak memory | 625504 kb |
| Host | smart-db434fba-8ebf-4e33-8a0a-1b711ab7131f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712023566 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.712023566 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1254716221 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3690922733 ps |
| CPU time | 610.73 seconds |
| Started | Jul 27 08:10:04 PM PDT 24 |
| Finished | Jul 27 08:20:15 PM PDT 24 |
| Peak memory | 625456 kb |
| Host | smart-3e3b778c-7309-40eb-a732-63a6a4c2dabe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254716221 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1254716221 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3015113620 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2566445883 ps |
| CPU time | 292.49 seconds |
| Started | Jul 27 08:10:41 PM PDT 24 |
| Finished | Jul 27 08:15:34 PM PDT 24 |
| Peak memory | 619580 kb |
| Host | smart-6a2ef860-9763-4a96-98af-8ec41f0d8a9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015113620 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3015113620 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1343390961 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2611970930 ps |
| CPU time | 292.28 seconds |
| Started | Jul 27 08:10:05 PM PDT 24 |
| Finished | Jul 27 08:14:57 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-e44b6009-156b-425e-b66a-6635c016a8b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343390961 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1343390961 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3926470107 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8542789349 ps |
| CPU time | 879.7 seconds |
| Started | Jul 27 08:13:58 PM PDT 24 |
| Finished | Jul 27 08:28:38 PM PDT 24 |
| Peak memory | 611308 kb |
| Host | smart-53ff499e-2739-49e4-8d80-177290b62eb4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926470107 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3926470107 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3098339212 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 4834985848 ps |
| CPU time | 562.92 seconds |
| Started | Jul 27 08:12:48 PM PDT 24 |
| Finished | Jul 27 08:22:12 PM PDT 24 |
| Peak memory | 611600 kb |
| Host | smart-540dbf92-60eb-4835-9432-74330fa52034 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098339212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.3098339212 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.393557539 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4580047172 ps |
| CPU time | 488.49 seconds |
| Started | Jul 27 08:13:41 PM PDT 24 |
| Finished | Jul 27 08:21:50 PM PDT 24 |
| Peak memory | 611356 kb |
| Host | smart-c4eb3e10-e43c-4179-8632-415ae802c1b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393557539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.393557539 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2983466672 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5278459417 ps |
| CPU time | 504.39 seconds |
| Started | Jul 27 08:14:40 PM PDT 24 |
| Finished | Jul 27 08:23:05 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-23ed2829-7033-490a-98e1-4183c0f22611 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983466672 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2983466672 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1545132447 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2791978720 ps |
| CPU time | 291.2 seconds |
| Started | Jul 27 08:18:27 PM PDT 24 |
| Finished | Jul 27 08:23:18 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-fa779885-7028-47a0-b8ee-d36854025475 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545132447 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1545132447 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2152129212 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 20009755268 ps |
| CPU time | 3219.98 seconds |
| Started | Jul 27 08:10:55 PM PDT 24 |
| Finished | Jul 27 09:04:36 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-6c271564-1595-45b3-aec7-cf3b2901dde8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152129212 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2152129212 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.294296074 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4220824533 ps |
| CPU time | 696.93 seconds |
| Started | Jul 27 08:11:58 PM PDT 24 |
| Finished | Jul 27 08:23:36 PM PDT 24 |
| Peak memory | 614124 kb |
| Host | smart-4d038125-0d33-47b2-acb1-19102dbc5d2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294296074 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.294296074 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4273166003 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2863734492 ps |
| CPU time | 235.13 seconds |
| Started | Jul 27 08:11:59 PM PDT 24 |
| Finished | Jul 27 08:15:55 PM PDT 24 |
| Peak memory | 613804 kb |
| Host | smart-f7d4182a-fece-4f1d-a9df-1911e97702b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273166003 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.4273166003 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1262366634 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3763022310 ps |
| CPU time | 437.87 seconds |
| Started | Jul 27 08:15:43 PM PDT 24 |
| Finished | Jul 27 08:23:02 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-ff0d5e6f-404f-4d5e-8f04-6d1d567686bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262366634 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1262366634 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.407281443 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 23361425560 ps |
| CPU time | 1610.19 seconds |
| Started | Jul 27 08:11:59 PM PDT 24 |
| Finished | Jul 27 08:38:49 PM PDT 24 |
| Peak memory | 615824 kb |
| Host | smart-be7a4a4f-5f53-4295-bd00-6389c5c1f038 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40728144 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.407281443 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4193660060 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6393668740 ps |
| CPU time | 555.61 seconds |
| Started | Jul 27 08:10:49 PM PDT 24 |
| Finished | Jul 27 08:20:05 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-111038fc-d29b-4a9e-a736-a78effe44652 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193660060 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4193660060 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2242760011 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 8267915050 ps |
| CPU time | 1820.07 seconds |
| Started | Jul 27 08:09:37 PM PDT 24 |
| Finished | Jul 27 08:39:59 PM PDT 24 |
| Peak memory | 619464 kb |
| Host | smart-a1282f19-2c01-4942-a9b9-4c564d643709 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2242760011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2242760011 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.2368313130 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 3091303056 ps |
| CPU time | 268.99 seconds |
| Started | Jul 27 08:17:26 PM PDT 24 |
| Finished | Jul 27 08:21:55 PM PDT 24 |
| Peak memory | 617668 kb |
| Host | smart-569bca0d-5822-4bd8-b397-ed5312740944 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368313130 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2368313130 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.1455032161 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4178172850 ps |
| CPU time | 619.41 seconds |
| Started | Jul 27 08:09:04 PM PDT 24 |
| Finished | Jul 27 08:19:24 PM PDT 24 |
| Peak memory | 625316 kb |
| Host | smart-0a93e7b0-8e11-4a78-ad60-2a50fae9d265 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455032161 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1455032161 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3441308602 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 8106420918 ps |
| CPU time | 1779.12 seconds |
| Started | Jul 27 08:11:27 PM PDT 24 |
| Finished | Jul 27 08:41:07 PM PDT 24 |
| Peak memory | 625304 kb |
| Host | smart-a9024b89-8cd1-47c5-b60c-c71b02039f89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441308602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3441308602 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.502195060 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 8704422156 ps |
| CPU time | 1082.82 seconds |
| Started | Jul 27 08:09:28 PM PDT 24 |
| Finished | Jul 27 08:27:32 PM PDT 24 |
| Peak memory | 625252 kb |
| Host | smart-1bd960da-4319-4566-bb3c-925e00557ea8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502195060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.502195060 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3136154503 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 79148406399 ps |
| CPU time | 14097.9 seconds |
| Started | Jul 27 08:10:12 PM PDT 24 |
| Finished | Jul 28 12:05:11 AM PDT 24 |
| Peak memory | 634592 kb |
| Host | smart-1924b5d8-2f6c-47e0-a09d-8bcccea37ddb |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3136154503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3136154503 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2210786321 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4274177880 ps |
| CPU time | 691.86 seconds |
| Started | Jul 27 08:08:35 PM PDT 24 |
| Finished | Jul 27 08:20:08 PM PDT 24 |
| Peak memory | 625308 kb |
| Host | smart-59ec9c62-59e4-48fe-a058-9068699b8ecd |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210786321 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2210786321 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2803094628 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 4470378234 ps |
| CPU time | 757.42 seconds |
| Started | Jul 27 08:10:40 PM PDT 24 |
| Finished | Jul 27 08:23:18 PM PDT 24 |
| Peak memory | 625344 kb |
| Host | smart-fcdd8b80-099c-4fcd-857e-251ca5d3ff8f |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803094628 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2803094628 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1350581171 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 3923068928 ps |
| CPU time | 852.56 seconds |
| Started | Jul 27 08:09:51 PM PDT 24 |
| Finished | Jul 27 08:24:04 PM PDT 24 |
| Peak memory | 625296 kb |
| Host | smart-20727a8c-dafa-4a91-9c6a-efd7567ecbd6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350581171 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1350581171 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.2596300882 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 18113378667 ps |
| CPU time | 2174.54 seconds |
| Started | Jul 27 08:14:52 PM PDT 24 |
| Finished | Jul 27 08:51:07 PM PDT 24 |
| Peak memory | 623020 kb |
| Host | smart-7c2560eb-a3fb-4c0a-96c3-33f3843f5946 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596300882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2596300882 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.298985044 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 15675577920 ps |
| CPU time | 4307.03 seconds |
| Started | Jul 27 08:21:26 PM PDT 24 |
| Finished | Jul 27 09:33:14 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-70b8103a-33bd-4ebb-88c0-629677e50e59 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298985044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.298985044 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.4271595634 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 15742955929 ps |
| CPU time | 3598.64 seconds |
| Started | Jul 27 08:20:24 PM PDT 24 |
| Finished | Jul 27 09:20:23 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-ecd9cc11-4ef1-4009-884a-c32f5de73654 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271595634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.4271595634 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2771682784 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 16491214354 ps |
| CPU time | 3657.72 seconds |
| Started | Jul 27 08:21:30 PM PDT 24 |
| Finished | Jul 27 09:22:28 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-9197ada1-3f3a-4d8b-b99f-bbd99aae30e4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771682784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2771682784 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2106282705 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 14513023592 ps |
| CPU time | 3705.7 seconds |
| Started | Jul 27 08:19:46 PM PDT 24 |
| Finished | Jul 27 09:21:32 PM PDT 24 |
| Peak memory | 611544 kb |
| Host | smart-8e65d72e-fe1c-4213-9427-e17b63f74588 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106282705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2106282705 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3727078945 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 11757316030 ps |
| CPU time | 3233.96 seconds |
| Started | Jul 27 08:21:21 PM PDT 24 |
| Finished | Jul 27 09:15:15 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-93a8e175-ec37-4c3f-86be-55e051123010 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727078945 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3727078945 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3545617122 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15336074248 ps |
| CPU time | 4556.21 seconds |
| Started | Jul 27 08:21:32 PM PDT 24 |
| Finished | Jul 27 09:37:29 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-b3443ed5-888a-45d6-860e-2a5ae13ec9b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545617122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3545617122 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1914032336 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 14591597336 ps |
| CPU time | 3276.95 seconds |
| Started | Jul 27 08:21:14 PM PDT 24 |
| Finished | Jul 27 09:15:51 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-4d2dd695-7408-4dfa-a80b-1ae6482066f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914032336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1914032336 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3013464679 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 15407509280 ps |
| CPU time | 3696.46 seconds |
| Started | Jul 27 08:20:35 PM PDT 24 |
| Finished | Jul 27 09:22:12 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-2eae48ec-e4ca-4d2a-b6a9-72d4bcb41528 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013464679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3013464679 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.1934443380 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 26076524392 ps |
| CPU time | 6115.36 seconds |
| Started | Jul 27 08:21:51 PM PDT 24 |
| Finished | Jul 27 10:03:47 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-c5302d9e-efb2-4b03-b6e2-3872604daabd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934443380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1934443380 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3374311236 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 15278343610 ps |
| CPU time | 3815.56 seconds |
| Started | Jul 27 08:20:20 PM PDT 24 |
| Finished | Jul 27 09:23:56 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-31e59a55-4f77-4f75-9cc0-4adf17417085 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374311236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.3374311236 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1542725507 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 26133197585 ps |
| CPU time | 3367.61 seconds |
| Started | Jul 27 08:21:00 PM PDT 24 |
| Finished | Jul 27 09:17:08 PM PDT 24 |
| Peak memory | 612208 kb |
| Host | smart-051e4461-4e27-4c93-a7f1-257d2c9567ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542725507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1542725507 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.366303815 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 15284159956 ps |
| CPU time | 3618.08 seconds |
| Started | Jul 27 08:20:25 PM PDT 24 |
| Finished | Jul 27 09:20:44 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-99b9b89b-8fee-43bc-bf18-c1c3f51493fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=366303815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.366303815 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.3113740529 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 17028069124 ps |
| CPU time | 4137.88 seconds |
| Started | Jul 27 08:20:12 PM PDT 24 |
| Finished | Jul 27 09:29:10 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-6beb459b-24cb-4e45-b471-fb482c8cef50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113740529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.3113740529 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.4123756843 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4518719580 ps |
| CPU time | 477.47 seconds |
| Started | Jul 27 08:17:06 PM PDT 24 |
| Finished | Jul 27 08:25:04 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-d32ca1e6-8087-431b-80ba-2a491dad68d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123756843 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.4123756843 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.121910276 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5713753198 ps |
| CPU time | 258.5 seconds |
| Started | Jul 27 08:16:52 PM PDT 24 |
| Finished | Jul 27 08:21:11 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-dba6e365-8b43-4130-a6de-8755bbe1350a |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=121910276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.121910276 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.4131520835 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3159857791 ps |
| CPU time | 111.96 seconds |
| Started | Jul 27 08:18:10 PM PDT 24 |
| Finished | Jul 27 08:20:02 PM PDT 24 |
| Peak memory | 623652 kb |
| Host | smart-0caa1bab-8cbb-4c33-aa5b-5bbf763b4c78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131520835 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.4131520835 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208632833 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4247372340 ps |
| CPU time | 382.33 seconds |
| Started | Jul 27 08:22:54 PM PDT 24 |
| Finished | Jul 27 08:29:17 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-a1a99227-355a-4c4d-89c4-31c9b2916381 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208632833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1208632833 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.4118091446 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5622409926 ps |
| CPU time | 652.29 seconds |
| Started | Jul 27 08:23:05 PM PDT 24 |
| Finished | Jul 27 08:33:57 PM PDT 24 |
| Peak memory | 650624 kb |
| Host | smart-6ac97fad-e71d-4a80-b7fe-c699cc1dca6f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4118091446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.4118091446 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1244842118 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4616819048 ps |
| CPU time | 727.26 seconds |
| Started | Jul 27 08:24:25 PM PDT 24 |
| Finished | Jul 27 08:36:32 PM PDT 24 |
| Peak memory | 620112 kb |
| Host | smart-b8a67a2d-d912-49dd-9eb9-68bf36e12a77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1244842118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1244842118 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3219118666 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3520557930 ps |
| CPU time | 385.81 seconds |
| Started | Jul 27 08:23:08 PM PDT 24 |
| Finished | Jul 27 08:29:34 PM PDT 24 |
| Peak memory | 649680 kb |
| Host | smart-5ef28fac-8bd3-4c3b-b789-931dc2a24ead |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219118666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3219118666 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.573612892 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 5610993952 ps |
| CPU time | 666.48 seconds |
| Started | Jul 27 08:23:13 PM PDT 24 |
| Finished | Jul 27 08:34:19 PM PDT 24 |
| Peak memory | 650496 kb |
| Host | smart-f56bdba6-faf1-41f3-b6cd-f2450a184558 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 573612892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.573612892 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393086472 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3261641320 ps |
| CPU time | 409.66 seconds |
| Started | Jul 27 08:24:41 PM PDT 24 |
| Finished | Jul 27 08:31:31 PM PDT 24 |
| Peak memory | 649464 kb |
| Host | smart-fd56cb17-c3f9-4b5d-a739-67c843e18be6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393086472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1393086472 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2148171381 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 4086143306 ps |
| CPU time | 389.67 seconds |
| Started | Jul 27 08:19:36 PM PDT 24 |
| Finished | Jul 27 08:26:06 PM PDT 24 |
| Peak memory | 649200 kb |
| Host | smart-8d22bac3-05a4-4383-ac7c-b2f089ab9837 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148171381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2148171381 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1395473097 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 6053677816 ps |
| CPU time | 372.65 seconds |
| Started | Jul 27 08:19:07 PM PDT 24 |
| Finished | Jul 27 08:25:20 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-7a13f56c-a537-46f4-81a3-fe3b0d3a0d0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1395473097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1395473097 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.856409221 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 20383867680 ps |
| CPU time | 5638.82 seconds |
| Started | Jul 27 08:19:13 PM PDT 24 |
| Finished | Jul 27 09:53:12 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-62ef9771-4664-491c-abaa-038d9849c510 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856409221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.856409221 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2510184058 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 6260280400 ps |
| CPU time | 862.08 seconds |
| Started | Jul 27 08:18:28 PM PDT 24 |
| Finished | Jul 27 08:32:51 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-385a1e5c-9a26-468e-94c6-c19a9546353a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2510184058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2510184058 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2288419866 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5273704391 ps |
| CPU time | 454.11 seconds |
| Started | Jul 27 08:19:03 PM PDT 24 |
| Finished | Jul 27 08:26:38 PM PDT 24 |
| Peak memory | 625364 kb |
| Host | smart-8ab2a4c6-7b23-4e32-962e-822b5b96eafc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288419866 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2288419866 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3669148316 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 4370279512 ps |
| CPU time | 621.47 seconds |
| Started | Jul 27 08:19:25 PM PDT 24 |
| Finished | Jul 27 08:29:47 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-78c478b1-290b-4f43-8ae9-ebd16a32ab9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36691483 16 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3669148316 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3170529256 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3950571116 ps |
| CPU time | 426.65 seconds |
| Started | Jul 27 08:17:49 PM PDT 24 |
| Finished | Jul 27 08:24:57 PM PDT 24 |
| Peak memory | 619392 kb |
| Host | smart-953fba98-eb62-413b-8e74-9111dee00dce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3170529256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3170529256 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.593494773 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 3645362220 ps |
| CPU time | 580.47 seconds |
| Started | Jul 27 08:19:10 PM PDT 24 |
| Finished | Jul 27 08:28:50 PM PDT 24 |
| Peak memory | 625296 kb |
| Host | smart-0b71907b-508e-4b47-9327-7e482e6709e0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593494773 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.593494773 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4088520153 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4373805123 ps |
| CPU time | 510.25 seconds |
| Started | Jul 27 08:20:07 PM PDT 24 |
| Finished | Jul 27 08:28:38 PM PDT 24 |
| Peak memory | 625268 kb |
| Host | smart-152bbf0a-540f-4466-9b78-08b492b3a6d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088520153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4088520153 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.619790382 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 4917325576 ps |
| CPU time | 639.89 seconds |
| Started | Jul 27 08:18:26 PM PDT 24 |
| Finished | Jul 27 08:29:07 PM PDT 24 |
| Peak memory | 625344 kb |
| Host | smart-eef9bf68-c2d5-4f49-8872-2b55cc229b9c |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619790382 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.619790382 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2738217476 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5024801080 ps |
| CPU time | 771.71 seconds |
| Started | Jul 27 08:18:52 PM PDT 24 |
| Finished | Jul 27 08:31:44 PM PDT 24 |
| Peak memory | 625320 kb |
| Host | smart-a514b71f-b9f1-4294-a3ba-1cf234badf3c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738217476 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2738217476 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3586918822 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4236989992 ps |
| CPU time | 762.69 seconds |
| Started | Jul 27 08:18:17 PM PDT 24 |
| Finished | Jul 27 08:31:00 PM PDT 24 |
| Peak memory | 625344 kb |
| Host | smart-af756b40-f9d7-4982-a41f-dd97e1777a4b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586918822 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3586918822 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.596172369 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 8411056334 ps |
| CPU time | 1026.16 seconds |
| Started | Jul 27 08:18:49 PM PDT 24 |
| Finished | Jul 27 08:35:55 PM PDT 24 |
| Peak memory | 621588 kb |
| Host | smart-de6f883a-e61b-4f48-9d02-50bcc1d7a683 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=596172369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.596172369 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3040677001 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2742476993 ps |
| CPU time | 128.76 seconds |
| Started | Jul 27 08:18:08 PM PDT 24 |
| Finished | Jul 27 08:20:17 PM PDT 24 |
| Peak memory | 621724 kb |
| Host | smart-0099fadd-b3ef-4696-81ac-02b236bee966 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040677001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3040677001 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2900482271 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3756314450 ps |
| CPU time | 427.62 seconds |
| Started | Jul 27 08:24:20 PM PDT 24 |
| Finished | Jul 27 08:31:27 PM PDT 24 |
| Peak memory | 649128 kb |
| Host | smart-30bd87bc-608b-471d-ac2a-9d6842b1dcf8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900482271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2900482271 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526439719 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4055730988 ps |
| CPU time | 532.7 seconds |
| Started | Jul 27 08:25:32 PM PDT 24 |
| Finished | Jul 27 08:34:25 PM PDT 24 |
| Peak memory | 649388 kb |
| Host | smart-71ae81aa-b6e5-4b6c-92c3-c08326650ce3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526439719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3526439719 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.449535389 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3506327864 ps |
| CPU time | 465.74 seconds |
| Started | Jul 27 08:24:27 PM PDT 24 |
| Finished | Jul 27 08:32:13 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-1ee7f650-1f1c-481f-9dca-15fa43e9a7da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449535389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.449535389 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1267073379 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 6298430904 ps |
| CPU time | 917.68 seconds |
| Started | Jul 27 08:23:22 PM PDT 24 |
| Finished | Jul 27 08:38:39 PM PDT 24 |
| Peak memory | 650504 kb |
| Host | smart-92d8d349-71ba-42e9-9b8d-ee0e865949c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1267073379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1267073379 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.2580754117 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5215098940 ps |
| CPU time | 666.92 seconds |
| Started | Jul 27 08:23:22 PM PDT 24 |
| Finished | Jul 27 08:34:30 PM PDT 24 |
| Peak memory | 650516 kb |
| Host | smart-91673e2b-8db3-4d90-a137-e4102e3116fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2580754117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2580754117 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2112262491 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3520846688 ps |
| CPU time | 355.16 seconds |
| Started | Jul 27 08:24:47 PM PDT 24 |
| Finished | Jul 27 08:30:42 PM PDT 24 |
| Peak memory | 649676 kb |
| Host | smart-7356cd7f-e1fa-4c6d-a57c-f343ec77dcca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112262491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2112262491 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3928309604 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4742519288 ps |
| CPU time | 722.15 seconds |
| Started | Jul 27 08:24:02 PM PDT 24 |
| Finished | Jul 27 08:36:04 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-d7f66372-a4ee-4e97-a3da-5f3bfbbe5996 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3928309604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3928309604 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2369805676 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3202868070 ps |
| CPU time | 489.72 seconds |
| Started | Jul 27 08:25:53 PM PDT 24 |
| Finished | Jul 27 08:34:03 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-ad4a5529-5b0d-49c4-a5e5-1562e63c0d1a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369805676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2369805676 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3400176528 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5041541356 ps |
| CPU time | 555.01 seconds |
| Started | Jul 27 08:24:34 PM PDT 24 |
| Finished | Jul 27 08:33:49 PM PDT 24 |
| Peak memory | 650984 kb |
| Host | smart-ba8e05fc-cc4d-48f1-bc35-9502a288a7d8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3400176528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3400176528 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.836926734 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4641903008 ps |
| CPU time | 473.9 seconds |
| Started | Jul 27 08:19:20 PM PDT 24 |
| Finished | Jul 27 08:27:14 PM PDT 24 |
| Peak memory | 649916 kb |
| Host | smart-d3e49780-73b3-4a8d-9e20-53735dfbb1f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836926734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.836926734 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.4155428474 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 6113816110 ps |
| CPU time | 775.96 seconds |
| Started | Jul 27 08:19:17 PM PDT 24 |
| Finished | Jul 27 08:32:13 PM PDT 24 |
| Peak memory | 650824 kb |
| Host | smart-a41fe8d2-7c31-4185-95e0-08228c7ed53f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4155428474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.4155428474 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1913014141 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 8336315928 ps |
| CPU time | 602.35 seconds |
| Started | Jul 27 08:23:42 PM PDT 24 |
| Finished | Jul 27 08:33:44 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-5db76dd9-fbae-4a76-a48f-5497512b5e3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1913014141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1913014141 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.659149327 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 12514296624 ps |
| CPU time | 3474.89 seconds |
| Started | Jul 27 08:24:48 PM PDT 24 |
| Finished | Jul 27 09:22:43 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-1bcbba52-ebce-41ed-9431-25953d8d0ba4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659149327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.659149327 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2217015140 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5896343370 ps |
| CPU time | 640.32 seconds |
| Started | Jul 27 08:19:09 PM PDT 24 |
| Finished | Jul 27 08:29:49 PM PDT 24 |
| Peak memory | 611604 kb |
| Host | smart-5ddc178d-43cb-49b3-ad79-0a64fe9cecda |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2217015140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2217015140 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.961823160 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 10456890728 ps |
| CPU time | 1149.64 seconds |
| Started | Jul 27 08:20:41 PM PDT 24 |
| Finished | Jul 27 08:39:51 PM PDT 24 |
| Peak memory | 621044 kb |
| Host | smart-a678b5b5-19c6-4249-afaa-888d76f125f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961823160 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.961823160 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1268424963 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6320786512 ps |
| CPU time | 628.98 seconds |
| Started | Jul 27 08:24:32 PM PDT 24 |
| Finished | Jul 27 08:35:01 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-6ccd90e0-4e0e-444f-a64e-949ba4b48050 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12684249 63 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.1268424963 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.844805545 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 4773209192 ps |
| CPU time | 529.03 seconds |
| Started | Jul 27 08:20:42 PM PDT 24 |
| Finished | Jul 27 08:29:31 PM PDT 24 |
| Peak memory | 619744 kb |
| Host | smart-3849ffa5-2bfd-436a-9f1d-fd603353b8ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=844805545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.844805545 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.2603910382 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 4064956812 ps |
| CPU time | 643.58 seconds |
| Started | Jul 27 08:19:25 PM PDT 24 |
| Finished | Jul 27 08:30:09 PM PDT 24 |
| Peak memory | 625292 kb |
| Host | smart-73694e3d-4d0d-46de-90d6-852b34c03497 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603910382 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2603910382 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1072227344 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 3172142513 ps |
| CPU time | 612.53 seconds |
| Started | Jul 27 08:24:35 PM PDT 24 |
| Finished | Jul 27 08:34:48 PM PDT 24 |
| Peak memory | 625288 kb |
| Host | smart-8fa3a33f-d2a7-460e-a2d6-b1610a87e58c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072227344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1072227344 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3389958162 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 4628169769 ps |
| CPU time | 484.22 seconds |
| Started | Jul 27 08:19:37 PM PDT 24 |
| Finished | Jul 27 08:27:42 PM PDT 24 |
| Peak memory | 625296 kb |
| Host | smart-5c0bb41a-1dab-452f-89ac-b5309c89d6a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389958162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3389958162 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3499360994 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4414794892 ps |
| CPU time | 664.95 seconds |
| Started | Jul 27 08:20:16 PM PDT 24 |
| Finished | Jul 27 08:31:22 PM PDT 24 |
| Peak memory | 625308 kb |
| Host | smart-137979ca-f08d-481a-b4a1-df413eb73128 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499360994 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3499360994 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3715886023 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 4032822740 ps |
| CPU time | 865.79 seconds |
| Started | Jul 27 08:20:16 PM PDT 24 |
| Finished | Jul 27 08:34:42 PM PDT 24 |
| Peak memory | 625296 kb |
| Host | smart-238bdc37-fe31-490d-9752-fe375de10ac8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715886023 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.3715886023 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3101629506 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 4435734808 ps |
| CPU time | 567.87 seconds |
| Started | Jul 27 08:19:12 PM PDT 24 |
| Finished | Jul 27 08:28:41 PM PDT 24 |
| Peak memory | 625248 kb |
| Host | smart-23116548-7279-4128-8745-87dd97c4d1f9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101629506 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3101629506 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3754448605 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3933665967 ps |
| CPU time | 334.77 seconds |
| Started | Jul 27 08:22:39 PM PDT 24 |
| Finished | Jul 27 08:28:14 PM PDT 24 |
| Peak memory | 622700 kb |
| Host | smart-a95bb8f9-adc4-4376-8e24-97a2abbdcd41 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3754448605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3754448605 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.2186375656 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 12932429907 ps |
| CPU time | 1619.42 seconds |
| Started | Jul 27 08:19:59 PM PDT 24 |
| Finished | Jul 27 08:46:59 PM PDT 24 |
| Peak memory | 621584 kb |
| Host | smart-3e58b9aa-46a3-437f-9b9b-7e87996d4189 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186375656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2186375656 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.3724430956 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4681717279 ps |
| CPU time | 324.99 seconds |
| Started | Jul 27 08:18:59 PM PDT 24 |
| Finished | Jul 27 08:24:24 PM PDT 24 |
| Peak memory | 632340 kb |
| Host | smart-e29542a8-1649-4d6a-b8c3-4469ea3fc0b3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724430956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3724430956 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.420527758 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3761988892 ps |
| CPU time | 319.73 seconds |
| Started | Jul 27 08:24:33 PM PDT 24 |
| Finished | Jul 27 08:29:53 PM PDT 24 |
| Peak memory | 649236 kb |
| Host | smart-f2f1f0c1-c132-4f4c-bc1a-7ced8352a415 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420527758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s w_alert_handler_lpg_sleep_mode_alerts.420527758 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.273271840 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 4787927992 ps |
| CPU time | 780.86 seconds |
| Started | Jul 27 08:25:27 PM PDT 24 |
| Finished | Jul 27 08:38:29 PM PDT 24 |
| Peak memory | 650676 kb |
| Host | smart-555bb562-e837-4cbf-b50c-4b2c93411bc1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 273271840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.273271840 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2307080457 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3952475512 ps |
| CPU time | 390.41 seconds |
| Started | Jul 27 08:24:53 PM PDT 24 |
| Finished | Jul 27 08:31:24 PM PDT 24 |
| Peak memory | 649688 kb |
| Host | smart-6e82cdfd-a018-4ca3-8fd3-731ffa05aa9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307080457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2307080457 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.453670031 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4814751064 ps |
| CPU time | 517.06 seconds |
| Started | Jul 27 08:25:14 PM PDT 24 |
| Finished | Jul 27 08:33:51 PM PDT 24 |
| Peak memory | 620284 kb |
| Host | smart-b63637c1-e33f-4c05-842f-62744c61f61b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 453670031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.453670031 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2675214580 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3883787188 ps |
| CPU time | 499.38 seconds |
| Started | Jul 27 08:26:10 PM PDT 24 |
| Finished | Jul 27 08:34:30 PM PDT 24 |
| Peak memory | 649472 kb |
| Host | smart-17f36e4d-2502-4207-ba2e-d6964f925735 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675214580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2675214580 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.173934336 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4003512208 ps |
| CPU time | 503.46 seconds |
| Started | Jul 27 08:25:24 PM PDT 24 |
| Finished | Jul 27 08:33:48 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-9dec71b3-38dd-4c39-a84d-e3053f1d9470 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173934336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.173934336 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.3598757848 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 5829143380 ps |
| CPU time | 642.07 seconds |
| Started | Jul 27 08:24:22 PM PDT 24 |
| Finished | Jul 27 08:35:04 PM PDT 24 |
| Peak memory | 650524 kb |
| Host | smart-2f733c1b-50a3-42ea-8a94-c311bfc77efe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3598757848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3598757848 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345945698 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3342504328 ps |
| CPU time | 394.37 seconds |
| Started | Jul 27 08:25:41 PM PDT 24 |
| Finished | Jul 27 08:32:15 PM PDT 24 |
| Peak memory | 649380 kb |
| Host | smart-35af524c-feb3-4e60-b91a-79cf2dd71ccd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345945698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2345945698 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2268600982 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 5139748296 ps |
| CPU time | 554.85 seconds |
| Started | Jul 27 08:25:30 PM PDT 24 |
| Finished | Jul 27 08:34:45 PM PDT 24 |
| Peak memory | 620268 kb |
| Host | smart-1ed422fe-b3a1-4936-bbfb-982ce3c22b21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2268600982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2268600982 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672231308 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3964902088 ps |
| CPU time | 516.8 seconds |
| Started | Jul 27 08:24:54 PM PDT 24 |
| Finished | Jul 27 08:33:31 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-cfaee729-9871-415c-abb4-1ee23f80a892 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672231308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1672231308 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.1074020937 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5730964096 ps |
| CPU time | 777.66 seconds |
| Started | Jul 27 08:26:31 PM PDT 24 |
| Finished | Jul 27 08:39:29 PM PDT 24 |
| Peak memory | 650808 kb |
| Host | smart-723d713e-fb7b-4cd6-8b7f-e41e69e8f96e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1074020937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1074020937 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3675058023 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 6309577580 ps |
| CPU time | 765.5 seconds |
| Started | Jul 27 08:25:39 PM PDT 24 |
| Finished | Jul 27 08:38:24 PM PDT 24 |
| Peak memory | 651476 kb |
| Host | smart-20da46ae-21a2-438d-b730-50ebba98a254 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3675058023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3675058023 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.1576509934 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 5528283218 ps |
| CPU time | 693.86 seconds |
| Started | Jul 27 08:26:10 PM PDT 24 |
| Finished | Jul 27 08:37:44 PM PDT 24 |
| Peak memory | 611584 kb |
| Host | smart-58d4f8b5-9dab-464d-8ea6-3c6d337391cb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1576509934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.1576509934 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.1446175338 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6168515896 ps |
| CPU time | 671.23 seconds |
| Started | Jul 27 08:28:10 PM PDT 24 |
| Finished | Jul 27 08:39:23 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-971c5a9b-79bf-4f57-b323-42b701b5e003 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1446175338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.1446175338 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4090602139 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3522238766 ps |
| CPU time | 420.71 seconds |
| Started | Jul 27 08:25:19 PM PDT 24 |
| Finished | Jul 27 08:32:20 PM PDT 24 |
| Peak memory | 649264 kb |
| Host | smart-2609ba25-3821-4f02-a2b6-ead3e1ce8626 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090602139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.4090602139 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.954200568 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4509140440 ps |
| CPU time | 680.25 seconds |
| Started | Jul 27 08:19:48 PM PDT 24 |
| Finished | Jul 27 08:31:09 PM PDT 24 |
| Peak memory | 650516 kb |
| Host | smart-3e6e9a80-c693-4155-9723-fd5bf017b423 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 954200568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.954200568 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1457508883 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 26781530412 ps |
| CPU time | 6919.91 seconds |
| Started | Jul 27 08:20:52 PM PDT 24 |
| Finished | Jul 27 10:16:13 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-0102da08-87d4-4c0a-b651-fe25f05b05df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457508883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1457508883 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.451283128 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5055727336 ps |
| CPU time | 649.66 seconds |
| Started | Jul 27 08:23:59 PM PDT 24 |
| Finished | Jul 27 08:34:50 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-b8617083-8d9b-4131-bf0a-95463f04c3d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=451283128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.451283128 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.121536833 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 12692424808 ps |
| CPU time | 932.06 seconds |
| Started | Jul 27 08:20:14 PM PDT 24 |
| Finished | Jul 27 08:35:46 PM PDT 24 |
| Peak memory | 621208 kb |
| Host | smart-c6182fdc-2ff2-4d1f-8288-e83dc6b22366 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121536833 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.121536833 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3575381136 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 8458392902 ps |
| CPU time | 1617.57 seconds |
| Started | Jul 27 08:24:55 PM PDT 24 |
| Finished | Jul 27 08:51:53 PM PDT 24 |
| Peak memory | 619752 kb |
| Host | smart-70bce80b-9a92-49f2-8957-f0f193d1ba17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3575381136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3575381136 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.1153287781 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5416551372 ps |
| CPU time | 632.94 seconds |
| Started | Jul 27 08:25:05 PM PDT 24 |
| Finished | Jul 27 08:35:39 PM PDT 24 |
| Peak memory | 650568 kb |
| Host | smart-1daace66-2d43-43b0-81df-995406b8dc93 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1153287781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1153287781 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4022439959 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 4111981880 ps |
| CPU time | 370.99 seconds |
| Started | Jul 27 08:26:48 PM PDT 24 |
| Finished | Jul 27 08:32:59 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-f2acfd24-cab8-43c8-b6c3-905b6db80fe0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022439959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4022439959 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2705729541 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3936630824 ps |
| CPU time | 524.08 seconds |
| Started | Jul 27 08:25:29 PM PDT 24 |
| Finished | Jul 27 08:34:13 PM PDT 24 |
| Peak memory | 649452 kb |
| Host | smart-ed594eb5-660d-4e66-83ac-dbee3ba3c0cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705729541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2705729541 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2943267613 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3660983650 ps |
| CPU time | 324.74 seconds |
| Started | Jul 27 08:26:40 PM PDT 24 |
| Finished | Jul 27 08:32:05 PM PDT 24 |
| Peak memory | 649388 kb |
| Host | smart-6b9cca62-59b2-4d0a-8faf-2334720b616a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943267613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2943267613 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.915473112 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 4148351232 ps |
| CPU time | 524.51 seconds |
| Started | Jul 27 08:27:43 PM PDT 24 |
| Finished | Jul 27 08:36:28 PM PDT 24 |
| Peak memory | 619772 kb |
| Host | smart-9ade01b9-cab1-41c4-9367-bfe83311c6f8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 915473112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.915473112 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.3049490498 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4553024582 ps |
| CPU time | 471.37 seconds |
| Started | Jul 27 08:27:06 PM PDT 24 |
| Finished | Jul 27 08:34:58 PM PDT 24 |
| Peak memory | 650484 kb |
| Host | smart-8bd8418d-d779-414b-8fa0-93728058460a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3049490498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3049490498 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155475832 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4364706552 ps |
| CPU time | 417.71 seconds |
| Started | Jul 27 08:26:15 PM PDT 24 |
| Finished | Jul 27 08:33:13 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-8e929179-3884-42ee-8730-1f3bc749d3da |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155475832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3155475832 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.757720944 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 6594803140 ps |
| CPU time | 751.5 seconds |
| Started | Jul 27 08:26:42 PM PDT 24 |
| Finished | Jul 27 08:39:13 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-e04a23e3-3a34-4a55-bf3a-00c71124b9a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 757720944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.757720944 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285811724 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3809274840 ps |
| CPU time | 373.42 seconds |
| Started | Jul 27 08:27:49 PM PDT 24 |
| Finished | Jul 27 08:34:03 PM PDT 24 |
| Peak memory | 649120 kb |
| Host | smart-d840bcb2-b832-4888-bd29-6d2bba333af8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285811724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4285811724 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.3745142320 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5130575790 ps |
| CPU time | 488.94 seconds |
| Started | Jul 27 08:27:54 PM PDT 24 |
| Finished | Jul 27 08:36:03 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-1b6ea267-e635-4bbd-b032-acfc116edd30 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3745142320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3745142320 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174305160 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3967168048 ps |
| CPU time | 486.79 seconds |
| Started | Jul 27 08:25:31 PM PDT 24 |
| Finished | Jul 27 08:33:38 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-ae02e8ef-6be2-48d5-b7a8-d0b14a2e73fe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174305160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2174305160 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.918874576 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3727124920 ps |
| CPU time | 465.53 seconds |
| Started | Jul 27 08:20:48 PM PDT 24 |
| Finished | Jul 27 08:28:34 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-6e2f7ad7-8629-4040-b0ba-f8aff9a03904 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918874576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.918874576 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.637640804 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5074712020 ps |
| CPU time | 663.83 seconds |
| Started | Jul 27 08:25:13 PM PDT 24 |
| Finished | Jul 27 08:36:17 PM PDT 24 |
| Peak memory | 650208 kb |
| Host | smart-910393d2-620a-48b3-83aa-132b35dde7a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 637640804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.637640804 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3306577575 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 17242820076 ps |
| CPU time | 3723.21 seconds |
| Started | Jul 27 08:26:10 PM PDT 24 |
| Finished | Jul 27 09:28:14 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-6e0a13bd-a62b-449f-b20f-747f64cbb8d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306577575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3306577575 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2826085410 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 7543716884 ps |
| CPU time | 667.98 seconds |
| Started | Jul 27 08:21:28 PM PDT 24 |
| Finished | Jul 27 08:32:37 PM PDT 24 |
| Peak memory | 621044 kb |
| Host | smart-acc9cac9-682e-49c6-b512-77e4d9be342b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826085410 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2826085410 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1493535846 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 7907332360 ps |
| CPU time | 1646.2 seconds |
| Started | Jul 27 08:21:38 PM PDT 24 |
| Finished | Jul 27 08:49:05 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-2817950c-5b50-4d9a-b224-3c102346d60a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1493535846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1493535846 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4071020253 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4557983782 ps |
| CPU time | 353.22 seconds |
| Started | Jul 27 08:27:13 PM PDT 24 |
| Finished | Jul 27 08:33:06 PM PDT 24 |
| Peak memory | 649824 kb |
| Host | smart-ead973c5-71b6-45a7-b2e7-5c1081c4d799 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071020253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4071020253 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.3640357779 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5646923024 ps |
| CPU time | 664.61 seconds |
| Started | Jul 27 08:26:08 PM PDT 24 |
| Finished | Jul 27 08:37:13 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-a77299bb-de71-4549-87f0-b7fd7057c272 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3640357779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3640357779 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3292681612 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3512507918 ps |
| CPU time | 434.8 seconds |
| Started | Jul 27 08:27:05 PM PDT 24 |
| Finished | Jul 27 08:34:20 PM PDT 24 |
| Peak memory | 649448 kb |
| Host | smart-e4812a63-98f5-4466-95ef-8bf70062c35d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292681612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3292681612 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3571275148 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 5362431168 ps |
| CPU time | 641.16 seconds |
| Started | Jul 27 08:28:22 PM PDT 24 |
| Finished | Jul 27 08:39:04 PM PDT 24 |
| Peak memory | 650572 kb |
| Host | smart-9b25218c-e9b5-4abf-8712-40ddb220f4cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3571275148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3571275148 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1621707459 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3221981160 ps |
| CPU time | 351.56 seconds |
| Started | Jul 27 08:27:14 PM PDT 24 |
| Finished | Jul 27 08:33:06 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-3802eade-542d-4883-bb43-dd2364861714 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621707459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1621707459 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1818667961 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3535597654 ps |
| CPU time | 366.29 seconds |
| Started | Jul 27 08:26:56 PM PDT 24 |
| Finished | Jul 27 08:33:02 PM PDT 24 |
| Peak memory | 649512 kb |
| Host | smart-be2bd526-55f9-4444-aad4-07fb75a30f55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818667961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1818667961 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.145711599 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3243078790 ps |
| CPU time | 384.22 seconds |
| Started | Jul 27 08:27:01 PM PDT 24 |
| Finished | Jul 27 08:33:25 PM PDT 24 |
| Peak memory | 649444 kb |
| Host | smart-26b453e8-2322-4cb3-91ba-73cf21601296 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145711599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.145711599 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3143374839 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 5954199266 ps |
| CPU time | 599.94 seconds |
| Started | Jul 27 08:28:44 PM PDT 24 |
| Finished | Jul 27 08:38:44 PM PDT 24 |
| Peak memory | 620372 kb |
| Host | smart-b996c16e-a4d3-4591-b6b0-5eecddd900b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3143374839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3143374839 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.15916613 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4360689790 ps |
| CPU time | 385.41 seconds |
| Started | Jul 27 08:28:31 PM PDT 24 |
| Finished | Jul 27 08:34:56 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-1dc02b07-19b8-4211-a4fd-29ce1df7a1d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15916613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw _alert_handler_lpg_sleep_mode_alerts.15916613 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3381514371 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4123809824 ps |
| CPU time | 436.58 seconds |
| Started | Jul 27 08:27:24 PM PDT 24 |
| Finished | Jul 27 08:34:40 PM PDT 24 |
| Peak memory | 649444 kb |
| Host | smart-a6943805-517c-4bc7-b278-4b5f794ec7d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381514371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3381514371 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.935632181 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5736874424 ps |
| CPU time | 469.34 seconds |
| Started | Jul 27 08:28:20 PM PDT 24 |
| Finished | Jul 27 08:36:10 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-386af569-6358-40f5-826c-520323d1f9bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 935632181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.935632181 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775209875 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3633337832 ps |
| CPU time | 516.77 seconds |
| Started | Jul 27 08:28:56 PM PDT 24 |
| Finished | Jul 27 08:37:33 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-7621f5a7-743e-4e80-bc01-7ac98540f849 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775209875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1775209875 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2699091671 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4203399864 ps |
| CPU time | 359.99 seconds |
| Started | Jul 27 08:26:49 PM PDT 24 |
| Finished | Jul 27 08:32:49 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-68115381-32d0-4820-879e-ea3080de42db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699091671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2699091671 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.1793731954 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4807133728 ps |
| CPU time | 721.35 seconds |
| Started | Jul 27 08:21:39 PM PDT 24 |
| Finished | Jul 27 08:33:41 PM PDT 24 |
| Peak memory | 650564 kb |
| Host | smart-ef6596db-46fa-46c5-98d0-1f5a86e674ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1793731954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1793731954 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1162656254 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 22604257336 ps |
| CPU time | 4911.97 seconds |
| Started | Jul 27 08:21:48 PM PDT 24 |
| Finished | Jul 27 09:43:41 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-193e5a96-3ec5-4ed3-a6e0-f10238c9405e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162656254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.1162656254 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3947345056 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 11235544423 ps |
| CPU time | 738.08 seconds |
| Started | Jul 27 08:25:48 PM PDT 24 |
| Finished | Jul 27 08:38:07 PM PDT 24 |
| Peak memory | 621492 kb |
| Host | smart-1315bc80-4506-451e-9b39-f2352de388bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947345056 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3947345056 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2387929347 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4459061628 ps |
| CPU time | 572.68 seconds |
| Started | Jul 27 08:20:17 PM PDT 24 |
| Finished | Jul 27 08:29:50 PM PDT 24 |
| Peak memory | 619772 kb |
| Host | smart-42ad35e1-4d08-4cb6-bfc6-8e27354b47cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2387929347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2387929347 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2374086917 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 3354229950 ps |
| CPU time | 445.52 seconds |
| Started | Jul 27 08:27:52 PM PDT 24 |
| Finished | Jul 27 08:35:18 PM PDT 24 |
| Peak memory | 649360 kb |
| Host | smart-a844b78f-c385-40f7-8e3c-e1cb6c508e41 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374086917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2374086917 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797677478 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 4072920222 ps |
| CPU time | 416.53 seconds |
| Started | Jul 27 08:28:01 PM PDT 24 |
| Finished | Jul 27 08:34:58 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-01b2e0d3-4aaf-4897-ac29-afa902a5f2cb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797677478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1797677478 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.235178519 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 6143042942 ps |
| CPU time | 740.08 seconds |
| Started | Jul 27 08:33:29 PM PDT 24 |
| Finished | Jul 27 08:45:50 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-09941d0b-c742-4569-9dab-ce2913b8264f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 235178519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.235178519 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2202569065 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4056268600 ps |
| CPU time | 349.24 seconds |
| Started | Jul 27 08:28:13 PM PDT 24 |
| Finished | Jul 27 08:34:02 PM PDT 24 |
| Peak memory | 649176 kb |
| Host | smart-ea8d64e2-e673-4970-927c-51d39ddf7dd0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202569065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2202569065 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2633612530 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4893949620 ps |
| CPU time | 660.93 seconds |
| Started | Jul 27 08:32:08 PM PDT 24 |
| Finished | Jul 27 08:43:09 PM PDT 24 |
| Peak memory | 650536 kb |
| Host | smart-865bfb3f-0ecf-4e33-8c86-64a8c6f7aa69 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2633612530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2633612530 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.837939794 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 3994286776 ps |
| CPU time | 410.24 seconds |
| Started | Jul 27 08:28:02 PM PDT 24 |
| Finished | Jul 27 08:34:53 PM PDT 24 |
| Peak memory | 649372 kb |
| Host | smart-c18f9be7-080f-4483-954a-d55f972acbb5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837939794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_s w_alert_handler_lpg_sleep_mode_alerts.837939794 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2397335387 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4727654986 ps |
| CPU time | 628.89 seconds |
| Started | Jul 27 08:33:46 PM PDT 24 |
| Finished | Jul 27 08:44:15 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-04eacd2d-b2d2-4c7f-996d-1a29f0a2b222 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2397335387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2397335387 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399622969 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4412304436 ps |
| CPU time | 411.7 seconds |
| Started | Jul 27 08:28:41 PM PDT 24 |
| Finished | Jul 27 08:35:33 PM PDT 24 |
| Peak memory | 649612 kb |
| Host | smart-4af1233f-6cb7-4da1-8d3f-87887ded8dbe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399622969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2399622969 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.805635778 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5316892210 ps |
| CPU time | 712.7 seconds |
| Started | Jul 27 08:29:26 PM PDT 24 |
| Finished | Jul 27 08:41:19 PM PDT 24 |
| Peak memory | 650228 kb |
| Host | smart-153cea13-8dab-415d-861d-46faed11ab5c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 805635778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.805635778 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.2161577863 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5099533530 ps |
| CPU time | 718.95 seconds |
| Started | Jul 27 08:33:20 PM PDT 24 |
| Finished | Jul 27 08:45:19 PM PDT 24 |
| Peak memory | 650852 kb |
| Host | smart-cac3f930-a001-4b8c-bb6f-76160e72e9e2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2161577863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2161577863 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.1315022409 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6147286040 ps |
| CPU time | 700.13 seconds |
| Started | Jul 27 08:29:17 PM PDT 24 |
| Finished | Jul 27 08:40:57 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-ff9a9703-6817-4420-846d-469b5596078f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1315022409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1315022409 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.425981766 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4589650828 ps |
| CPU time | 468.38 seconds |
| Started | Jul 27 08:29:19 PM PDT 24 |
| Finished | Jul 27 08:37:08 PM PDT 24 |
| Peak memory | 649804 kb |
| Host | smart-80a6838d-ec6c-422b-bfa4-3277c69fc9a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425981766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.425981766 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1452204781 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 6216367640 ps |
| CPU time | 728.38 seconds |
| Started | Jul 27 08:33:41 PM PDT 24 |
| Finished | Jul 27 08:45:50 PM PDT 24 |
| Peak memory | 650800 kb |
| Host | smart-7abbe5bb-7827-406f-bac8-1af7c679cff1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1452204781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1452204781 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3855087630 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5772148540 ps |
| CPU time | 742.61 seconds |
| Started | Jul 27 08:33:25 PM PDT 24 |
| Finished | Jul 27 08:45:48 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-2d16b43f-915e-4b4c-87ec-ecdd66688b62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3855087630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3855087630 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2415142742 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 3666957740 ps |
| CPU time | 368.18 seconds |
| Started | Jul 27 08:21:59 PM PDT 24 |
| Finished | Jul 27 08:28:07 PM PDT 24 |
| Peak memory | 649432 kb |
| Host | smart-f14b320e-5478-4576-a832-77268d969fcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415142742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2415142742 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.830194478 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 6145862614 ps |
| CPU time | 796.48 seconds |
| Started | Jul 27 08:22:57 PM PDT 24 |
| Finished | Jul 27 08:36:14 PM PDT 24 |
| Peak memory | 650804 kb |
| Host | smart-678c20da-adea-4fe5-a8d2-09d5198f0c47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 830194478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.830194478 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1904378172 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 25821256864 ps |
| CPU time | 5753.83 seconds |
| Started | Jul 27 08:23:22 PM PDT 24 |
| Finished | Jul 27 09:59:16 PM PDT 24 |
| Peak memory | 610880 kb |
| Host | smart-82138de1-3e5c-4d32-ad8d-69a9013b2d73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904378172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.1904378172 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3702081437 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 9278870024 ps |
| CPU time | 1099.94 seconds |
| Started | Jul 27 08:20:47 PM PDT 24 |
| Finished | Jul 27 08:39:08 PM PDT 24 |
| Peak memory | 621780 kb |
| Host | smart-56bc6cfb-f0fe-48e5-aa5f-7fe31f4f9197 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702081437 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3702081437 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964293014 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3596811616 ps |
| CPU time | 499.68 seconds |
| Started | Jul 27 08:29:05 PM PDT 24 |
| Finished | Jul 27 08:37:24 PM PDT 24 |
| Peak memory | 649480 kb |
| Host | smart-60fb67a6-42fe-4bac-b3f6-5e61a6b9c430 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964293014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1964293014 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1034522258 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 5292198820 ps |
| CPU time | 549.45 seconds |
| Started | Jul 27 08:28:25 PM PDT 24 |
| Finished | Jul 27 08:37:35 PM PDT 24 |
| Peak memory | 650612 kb |
| Host | smart-bb56dd8c-8315-4863-992c-8ed397ea47d9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1034522258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1034522258 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830000774 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4541330688 ps |
| CPU time | 533.8 seconds |
| Started | Jul 27 08:28:55 PM PDT 24 |
| Finished | Jul 27 08:37:49 PM PDT 24 |
| Peak memory | 649740 kb |
| Host | smart-636d22a0-ab09-4513-97a5-267a8b8df4d4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830000774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3830000774 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.805911875 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 5686948312 ps |
| CPU time | 656.26 seconds |
| Started | Jul 27 08:28:56 PM PDT 24 |
| Finished | Jul 27 08:39:53 PM PDT 24 |
| Peak memory | 650504 kb |
| Host | smart-a98c3ae3-26cf-4f64-80f4-85b8498d0132 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 805911875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.805911875 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3675042461 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4685594260 ps |
| CPU time | 532.47 seconds |
| Started | Jul 27 08:29:40 PM PDT 24 |
| Finished | Jul 27 08:38:32 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-5456c3eb-0795-41c3-8450-ebee91bb03dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3675042461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3675042461 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1057451156 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3411782830 ps |
| CPU time | 419.52 seconds |
| Started | Jul 27 08:29:47 PM PDT 24 |
| Finished | Jul 27 08:36:46 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-cfc945df-9f1b-488c-8177-0f0e9fd45d44 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057451156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1057451156 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.3799380375 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4607508682 ps |
| CPU time | 579.31 seconds |
| Started | Jul 27 08:28:36 PM PDT 24 |
| Finished | Jul 27 08:38:16 PM PDT 24 |
| Peak memory | 650576 kb |
| Host | smart-fb6992f5-0b93-4b6b-9dfd-aa1b469f5d08 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3799380375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3799380375 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2796006103 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3623047120 ps |
| CPU time | 369.8 seconds |
| Started | Jul 27 08:29:39 PM PDT 24 |
| Finished | Jul 27 08:35:49 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-80a5e545-d109-42fd-92e6-5f189c11b523 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796006103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2796006103 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.288450195 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3496193980 ps |
| CPU time | 406.99 seconds |
| Started | Jul 27 08:28:44 PM PDT 24 |
| Finished | Jul 27 08:35:31 PM PDT 24 |
| Peak memory | 649596 kb |
| Host | smart-eb4d0bcc-edeb-452e-9847-e80d89cfcfce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288450195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_s w_alert_handler_lpg_sleep_mode_alerts.288450195 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.775486969 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 5310619176 ps |
| CPU time | 722.34 seconds |
| Started | Jul 27 08:29:51 PM PDT 24 |
| Finished | Jul 27 08:41:54 PM PDT 24 |
| Peak memory | 611496 kb |
| Host | smart-6483f9e7-14a4-47e7-91b0-2acbcd740779 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 775486969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.775486969 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479800292 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3367638550 ps |
| CPU time | 458.33 seconds |
| Started | Jul 27 08:30:31 PM PDT 24 |
| Finished | Jul 27 08:38:09 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-d601772a-eb7d-42ec-94d7-b02586b7fc9f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479800292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1479800292 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.685006764 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4112064584 ps |
| CPU time | 513.69 seconds |
| Started | Jul 27 08:30:43 PM PDT 24 |
| Finished | Jul 27 08:39:17 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-efaa962e-b3d6-4957-8613-a21e8d389831 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685006764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.685006764 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.2474414871 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 5194920250 ps |
| CPU time | 793.14 seconds |
| Started | Jul 27 08:28:41 PM PDT 24 |
| Finished | Jul 27 08:41:54 PM PDT 24 |
| Peak memory | 650580 kb |
| Host | smart-3826cc7b-c6f9-46a8-bdad-450d09896a3e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2474414871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.2474414871 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.585382326 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5758541720 ps |
| CPU time | 556.6 seconds |
| Started | Jul 27 08:29:27 PM PDT 24 |
| Finished | Jul 27 08:38:44 PM PDT 24 |
| Peak memory | 650616 kb |
| Host | smart-cdb2b148-2e16-49ab-8c87-dfd4f1956b67 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 585382326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.585382326 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2625414694 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3515629392 ps |
| CPU time | 415.76 seconds |
| Started | Jul 27 08:21:35 PM PDT 24 |
| Finished | Jul 27 08:28:31 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-6c831d76-d6a4-4a47-a9b5-52565153004a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625414694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2625414694 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.2995518494 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 6039271928 ps |
| CPU time | 811.81 seconds |
| Started | Jul 27 08:22:19 PM PDT 24 |
| Finished | Jul 27 08:35:52 PM PDT 24 |
| Peak memory | 650648 kb |
| Host | smart-08493bd8-c942-49c9-837f-327ecc90dc98 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2995518494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2995518494 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.290020731 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 18712148528 ps |
| CPU time | 3911.63 seconds |
| Started | Jul 27 08:21:04 PM PDT 24 |
| Finished | Jul 27 09:26:16 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-f842d3ce-cd64-4489-9f07-f292d4b2c008 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290020731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.290020731 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3216765743 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 8861304694 ps |
| CPU time | 656.54 seconds |
| Started | Jul 27 08:22:03 PM PDT 24 |
| Finished | Jul 27 08:33:00 PM PDT 24 |
| Peak memory | 621520 kb |
| Host | smart-812d19d6-b4b4-4dab-8c1f-550cb2e68077 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216765743 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.3216765743 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1507264575 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4551304232 ps |
| CPU time | 713.98 seconds |
| Started | Jul 27 08:22:40 PM PDT 24 |
| Finished | Jul 27 08:34:34 PM PDT 24 |
| Peak memory | 619724 kb |
| Host | smart-feb0545a-dcdd-4d1a-88a3-eb4a21cbfed0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1507264575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1507264575 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.4067623288 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4296838896 ps |
| CPU time | 696.11 seconds |
| Started | Jul 27 08:29:05 PM PDT 24 |
| Finished | Jul 27 08:40:42 PM PDT 24 |
| Peak memory | 650544 kb |
| Host | smart-dedee89d-e776-4358-835d-cfcd8b5de4b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4067623288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.4067623288 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.62930847 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4575882636 ps |
| CPU time | 509.62 seconds |
| Started | Jul 27 08:29:37 PM PDT 24 |
| Finished | Jul 27 08:38:07 PM PDT 24 |
| Peak memory | 620396 kb |
| Host | smart-92fab59f-1eb0-4020-856b-9f889ee7a2d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 62930847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.62930847 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1183224063 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 4069648984 ps |
| CPU time | 547.55 seconds |
| Started | Jul 27 08:28:46 PM PDT 24 |
| Finished | Jul 27 08:37:54 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-0d242a24-4bab-4247-8ef5-1042c74a6508 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1183224063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1183224063 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.681721865 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4836845966 ps |
| CPU time | 786.53 seconds |
| Started | Jul 27 08:29:42 PM PDT 24 |
| Finished | Jul 27 08:42:49 PM PDT 24 |
| Peak memory | 650676 kb |
| Host | smart-45c69c89-216f-4473-a62a-c6ce48e89864 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 681721865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.681721865 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1505860469 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4673696508 ps |
| CPU time | 532.49 seconds |
| Started | Jul 27 08:28:42 PM PDT 24 |
| Finished | Jul 27 08:37:35 PM PDT 24 |
| Peak memory | 650372 kb |
| Host | smart-d1fed5c0-be88-4d22-bf64-88d3d0ad125e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1505860469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1505860469 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.17722909 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 5272334840 ps |
| CPU time | 575.82 seconds |
| Started | Jul 27 08:30:02 PM PDT 24 |
| Finished | Jul 27 08:39:38 PM PDT 24 |
| Peak memory | 620108 kb |
| Host | smart-e9dbefb6-05fa-4144-9cbf-0d04f0c89b5b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 17722909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.17722909 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.891035824 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5684633360 ps |
| CPU time | 677.99 seconds |
| Started | Jul 27 08:28:49 PM PDT 24 |
| Finished | Jul 27 08:40:08 PM PDT 24 |
| Peak memory | 611456 kb |
| Host | smart-2ca7449d-6eb1-41cb-a4b8-a6dc54b7e76a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 891035824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.891035824 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.470528804 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5450530472 ps |
| CPU time | 732.53 seconds |
| Started | Jul 27 08:28:55 PM PDT 24 |
| Finished | Jul 27 08:41:07 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-04a891fa-9ff9-4797-b86b-f43668405595 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 470528804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.470528804 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.265820525 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4635073326 ps |
| CPU time | 516.3 seconds |
| Started | Jul 27 08:29:29 PM PDT 24 |
| Finished | Jul 27 08:38:05 PM PDT 24 |
| Peak memory | 650580 kb |
| Host | smart-e1c535db-ef7e-4cdd-aedd-b4fc8d834910 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 265820525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.265820525 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3381088067 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4721231164 ps |
| CPU time | 208.61 seconds |
| Started | Jul 27 08:50:08 PM PDT 24 |
| Finished | Jul 27 08:53:37 PM PDT 24 |
| Peak memory | 641504 kb |
| Host | smart-8a185eef-f649-4260-a47a-2562852b163d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381088067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.3381088067 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.241269224 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4890119832 ps |
| CPU time | 235.21 seconds |
| Started | Jul 27 08:49:52 PM PDT 24 |
| Finished | Jul 27 08:53:47 PM PDT 24 |
| Peak memory | 649784 kb |
| Host | smart-e7929117-e567-46d6-b569-b29a47fb9619 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241269224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.241269224 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.21651967 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4717382352 ps |
| CPU time | 219.85 seconds |
| Started | Jul 27 08:49:52 PM PDT 24 |
| Finished | Jul 27 08:53:32 PM PDT 24 |
| Peak memory | 657432 kb |
| Host | smart-bcd975ba-8272-4440-9553-05d3cb0e1c1c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 3.chip_padctrl_attributes.21651967 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.233123665 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 5577159480 ps |
| CPU time | 239.96 seconds |
| Started | Jul 27 08:50:05 PM PDT 24 |
| Finished | Jul 27 08:54:05 PM PDT 24 |
| Peak memory | 649700 kb |
| Host | smart-3b252552-16a7-485b-b170-9d6bbf4f56f1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233123665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.233123665 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2523071507 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 5447298528 ps |
| CPU time | 257.4 seconds |
| Started | Jul 27 08:50:05 PM PDT 24 |
| Finished | Jul 27 08:54:23 PM PDT 24 |
| Peak memory | 641468 kb |
| Host | smart-937f6f30-9a1e-4561-aac6-a2547cbf14c5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523071507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2523071507 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.417587248 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4705176724 ps |
| CPU time | 362.74 seconds |
| Started | Jul 27 08:49:56 PM PDT 24 |
| Finished | Jul 27 08:55:59 PM PDT 24 |
| Peak memory | 649688 kb |
| Host | smart-825de2f0-e60c-4b17-b1c3-fedda9e41992 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417587248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 7.chip_padctrl_attributes.417587248 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.774603622 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4846273952 ps |
| CPU time | 238.62 seconds |
| Started | Jul 27 08:50:08 PM PDT 24 |
| Finished | Jul 27 08:54:07 PM PDT 24 |
| Peak memory | 649696 kb |
| Host | smart-707af72a-6d16-414e-bfad-26a8823df144 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774603622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.774603622 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4058339183 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4923207026 ps |
| CPU time | 237.17 seconds |
| Started | Jul 27 08:49:55 PM PDT 24 |
| Finished | Jul 27 08:53:52 PM PDT 24 |
| Peak memory | 657888 kb |
| Host | smart-862546c9-1447-4a6b-96de-4aaaff204456 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058339183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.4058339183 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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