| T257 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1412652380 |
|
|
Jul 29 08:15:42 PM PDT 24 |
Jul 29 08:20:05 PM PDT 24 |
2396106248 ps |
| T710 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.837047774 |
|
|
Jul 29 08:48:09 PM PDT 24 |
Jul 29 08:56:55 PM PDT 24 |
5933383838 ps |
| T831 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1873890759 |
|
|
Jul 29 08:49:24 PM PDT 24 |
Jul 29 08:58:13 PM PDT 24 |
4175012746 ps |
| T941 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1674674414 |
|
|
Jul 29 08:44:01 PM PDT 24 |
Jul 29 08:50:31 PM PDT 24 |
3556743904 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3952264166 |
|
|
Jul 29 08:40:02 PM PDT 24 |
Jul 29 09:06:28 PM PDT 24 |
11151929147 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_example_rom.1024431340 |
|
|
Jul 29 08:26:05 PM PDT 24 |
Jul 29 08:28:20 PM PDT 24 |
2317697924 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.900353888 |
|
|
Jul 29 08:34:04 PM PDT 24 |
Jul 29 08:42:56 PM PDT 24 |
7765621640 ps |
| T359 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.810658942 |
|
|
Jul 29 08:48:01 PM PDT 24 |
Jul 29 08:57:29 PM PDT 24 |
4683679760 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2545356440 |
|
|
Jul 29 08:29:34 PM PDT 24 |
Jul 29 08:52:57 PM PDT 24 |
21770664136 ps |
| T461 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1830839024 |
|
|
Jul 29 08:16:21 PM PDT 24 |
Jul 29 08:54:11 PM PDT 24 |
8797396104 ps |
| T777 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.487171983 |
|
|
Jul 29 08:36:09 PM PDT 24 |
Jul 29 08:54:27 PM PDT 24 |
6419943068 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_example_flash.1427211543 |
|
|
Jul 29 08:15:03 PM PDT 24 |
Jul 29 08:19:04 PM PDT 24 |
2476247634 ps |
| T99 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.4283279383 |
|
|
Jul 29 08:25:38 PM PDT 24 |
Jul 29 08:29:30 PM PDT 24 |
2828695036 ps |
| T408 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3566131819 |
|
|
Jul 29 08:38:06 PM PDT 24 |
Jul 29 08:47:11 PM PDT 24 |
4788540686 ps |
| T412 |
/workspace/coverage/default/2.chip_sw_example_rom.1734859078 |
|
|
Jul 29 08:29:05 PM PDT 24 |
Jul 29 08:30:59 PM PDT 24 |
2720986872 ps |
| T413 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2805606349 |
|
|
Jul 29 08:46:57 PM PDT 24 |
Jul 29 09:02:23 PM PDT 24 |
6287744368 ps |
| T414 |
/workspace/coverage/default/2.chip_sw_aes_enc.1635617524 |
|
|
Jul 29 08:39:12 PM PDT 24 |
Jul 29 08:43:01 PM PDT 24 |
3214023584 ps |
| T262 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1878161500 |
|
|
Jul 29 08:26:16 PM PDT 24 |
Jul 29 08:56:57 PM PDT 24 |
11404841386 ps |
| T163 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2102092010 |
|
|
Jul 29 08:47:39 PM PDT 24 |
Jul 29 08:55:01 PM PDT 24 |
3509577460 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3316350017 |
|
|
Jul 29 08:25:50 PM PDT 24 |
Jul 29 08:31:54 PM PDT 24 |
3675788360 ps |
| T150 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2075196293 |
|
|
Jul 29 08:19:01 PM PDT 24 |
Jul 29 09:26:33 PM PDT 24 |
24887815346 ps |
| T81 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1092582839 |
|
|
Jul 29 08:51:30 PM PDT 24 |
Jul 29 09:02:24 PM PDT 24 |
4367457008 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2438147294 |
|
|
Jul 29 08:37:44 PM PDT 24 |
Jul 29 09:10:51 PM PDT 24 |
9559259804 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.319794140 |
|
|
Jul 29 08:26:22 PM PDT 24 |
Jul 29 08:36:48 PM PDT 24 |
4363810838 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.395822927 |
|
|
Jul 29 08:13:07 PM PDT 24 |
Jul 29 10:07:33 PM PDT 24 |
31425919220 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2794021885 |
|
|
Jul 29 08:38:19 PM PDT 24 |
Jul 29 08:52:01 PM PDT 24 |
8860246824 ps |
| T757 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2994569686 |
|
|
Jul 29 08:49:30 PM PDT 24 |
Jul 29 08:59:10 PM PDT 24 |
4691266032 ps |
| T828 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1821685493 |
|
|
Jul 29 08:52:02 PM PDT 24 |
Jul 29 08:58:32 PM PDT 24 |
3628740510 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1827306872 |
|
|
Jul 29 08:29:59 PM PDT 24 |
Jul 29 08:35:57 PM PDT 24 |
2929980488 ps |
| T946 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1360369466 |
|
|
Jul 29 08:34:02 PM PDT 24 |
Jul 29 09:47:09 PM PDT 24 |
15503736570 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2026854478 |
|
|
Jul 29 08:34:19 PM PDT 24 |
Jul 29 09:30:19 PM PDT 24 |
32525792396 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.837391418 |
|
|
Jul 29 08:13:19 PM PDT 24 |
Jul 29 08:23:52 PM PDT 24 |
4296705920 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_example_flash.3753580638 |
|
|
Jul 29 08:24:58 PM PDT 24 |
Jul 29 08:27:48 PM PDT 24 |
2475277056 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1594430998 |
|
|
Jul 29 08:21:06 PM PDT 24 |
Jul 29 08:43:22 PM PDT 24 |
7792371612 ps |
| T950 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2575122524 |
|
|
Jul 29 08:35:39 PM PDT 24 |
Jul 29 08:43:42 PM PDT 24 |
3561000548 ps |
| T833 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.69019131 |
|
|
Jul 29 08:46:41 PM PDT 24 |
Jul 29 08:57:18 PM PDT 24 |
5754900308 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3690352949 |
|
|
Jul 29 08:37:23 PM PDT 24 |
Jul 29 08:49:13 PM PDT 24 |
4906541928 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3082273164 |
|
|
Jul 29 08:32:34 PM PDT 24 |
Jul 29 09:01:10 PM PDT 24 |
8599239336 ps |
| T772 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.155821697 |
|
|
Jul 29 08:51:12 PM PDT 24 |
Jul 29 08:57:36 PM PDT 24 |
4024774664 ps |
| T811 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4242899853 |
|
|
Jul 29 08:50:21 PM PDT 24 |
Jul 29 08:56:28 PM PDT 24 |
2970435514 ps |
| T778 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2718299057 |
|
|
Jul 29 08:48:01 PM PDT 24 |
Jul 29 08:54:08 PM PDT 24 |
3991016362 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2056224327 |
|
|
Jul 29 08:34:57 PM PDT 24 |
Jul 29 08:45:26 PM PDT 24 |
4222270972 ps |
| T700 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1250055651 |
|
|
Jul 29 08:42:28 PM PDT 24 |
Jul 29 09:34:59 PM PDT 24 |
15989035700 ps |
| T535 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.658145576 |
|
|
Jul 29 08:31:20 PM PDT 24 |
Jul 29 08:56:09 PM PDT 24 |
10727425243 ps |
| T953 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.728009298 |
|
|
Jul 29 08:40:25 PM PDT 24 |
Jul 29 08:48:07 PM PDT 24 |
6176714064 ps |
| T954 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1299658456 |
|
|
Jul 29 08:43:50 PM PDT 24 |
Jul 29 09:19:28 PM PDT 24 |
13393466562 ps |
| T955 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.777290834 |
|
|
Jul 29 08:27:43 PM PDT 24 |
Jul 29 08:32:28 PM PDT 24 |
2903991396 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1897961546 |
|
|
Jul 29 08:36:53 PM PDT 24 |
Jul 29 08:47:50 PM PDT 24 |
8592797028 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3987856173 |
|
|
Jul 29 08:25:29 PM PDT 24 |
Jul 29 08:36:40 PM PDT 24 |
4151724227 ps |
| T707 |
/workspace/coverage/default/1.chip_sw_edn_kat.3424463896 |
|
|
Jul 29 08:30:44 PM PDT 24 |
Jul 29 08:41:31 PM PDT 24 |
2982084328 ps |
| T403 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3016749396 |
|
|
Jul 29 08:15:46 PM PDT 24 |
Jul 29 08:19:47 PM PDT 24 |
2862233872 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2169320856 |
|
|
Jul 29 08:33:01 PM PDT 24 |
Jul 29 08:48:14 PM PDT 24 |
9305147562 ps |
| T175 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2005763001 |
|
|
Jul 29 08:43:21 PM PDT 24 |
Jul 29 08:53:10 PM PDT 24 |
5780078020 ps |
| T400 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2366847135 |
|
|
Jul 29 08:26:01 PM PDT 24 |
Jul 29 08:32:26 PM PDT 24 |
6065558496 ps |
| T957 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2419516606 |
|
|
Jul 29 08:42:21 PM PDT 24 |
Jul 29 08:59:54 PM PDT 24 |
14522691502 ps |
| T151 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.334221605 |
|
|
Jul 29 08:27:56 PM PDT 24 |
Jul 29 09:21:36 PM PDT 24 |
17288765644 ps |
| T231 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.846051642 |
|
|
Jul 29 08:50:02 PM PDT 24 |
Jul 29 08:55:40 PM PDT 24 |
3055613050 ps |
| T406 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.252939626 |
|
|
Jul 29 08:14:04 PM PDT 24 |
Jul 29 08:49:10 PM PDT 24 |
27524999244 ps |
| T706 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4144383232 |
|
|
Jul 29 08:48:21 PM PDT 24 |
Jul 29 10:11:13 PM PDT 24 |
24128158660 ps |
| T704 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943232170 |
|
|
Jul 29 08:49:54 PM PDT 24 |
Jul 29 08:56:12 PM PDT 24 |
3863961820 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3701431224 |
|
|
Jul 29 08:35:11 PM PDT 24 |
Jul 29 08:43:00 PM PDT 24 |
3817886580 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2754233109 |
|
|
Jul 29 08:15:13 PM PDT 24 |
Jul 29 08:23:42 PM PDT 24 |
5306444392 ps |
| T358 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3809760488 |
|
|
Jul 29 08:48:00 PM PDT 24 |
Jul 29 08:57:48 PM PDT 24 |
5267165194 ps |
| T959 |
/workspace/coverage/default/0.rom_e2e_self_hash.2320728661 |
|
|
Jul 29 08:29:43 PM PDT 24 |
Jul 29 10:10:55 PM PDT 24 |
26475371212 ps |
| T702 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1593461766 |
|
|
Jul 29 08:33:13 PM PDT 24 |
Jul 29 08:38:12 PM PDT 24 |
2841064643 ps |
| T142 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3507576982 |
|
|
Jul 29 08:44:37 PM PDT 24 |
Jul 29 09:05:55 PM PDT 24 |
7633603188 ps |
| T454 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2033855418 |
|
|
Jul 29 08:26:32 PM PDT 24 |
Jul 29 09:11:42 PM PDT 24 |
24682829473 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1617950476 |
|
|
Jul 29 08:38:52 PM PDT 24 |
Jul 29 08:46:28 PM PDT 24 |
3843673192 ps |
| T13 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2946428122 |
|
|
Jul 29 08:31:02 PM PDT 24 |
Jul 29 08:39:52 PM PDT 24 |
6351337190 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3457306047 |
|
|
Jul 29 08:37:57 PM PDT 24 |
Jul 29 08:53:15 PM PDT 24 |
5330597816 ps |
| T961 |
/workspace/coverage/default/2.rom_e2e_self_hash.2030692894 |
|
|
Jul 29 08:46:02 PM PDT 24 |
Jul 29 10:17:47 PM PDT 24 |
26051661750 ps |
| T962 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3578077233 |
|
|
Jul 29 08:33:47 PM PDT 24 |
Jul 29 09:21:01 PM PDT 24 |
11198456506 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1969738357 |
|
|
Jul 29 08:32:52 PM PDT 24 |
Jul 29 08:39:15 PM PDT 24 |
2506476520 ps |
| T964 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.598131544 |
|
|
Jul 29 08:27:21 PM PDT 24 |
Jul 29 09:13:57 PM PDT 24 |
10934110768 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.1921300075 |
|
|
Jul 29 08:30:04 PM PDT 24 |
Jul 29 09:00:59 PM PDT 24 |
8164751250 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4123959128 |
|
|
Jul 29 08:35:52 PM PDT 24 |
Jul 29 08:42:52 PM PDT 24 |
3399451186 ps |
| T232 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.931961741 |
|
|
Jul 29 08:51:35 PM PDT 24 |
Jul 29 09:02:58 PM PDT 24 |
5404634156 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.97690299 |
|
|
Jul 29 08:30:54 PM PDT 24 |
Jul 29 08:34:00 PM PDT 24 |
3490967170 ps |
| T388 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.554212843 |
|
|
Jul 29 08:21:33 PM PDT 24 |
Jul 29 08:26:18 PM PDT 24 |
2662959708 ps |
| T215 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2090555281 |
|
|
Jul 29 08:31:40 PM PDT 24 |
Jul 29 08:59:25 PM PDT 24 |
7502679540 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.4071371579 |
|
|
Jul 29 08:13:45 PM PDT 24 |
Jul 29 09:02:48 PM PDT 24 |
12011896868 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3752432096 |
|
|
Jul 29 08:26:46 PM PDT 24 |
Jul 29 08:34:25 PM PDT 24 |
5767302244 ps |
| T763 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3867962090 |
|
|
Jul 29 08:46:35 PM PDT 24 |
Jul 29 08:54:07 PM PDT 24 |
3570318364 ps |
| T967 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3507814773 |
|
|
Jul 29 08:28:58 PM PDT 24 |
Jul 29 09:41:52 PM PDT 24 |
15069762536 ps |
| T968 |
/workspace/coverage/default/0.chip_tap_straps_prod.2590862512 |
|
|
Jul 29 08:17:13 PM PDT 24 |
Jul 29 08:20:09 PM PDT 24 |
3065288473 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.250790624 |
|
|
Jul 29 08:15:54 PM PDT 24 |
Jul 29 08:33:21 PM PDT 24 |
5369929956 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1928417477 |
|
|
Jul 29 08:16:07 PM PDT 24 |
Jul 29 08:43:00 PM PDT 24 |
13631130648 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.4044787395 |
|
|
Jul 29 08:27:34 PM PDT 24 |
Jul 29 08:31:06 PM PDT 24 |
3650065718 ps |
| T972 |
/workspace/coverage/default/0.rom_keymgr_functest.1744638113 |
|
|
Jul 29 08:25:37 PM PDT 24 |
Jul 29 08:36:32 PM PDT 24 |
4207894956 ps |
| T349 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.3424116379 |
|
|
Jul 29 08:26:45 PM PDT 24 |
Jul 29 08:31:06 PM PDT 24 |
2720799952 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1864060091 |
|
|
Jul 29 08:34:14 PM PDT 24 |
Jul 29 08:46:47 PM PDT 24 |
4540853279 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.4160786059 |
|
|
Jul 29 08:36:46 PM PDT 24 |
Jul 29 09:07:28 PM PDT 24 |
19748038518 ps |
| T975 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3034000671 |
|
|
Jul 29 08:24:20 PM PDT 24 |
Jul 29 08:33:49 PM PDT 24 |
4106537552 ps |
| T976 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.741524537 |
|
|
Jul 29 08:25:01 PM PDT 24 |
Jul 29 08:29:59 PM PDT 24 |
3092542324 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.2766097750 |
|
|
Jul 29 08:34:59 PM PDT 24 |
Jul 29 08:41:33 PM PDT 24 |
2783440040 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3392455427 |
|
|
Jul 29 08:35:59 PM PDT 24 |
Jul 29 08:42:14 PM PDT 24 |
2486727972 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2740082173 |
|
|
Jul 29 08:31:52 PM PDT 24 |
Jul 29 08:41:38 PM PDT 24 |
5756345096 ps |
| T730 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2691296473 |
|
|
Jul 29 08:19:57 PM PDT 24 |
Jul 29 08:25:19 PM PDT 24 |
2992032808 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.3642516487 |
|
|
Jul 29 08:29:47 PM PDT 24 |
Jul 29 08:34:26 PM PDT 24 |
2922661800 ps |
| T41 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.534275047 |
|
|
Jul 29 08:15:37 PM PDT 24 |
Jul 29 08:30:33 PM PDT 24 |
6498152529 ps |
| T190 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.857813465 |
|
|
Jul 29 08:26:31 PM PDT 24 |
Jul 29 09:46:30 PM PDT 24 |
44827956284 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.513909038 |
|
|
Jul 29 08:15:14 PM PDT 24 |
Jul 29 08:19:55 PM PDT 24 |
2431636450 ps |
| T165 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2442919015 |
|
|
Jul 29 08:50:40 PM PDT 24 |
Jul 29 08:56:14 PM PDT 24 |
3103623400 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3061033858 |
|
|
Jul 29 08:30:13 PM PDT 24 |
Jul 29 08:34:27 PM PDT 24 |
3376818440 ps |
| T711 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3205311989 |
|
|
Jul 29 08:45:06 PM PDT 24 |
Jul 29 08:55:08 PM PDT 24 |
5522404376 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.1747198466 |
|
|
Jul 29 08:25:25 PM PDT 24 |
Jul 29 09:01:32 PM PDT 24 |
9294440928 ps |
| T983 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.773074680 |
|
|
Jul 29 08:35:41 PM PDT 24 |
Jul 29 08:42:03 PM PDT 24 |
3552613848 ps |
| T155 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.378989875 |
|
|
Jul 29 08:28:00 PM PDT 24 |
Jul 29 11:18:02 PM PDT 24 |
59623687045 ps |
| T984 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3730268761 |
|
|
Jul 29 08:44:36 PM PDT 24 |
Jul 29 09:41:27 PM PDT 24 |
14775478568 ps |
| T985 |
/workspace/coverage/default/2.chip_sival_flash_info_access.1542196266 |
|
|
Jul 29 08:29:42 PM PDT 24 |
Jul 29 08:34:03 PM PDT 24 |
3196951244 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.906316506 |
|
|
Jul 29 08:26:09 PM PDT 24 |
Jul 29 08:46:29 PM PDT 24 |
5714897588 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3497786688 |
|
|
Jul 29 08:35:19 PM PDT 24 |
Jul 29 08:41:53 PM PDT 24 |
4606642300 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3431723602 |
|
|
Jul 29 08:29:04 PM PDT 24 |
Jul 29 08:35:13 PM PDT 24 |
3352063312 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2357880760 |
|
|
Jul 29 08:15:34 PM PDT 24 |
Jul 29 08:31:28 PM PDT 24 |
5133646644 ps |
| T796 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1943869828 |
|
|
Jul 29 08:50:26 PM PDT 24 |
Jul 29 09:00:55 PM PDT 24 |
5355512902 ps |
| T708 |
/workspace/coverage/default/2.chip_sw_edn_kat.2028711165 |
|
|
Jul 29 08:37:23 PM PDT 24 |
Jul 29 08:49:10 PM PDT 24 |
3249348052 ps |
| T242 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3290592611 |
|
|
Jul 29 08:26:59 PM PDT 24 |
Jul 29 09:05:24 PM PDT 24 |
22428487659 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1719774973 |
|
|
Jul 29 08:39:40 PM PDT 24 |
Jul 29 08:49:36 PM PDT 24 |
5353955618 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.4268979354 |
|
|
Jul 29 08:28:12 PM PDT 24 |
Jul 29 08:32:36 PM PDT 24 |
2959290936 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3771131709 |
|
|
Jul 29 08:43:26 PM PDT 24 |
Jul 29 08:47:01 PM PDT 24 |
2760518600 ps |
| T203 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3845151929 |
|
|
Jul 29 08:26:46 PM PDT 24 |
Jul 29 08:40:23 PM PDT 24 |
7688347290 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.237349777 |
|
|
Jul 29 08:28:49 PM PDT 24 |
Jul 29 08:34:02 PM PDT 24 |
2754130996 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3256539531 |
|
|
Jul 29 08:15:14 PM PDT 24 |
Jul 29 08:22:11 PM PDT 24 |
4523109288 ps |
| T738 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.775262136 |
|
|
Jul 29 08:45:53 PM PDT 24 |
Jul 29 08:54:43 PM PDT 24 |
4234186128 ps |
| T240 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.748444533 |
|
|
Jul 29 08:32:12 PM PDT 24 |
Jul 29 09:56:21 PM PDT 24 |
49484594226 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1552621795 |
|
|
Jul 29 08:36:14 PM PDT 24 |
Jul 29 08:44:51 PM PDT 24 |
4912149248 ps |
| T767 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.399796692 |
|
|
Jul 29 08:49:37 PM PDT 24 |
Jul 29 08:58:40 PM PDT 24 |
4638155916 ps |
| T992 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3547327074 |
|
|
Jul 29 08:31:14 PM PDT 24 |
Jul 29 09:28:10 PM PDT 24 |
16163825562 ps |
| T830 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2693363761 |
|
|
Jul 29 08:49:26 PM PDT 24 |
Jul 29 08:58:07 PM PDT 24 |
4735766514 ps |
| T835 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2491143774 |
|
|
Jul 29 08:46:52 PM PDT 24 |
Jul 29 08:56:26 PM PDT 24 |
5627388860 ps |
| T993 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1338606664 |
|
|
Jul 29 08:39:15 PM PDT 24 |
Jul 29 09:50:55 PM PDT 24 |
16204213880 ps |
| T392 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3978050088 |
|
|
Jul 29 08:30:59 PM PDT 24 |
Jul 29 08:33:25 PM PDT 24 |
2196959284 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1329297253 |
|
|
Jul 29 08:14:11 PM PDT 24 |
Jul 29 08:33:07 PM PDT 24 |
6479057120 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_alert_test.4179812984 |
|
|
Jul 29 08:30:59 PM PDT 24 |
Jul 29 08:35:01 PM PDT 24 |
2820190160 ps |
| T995 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1533569168 |
|
|
Jul 29 08:34:14 PM PDT 24 |
Jul 29 09:35:47 PM PDT 24 |
18204085799 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2429819582 |
|
|
Jul 29 08:25:09 PM PDT 24 |
Jul 29 08:30:56 PM PDT 24 |
3569764516 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.504091563 |
|
|
Jul 29 08:34:00 PM PDT 24 |
Jul 29 08:55:40 PM PDT 24 |
6479015756 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1517128058 |
|
|
Jul 29 08:13:35 PM PDT 24 |
Jul 29 08:26:26 PM PDT 24 |
5070763740 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.333204754 |
|
|
Jul 29 08:32:00 PM PDT 24 |
Jul 29 08:47:54 PM PDT 24 |
9861833131 ps |
| T770 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1052144262 |
|
|
Jul 29 08:47:18 PM PDT 24 |
Jul 29 08:57:03 PM PDT 24 |
4442793354 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.588746461 |
|
|
Jul 29 08:30:45 PM PDT 24 |
Jul 29 09:02:59 PM PDT 24 |
9914310790 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4008737893 |
|
|
Jul 29 08:13:57 PM PDT 24 |
Jul 29 08:30:47 PM PDT 24 |
7226575064 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2906900184 |
|
|
Jul 29 08:30:49 PM PDT 24 |
Jul 29 08:40:46 PM PDT 24 |
6810696280 ps |
| T779 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.36235145 |
|
|
Jul 29 08:30:30 PM PDT 24 |
Jul 29 08:39:42 PM PDT 24 |
5756823922 ps |
| T1001 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3864871642 |
|
|
Jul 29 08:22:53 PM PDT 24 |
Jul 29 08:28:15 PM PDT 24 |
3181043756 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.609373178 |
|
|
Jul 29 08:27:33 PM PDT 24 |
Jul 29 08:32:46 PM PDT 24 |
3461803072 ps |
| T391 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3523235156 |
|
|
Jul 29 08:31:15 PM PDT 24 |
Jul 29 10:08:24 PM PDT 24 |
23629047394 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.293065166 |
|
|
Jul 29 08:25:40 PM PDT 24 |
Jul 29 08:30:06 PM PDT 24 |
2923913316 ps |
| T1003 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.346648701 |
|
|
Jul 29 08:44:38 PM PDT 24 |
Jul 29 08:54:34 PM PDT 24 |
4441888968 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2884828798 |
|
|
Jul 29 08:43:14 PM PDT 24 |
Jul 29 08:49:39 PM PDT 24 |
3672722878 ps |
| T1005 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1739863825 |
|
|
Jul 29 08:31:19 PM PDT 24 |
Jul 29 09:18:02 PM PDT 24 |
11899216148 ps |
| T705 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4011271451 |
|
|
Jul 29 08:39:06 PM PDT 24 |
Jul 30 01:50:05 AM PDT 24 |
138327147810 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2949042799 |
|
|
Jul 29 08:16:15 PM PDT 24 |
Jul 29 08:21:40 PM PDT 24 |
2993801111 ps |
| T1007 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1152346252 |
|
|
Jul 29 08:42:54 PM PDT 24 |
Jul 29 08:55:21 PM PDT 24 |
9176229011 ps |
| T775 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.537021637 |
|
|
Jul 29 08:46:28 PM PDT 24 |
Jul 29 08:57:00 PM PDT 24 |
6531231066 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.61442050 |
|
|
Jul 29 08:29:28 PM PDT 24 |
Jul 29 08:40:00 PM PDT 24 |
7073339344 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.620825525 |
|
|
Jul 29 08:35:10 PM PDT 24 |
Jul 29 09:00:04 PM PDT 24 |
7522343708 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.700305611 |
|
|
Jul 29 08:33:52 PM PDT 24 |
Jul 29 09:00:40 PM PDT 24 |
6283524912 ps |
| T1011 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2018596467 |
|
|
Jul 29 08:44:11 PM PDT 24 |
Jul 29 09:06:45 PM PDT 24 |
8565641310 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2357238573 |
|
|
Jul 29 08:33:49 PM PDT 24 |
Jul 29 08:38:13 PM PDT 24 |
2970085560 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.212436987 |
|
|
Jul 29 08:38:34 PM PDT 24 |
Jul 29 08:55:36 PM PDT 24 |
5816368280 ps |
| T158 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1619936779 |
|
|
Jul 29 08:15:10 PM PDT 24 |
Jul 29 08:22:29 PM PDT 24 |
3489558824 ps |
| T719 |
/workspace/coverage/default/2.chip_tap_straps_dev.2742152196 |
|
|
Jul 29 08:38:07 PM PDT 24 |
Jul 29 09:08:40 PM PDT 24 |
16169435034 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1522436164 |
|
|
Jul 29 08:29:13 PM PDT 24 |
Jul 29 09:04:26 PM PDT 24 |
11682481706 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2160272629 |
|
|
Jul 29 08:16:52 PM PDT 24 |
Jul 29 08:47:30 PM PDT 24 |
9915215480 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1488450450 |
|
|
Jul 29 08:24:22 PM PDT 24 |
Jul 29 08:33:18 PM PDT 24 |
3979533350 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2807369314 |
|
|
Jul 29 08:35:10 PM PDT 24 |
Jul 29 08:41:15 PM PDT 24 |
2897708850 ps |
| T204 |
/workspace/coverage/default/0.chip_sw_power_virus.3950178891 |
|
|
Jul 29 08:21:01 PM PDT 24 |
Jul 29 08:44:44 PM PDT 24 |
5922818572 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3243674008 |
|
|
Jul 29 08:33:22 PM PDT 24 |
Jul 29 08:46:08 PM PDT 24 |
5041288232 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2329326094 |
|
|
Jul 29 08:14:32 PM PDT 24 |
Jul 29 08:19:05 PM PDT 24 |
2891921523 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.730030548 |
|
|
Jul 29 08:34:54 PM PDT 24 |
Jul 29 08:57:41 PM PDT 24 |
8101327492 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3801572021 |
|
|
Jul 29 08:15:42 PM PDT 24 |
Jul 29 08:27:40 PM PDT 24 |
4778106541 ps |
| T720 |
/workspace/coverage/default/0.chip_tap_straps_dev.1516332575 |
|
|
Jul 29 08:15:47 PM PDT 24 |
Jul 29 08:47:53 PM PDT 24 |
15195084831 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2946977604 |
|
|
Jul 29 08:37:34 PM PDT 24 |
Jul 29 09:02:07 PM PDT 24 |
5953062526 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3757030480 |
|
|
Jul 29 08:35:46 PM PDT 24 |
Jul 29 08:46:19 PM PDT 24 |
4679396484 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1088269408 |
|
|
Jul 29 08:37:39 PM PDT 24 |
Jul 29 08:43:59 PM PDT 24 |
3808244090 ps |
| T321 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3166777541 |
|
|
Jul 29 08:27:38 PM PDT 24 |
Jul 29 08:41:55 PM PDT 24 |
4131336196 ps |
| T1020 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.103528282 |
|
|
Jul 29 08:43:04 PM PDT 24 |
Jul 29 08:58:01 PM PDT 24 |
10746141934 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3430824977 |
|
|
Jul 29 08:31:46 PM PDT 24 |
Jul 29 08:45:55 PM PDT 24 |
6956080928 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.2355569204 |
|
|
Jul 29 08:24:09 PM PDT 24 |
Jul 29 08:28:58 PM PDT 24 |
2839209482 ps |
| T100 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3618951490 |
|
|
Jul 29 08:15:45 PM PDT 24 |
Jul 29 08:20:21 PM PDT 24 |
3002768420 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.1056587228 |
|
|
Jul 29 08:29:33 PM PDT 24 |
Jul 29 08:48:32 PM PDT 24 |
4833650232 ps |
| T1024 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.184709606 |
|
|
Jul 29 08:13:58 PM PDT 24 |
Jul 29 09:18:41 PM PDT 24 |
18973151120 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1252550925 |
|
|
Jul 29 08:16:03 PM PDT 24 |
Jul 29 08:24:16 PM PDT 24 |
5313280072 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2643211874 |
|
|
Jul 29 08:27:11 PM PDT 24 |
Jul 29 08:32:30 PM PDT 24 |
4012603580 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_kmac_idle.598442247 |
|
|
Jul 29 08:18:51 PM PDT 24 |
Jul 29 08:23:03 PM PDT 24 |
3442696904 ps |
| T1027 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1487453541 |
|
|
Jul 29 08:31:30 PM PDT 24 |
Jul 29 09:32:24 PM PDT 24 |
15012666812 ps |
| T333 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1343493884 |
|
|
Jul 29 08:42:25 PM PDT 24 |
Jul 29 08:55:18 PM PDT 24 |
4000697432 ps |
| T754 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.560248169 |
|
|
Jul 29 08:44:58 PM PDT 24 |
Jul 29 08:56:56 PM PDT 24 |
4729501678 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2367201128 |
|
|
Jul 29 08:25:12 PM PDT 24 |
Jul 29 08:35:27 PM PDT 24 |
3952990840 ps |
| T290 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1198013741 |
|
|
Jul 29 08:42:43 PM PDT 24 |
Jul 29 08:51:59 PM PDT 24 |
4804673557 ps |
| T101 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.882430114 |
|
|
Jul 29 08:15:37 PM PDT 24 |
Jul 29 08:43:03 PM PDT 24 |
20363191406 ps |
| T740 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1118680456 |
|
|
Jul 29 08:46:00 PM PDT 24 |
Jul 29 08:57:23 PM PDT 24 |
5181426804 ps |
| T792 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1644014470 |
|
|
Jul 29 08:49:41 PM PDT 24 |
Jul 29 09:01:13 PM PDT 24 |
5006907476 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.713804736 |
|
|
Jul 29 08:27:49 PM PDT 24 |
Jul 29 08:35:04 PM PDT 24 |
6866137284 ps |
| T1030 |
/workspace/coverage/default/2.chip_sw_example_concurrency.1708238391 |
|
|
Jul 29 08:34:37 PM PDT 24 |
Jul 29 08:38:36 PM PDT 24 |
3426767670 ps |
| T1031 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.511889360 |
|
|
Jul 29 08:32:50 PM PDT 24 |
Jul 29 09:36:58 PM PDT 24 |
14972641980 ps |
| T1032 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.866555615 |
|
|
Jul 29 08:35:34 PM PDT 24 |
Jul 29 08:53:04 PM PDT 24 |
6541216832 ps |
| T1033 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3628096720 |
|
|
Jul 29 08:39:14 PM PDT 24 |
Jul 29 09:50:36 PM PDT 24 |
15598984524 ps |
| T765 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668072328 |
|
|
Jul 29 08:46:38 PM PDT 24 |
Jul 29 08:53:27 PM PDT 24 |
3223222016 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3901107791 |
|
|
Jul 29 08:14:21 PM PDT 24 |
Jul 29 09:09:51 PM PDT 24 |
12448065161 ps |
| T780 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.69338031 |
|
|
Jul 29 08:50:11 PM PDT 24 |
Jul 29 08:58:34 PM PDT 24 |
4832516290 ps |
| T1035 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.3590281757 |
|
|
Jul 29 08:32:57 PM PDT 24 |
Jul 29 09:29:09 PM PDT 24 |
15079459469 ps |
| T1036 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.621885967 |
|
|
Jul 29 08:43:58 PM PDT 24 |
Jul 29 10:01:41 PM PDT 24 |
20425757156 ps |
| T1037 |
/workspace/coverage/default/1.rom_e2e_static_critical.3198525960 |
|
|
Jul 29 08:39:45 PM PDT 24 |
Jul 29 09:52:36 PM PDT 24 |
17623613528 ps |
| T1038 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.583411279 |
|
|
Jul 29 08:26:10 PM PDT 24 |
Jul 29 08:31:39 PM PDT 24 |
3459470390 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2730640155 |
|
|
Jul 29 08:16:13 PM PDT 24 |
Jul 29 08:34:53 PM PDT 24 |
7415033592 ps |
| T27 |
/workspace/coverage/default/0.chip_sw_gpio.1459424129 |
|
|
Jul 29 08:14:06 PM PDT 24 |
Jul 29 08:20:50 PM PDT 24 |
3410057800 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.657809116 |
|
|
Jul 29 08:16:51 PM PDT 24 |
Jul 29 08:49:08 PM PDT 24 |
10262023544 ps |
| T1041 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.4255333259 |
|
|
Jul 29 08:16:34 PM PDT 24 |
Jul 29 08:23:20 PM PDT 24 |
6497693684 ps |
| T1042 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1402709287 |
|
|
Jul 29 08:36:25 PM PDT 24 |
Jul 29 08:44:32 PM PDT 24 |
5108820392 ps |
| T1043 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.945179385 |
|
|
Jul 29 08:16:51 PM PDT 24 |
Jul 29 08:45:43 PM PDT 24 |
15178954144 ps |
| T1044 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.4129126947 |
|
|
Jul 29 08:15:56 PM PDT 24 |
Jul 29 08:26:05 PM PDT 24 |
3817561360 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.936982221 |
|
|
Jul 29 08:27:06 PM PDT 24 |
Jul 29 08:37:11 PM PDT 24 |
4657188124 ps |
| T301 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1835262737 |
|
|
Jul 29 08:18:22 PM PDT 24 |
Jul 29 08:22:21 PM PDT 24 |
2853666968 ps |
| T1046 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3449050761 |
|
|
Jul 29 08:25:03 PM PDT 24 |
Jul 29 08:33:20 PM PDT 24 |
5996471176 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.3470325516 |
|
|
Jul 29 08:14:15 PM PDT 24 |
Jul 29 08:18:08 PM PDT 24 |
2897229584 ps |
| T1048 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3346602303 |
|
|
Jul 29 08:31:22 PM PDT 24 |
Jul 29 10:01:25 PM PDT 24 |
22664305173 ps |
| T211 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3560986936 |
|
|
Jul 29 08:26:56 PM PDT 24 |
Jul 29 08:37:11 PM PDT 24 |
4715641438 ps |
| T739 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.4082794774 |
|
|
Jul 29 08:43:06 PM PDT 24 |
Jul 29 08:53:34 PM PDT 24 |
5429129320 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3123776158 |
|
|
Jul 29 08:14:10 PM PDT 24 |
Jul 29 08:50:37 PM PDT 24 |
13109768028 ps |
| T263 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2385735341 |
|
|
Jul 29 08:26:27 PM PDT 24 |
Jul 29 08:58:35 PM PDT 24 |
11408698954 ps |
| T1049 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3495092355 |
|
|
Jul 29 08:49:16 PM PDT 24 |
Jul 29 08:54:47 PM PDT 24 |
3513208330 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2873448369 |
|
|
Jul 29 08:33:26 PM PDT 24 |
Jul 29 08:51:29 PM PDT 24 |
7296085433 ps |
| T1051 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3197210163 |
|
|
Jul 29 08:47:33 PM PDT 24 |
Jul 29 10:13:56 PM PDT 24 |
23728921176 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1060978866 |
|
|
Jul 29 08:16:07 PM PDT 24 |
Jul 29 08:21:21 PM PDT 24 |
3506203195 ps |
| T36 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3752252286 |
|
|
Jul 29 08:35:17 PM PDT 24 |
Jul 29 08:43:55 PM PDT 24 |
5822407004 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3249178497 |
|
|
Jul 29 08:27:29 PM PDT 24 |
Jul 29 08:39:37 PM PDT 24 |
4342340982 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3744998111 |
|
|
Jul 29 08:15:29 PM PDT 24 |
Jul 29 08:29:04 PM PDT 24 |
10531667601 ps |
| T1054 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1120250314 |
|
|
Jul 29 08:26:40 PM PDT 24 |
Jul 29 08:30:14 PM PDT 24 |
3084480392 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2151899896 |
|
|
Jul 29 08:19:13 PM PDT 24 |
Jul 29 08:47:24 PM PDT 24 |
23940548730 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1639156666 |
|
|
Jul 29 08:23:43 PM PDT 24 |
Jul 29 08:27:55 PM PDT 24 |
2534259150 ps |
| T825 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031632924 |
|
|
Jul 29 08:49:02 PM PDT 24 |
Jul 29 08:55:22 PM PDT 24 |
3918667290 ps |
| T797 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.4212364338 |
|
|
Jul 29 08:44:50 PM PDT 24 |
Jul 29 08:58:34 PM PDT 24 |
5930817876 ps |
| T783 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.18419879 |
|
|
Jul 29 08:50:13 PM PDT 24 |
Jul 29 08:59:07 PM PDT 24 |
5900311480 ps |
| T1055 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.244232658 |
|
|
Jul 29 08:27:15 PM PDT 24 |
Jul 29 08:34:27 PM PDT 24 |
5399395606 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3508995380 |
|
|
Jul 29 08:35:22 PM PDT 24 |
Jul 29 08:43:35 PM PDT 24 |
7952480670 ps |
| T1057 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.982534778 |
|
|
Jul 29 08:15:00 PM PDT 24 |
Jul 29 08:18:17 PM PDT 24 |
2947802794 ps |
| T1058 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574704721 |
|
|
Jul 29 08:46:58 PM PDT 24 |
Jul 29 08:55:03 PM PDT 24 |
3319747096 ps |
| T1059 |
/workspace/coverage/default/0.rom_e2e_smoke.3765070468 |
|
|
Jul 29 08:21:56 PM PDT 24 |
Jul 29 09:32:34 PM PDT 24 |
14544363948 ps |
| T129 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2819012183 |
|
|
Jul 29 08:35:21 PM PDT 24 |
Jul 29 08:43:42 PM PDT 24 |
5604151600 ps |
| T1060 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3848643146 |
|
|
Jul 29 08:30:09 PM PDT 24 |
Jul 29 09:34:11 PM PDT 24 |
16296141552 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4049059777 |
|
|
Jul 29 08:25:57 PM PDT 24 |
Jul 29 08:46:15 PM PDT 24 |
9654521700 ps |
| T334 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.607336805 |
|
|
Jul 29 08:25:30 PM PDT 24 |
Jul 29 08:37:33 PM PDT 24 |
5223108920 ps |
| T1062 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3826687295 |
|
|
Jul 29 08:14:34 PM PDT 24 |
Jul 29 08:22:53 PM PDT 24 |
4653367280 ps |
| T781 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.4031596312 |
|
|
Jul 29 08:45:32 PM PDT 24 |
Jul 29 08:57:05 PM PDT 24 |
5134407600 ps |
| T1063 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1321973103 |
|
|
Jul 29 08:45:49 PM PDT 24 |
Jul 29 09:19:57 PM PDT 24 |
12378483016 ps |
| T254 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3793062802 |
|
|
Jul 29 08:48:18 PM PDT 24 |
Jul 29 09:00:05 PM PDT 24 |
6235681920 ps |
| T1064 |
/workspace/coverage/default/2.rom_e2e_static_critical.955942870 |
|
|
Jul 29 08:43:26 PM PDT 24 |
Jul 29 09:58:11 PM PDT 24 |
16470961100 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.37540819 |
|
|
Jul 29 08:18:40 PM PDT 24 |
Jul 29 08:29:36 PM PDT 24 |
7822453268 ps |